Display module and display terminal

Abstract

The application relates to a display module and a display terminal. The display module comprises a data driver and a timing controller. The timing controller is connected with the data driver. The timing controller is used for sending a display signal to the data driver. The display signal comprises a data signal and a flag signal. The data driver is used for controlling a target module in the data driver to enter a first preset mode with lower power consumption when the flag signal is a first flag signal. The first flag signal is sent to the data driver by the timing controller when a synchronization signal received by the timing controller enters a blanking period. The application can control the target module in the data driver to enter the first preset mode with lower power consumption by using the first flag signal in the display signal when the synchronization signal received by the timing controller enters the blanking period. Thus, the power consumption of the data driver is reduced, and the energy efficiency of the display module is improved.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a display module and a display terminal. Background Technology

[0002] In panel display technology, technologies such as thin-film transistor liquid crystal display (TFT-LCD) occupy an important position in the panel display market due to their advantages such as low operating voltage, long lifespan, no radiation, and low cost.

[0003] However, these panel display technologies typically consume a lot of power, resulting in lower energy efficiency for display products such as televisions (TVs), monitors (MNTs), and notebooks (NBs). Summary of the Invention

[0004] This application provides a display module and a display terminal that can reduce power consumption and improve the energy efficiency of the display module.

[0005] This application provides a display module, including:

[0006] Data drive; and

[0007] A timing controller, connected to the data driver, is used to send display signals to the data driver, the display signals including data signals and flag signals;

[0008] The data driver is used to control the target module in the data driver to enter a first preset mode when the flag signal is the first flag signal. The power consumption of the target module in the first preset mode is less than the power consumption of the target module in the second preset mode. The first flag signal is sent by the timing controller to the data driver when the synchronization signal received by the timing controller enters the blanking period.

[0009] In one embodiment of this application, the data driver is further configured to control the target module in the data driver to exit the first preset mode when the flag signal is a second flag signal, wherein the second flag signal is sent to the data driver by the timing controller when the synchronization signal exits the blanking period.

[0010] In one embodiment of this application, the timing controller includes a transmitting module, and the data driver further includes a receiving module and a data register. The transmitting module is used to transmit the display signal to the data register through the receiving module.

[0011] The data register controls the target module to enter or exit the first preset mode based on the flag signal.

[0012] In one embodiment of this application, the receiving module and the sending module are connected via differential pair communication.

[0013] In one embodiment of this application, the target module includes at least one of a latch unit, a level conversion unit, a digital-to-analog conversion unit, and an output buffer unit.

[0014] In one embodiment of this application, the data driver further includes a first preset pin and a switching device connected between the data register and the target module;

[0015] When the flag signal is the first flag signal, the data register turns on the switching device through the first preset pin, so that the target module enters the first preset mode;

[0016] When the flag signal is the second flag signal, the data register turns off the switching device through the first preset pin, causing the target module to exit the first preset mode.

[0017] In one embodiment of this application, the timing controller is further configured to:

[0018] After the timing controller sends the first flag signal to the data driver, it controls the transmitting module to enter a sleep state; and

[0019] When the synchronization signal exits the blanking period, the transmitting module is controlled to exit the sleep state.

[0020] In one embodiment of this application, when the target module is in the first preset mode, the receiving module and the data register are in a working state.

[0021] In one embodiment of this application, the display module includes a plurality of data drivers, and the timing controller is connected to the plurality of data drivers respectively, for sending the display signal to the plurality of data drivers respectively.

[0022] In one embodiment of this application, the blanking period includes at least one of a horizontal blanking period and a vertical blanking period.

[0023] In accordance with the above-mentioned objectives of this application, embodiments of this application also provide a display terminal, including a housing and any of the display modules described in the present application, wherein the housing has an accommodating space and the display module is disposed within the accommodating space.

[0024] This application provides a display module and a display terminal. The display module includes a data driver and a timing controller. When the synchronization signal received by the timing controller enters the blanking period, the timing controller can use a first flag signal in the display signal to control the target module in the data driver to enter a first preset mode with lower power consumption, thereby reducing the power consumption of the data driver and improving the energy efficiency of the display module.

[0025] Other features and advantages of this application will be described in detail in the following detailed description section. Attached Figure Description

[0026] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0027] To gain a more complete understanding of this application and its beneficial effects, the following description will be provided in conjunction with the accompanying drawings, wherein the same reference numerals in the following description denote the same parts.

[0028] Figure 1 A schematic diagram illustrating the implementation of low-power modes provided in related technologies (rotated 90° counterclockwise);

[0029] Figure 2 This is a schematic diagram of a display module provided in an embodiment of this application;

[0030] Figure 3 This is another structural schematic diagram of the display module provided in the embodiments of this application;

[0031] Figure 4 This is another structural schematic diagram of the display module provided in the embodiments of this application;

[0032] Figure 5 This is another structural schematic diagram of the display module provided in the embodiments of this application. Detailed Implementation

[0033] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the protection scope of this application.

[0034] Based on the problems mentioned in the background technology, the China Standard Point-to-Point Interface (CSPI) protocol can be used to implement panel display in related technologies. The CSPI protocol proposes a variable power saving (VPS) power reduction implementation method. Specifically, refer to... Figure 1 During the blanking (BK) period of the vertical synchronization signal (Start Vertical, STV), the timing controller (TCON) pulls the VPS pin connected to the source driver (SD) low, that is... Figure 1 The wake signal level is pulled low. Upon receiving a low-level signal from the VPS pin, the data driver enters low-power mode. However, this VPS power reduction implementation requires an additional VPS pin between the timing controller and the data driver to control the entry and exit of low-power mode. Furthermore, after the data driver exits low-power mode, the timing controller needs to re-train the link, leading to increased communication latency and power consumption between the timing controller and the data driver.

[0035] In response, this application provides a display module and a display terminal to at least partially solve the above-mentioned problems.

[0036] According to the first aspect of this application, referring to Figures 2 to 5 A display module is provided. Specifically, the display module is used to implement image display functions and includes a data driver SD and a timing controller TCON, with the timing controller TCON connected to the data driver SD. The timing controller TCON in the display module performs timing management of display signals and is used to send display signals to the data driver SD. The display signals include data signals and flag signals. The data signals may include frame data, which contains information such as pixel data required to present the correct image on the display screen, and is used for the display of the control panel screen. The flag signals are used to instruct the target module in the data driver SD to enter a first preset mode.

[0037] The power consumption of the target module in the first preset mode is less than that in the second preset mode. This indicates that the first preset mode is a lower power consumption mode, also known as a low-power mode. A low-power mode is a pre-set operating mode. For example, in a low-power mode, the supply voltage of the target module is lower than a set voltage threshold, or the target module is directly shut down, thus reducing the power consumption of the target module below the set power consumption threshold. Shutting down the target module can be achieved by disconnecting the connection to the target module, thereby stopping the power supply to the target module.

[0038] It can be seen that the power supply voltage of the target module in the first preset mode is less than the power supply voltage of the target module in the second preset mode, or the target module is turned off when it is in the first preset mode but not turned off when it is in the second preset mode, so that the power consumption of the target module in the first preset mode can be less than the power consumption of the target module in the second preset mode.

[0039] Data signals and flag signals can be sent to the data driver SD at different times by the timing controller TCON, meaning that data signals and flag signals time-division multiplex the same data channel. For example, the data signal can be sent to the data driver SD by the timing controller TCON before the synchronization signal received by the timing controller TCON enters the blanking period. The flag signal can be sent to the data driver SD by the timing controller TCON when the synchronization signal received by the timing controller TCON is in the blanking period. "When the synchronization signal received by the timing controller TCON is in the blanking period" can be any moment when the synchronization signal received by the timing controller TCON is in the blanking period. The synchronization signal is used to ensure that all parts of the display terminal can work synchronously when displaying images. For example, the synchronization signal can ensure that the display of each row of pixels starts and ends at the correct time, and that the display of each frame can switch at the correct time.

[0040] The data driver SD is used to control the target module in the data driver SD to enter a first preset mode when the flag signal is the first flag signal. The first flag signal can be a signal that includes a first flag, such as the value 1. The flag signal is made the first flag signal by setting the value of a preset fixed position (e.g., a blank bit at a fixed position in the flag signal) to the first flag. The data driver SD can determine whether the flag signal is the first flag signal by reading the value of the preset fixed position.

[0041] The first flag signal is sent by the timing controller TCON to the data driver SD when the synchronization signal received by the timing controller TCON enters the blanking period. For example, when the synchronization signal enters the blanking period, the timing controller TCON detects this change in state and then generates the first flag signal according to preset logic. The first flag signal is then sent to the data driver SD. After receiving the first flag signal, the data driver SD controls the target module to enter a first preset mode. This allows the display module to enter the first preset mode during the blanking period when pixel data display is not required, thereby achieving energy saving.

[0042] "When the synchronization signal received by the timing controller TCON enters the blanking period" can be either the simultaneous entry of the synchronization signal received by the timing controller TCON into the blanking period, or a certain moment after the synchronization signal received by the timing controller TCON enters the blanking period. For example, since the synchronization signal received by the timing controller TCON transitions from a low level to a high level when entering the blanking period, "when the synchronization signal received by the timing controller TCON enters the blanking period" can be either the simultaneous entry of the synchronization signal from a low level to a high level, or a preset delay time after the entry of the synchronization signal from a low level to a high level. This preset delay time could be, for example, 1 millisecond after the entry of the synchronization signal from a low level to a high level.

[0043] As can be seen, in this embodiment, the timing controller TCON can control the target module in the data driver SD to enter a first preset mode when the synchronization signal received by the timing controller TCON enters the blanking period, using the first flag signal in the display signal. This reduces the power consumption of the data driver SD and improves the energy efficiency of the display module. For example, in some mobile devices (such as smartphones and tablets), this can effectively extend the battery life of the device. Furthermore, the target module in the data driver SD enters the first preset mode during the blanking period, so it does not affect the display function of the display module itself. In addition, compared to adding an extra VPS pin between the timing controller TCON and the data driver SD, this software control method using the first flag signal in the display signal reduces the number of pins between the timing controller TCON and the data driver SD, thereby saving hardware costs for the display module.

[0044] In some embodiments, refer to Figure 1The IC state is the status signal of the timing controller TCON, indicating whether control of the data driver SD is required. For example, in the Rest mode phase, the timing controller TCON does not need to control the data driver SD; in the Power on and ready phase, the timing controller TCON needs to send a command signal to the data driver SD to enable the data driver SD to perform preparatory work for screen display; in the Receive data and Output data phase, the timing controller TCON needs to receive data signals and send them to the data driver SD to enable the data driver SD to perform pixel control related to screen display.

[0045] In some embodiments, an exit strategy for a first preset mode of the target module in the data driver SD is also provided. Specifically, the data driver SD is further configured to control the target module in the data driver SD to exit the first preset mode when the flag signal is a second flag signal. The second flag signal may be a signal including a second flag, such as a value of 0. The flag signal is made to be the second flag signal by setting the value of a preset fixed position (e.g., a blank bit at a fixed position in the flag signal) to the second flag. The data driver SD can determine whether the flag signal is the second flag signal by reading the value of the preset fixed position. The second flag signal is sent to the data driver SD by the timing controller TCON when the synchronization signal received by the timing controller TCON exits the blanking period.

[0046] "When the synchronization signal received by the timing controller TCON exits the blanking period" can be either the simultaneous exit of the synchronization signal received by the timing controller TCON from the blanking period or a certain moment before the exit of the blanking period. For example, since the synchronization signal received by the timing controller TCON transitions from a high level to a low level when exiting the blanking period, "when the synchronization signal received by the timing controller TCON exits the blanking period" can be either the simultaneous exit of the high level of the synchronization signal from the low level or a preset advance time before the exit of the high level of the synchronization signal from the low level. This preset advance time could be, for example, 1 millisecond before the exit of the high level of the synchronization signal from the low level. That is, taking a blanking period of 12 milliseconds as an example, the preset advance time could be 11 milliseconds after the synchronization signal enters the blanking period.

[0047] In some embodiments, the timing controller TCON includes a transmitting module TX, and the data driver SD includes a receiving module RX and a data register DR. The transmitting module TX is connected to the receiving module RX, and the receiving module RX is connected to the data register DR. Thus, the transmitting module TX can send a display signal to the data register DR through the receiving module RX. When the display signal includes a flag signal, the data register DR can control the target module to enter or exit a first preset mode based on the flag signal. For example, the data register DR can control the target module to enter the first preset mode based on a first flag signal, or it can control the target module to exit the first preset mode based on a second flag signal.

[0048] In some embodiments, the receiving module RX and the transmitting module TX are connected via differential pair communication. That is, the receiving module RX is connected to the transmitting module TX via differential signal lines, and the display signal is transmitted between the transmitting module TX and the receiving module RX in the form of a differential signal. Based on the differential pair communication connection, the transmitting module TX needs to encode the display signal before transmitting it, and after receiving the encoded display signal, the transmitting module TX needs to decode it. For example, differential signal lines... Figures 2 to 5 The DataP and DataN signal lines transmit signals of equal magnitude but opposite polarity. In this transmission method, the differential signal can suppress common-mode noise interference and ensure accurate reception of the display signal.

[0049] In some embodiments, the target module includes at least one of a latch unit, a level shift unit (LS), a digital-to-analog conversion unit (DAC), and an output buffer unit (OB). For example Figures 2 to 4 As shown, the data driver SD includes a receiving module RX, a data register DR, a latch unit Latch, a level conversion unit LS, a digital-to-analog converter unit DAC, and an output buffer unit OB connected in sequence. The data register DR can simultaneously control the latch unit Latch, the level conversion unit LS, the digital-to-analog converter unit DAC, and the output buffer unit OB to enter or exit a first preset mode based on a flag signal.

[0050] In the display module, the latch unit is used to temporarily store data. During the display process, data needs to be processed and transmitted accurately at the appropriate time. The latch unit can temporarily store this data to ensure its stability and accuracy. For example, during the transmission of data signals from the timing controller TCON to the data driver SD, the data may arrive sequentially according to a certain timing sequence. The latch unit can lock this data at specific times to prevent data loss or errors, providing a stable data source for subsequent processing steps.

[0051] The level conversion unit LS is used to convert the input level signal. Since different circuit sections may require signals of different levels to operate normally, the input signal level in the display module may not be suitable for some units to use directly. For example, some data may be input as a low-level digital signal, but the subsequent digital-to-analog converter (DAC) and output buffer unit (OB) may require a higher-level signal to function properly. The level conversion unit LS can convert the low-level signal into a suitable high-level signal to meet the needs of the subsequent units.

[0052] The digital-to-analog converter (DAC) is used to convert digital signals into analog signals, because display terminals often require analog signals to drive the display. The data signals transmitted from the timing controller (TCON) are usually digital signals, and the DAC converts these digital signals into analog signals so that images can be correctly displayed on the display terminal.

[0053] The output buffer unit OB is used to buffer and optimize the signal to be output, ensuring stable signal output. For example, in a display module, the analog signal output from the digital-to-analog converter (DAC) may have some fluctuations or instability. The output buffer unit OB can buffer these signals and improve signal quality through optimization measures such as signal smoothing. The signal processed by the output buffer unit OB can be output more stably, thereby improving the display quality and stability.

[0054] In some embodiments, a first preset mode for the latch unit (Latch), level conversion unit (LS), digital-to-analog converter (DAC), and output buffer unit (OB) is described. Specifically, taking the latch unit as an example, during normal operation, the latch unit continuously latches input data, which consumes power. When entering the first preset mode, the latch unit can stop or reduce some unnecessary operations, thereby reducing power consumption. Taking the level conversion unit (LS) as an example, in the first preset mode, the level conversion unit (LS) may stop some unnecessary level conversion detection or adjustment operations. Taking the digital-to-analog converter (DAC) as an example, in the first preset mode, the DAC can pause or perform digital-to-analog conversion at a lower frequency. Taking the output buffer unit (OB) as an example, the output buffer unit (OB) can also reduce the buffer update frequency or pause some buffer management operations.

[0055] In some embodiments, the implementation method of the data register DR controlling the target module to enter or exit a first preset mode is described. Specifically, refer to Figure 2 The data driver SD also includes a first preset pin, which is a low-power pin LP, and a switching device connected between the data register DR and the target module. The switching device is connected to the low-power pin LP. (See reference...) Figure 3 When the flag signal is the first flag signal, the data register DR turns on the switching device through the low-power pin LP, causing the target module to enter the first preset mode. For example, the data register DR can turn on the switching device by pulling the level of the low-power pin LP low, thus disconnecting the connection between the data register DR and the target module, thereby causing the target module to enter the first preset mode. (Refer to...) Figure 4 When the flag signal is the second flag signal, the data register DR turns off the switching device through the low-power pin LP, causing the target module to exit the first preset mode. For example, the data register DR can turn off the switching device by pulling the level of the low-power pin LP high. In this way, the data register DR and the target module will be reconnected, thereby causing the target module to exit the first preset mode. (Refer to...) Figure 5 Taking a target module that includes a latch unit as an example, the data register DR turns on the switching device through the low-power pin LP, causing the latch unit to enter the first preset mode, or the data register DR turns off the switching device through the low-power pin LP, causing the latch unit to exit the first preset mode.

[0056] In some embodiments, a first preset mode for the timing controller TCON is also provided. Specifically, the timing controller TCON can also be used to: control the transmitting module TX to enter a sleep state after the timing controller TCON sends a first flag signal to the data driver SD; and control the transmitting module TX to exit the sleep state when the synchronization signal received by the timing controller TCON exits the blanking period. It can be seen that the transmitting module TX of the timing controller TCON is in a sleep state only when the synchronization signal received by the timing controller TCON is in the blanking period, thus not affecting the display function of the display module itself, thereby saving the power consumption of the timing controller TCON and further improving the energy efficiency of the display module.

[0057] In some embodiments, when the target module in the data driver SD is in a first preset mode, the receiving module RX and the data register DR in the data driver SD are in an active state. Since the receiving module RX remains active, after the target module exits the first preset mode, the transmitting module TX of the timing controller TCON does not need to re-train the receiving module RX with a link, and can directly send data signals to the receiving module RX. This avoids increased communication delay and power consumption between the timing controller TCON and the data driver SD, ensuring the stability of the display terminal's screen at high refresh rates. The goal of link training is to dynamically adjust link parameters so that the transmitting module TX and the receiving module RX achieve consistency in electrical characteristics (such as signal strength, clock synchronization, etc.) and protocol layers (such as rate, number of channels, etc.), thereby optimizing signal quality and reducing the bit error rate (BER).

[0058] Furthermore, communication between the data driver SD and the timing controller TCON can be implemented based on the CSPI protocol. In the CSPI protocol, the receiving module RX of the data driver SD and the transmitting module TX of the timing controller TCON are connected not only via differential pair communication but also via a link status pin. When the target module in the data driver SD is in the first preset mode, the link status pin of the receiving module RX is maintained at a high level to indicate that link training of the receiving module RX is complete. Thus, the transmitting module TX of the timing controller TCON can directly send data signals to the receiving module RX based on the high level of the link status pin, without retraining the receiving module RX.

[0059] In some embodiments, the display module includes multiple data drivers, and a timing controller is connected to the multiple data drivers respectively to send display signals to the multiple data drivers respectively, thereby controlling the target modules in the multiple data drivers to enter a first preset mode with lower power consumption, reducing the power consumption of the multiple data drivers, and further improving the energy efficiency of the display module.

[0060] In some embodiments, since the display terminal does not need to perform pixel data display operations during the horizontal blanking (HBlank) period and the vertical blanking (VBlank) period, the target module in the data driver SD enters the first preset mode during both the horizontal and vertical blanking periods without affecting the display function of the display module itself. Therefore, the aforementioned blanking period can be at least one of the horizontal blanking period and the vertical blanking period. That is, in this embodiment, the control of the target module in the data driver SD and the transmission module TX of the timing controller TCON is applicable to both the horizontal and vertical blanking periods, thereby further reducing the power consumption of the display module and improving its energy efficiency.

[0061] The horizontal blanking period refers to the additional processing required after each row of image data acquisition to prepare for the acquisition of the next row. The vertical blanking period refers to the preparatory work for screen switching (such as frame synchronization adjustments) required after each frame of image data acquisition.

[0062] According to a second aspect of this application, a display terminal is provided, including a housing and a display module as described in any embodiment. The housing has an accommodating space, and the display module is disposed within the accommodating space. The display terminal may be, for example, a television (TV), a monitor (MNT), a notebook computer (NB), or other display products. This display terminal possesses all the beneficial effects of the aforementioned display module, which will not be elaborated further herein.

[0063] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0064] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0065] The embodiments, implementation methods, and related technical features of this application can be combined and substituted for each other without conflict.

[0066] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of this application without departing from the technical solution of this application shall still fall within the scope of the technical solution of this application.

Claims

1. A display module, characterized in that, include: Data drive; as well as A timing controller, connected to the data driver, is used to send display signals to the data driver, the display signals including data signals and flag signals; The data driver is used to control the target module in the data driver to enter a first preset mode when the flag signal is the first flag signal. The power consumption of the target module in the first preset mode is less than the power consumption of the target module in the second preset mode. The first flag signal is sent by the timing controller to the data driver when the synchronization signal received by the timing controller enters the blanking period. The timing controller includes a transmitting module, and the data driver further includes a receiving module and a data register. The transmitting module is used to send the display signal to the data register through the receiving module. The data register controls the target module to enter or exit the first preset mode based on the flag signal; when the target module is in the first preset mode, the receiving module and the data register are in working state.

2. The display module according to claim 1, characterized in that, The data driver is also used to control the target module in the data driver to exit the first preset mode when the flag signal is the second flag signal, wherein the second flag signal is sent to the data driver by the timing controller when the synchronization signal exits the blanking period.

3. The display module according to claim 1, characterized in that, The receiving module and the sending module are connected via differential pair communication.

4. The display module according to claim 1, characterized in that, The target module includes at least one of a latch unit, a level conversion unit, a digital-to-analog conversion unit, and an output buffer unit.

5. The display module according to claim 1, characterized in that, The data driver also includes a first preset pin and a switching device connected between the data register and the target module; When the flag signal is the first flag signal, the data register turns on the switching device through the first preset pin, so that the target module enters the first preset mode; When the flag signal is the second flag signal, the data register turns off the switching device through the first preset pin, causing the target module to exit the first preset mode.

6. The display module according to claim 1, characterized in that, The timing controller is also used for: After the timing controller sends the first flag signal to the data driver, it controls the transmitting module to enter a sleep state; and When the synchronization signal exits the blanking period, the transmitting module is controlled to exit the sleep state.

7. The display module according to claim 1, characterized in that, When the target module is in the first preset mode, the receiving module and the data register are in working state.

8. The display module according to claim 1, characterized in that, The display module includes multiple data drivers, and the timing controller is connected to each of the multiple data drivers to send the display signal to each of the multiple data drivers.

9. The display module according to any one of claims 1 to 8, characterized in that, The closing period includes at least one of a horizontal closing period and a vertical closing period.

10. A display terminal, characterized in that, The device includes a housing and a display module as described in any one of claims 1 to 9, wherein the housing has an accommodating space and the display module is disposed within the accommodating space.

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