Voltage regulation driving circuit and method thereof, display panel, and display device

Abstract

The application discloses a voltage regulation driving circuit and method thereof, a display panel and a display device, and relates to the technical field of display. The circuit comprises a timing control module, which is used for determining a gray mapping voltage according to a current pixel brightness degree of an input video image and a preset gray scale sequence; a power module, which is connected with the timing control module and is used for adjusting an original output voltage of the input video image to the gray mapping voltage and then outputting the gray mapping voltage to a driving integrated module during a frame blanking period; and a signal processing module, which is connected with the timing control module and the power module respectively and is used for collecting the gray mapping voltage sent by the power module to the driving integrated module, generating a voltage compensation signal according to the gray mapping voltage and the original output voltage, and feeding back the voltage compensation signal to the timing control module to correct the gray mapping voltage of the driving integrated module, so as to ensure the image display quality and reduce the display power consumption.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a voltage regulation driving circuit and method thereof, a display panel, and a display device. Background Technology

[0002] With the continuous development of display technology, how to reduce the power consumption of LCD (Liquid Crystal Display) products has become an important development direction in the display field.

[0003] Currently, the power consumption of the output coupling (OC) terminals in LCD screens is mainly concentrated in four parts: TCON IC (Timing Controller Integrated Circuit), PMIC (Power Management Integrated Circuit), Driver IC (Driver Integrated Circuit), and Panel. Existing power reduction technologies are primarily limited to optimizing each individual component. For example, TCON ICs reduce power consumption by lowering core power, PMICs use multi-IC integration to achieve low power consumption, and Panels use new materials such as IGZO (Indium Gallium Zinc Oxide) and LTPS (Low Temperature Polycrystalline Silicon) to reduce power consumption. However, while these technologies can reduce power consumption to some extent, they only provide limited optimization for each individual integrated circuit and do not fundamentally solve the problem of high overall power consumption. In particular, in the Driver IC, high AVDD voltage leads to high power consumption, while lowering the AVDD voltage may cause a decrease in image display quality.

[0004] Therefore, while ensuring image display quality, how to reduce the power consumption of LCD products is a technical problem that urgently needs to be solved. Summary of the Invention

[0005] The main objective of this application is to provide a voltage regulation driving circuit and method thereof, a display panel and a display device, which aim to reduce the power consumption of LCD products while ensuring image display quality.

[0006] To achieve the above objectives, this application provides a voltage regulation drive circuit, the voltage regulation drive circuit comprising:

[0007] The voltage regulation drive circuit includes:

[0008] A timing control module is configured to determine the grayscale mapping voltage based on the current pixel brightness level of the input video image and a preset grayscale level sequence.

[0009] A power supply module is connected to the timing control module. The power supply module is configured to adjust the original output voltage of the input video image to the grayscale mapping voltage sent by the timing control module during the frame blanking period and then output it to the driver integration module.

[0010] The signal processing module is connected to both the timing control module and the power supply module. The signal processing module is configured to acquire the grayscale mapping voltage sent by the power supply module to the driver integration module, generate a voltage compensation signal based on the grayscale mapping voltage and the original output voltage, and feed it back to the timing control module to correct the grayscale mapping voltage of the driver integration module.

[0011] In one embodiment, the signal processing module includes:

[0012] A signal acquisition unit is connected to the transmission link from the power module to the driver integration module. The signal acquisition unit is configured to acquire the grayscale mapping voltage output by the power module to the driver integration module during the frame blanking period.

[0013] The control unit is connected to the signal acquisition unit and the timing control module respectively. The control unit is configured to determine the voltage compensation signal based on the grayscale mapping voltage and the original output voltage, and send the voltage compensation signal to the timing control module.

[0014] Furthermore, to achieve the above objectives, this application also provides a voltage regulation driving method, which is applied to the voltage regulation driving circuit described in any of the above claims, and the voltage regulation driving method includes:

[0015] After the timing control module determines the grayscale mapping voltage based on the current pixel brightness level of the input video image and the preset grayscale level sequence, the power supply module adjusts the original output voltage of the input video image to the grayscale mapping voltage sent by the timing control module during the frame blanking period and then outputs it to the driver integration module.

[0016] The signal processing module acquires the grayscale mapping voltage sent from the power supply module to the driver integration module, and determines a voltage compensation signal based on the grayscale mapping voltage and the original output voltage. The voltage compensation signal is then fed back to the timing control module to correct the grayscale mapping voltage of the driver integration module.

[0017] In one embodiment, the step of the timing control module determining the grayscale mapping voltage based on the current pixel brightness level of the input video image and a preset grayscale level sequence includes:

[0018] The timing control module obtains the current pixel brightness level of the input video image;

[0019] Based on the current pixel brightness level, a preset grayscale level sequence is traversed to obtain the grayscale mapping voltage.

[0020] In one embodiment, the step of obtaining the current pixel brightness level of the input video image through the timing control module includes:

[0021] The timing control module acquires the pixel distribution brightness of multiple consecutive frames of the input video image;

[0022] Detect whether the absolute difference in brightness between the pixel distribution brightness of two adjacent frames exceeds a preset brightness change threshold, and accumulate the number of consecutive frames in which the absolute difference in brightness does not exceed the brightness change threshold. Perform time filtering processing on the pixel distribution brightness of the consecutive frames to obtain the current pixel brightness level.

[0023] In one embodiment, the step of obtaining the grayscale mapping voltage by traversing a preset grayscale level sequence based on the current pixel brightness level includes:

[0024] The brightness level of the current pixel is traversed sequentially according to a preset gray level sequence, wherein the gray level sequence includes multiple preset gray levels arranged in descending order of gray level.

[0025] If the current pixel brightness level is within the brightness level range corresponding to the currently traversed preset gray level, then the currently traversed preset gray level is taken as the target gray level to which the current pixel brightness level belongs, and the preset voltage value mapped by the target gray level is taken as the gray level mapping voltage.

[0026] In one embodiment, the voltage compensation signal is determined based on the grayscale mapping voltage and the original output voltage;

[0027] Detect whether the voltage difference between the grayscale mapping voltage and the original output voltage is greater than zero;

[0028] If the voltage difference is greater than zero, then the voltage compensation signal is determined to be a negative voltage difference.

[0029] If the voltage difference is less than zero, then the voltage compensation signal is determined to be a positive voltage difference.

[0030] In one embodiment, the step of feeding back the voltage compensation signal to the timing control module to correct the grayscale mapping voltage of the drive integration module includes:

[0031] After the timing control module receives the voltage compensation signal fed back by the signal processing module, it superimposes the voltage compensation signal onto the grayscale mapping voltage of the drive integration module to obtain the corrected grayscale mapping voltage.

[0032] In addition, to achieve the above objectives, this application also provides a display panel, the display panel including a color filter substrate, a liquid crystal layer and an array substrate, the liquid crystal layer being disposed between the array substrate and the color filter substrate, and the array substrate including the voltage regulation driving circuit described in any of the above claims.

[0033] In addition, to achieve the above objectives, this application also provides a display device, which includes the display panel described above;

[0034] Alternatively, a memory, a processor, and a voltage regulation driver stored in the memory and executable on the processor, wherein the processor, when executing the voltage regulation driver, implements the steps of the voltage regulation driving method as described in any of the preceding claims.

[0035] The voltage regulation drive circuit described in this application, through the coordinated optimization of the timing control module, power supply module, signal processing module, and drive integration module, significantly reduces LCD driving power consumption while ensuring image display quality. Specifically, the timing control module, based on the current pixel brightness level of the input video image and a preset grayscale level sequence, can effectively match the grayscale mapping voltage corresponding to the current pixel brightness level. This achieves the goal of adaptively and dynamically adjusting the voltage according to the current pixel brightness level, avoiding the high power consumption problem caused by a single fixed high AVDD voltage, and fundamentally reducing the overall driving power consumption of the LCD. Next, during the frame blanking period, the power supply module switches the original output voltage of the input video image to the grayscale mapping voltage and outputs it to the drive integration module. This achieves voltage regulation during the non-display period between frames (i.e., the frame blanking period) to avoid the high power consumption caused by a single fixed high AVDD voltage. Image display interference caused by voltage fluctuations is mitigated by ensuring the stability of the grayscale mapping voltage input to the driver integrated module. At this time, the signal processing module synchronously acquires the grayscale mapping voltage output by the power supply module to the driver integrated module during the frame blanking period, and generates a voltage compensation signal based on the grayscale mapping voltage and the original output voltage, which is then fed back to the timing control module to correct the grayscale mapping voltage of the driver integrated module. This effectively eliminates voltage deviations caused by circuit losses or noise, prevents excessively high grayscale mapping voltage from causing power waste, and prevents excessively low grayscale mapping voltage from causing display abnormalities. Ultimately, this significantly reduces LCD driving power consumption while ensuring image display quality. Attached Figure Description

[0036] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0037] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0038] Figure 1 This is a structural block diagram of the first embodiment of the voltage regulation drive circuit of this application;

[0039] Figure 2 This is a schematic diagram of the driving process involved in the first embodiment of the voltage regulation driving circuit of this application;

[0040] Figure 3 This is a schematic diagram of the hardware architecture involved in the first embodiment of the voltage regulation drive circuit of this application;

[0041] Figure 4 This is a schematic diagram of the frame filtering period involved in the voltage regulation driving method of this application;

[0042] Figure 5 This is a schematic diagram of the structure of the display device involved in the embodiments of this application.

[0043] Explanation of icon numbers:

[0044] 10. Timing control module; 20. Power supply module; 30. Driver integration module; 40. Signal processing module; 41. Signal acquisition unit; 42. Control unit.

[0045] The realization of the purpose, functional features and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0046] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0047] It should be noted that if the embodiments of this application involve directional indicators (such as up, down, left, right, front, back, etc.), the directional indicators are only used to explain the relative positional relationship and movement of the components in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indicators will also change accordingly.

[0048] Furthermore, if the embodiments of this application involve descriptions such as "first" or "second," these descriptions are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, features defined with "first" or "second" may explicitly or implicitly include at least one of those features. Additionally, the technical solutions of various embodiments can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. If the combination of technical solutions is contradictory or impossible to implement, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection claimed in this application.

[0049] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application.

[0050] With the continuous development of display technology, how to reduce the power consumption of LCD (Liquid Crystal Display) products has become an important development direction in the display field.

[0051] Currently, the power consumption of the output coupling (OC) terminals in LCD screens is mainly concentrated in four parts: TCON IC (Timing Controller Integrated Circuit), PMIC (Power Management Integrated Circuit), Driver IC (Driver Integrated Circuit), and Panel. Existing power reduction technologies are primarily limited to optimizing each individual component. For example, TCONIC reduces power consumption by lowering core power, PMIC uses multi-IC integration to achieve low power consumption, and the Panel uses new materials such as IGZO (Indium Gallium Zinc Oxide) and LTPS (Low Temperature Polycrystalline Silicon) to reduce power consumption. However, while these technologies can reduce power consumption to some extent, they only provide limited optimization for each individual integrated circuit and do not fundamentally solve the problem of high overall power consumption. In particular, in the Driver IC, high AVDD voltage leads to high power consumption, while lowering the AVDD voltage may cause a decrease in image display quality.

[0052] Therefore, while ensuring image display quality, how to reduce the power consumption of LCD products is a technical problem that urgently needs to be solved.

[0053] To address the display defects of existing LCD display technologies, this application provides a voltage regulation driving circuit and method thereof, a display panel, and a display device.

[0054] This application provides a voltage regulation drive circuit, referring to... Figure 1 As shown, Figure 1 This is a structural block diagram of a first embodiment of the voltage regulation drive circuit of this application. The voltage regulation drive circuit includes:

[0055] The timing control module 10 is configured to determine the grayscale mapping voltage based on the current pixel brightness level of the input video image and a preset grayscale level sequence.

[0056] In this embodiment, refer to Figures 1 to 2 After the video signal of the input video image is input to the timing control module 10, the timing control module 10 collects the pixel data of each frame of the input video image to calculate the current pixel brightness level. This current pixel brightness level is used to characterize the overall pixel brightness features of the input video image. Since the preset gray level sequence is composed of multiple preset gray level sequences arranged from high to low, after determining the current pixel brightness level of the input video image, a preset gray level matching the current pixel brightness level can be found from the preset gray level sequence. The preset voltage value mapped by the matched preset gray level is used as the gray level mapping voltage corresponding to the current pixel brightness level. This realizes adaptive dynamic voltage adjustment based on the current pixel brightness level, effectively avoiding the high power consumption problem caused by the traditional single fixed high AVDD voltage design, thereby significantly reducing the overall driving power consumption of the LCD.

[0057] It should be noted that the timing control module 10 can be understood as a TCON IC (Timing Controller Integrated Circuit), which integrates at least the following: Figure 3 The image detection module and the image AVDD controller module are connected via communication. The image detection module has a pre-set grayscale level sequence, which includes multiple preset grayscale levels arranged from high to low, and a preset voltage value mapped to each preset grayscale level. The expression for this grayscale level sequence is as follows:

[0058] AVDD0[[L(01)] [L(02)] [L(03)]…[L(0n)]]

[0059] AVDD1[[L(11)] [L(12)] [L(13)]…[L(1n)]]

[0060] AVDD2[[L(21)] [L(22)] [L(23)]…[L(2n)]]

[0061] AVDD3[[L(31)] [L(32)] [L(33)]…[L(3n)]]

[0062] AVDD4[[L(41)] [L(42)] [L(43)]…[L(4n)]]

[0063] AVDD5[[L(51)] [L(52)] [L(53)]…[L(5n)]]

[0064] That is, the grayscale level sequence can be set with 6 preset grayscale levels arranged from high to low, and the number of preset grayscale levels can also be customized according to application requirements. This application does not impose any restrictions here. Specifically, each preset voltage value is used to mark the corresponding preset grayscale level. For example, the preset grayscale level corresponding to voltage AVDD0 is marked as AVDD0 level. The brightness range of AVDD0 level is [[L(01)][L(02)][L(03)]…[L(0n)]], where [L(01)], [L(02)], [L(03)], [L(03)], ..., and ...[L(0n)] respectively represent the grayscale values ​​of this brightness range. In addition, AVDD0 level > AVDD1 level > AVDD2 level > AVDD3 level > AVDD4 level > AVDD5 level, that is, the highest grayscale brightness is AVDD0 level and the lowest grayscale brightness is AVDD5 level.

[0065] In a specific embodiment, refer to Figures 2 to 3 The image detection module first acquires pixel data frame by frame from each input video image; then, following a time sequence (i.e., chronological order), the module converts the pixel data of each pixel in each frame of the input video image into its corresponding brightness grayscale value; specifically, assuming... Figure 2The checkerboard-shaped image shown is the input video image. Each rectangle in this input video image represents a pixel. By accumulating the product of the red pixel value and its weight ratio, the product of the green pixel value and its weight ratio, and the product of the blue pixel value and its weight ratio in the second row and second column, the brightness grayscale value of the pixel in the second row and second column can be accurately obtained as 32. Next, the grayscale average of all brightness grayscale values ​​in each frame is calculated, and this grayscale average is used as the pixel distribution brightness of that frame. Subsequently, the image detection module performs time filtering based on the pixel distribution brightness of all frames, which can accurately obtain the current pixel brightness level reflecting the grayscale type of the input image. Next, through the communication connection between the image detection module and the image AVDD controller module, the image detection module transmits the current pixel brightness level reflecting the grayscale type of the input image to the image AVDD controller module. Subsequently, the image AVDD controller module queries the preset grayscale level sequence to accurately match the preset grayscale level corresponding to the current pixel brightness level, and uses the preset voltage value mapped by the matched preset grayscale level as the grayscale mapping voltage corresponding to the current pixel brightness level. This achieves adaptive dynamic voltage adjustment based on the current pixel brightness level, effectively avoiding the high power consumption problem caused by the traditional single fixed high AVDD voltage design, thereby significantly reducing the overall driving power consumption of the LCD.

[0066] A power module 20 is connected to the timing control module 10. The power module 20 is configured to adjust the original output voltage of the input video image to the grayscale mapping voltage sent by the timing control module 10 during the frame blanking period and then output it to the driver integration module 30.

[0067] In this embodiment, the power module 20 provided in this application stores the raw output voltage required to output to the driver integration module 30 to display the input video image of the current frame. For example, refer to... Figure 3 The timing control module 10 establishes a connection with the power supply module 20 based on the IICW / R communication method. That is, the timing control module 10 sends the corresponding preset voltage value (i.e., grayscale mapping voltage) to the power supply module 20 via the IICW / R communication method according to the matched preset grayscale level. Upon receiving the grayscale mapping voltage from the timing control module 10, the power supply module 20 immediately triggers a preset voltage adjustment command, switching the original output voltage to the grayscale mapping voltage (i.e., grayscale mapping voltage) during the non-display period between the current frame and the next frame (i.e., the frame blanking period). Figure 2 The V_avdd shown is transmitted to the driver integration module 30, which realizes voltage regulation during non-display periods between frames to avoid screen flicker caused by voltage fluctuations, thereby improving the image display quality of the display device.

[0068] The signal processing module 40 is connected to the timing control module 10 and the power supply module 20 respectively. The signal processing module 40 is configured to acquire the grayscale mapping voltage sent by the power supply module 20 to the drive integration module 30, and generate a voltage compensation signal based on the grayscale mapping voltage and the original output voltage, and feed it back to the timing control module 10 to correct the grayscale mapping voltage of the drive integration module 30.

[0069] In this embodiment, refer to Figure 1 The signal processing module 40 and the power supply module 20 provide a transmission link for the grayscale mapping voltage to the driver integrated module 30. The signal processing module 40 synchronously acquires the grayscale mapping voltage sent by the power supply module 20 to the driver integrated module 30 during the frame blanking period. Next, a voltage compensation signal is generated based on the grayscale mapping voltage and the original output voltage and fed back to the timing control module 10 to correct the grayscale mapping voltage of the driver integrated module 30. This effectively eliminates voltage deviation caused by circuit loss or noise, prevents excessively high grayscale mapping voltage from causing power waste, and prevents excessively low grayscale mapping voltage from causing display abnormalities. Ultimately, this significantly reduces LCD driving power consumption while ensuring image display quality.

[0070] In a specific embodiment, refer to Figure 2 The signal processing module 40 establishes a connection with the timing control module 10 based on the IIC W / R communication method. The timing control module 10 establishes a connection with the power supply module 20 based on the IIC W / R communication method. After the power supply module 20 feeds back the original output voltage required to display the input video image of the current frame to the timing control module 10 through the IIC W / R communication method, the timing control module 10 sends the original output voltage to the signal processing module 40 through the IIC W / R communication method so that the signal processing module 40 can store the original output voltage.

[0071] Furthermore, in some feasible embodiments, the signal processing module 40 includes:

[0072] The signal acquisition unit 41 is connected to the transmission link from the power module 20 to the drive integration module 30. The signal acquisition unit 41 is configured to acquire the grayscale mapping voltage output by the power module 20 to the drive integration module 30 during the frame blanking period.

[0073] In this embodiment, refer to Figure 2The signal acquisition unit 41 in the signal processing module 40 is connected to the power supply module 20 to provide grayscale mapping voltage to the driver integrated module 30 via a transmission link. Specifically, when the power supply module 20 switches the original output voltage to grayscale mapping voltage and transmits it to the driver integrated module 30 during the frame blanking period, the signal acquisition unit 41 acquires the grayscale mapping voltage transmitted from the power supply module 20 to the driver integrated module 30 during the frame blanking period through its own ADC sampling channel.

[0074] It should be noted that the signal acquisition unit 41 can be understood as an analog-to-digital converter.

[0075] Control unit 42 is connected to signal acquisition unit 41 and timing control module 10 respectively. Control unit 42 is configured to determine voltage compensation signal based on grayscale mapping voltage and original output voltage, and send voltage compensation signal to timing control module 10.

[0076] In this embodiment, refer to Figure 2 Based on the communication connection between the control unit 42 and the signal acquisition unit 41, the control unit 42 can receive the grayscale mapping voltage sent by the signal acquisition unit 41; based on the connection established between the control unit 42 and the timing control module 10 using the IIC W / R communication method, the control unit 42 can also receive the original output voltage required by the power module 20 to be output to the drive integration module 30 to display the input video image of the current frame, fed back by the timing control module 10; next, the control unit 42 integrates... Figure 3 The image quality compensation module shown determines the voltage compensation signal by comparing the grayscale mapping voltage and the original output voltage, and sends the voltage compensation signal to the timing control module 10 through the IIC W / R communication method. The timing control module 10 then performs secondary compensation on the grayscale mapping voltage of the drive integration module 30, preventing excessively high grayscale mapping voltage from causing power waste or excessively low grayscale mapping voltage from causing display abnormalities. Ultimately, it achieves significant reduction in LCD drive power consumption while ensuring image display quality.

[0077] In summary, the voltage regulation drive circuit configured in this application, through the coordinated optimization of the timing control module 10, power supply module 20, signal processing module 40, and drive integration module 30, significantly reduces LCD driving power consumption while ensuring image display quality. Specifically, the timing control module 10, based on the current pixel brightness level of the input video image and a preset grayscale level sequence, can effectively match the grayscale mapping voltage corresponding to the current pixel brightness level, achieving the purpose of adaptively and dynamically adjusting the voltage according to the current pixel brightness level, avoiding the high power consumption problem caused by a single fixed high AVDD voltage, and fundamentally reducing the overall driving power consumption of the LCD. Next, during the frame blanking period, the power supply module 20 switches the original output voltage of the input video image to the grayscale mapping voltage and outputs it to the drive integration module 30, realizing voltage regulation during the non-display period between frames (i.e., the frame blanking period) to avoid voltage fluctuations. To prevent image display interference caused by motion, the stability of the grayscale mapping voltage input to the drive integration module 30 is ensured. At this time, the signal processing module 40 synchronously acquires the grayscale mapping voltage output by the power supply module 20 to the drive integration module 30 during the frame blanking period, and generates a voltage compensation signal based on the grayscale mapping voltage and the original output voltage, and feeds it back to the timing control module 10 to correct the grayscale mapping voltage of the drive integration module 30. This effectively eliminates voltage deviation caused by circuit loss or noise, prevents excessively high grayscale mapping voltage from causing power waste, or excessively low grayscale mapping voltage from causing display abnormalities, and ultimately achieves significant reduction in LCD driving power consumption while ensuring image display quality.

[0078] Furthermore, based on the first embodiment of the voltage regulation drive circuit of this application, a second embodiment of the voltage regulation drive method of this application is proposed, referring to... Figure 3 , Figure 3 This is a schematic flowchart of the second embodiment of the voltage regulation driving method of this application.

[0079] The voltage regulation driving method of this application is applied to the voltage regulation driving circuit of any of the above claims. The voltage regulation driving method of this application is executed by a display device applied to the voltage regulation driving circuit. The voltage regulation driving method of this application includes the following implementation steps S10 to S20.

[0080] Step S10: After the timing control module 10 determines the grayscale mapping voltage based on the current pixel brightness level of the input video image and the preset grayscale level sequence, the power supply module 20 adjusts the original output voltage of the input video image to the grayscale mapping voltage sent by the timing control module 10 during the frame blanking period and then outputs it to the driver integration module 30.

[0081] In this embodiment, refer to Figures 1 to 2After the video signal of the input video image is input to the timing control module 10, the timing control module 10 collects the pixel data of each frame of the input video image to calculate the current pixel brightness level. This current pixel brightness level is used to characterize the overall pixel brightness features of the input video image. Since the preset gray level sequence is composed of multiple preset gray level sequences arranged from high to low, after determining the current pixel brightness level of the input video image, a preset gray level matching the current pixel brightness level can be found from the preset gray level sequence. The preset voltage value mapped by the matched preset gray level is used as the gray level mapping voltage corresponding to the current pixel brightness level. This realizes adaptive dynamic voltage adjustment based on the current pixel brightness level, effectively avoiding the high power consumption problem caused by the traditional single fixed high AVDD voltage design, thereby significantly reducing the overall driving power consumption of the LCD. Next, since the timing control module 10 establishes a connection with the power supply module 20 based on the IIC W / R communication method, the timing control module 10 sends the corresponding preset voltage value (i.e., grayscale mapping voltage) to the power supply module 20 through the IIC W / R communication method according to the matched preset grayscale level. At this time, after receiving the grayscale mapping voltage sent by the timing control module 10, the power supply module 20 immediately triggers the preset voltage adjustment command, and switches the original output voltage of the input video image to the grayscale mapping voltage (i.e., grayscale mapping voltage) during the non-display period between the current frame and the next frame (i.e., the frame blanking period). Figure 2 The V_avdd shown is transmitted to the driver integration module 30, which realizes voltage regulation during non-display periods between frames to avoid screen flicker caused by voltage fluctuations, thereby improving the image display quality of the display device.

[0082] Step S20: The signal processing module 40 acquires the grayscale mapping voltage sent by the power supply module 20 to the drive integration module 30, and determines a voltage compensation signal based on the grayscale mapping voltage and the original output voltage. The voltage compensation signal is then fed back to the timing control module 10 to correct the grayscale mapping voltage of the drive integration module 30.

[0083] In this embodiment, refer to Figure 1 The signal processing module 40 and the power supply module 20 provide a transmission link for the grayscale mapping voltage to the driver integrated module 30. The signal processing module 40 synchronously acquires the grayscale mapping voltage sent by the power supply module 20 to the driver integrated module 30 during the frame blanking period. Next, a voltage compensation signal is generated based on the grayscale mapping voltage and the original output voltage and fed back to the timing control module 10 to correct the grayscale mapping voltage of the driver integrated module 30. This effectively eliminates voltage deviation caused by circuit loss or noise, prevents excessively high grayscale mapping voltage from causing power waste, and prevents excessively low grayscale mapping voltage from causing display abnormalities. Ultimately, this significantly reduces LCD driving power consumption while ensuring image display quality.

[0084] Furthermore, in some feasible embodiments, the above step S10: the timing control module 10 determines the grayscale mapping voltage based on the current pixel brightness level of the input video image and the preset grayscale level sequence, may also include the following implementation steps S101 to S102.

[0085] Step S101: Obtain the current pixel brightness level of the input video image through the timing control module 10;

[0086] Step S102: Based on the current pixel brightness level, traverse the preset grayscale level sequence to obtain the grayscale mapping voltage.

[0087] In this embodiment, after the timing control module 10 obtains the current pixel brightness level of the input video image, it traverses the preset gray level sequence according to the current pixel brightness level to determine the preset voltage value corresponding to the target gray level to which the current pixel brightness level belongs as the gray level mapping voltage. This realizes adaptive dynamic voltage adjustment based on the current pixel brightness level, effectively avoiding the high power consumption problem caused by the traditional single fixed high AVDD voltage design, thereby significantly reducing the overall driving power consumption of the LCD.

[0088] In a specific embodiment, if the current pixel brightness level is [L(23)], the expression for determining the grayscale mapping voltage based on the current pixel brightness level by traversing the preset grayscale level sequence is as follows:

[0089]

[0090] Specifically, iterate through the brightness level intervals [[L(01)] [L(02)] [L(03)]…[L(0n)]] corresponding to AVDD0 level to see if the current pixel brightness level exists [L(23)]. If the brightness level interval [L(23)] corresponding to AVDD0 level does not exist, then continue iterating through the brightness level intervals [[L(11)] [L(12)] [L(13)]…[L(1n)]] corresponding to AVDD1 level to see if the current pixel brightness level exists [L(23)]. If the brightness level interval [L(23)] corresponding to AVDD1 level does not exist, then continue iterating through the brightness level intervals [[L(21)] [L(22)] [L(23)]…[L(2n)]] corresponding to AVDD2 level to see if the current pixel brightness level exists [L(23)]. Since the brightness level interval [[L(21)] [L(22)] corresponding to AVDD2 level…[L(2n)]…[L(21)]…[L(22)]…[L(2n)]…[L(22)]…[L(23)]…[L(2n)]…[L(21 ... If [L(23)]…[L(2n)]] exists, then the grayscale mapping voltage represented by AVDD(IP) is determined to be the voltage preset value AVDD3.

[0091] Furthermore, in some other feasible embodiments, the above step S101: obtaining the current pixel brightness level of the input video image through the timing control module 10 may also include the following implementation steps S1011 to S1012.

[0092] Step S1011: Acquire the pixel distribution brightness of multiple consecutive frames of the input video image through the timing control module 10.

[0093] In this embodiment, the timing control module 10 acquires the pixel distribution brightness of multiple consecutive frames of the input video image. Specifically, five consecutive frames of the input video image constitute one frame filtering cycle. Figure 4 Frames 1 to 5 shown represent the first frame filtering period. Figure 4 The frames n to n+4 shown represent the nth frame filtering period. This frame filtering period setting method is based on the dynamic characteristics of the video signal and actual processing requirements. It can capture short-term changes in video content without causing processing delays due to excessively long periods, thus avoiding impacting the system's real-time performance. Figure 4 Taking the frame filtering period of frames 1 to 5 as an example, the timing control module 10 collects the pixel data of the input video images from frames 1 to 5 frame by frame, and converts the data of each pixel in each frame image into the corresponding brightness gray value, so as to calculate the gray average value of all brightness gray values ​​in each frame image, and uses the gray average value of each frame image as the pixel distribution brightness of the corresponding frame.

[0094] It should be noted that the frame filtering period can be customized according to the user's needs, and this application does not impose any restrictions on it.

[0095] Step S1012: Detect whether the absolute difference in brightness between the pixel distribution brightness of two adjacent frames exceeds a preset brightness change threshold, and accumulate the number of consecutive frames in which the absolute difference in brightness does not exceed the brightness change threshold. Perform time filtering processing on the pixel distribution brightness of the consecutive frames to obtain the current pixel brightness level.

[0096] In this embodiment, the absolute difference in brightness between the pixel distribution brightness of two adjacent frames is calculated, and this absolute difference is compared with a preset brightness change threshold. When the absolute difference exceeds the preset brightness change threshold, abnormal brightness changes can be detected in a timely manner, providing an accurate basis for subsequent processing measures. Next, the number of consecutive frames where the absolute difference in brightness is less than the brightness change threshold is accumulated, thereby comprehensively considering the brightness stability of the input video image over a period of time, effectively filtering out brief, non-continuous brightness fluctuation interference. Then, the pixel distribution brightness of the accumulated consecutive frames is subjected to time filtering processing, further smoothing the brightness data, removing the influence of noise and local brightness anomalies, and obtaining a more stable and accurate current pixel brightness level, thus more realistically reflecting the overall brightness state of the input video image at the current moment.

[0097] In a specific embodiment, assuming the pixel distribution brightness of the input video image in frame 1 is L1, the pixel distribution brightness of the input video image in frame 2 is L2, the pixel distribution brightness of the input video image in frame 3 is L3, the pixel distribution brightness of the input video image in frame 4 is L4, and the pixel distribution brightness of the input video image in frame 5 is L5; if |L1-L2|<Lth, |L2-L3|<Lth, |L3-L4|<Lth, and |L4-L5|>Lth, then the cumulative number of consecutive frames that satisfy the absolute difference in brightness being less than the brightness change threshold Lth is frames 1 to 4, thus filtering out the brightness change L5; next, by averaging the pixel distribution brightness corresponding to frames 1 to 4, the current pixel brightness level of the input video image can be obtained.

[0098] Furthermore, in some feasible embodiments, the above step S102: obtaining the grayscale mapping voltage by traversing a preset grayscale level sequence according to the current pixel brightness level, may also include the following implementation steps S1021 to S1022.

[0099] Step S1021: The brightness level of the current pixel is traversed sequentially according to a preset gray level sequence, wherein the gray level sequence includes multiple preset gray levels arranged in descending order of gray level.

[0100] In this embodiment, the brightness of the current pixel is traversed sequentially according to a preset gray level sequence (multiple preset gray levels arranged in descending order of gray level). This allows for a comprehensive and orderly check of the matching possibility between the current pixel brightness and each gray level. This traversal method ensures that no potential gray level attribution is missed, providing a complete search range for accurately determining the target gray level.

[0101] Step S1022: If the current pixel brightness level is within the brightness level range corresponding to the currently traversed preset gray level, then the currently traversed preset gray level is taken as the target gray level to which the current pixel brightness level belongs, and the preset voltage value mapped by the target gray level is taken as the gray level mapping voltage.

[0102] In this embodiment, if the current pixel brightness level is within the brightness level range corresponding to the currently traversed preset gray level, then the currently traversed preset gray level is taken as the target gray level to which the current pixel brightness level belongs, and the preset voltage value mapped by the target gray level is taken as the gray level mapping voltage. This realizes adaptive dynamic voltage adjustment based on the current pixel brightness level, effectively avoiding the high power consumption problem caused by the traditional single fixed high AVDD voltage design, thereby significantly reducing the overall driving power consumption of the LCD.

[0103] Furthermore, in some other feasible embodiments, the above step S20: determining the voltage compensation signal based on the grayscale mapping voltage and the original output voltage may also include the following implementation steps S201 to S203.

[0104] Step S201: Detect whether the voltage difference between the grayscale mapping voltage and the original output voltage is greater than zero.

[0105] In this embodiment, detecting whether the voltage difference between the grayscale mapping voltage and the original output voltage is greater than zero can accurately determine the voltage difference between the two, providing a clear basis for determining the direction of the voltage compensation signal.

[0106] Step S202: If the voltage difference is greater than zero, then the voltage compensation signal is determined to be a negative voltage difference.

[0107] In this embodiment, if the voltage difference is greater than zero, the voltage compensation signal is determined to be a negative voltage difference. For example, if the voltage difference ΔV is greater than zero (i.e., the voltage difference ΔV is positive), the voltage compensation signal is determined to be a negative voltage difference, which is the opposite of ΔV - ΔV.

[0108] In a specific embodiment,

[0109] AVDD(ΔIP1) = [+VD(01),+VD(02),+VD(03),……,+VD(0n)]; AVDD(ΔIP2) = [-VD(01),-VD(02),-VD(03),……,-VD(0n)], where AVDD(ΔIP1) is set to store the voltage difference between the grayscale mapping voltage and the original output voltage, and AVDD(ΔIP2) stores the compensation value corresponding to each voltage difference. For example, if the voltage difference ΔV between the grayscale mapping voltage and the original output voltage is +VD(01), then the compensation value corresponding to +VD(01) can be found in AVDD(ΔIP2) as -VD(01).

[0110] Step S203: If the voltage difference is less than zero, then the voltage compensation signal is determined to be a positive voltage difference.

[0111] In this embodiment, if the voltage difference is less than zero, the voltage compensation signal is determined to be a positive voltage difference. For example, if the voltage difference is less than zero (i.e., the voltage difference ΔV is negative), the voltage compensation signal is determined to be a positive voltage difference, which is the opposite of ΔV + ΔV.

[0112] In summary, this application achieves compensation with a voltage signal in the opposite direction based on the actual voltage difference by comparing the voltage difference between the grayscale mapping voltage and the original output voltage. This ensures the accuracy of the grayscale mapping voltage output, prevents excessively high grayscale mapping voltage from causing power waste, and prevents excessively low grayscale mapping voltage from causing display abnormalities. Ultimately, it significantly reduces LCD driving power consumption while ensuring image display quality.

[0113] Furthermore, in some feasible embodiments, the above step S20: feeding back the voltage compensation signal to the timing control module 10 to correct the grayscale mapping voltage of the drive integration module 30 may also include the following implementation step A10.

[0114] Step A10: After the timing control module 10 receives the voltage compensation signal fed back by the signal processing module 40, it superimposes the voltage compensation signal onto the grayscale mapping voltage of the drive integration module 30 to obtain the corrected grayscale mapping voltage.

[0115] In this embodiment, after the timing control module 10 receives the voltage compensation signal fed back by the signal processing module 40, it superimposes the voltage compensation signal onto the grayscale mapping voltage of the drive integration module 30 to obtain the corrected grayscale mapping voltage. This achieves the purpose of secondary compensation of the grayscale mapping voltage of the drive integration module 30, preventing excessively high grayscale mapping voltage from causing power waste or excessively low grayscale mapping voltage from causing display abnormalities. Ultimately, it achieves significant reduction in LCD driving power consumption while ensuring image display quality.

[0116] In addition, this application also provides a display panel, the display panel including a color filter substrate, a liquid crystal layer and an array substrate, the liquid crystal layer being disposed between the array substrate and the color filter substrate, and the array substrate including a voltage regulation driving circuit of any of the above.

[0117] In addition, this application also provides a display device. Please refer to... Figure 5 , Figure 5 This is a schematic diagram of the structure of a display device involved in an embodiment of this application. Specifically, the display device in this embodiment may be a device that uses a locally operating voltage regulation driving method.

[0118] like Figure 5 As shown, the display device in this embodiment may include: a display panel or processor 1001, such as a CPU, a communication bus 1002, a user interface 1003, a network interface 1004, and a memory 1005. The communication bus 1002 is used to enable communication between these components. The user interface 1003 may include a display screen and an input unit such as a keyboard; optionally, the user interface 1003 may also include a standard wired interface or a wireless interface. The network interface 1004 may optionally include a standard wired interface or a wireless interface (such as a Wi-Fi interface).

[0119] The memory 1005 is disposed on the main body of the display device. The memory 1005 stores a program that performs corresponding operations when executed by the processor 1001. The memory 1005 is also used to store parameters used by the display device. The memory 1005 can be a high-speed RAM or a stable, non-volatile memory, such as a disk storage device. Optionally, the memory 1005 can also be a storage device independent of the aforementioned processor 1001.

[0120] Those skilled in the art will understand that Figure 5 The display device structure shown does not constitute a limitation on the display device and may include more or fewer components than shown, or combine certain components, or have different component arrangements.

[0121] like Figure 5 As shown, the memory 1005, which serves as a storage medium, may include an operating system, a network communication module, a user interface module, and a voltage regulation driver.

[0122] exist Figure 5 In the display device shown, the processor 1001 can be used to call the voltage regulation driver stored in the memory 1005 and execute the steps of the voltage regulation driver method as described above.

[0123] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or system that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or system. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or system that includes that element.

[0124] The sequence numbers of the embodiments in this application are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0125] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) as described above, and includes several instructions to cause a display device (which may be a mobile phone, computer, server, or network device, etc.) to execute the methods described in the various embodiments of this application.

[0126] The above are merely preferred embodiments of this application and do not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A voltage regulation drive circuit, characterized in that, The voltage regulation drive circuit includes: A timing control module is configured to acquire pixel distribution brightness of multiple consecutive frames of an input video image; detect whether the absolute difference in brightness between two adjacent frames exceeds a preset brightness change threshold; accumulate the number of consecutive frames where the absolute difference in brightness does not exceed the brightness change threshold; perform time filtering on the pixel distribution brightness of the consecutive frames to obtain the current pixel brightness level; and determine the grayscale mapping voltage based on the current pixel brightness level and a preset grayscale level sequence. The timing control module includes an image detection module and an image AVDD controller module connected via communication. The image detection module is used to accumulate the product data of the red pixel value and the red weight ratio, the product data of the green pixel value and the green weight ratio, and the product data of the blue pixel value and the blue weight ratio for each pixel in the input video image to obtain the brightness grayscale value of the pixel, and to calculate the average of the brightness grayscale values ​​of all pixels in the input video image to obtain the pixel distribution brightness of the input video image; the image AVDD controller module is used to traverse a preset grayscale level sequence based on the current pixel brightness level sent by the image detection module to determine the grayscale mapping voltage; A power supply module is connected to the timing control module. The power supply module is configured to adjust the original output voltage of the input video image to the grayscale mapping voltage sent by the timing control module during the frame blanking period and then output it to the driver integration module. A signal processing module is provided, which is connected to both the timing control module and the power supply module. The signal processing module includes a signal acquisition unit and a control unit. The signal acquisition unit is connected to the transmission link from the power supply module to the driver integration module. The control unit is connected to both the signal acquisition unit and the timing control module. The signal processing module is configured to acquire the grayscale mapping voltage output by the power supply module to the driver integration module during the frame blanking period through the signal acquisition unit, and control the control unit to generate a voltage compensation signal based on the grayscale mapping voltage and the original output voltage. The voltage compensation signal is then fed back to the timing control module to correct the grayscale mapping voltage of the driver integration module.

2. A voltage regulation driving method, characterized in that, The voltage regulation driving method is applied to the voltage regulation driving circuit as described in claim 1, and the voltage regulation driving method includes: The timing control module acquires pixel distribution brightness of multiple consecutive frames of the input video image; detects whether the absolute difference in brightness between two adjacent frames exceeds a preset brightness change threshold, accumulates the number of consecutive frames where the absolute difference in brightness does not exceed the brightness change threshold, performs time filtering on the pixel distribution brightness of the consecutive frames to obtain the current pixel brightness level, and determines the grayscale mapping voltage based on the current pixel brightness level and a preset grayscale level sequence; wherein, the timing control module includes an image detection module and an image AVDD controller module connected by communication, the image detection module is used to accumulate the product data of red pixel value and red weight ratio, green pixel value and green weight ratio, and blue pixel value and blue weight ratio for each pixel in the input video image to obtain the brightness grayscale value of the pixel, and calculates the average of the brightness grayscale values ​​of all pixels in the input video image to obtain the pixel distribution brightness of the input video image; the image AVDD controller module is used to traverse the preset grayscale level sequence based on the current pixel brightness level sent by the image detection module to determine the grayscale mapping voltage. The power module adjusts the original output voltage of the input video image during the frame blanking period to the grayscale mapping voltage sent by the timing control module, and then outputs it to the driver integration module. The grayscale mapping voltage sent from the power supply module to the drive integration module is acquired by the signal acquisition unit in the signal processing module; The control unit in the control signal processing module determines a voltage compensation signal based on the grayscale mapping voltage and the original output voltage, and feeds the voltage compensation signal back to the timing control module to correct the grayscale mapping voltage of the drive integration module.

3. The voltage regulation driving method as described in claim 2, characterized in that, The step of determining the grayscale mapping voltage by traversing a preset grayscale level sequence based on the current pixel brightness level sent by the image detection module includes: The brightness level of the current pixel is traversed sequentially according to a preset gray level sequence, wherein the gray level sequence includes multiple preset gray levels arranged in descending order of gray level. If the current pixel brightness level is within the brightness level range corresponding to the currently traversed preset gray level, then the currently traversed preset gray level is taken as the target gray level to which the current pixel brightness level belongs, and the preset voltage value mapped by the target gray level is taken as the gray level mapping voltage.

4. The voltage regulation driving method as described in claim 2, characterized in that, The voltage compensation signal is determined based on the grayscale mapping voltage and the original output voltage; Detect whether the voltage difference between the grayscale mapping voltage and the original output voltage is greater than zero; If the voltage difference is greater than zero, then the voltage compensation signal is determined to be a negative voltage difference. If the voltage difference is less than zero, then the voltage compensation signal is determined to be a positive voltage difference.

5. The voltage regulation driving method as described in claim 2, characterized in that, The step of feeding back the voltage compensation signal to the timing control module to correct the grayscale mapping voltage of the drive integration module includes: After the timing control module receives the voltage compensation signal fed back by the signal processing module, it superimposes the voltage compensation signal onto the grayscale mapping voltage of the drive integration module to obtain the corrected grayscale mapping voltage.

6. A display panel, characterized in that, The display panel includes a color filter substrate, a liquid crystal layer, and an array substrate. The liquid crystal layer is disposed between the array substrate and the color filter substrate. The array substrate includes the voltage regulation driving circuit as described in claim 1.

7. A display device, characterized in that, The display device includes: The display panel as described in claim 6; A memory, a processor, and a voltage regulation driver stored in the memory and executable on the processor, wherein the processor, when executing the voltage regulation driver, implements the steps of the voltage regulation driving method as described in any one of claims 2 to 5.

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