Memory, flash memory unit capable of being programmed for multiple times and preparation method of flash memory unit
CN120264758APending Publication Date: 2025-07-04CHINA FLASH CO LTD
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Patent Information
- Application Number
- CN202510196903.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-02-21
- Publication Date
- 2025-07-04
AI Technical Summary
Technical Problem
The existing PMOS-based multi-programming flash memory unit has complex processes, large area and high cost.
Method used
The flash memory cell with a single-layer polysilicon gate structure, including a P-type selector, a P-type memory transistor and transistor capacitor, is programmed through hot carrier injection, and an erasing operation is achieved through the F-N tunneling effect between the substrate and the floating gate, and a low-concentration P-type injection is added to the control gate to increase the junction breakdown voltage, simplifying the process.
Benefits of technology
The process flow is simplified, the area of flash memory cells is reduced, the production cost is reduced, and the production efficiency is improved.
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Figure CN120264758A_ABST
Abstract
The invention provides a memory, a multi-time programmable flash memory unit and a preparation method thereof, the flash memory unit adopts a single-layer polysilicon gate structure and comprises a P-type selection tube, a P-type storage transistor and a transistor capacitor, the gate of the P-type storage transistor is floated to store charges, the extension part of the P-type storage transistor serves as a pole plate of the transistor capacitor, and the P-type selection tube is connected with the transistor capacitor. The substrate of the P-type storage transistor and the substrate of the transistor capacitor C1 are isolated through a shallow trench. According to the P-type storage transistor, the programming operation of the storage unit is executed through hot carrier injection, and the erasing operation is executed through the F-N tunneling effect of the substrate and the floating gate. According to the invention, only one trap (NW) injection is adopted, and then the P-type injection with lower concentration is added at the control gate to improve the junction breakdown voltage between the control gate and the N trap, so that the existing technological process is simplified, the distance between different traps is removed, the area of the flash memory unit is reduced, and the cost is reduced.
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