Micro-LED epitaxial wafer and Micro-LED

Abstract

The invention discloses a Micro-LED epitaxial wafer and a Micro-LED, and relates to the field of semiconductor photoelectric devices. The epitaxial wafer sequentially comprises a substrate, a buffer layer, a non-doped GaN layer, an N-type semiconductor layer, a multi-quantum well layer and a P-type GaN layer; the N-type semiconductor layer sequentially comprises a first superlattice layer and a second superlattice layer; the first superlattice layer comprises a first Si-doped GaN layer, a Si3N4 layer, a second Si-doped GaN layer and an InN annihilation layer; a plurality of holes are formed in the InN annihilation layer; the second superlattice layer comprises a third Si-doped GaN layer and an AlInGaN layer; the Si doping concentration of the first Si-doped GaN layer and the Si doping concentration of the second Si-doped GaN layer are smaller than the Si doping concentration of the third Si-doped GaN layer. And the Si doping concentration of the third Si-doped GaN layer is greater than or equal to 1 * 10 < 19 > cm <-3 >. By implementing the invention, the lighting effect and the wavelength uniformity can be improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor optoelectronic devices, and particularly to a Micro-LED epitaxial wafer and a Micro-LED. Background Art

[0002] Micro-LED generally refers to a chip with a size less than 100 μm. It has excellent performance and low power consumption, and is the latest and best application technology in multiple foreseeable display scenarios at the current stage. However, the working current density of Micro-LED is generally between 0.1 A / cm 2 ~2 A / cm 2 . Under such a small current density, how to achieve uniform current distribution and how to improve the light-emitting efficiency become extremely important issues. The epitaxial structure of Micro-LED generally includes a substrate, an AlN buffer layer, an undoped GaN layer, an N-type GaN layer, a multi-quantum well layer, and a P-type GaN layer. Currently, a common method to improve the uniformity of current distribution is to increase the doping concentration of Si in the N-type GaN layer to reduce its resistivity and reduce current congestion. However, after increasing the Si doping concentration, the crystal quality of this layer is likely to decrease significantly, resulting in the dislocation of the lower layer being prone to spread upward, forming a leakage channel and leading to poor reliability; moreover, after the upward-extending dislocations enter the multi-quantum well layer, the compressive strain in the multi-quantum well layer will increase, resulting in an increase in non-radiative recombination and a decrease in the light-emitting efficiency. Summary of the Invention

[0003] The technical problem to be solved by the present invention is to provide a Micro-LED epitaxial wafer with high light-emitting efficiency and good light-emitting uniformity.

[0004] Another technical problem to be solved by the present invention is to provide a Micro-LED.

[0005] To solve the above technical problems, the present invention provides a Micro-LED epitaxial wafer, which includes a substrate, a buffer layer, an undoped GaN layer, an N-type semiconductor layer, a multi-quantum well layer, and a P-type GaN layer that are sequentially stacked on the substrate; wherein, the N-type semiconductor layer includes a first superlattice layer and a second superlattice layer that are sequentially stacked on the undoped GaN layer; the first superlattice layer is a periodic structure, and each period includes a first Si-doped GaN layer, a Si3N4 layer, a second Si-doped GaN layer, and an InN annihilation layer that are sequentially stacked; and a plurality of holes are provided in the InN annihilation layer; The second superlattice layer is a periodic structure, and each period includes a third Si-doped GaN layer and an AlInGaN layer stacked in sequence; the Si doping concentrations of the first Si-doped GaN layer and the second Si-doped GaN layer are less than the Si doping concentration of the third Si-doped GaN layer; the Si doping concentration of the third Si-doped GaN layer ≥ 1×10 19 cm -3 .

[0006] As an improvement to the above technical solution, in the first superlattice layer, the Si doping concentrations of the first Si-doped GaN layer and the second Si-doped GaN layer in the Nth period are respectively greater than the Si doping concentrations of the first Si-doped GaN layer and the second Si-doped GaN layer in the (N - 1)th period; where N is a positive integer and N ≥ 2; and / or In the second superlattice layer, the Si doping concentration of the third Si-doped GaN layer in the Mth period is greater than the Si doping concentration of the third Si-doped GaN layer in the (M - 1)th period; where M is a positive integer and M ≥ 2.

[0007] As an improvement to the above technical solution, in the first superlattice layer, the Si doping concentrations of the first Si-doped GaN layer and the second Si-doped GaN layer in the Nth period are respectively 2% - 20% greater than the Si doping concentrations of the first Si-doped GaN layer and the second Si-doped GaN layer in the (N - 1)th period; where N is a positive integer and N ≥ 2; and / or In the second superlattice layer, the Si doping concentration of the third Si-doped GaN layer in the Mth period is 10% - 50% greater than the Si doping concentration of the third Si-doped GaN layer in the (M - 1)th period; where M is a positive integer and M ≥ 2.

[0008] As an improvement to the above technical solution, the preparation method of the InN annihilation layer includes: growing an InN layer, and then performing heat treatment in an atmosphere containing H2 to form holes, thus obtaining the InN annihilation layer; wherein, the growth temperature of the InN layer is 700°C - 800°C, and the temperature of the heat treatment is 1000°C - 1100°C.

[0009] As an improvement to the above technical solution, the number of periods of the first superlattice layer is 2 - 20; and / or The thickness of the first Si-doped GaN layer is 10 nm - 60 nm, and its Si doping concentration is 1×10 18 cm -3 ~1×10 19 cm -3 ; and / or The thickness of the Si3N4 layer is 1 nm - 10 nm; and / or The thickness of the second Si-doped GaN layer is 10 nm to 60 nm, and its Si doping concentration is 1×10 18 cm -3 ~1×10 19 cm -3 ; and / or The thickness of the InN annihilation layer is 0.5 nm to 5 nm; and / or The number of periods of the second superlattice layer is 2 to 15; and / or The thickness of the third Si-doped GaN layer is 5 nm to 30 nm, and its Si doping concentration is 1×10 19 cm -3 ~5×10 20 cm -3 ; The thickness of the AlInGaN layer is 5 nm to 50 nm, its In component ratio is 0.01 to 0.1, and the Al component ratio is 0.01 to 0.1.

[0010] As an improvement to the above technical solution, the N-type semiconductor layer further includes a third superlattice layer disposed between the first superlattice layer and the second superlattice layer; The third superlattice layer is a periodic structure, and each period includes an AlN layer, a fourth Si-doped GaN layer, a porous InGaN layer, and an intrinsic GaN layer stacked in sequence; multiple holes are formed in the porous InGaN layer and are filled by the intrinsic GaN layer; Among them, the doping concentration of the fourth Si-doped GaN layer is less than the Si doping concentration of the third Si-doped GaN layer, and the Si doping concentrations of the first Si-doped GaN layer and the second Si-doped GaN layer are less than the Si doping concentration of the fourth Si-doped GaN layer.

[0011] As an improvement to the above technical solution, the number of periods of the third superlattice layer is 2 to 20; and / or The thickness of the AlN layer is 1 nm to 10 nm; and / or The thickness of the fourth Si-doped GaN layer is 10 nm to 50 nm, and its Si doping concentration is 5×10 18 cm -3 ~5×10 19 cm -3 ; and / or The thickness of the porous InGaN layer is 0.5 nm to 5 nm, and its In component ratio is 0.01 to 0.1; and / or The thickness of the intrinsic GaN layer is 10 nm to 50 nm.

[0012] As an improvement of the above technical solution, in the third superlattice layer, the Si doping concentration of the fourth Si-doped GaN layer in the Oth period is greater than that of the fourth Si-doped GaN layer in the (O-1)th period; where O is a positive integer and O≥2.

[0013] As an improvement of the above technical solution, the method for preparing the porous InGaN layer includes: growing an InGaN layer, and then performing heat treatment in an atmosphere containing H2 to form pores, thereby obtaining the porous InGaN layer; wherein, the growth temperature of the InGaN layer is 800°C to 900°C, and the heat treatment temperature is 1000°C to 1100°C.

[0014] Correspondingly, the present invention also discloses a Micro-LED, which includes the above-mentioned Micro-LED epitaxial wafer.

[0015] Implementing the present invention has the following beneficial effects: In the Micro-LED epitaxial wafer in an embodiment of the present invention, the N-type semiconductor layer includes a first superlattice layer and a second superlattice layer that are sequentially stacked on the undoped GaN layer; the first superlattice layer is a periodic structure, and each period includes a first Si-doped GaN layer, a Si3N4 layer, a second Si-doped GaN layer, and an InN annihilation layer that are sequentially stacked; a plurality of pores are provided in the InN annihilation layer; wherein, the Si3N4 layer can block the upward extension of dislocations and reduce the dislocation density; the pores in the InN annihilation layer can annihilate various types of defects (such as point defects, line defects, etc.), improving the crystal quality of the entire layer. Moreover, by adopting the periodic repeating structure of the first Si-doped GaN layer - Si3N4 layer - second Si-doped GaN layer - InN annihilation layer, the dislocation propagation path is changed multiple times, further reducing the dislocation density, optimizing the crystal quality, and improving the reliability. The second superlattice layer is a periodic structure, and each period includes a third Si-doped GaN layer and an AlInGaN layer that are sequentially stacked; by greatly optimizing the crystal quality through the first superlattice layer, the Si doping concentration in the third Si-doped GaN layer can be effectively increased, making it greater than 1×10 19 cm -3, and a doping method can be adopted in which the Si doping concentrations of the first Si-doped GaN layer and the second Si-doped GaN layer are less than that of the third Si-doped GaN layer. This doping method reduces the resistivity of the N-type semiconductor layer as a whole, optimizes current spreading, and improves light-emitting uniformity. In addition, the AlInGaN layer introduced in the second superlattice layer has a relatively high potential barrier, which can promote electrons to enter the multi-quantum well layer more uniformly. Moreover, it can further reduce the lattice mismatch between the N-type semiconductor layer and the multi-quantum well layer, reduce the compressive stress in the multi-quantum well layer, and improve the light-emitting efficiency. Therefore, based on the technical solution of this embodiment, not only is the current distribution effectively improved, the light-emitting uniformity optimized, but also the light-emitting efficiency is improved, leakage is effectively prevented, and the reliability is enhanced. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 is a schematic structural diagram of a Micro-LED epitaxial wafer in an embodiment of the present invention; Figure 2 is a schematic structural diagram of a Micro-LED epitaxial wafer in another embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0017] To make the objectives, technical solutions, and advantages of the present invention clearer, the present invention will be further described in detail below.

[0018] Refer to Figure 1 , the present invention discloses a Micro-LED epitaxial wafer, which includes a substrate 100, a buffer layer 200, an undoped GaN layer 300, an N-type semiconductor layer 400, a multi-quantum well layer 500, and a P-type GaN layer 600 that are sequentially stacked on the substrate 100.

[0019] Among them, the N-type semiconductor layer 400 includes a first superlattice layer 410 and a second superlattice layer 420 that are sequentially stacked on the undoped GaN layer 300; the first superlattice layer 410 is a periodic structure, and each period includes a first Si-doped GaN layer 411, a Si3N4 layer 412, a second Si-doped GaN layer 413, and an InN annihilation layer 414 that are sequentially stacked; a plurality of holes are provided in the InN annihilation layer 414; among them, the Si3N4 layer 412 can block the upward extension of dislocations and reduce the dislocation density; the holes in the InN annihilation layer 414 can annihilate various types of defects (such as point defects, line defects, etc.) and improve the crystal quality of the entire layer. Moreover, by adopting the periodic repeating structure of the first Si-doped GaN layer 411 - Si3N4 layer 412 - second Si-doped GaN layer 413 - InN annihilation layer 414, the dislocation propagation path is changed multiple times, further reducing the dislocation density, optimizing the crystal quality, and enhancing the reliability.

[0020] Among them, the second superlattice layer 420 is a periodic structure, and each period includes a third Si-doped GaN layer 421 and an AlInGaN layer 422 stacked in sequence. By significantly optimizing the crystal quality through the first superlattice layer 410, the Si doping concentration in the third Si-doped GaN layer 421 can be effectively increased, making it greater than 1×10 19 cm -3 , and a doping method can be adopted in which the Si doping concentrations of the first Si-doped GaN layer 411 and the second Si-doped GaN layer 413 are less than that of the third Si-doped GaN layer 421. This doping method reduces the resistivity of the N-type semiconductor layer 400 as a whole, optimizes current spreading, and improves the luminescence uniformity. In addition, the AlInGaN layer 422 introduced in the second superlattice layer 420 has a relatively high potential barrier, which can promote electrons to enter the multi-quantum well layer 500 more uniformly. In addition, it can further reduce the lattice mismatch between the N-type semiconductor layer 400 and the multi-quantum well layer 500, reduce the compressive stress in the multi-quantum well layer 500, and improve the luminescence efficiency. Therefore, based on the technical solution of this embodiment, not only the current distribution is effectively optimized, the luminescence uniformity is optimized, but also the luminescence efficiency is improved, the leakage is effectively prevented, and the reliability is improved.

[0021] Specifically, in some embodiments, the number of periods of the first superlattice layer 410 is 2 to 20, preferably 5 to 15. The thickness of the first Si-doped GaN layer 411 is 10 nm to 60 nm, preferably 20 nm to 50 nm. The Si doping concentration of the first Si-doped GaN layer 411 is 1×10 18 cm -3 ~1×10 19 cm -3 , preferably 1×10 18 cm -3 ~5×10 18 cm -3 . The thickness of the Si3N4 layer 412 is 1 nm to 10 nm, preferably 1 nm to 5 nm. The thickness of the second Si-doped GaN layer 413 is 10 nm to 60 nm, preferably 20 nm to 50 nm. The Si doping concentration of the second Si-doped GaN layer 413 is 1×10 18 cm -3 ~1×10 19 cm -3 , preferably 1×10 18 cm -3 ~5×10 18 cm -3 . The thickness of the InN annihilation layer 414 is 0.5 nm to 5 nm, preferably 2 nm to 5 nm.

[0022] Specifically, the Si doping concentration of the first Si-doped GaN layer 411 is the same as or different from that of the second Si-doped GaN layer 413. Preferably, the Si doping concentration of the first Si-doped GaN layer 411 is less than that of the second Si-doped GaN layer 413. Based on this setting, the current spreading can be further optimized and the luminescence uniformity can be improved.

[0023] Specifically, in some embodiments, the number of periods of the second superlattice layer 420 is 2 to 15, preferably 5 to 12. The thickness of the third Si-doped GaN layer 421 is 5 nm to 30 nm, preferably 10 nm to 20 nm. The Si doping concentration of the third Si-doped GaN layer 421 is 1×10 19 cm -3 ~5×10 20 cm -3 and preferably 2×10 19 cm -3 ~5×10 19 cm -3 . The thickness of the AlInGaN layer 422 is 5 nm to 50 nm, preferably 10 nm to 20 nm. The proportion of In component in the AlInGaN layer 422 is 0.01 to 0.1, preferably 0.01 to 0.05. The proportion of Al component in the AlInGaN layer 422 is 0.01 to 0.1, preferably 0.05 to 0.1.

[0024] Specifically, in some embodiments, the substrate 100 is a sapphire substrate or a silicon substrate, but not limited thereto.

[0025] Specifically, in some embodiments, the buffer layer 200 is an AlN layer or an AlGaN layer, but not limited thereto. The thickness of the buffer layer 200 is 30 nm to 80 nm.

[0026] Specifically, in some embodiments, the thickness of the undoped GaN layer 300 is 1 μm to 3 μm.

[0027] Specifically, in some embodiments, the multiple quantum well layer 500 includes alternately stacked InGaN quantum well layers and GaN quantum barrier layers, and the number of periods is 3 to 15. The thickness of a single InGaN quantum well layer is 3 nm to 5 nm, and the proportion of In component therein is 0.1 to 0.4; the thickness of a single GaN quantum barrier layer is 5 nm to 15 nm.

[0028] Specifically, the doping element of the P-type GaN layer 600 is Mg, but not limited thereto. The Mg doping concentration in the P-type GaN layer 600 is 1×10 19 cm -3 ~5×10 20 cm -3, with a thickness of 20 nm to 200 nm.

[0029] Preferably, in some embodiments, in the first superlattice layer 410, the Si doping concentrations of the first Si-doped GaN layer 411 and the second Si-doped GaN layer 413 in the Nth period are respectively greater than those of the first Si-doped GaN layer 411 and the second Si-doped GaN layer 413 in the (N - 1)th period; where N is a positive integer and N ≥ 2. That is, as the number of periods of the first superlattice layer 410 increases, the Si doping concentrations of the first Si-doped GaN layer 411 and the second Si-doped GaN layer 413 in different periods show an increasing change. Based on this embodiment, it is possible to avoid the overall crystal quality of the N-type semiconductor layer 400 from deteriorating due to too high doping concentration, and the reliability is improved. At the same time, this increasing doping method also further improves the uniformity of the current distribution and the luminescence uniformity.

[0030] More preferably, in the first superlattice layer 410, the Si doping concentrations of the first Si-doped GaN layer 411 and the second Si-doped GaN layer 413 in the Nth period are respectively 2% to 20% greater than those of the first Si-doped GaN layer 411 and the second Si-doped GaN layer 413 in the (N - 1)th period. It should be noted that in any period, the Si doping concentration of the first Si-doped GaN layer 411 can increase, decrease, or remain unchanged as its thickness increases. The Si doping concentration of the second Si-doped GaN layer 413 can increase, decrease, or remain unchanged as its thickness increases.

[0031] Preferably, in some embodiments, in the second superlattice layer 420, the Si doping concentration of the third Si-doped GaN layer 421 in the Mth period is greater than that of the third Si-doped GaN layer 421 in the (M - 1)th period; where M is a positive integer and M ≥ 2. That is, as the number of periods of the second superlattice layer 420 increases, the Si doping concentration of the third Si-doped GaN layer 421 in different periods shows an increasing change. Based on this embodiment, it is possible to avoid the overall crystal quality of the N-type semiconductor layer 400 from deteriorating due to too high doping concentration, and the reliability is improved. At the same time, this increasing doping method also further improves the uniformity of the current distribution and the luminescence uniformity.

[0032] More preferably, in the second superlattice layer 420, the Si doping concentration of the third Si-doped GaN layer 421 in the Mth period is 10% to 50% greater than that of the third Si-doped GaN layer 421 in the (M - 1)th period. It should be noted that in any period, the Si doping concentration of the third Si-doped GaN layer 421 can increase, decrease, or remain unchanged as its thickness increases.

[0033] Specifically, the InN annihilation layer 414 can form multiple holes through a photolithography-etching process, but is not limited thereto. Preferably, in some embodiments, the preparation method of the InN annihilation layer 414 is as follows: grow an InN layer, and then perform heat treatment in an H2-containing atmosphere to form holes, thus obtaining the InN annihilation layer 414. Among them, the growth temperature of the InN layer is 700°C to 800°C, and the heat treatment temperature is 1000°C to 1100°C. Based on this embodiment, on the one hand, the growth temperature of the InN layer is relatively low, which is beneficial to the release of the thermal stress accumulated in the N-type semiconductor layer 400. On the other hand, by forming holes through heat treatment in an H2-containing atmosphere, the defects converged in the InN layer can be annihilated through the holes obtained by high-temperature thermal decomposition, significantly reducing the dislocation density extending upward.

[0034] Preferably, referring to Figure 2 , in some embodiments, the N-type semiconductor layer 400 further includes a third superlattice layer 430 disposed between the first superlattice layer 410 and the second superlattice layer 420; the third superlattice layer 430 is a periodic structure, and each period includes an AlN layer 431, a fourth Si-doped GaN layer 432, a porous InGaN layer 433, and an intrinsic GaN layer 434 stacked in sequence; a plurality of holes are formed in the porous InGaN layer 433 and are filled by the intrinsic GaN layer 434; among them, the AlN layer 431 has a high density, which is convenient for dislocation kinking and reduces the dislocation density. The porous InGaN layer 433 can further annihilate dislocations through the holes, improving the overall crystal quality of the N-type semiconductor layer 400; by filling the holes with the intrinsic GaN layer 434, a good growth foundation is provided for the subsequently grown third superlattice layer 430, further reducing stress accumulation and improving the light-emitting efficiency. In addition, the Si doping concentration of the fourth Si-doped layer is less than that of the third Si-doped layer, but greater than the Si doping concentrations of the first Si-doped GaN layer 411 and the second Si-doped GaN layer 413. This stepped increasing doping method also further improves the crystal quality and optimizes the current spreading.

[0035] Specifically, in some embodiments, the number of periods of the third superlattice layer 430 is 2 to 20, preferably 5 to 15. The thickness of the AlN layer 431 is 1 nm to 10 nm, preferably 2 nm to 8 nm. The thickness of the fourth Si-doped GaN layer 432 is 10 nm to 50 nm, preferably 30 nm to 50 nm. The Si doping concentration of the fourth Si-doped GaN layer 432 is 5×10 18 cm -3 ~5×10 19 cm -3 , preferably 5×10 18 cm -3 ~1×10 19 cm -3。The thickness of the porous InGaN layer 433 is 0.5 nm to 5 nm, preferably 2 nm to 5 nm. The proportion of the In component in the porous InGaN layer 433 is 0.01 to 0.1, preferably 0.03 to 0.08. The thickness of the intrinsic GaN layer 434 is 10 nm to 50 nm, preferably 30 nm to 50 nm.

[0036] Preferably, in some embodiments, in the third superlattice layer 430, the Si doping concentration of the fourth Si-doped GaN layer 432 in the Oth period is greater than the Si doping concentration of the fourth Si-doped GaN layer 432 in the (O - 1)th period; where O is a positive integer and O ≥ 2. That is, as the number of periods of the third superlattice layer 430 increases, the Si doping concentration of the fourth Si-doped GaN layer 432 in different periods shows an increasing change. Based on this embodiment, it is possible to avoid the overall crystal quality degradation of the N-type semiconductor layer 400 due to too high doping concentration, improving the reliability. At the same time, this increasing doping method also further improves the uniformity of the current distribution and the light emission uniformity. It should be noted that in any period, the Si doping concentration of the fourth Si-doped GaN layer 432 may increase, decrease, or remain unchanged as its thickness increases.

[0037] Specifically, the holes in the porous InGaN layer 433 can be formed by a photolithography-etching process, but are not limited thereto. Preferably, in some embodiments, the preparation method of the porous InGaN layer 433 is: grow an InGaN layer, and then perform heat treatment in an atmosphere containing H2 to form holes, thus obtaining the porous InGaN layer 433. Among them, the growth temperature of the InGaN layer is 800 °C to 900 °C, and the heat treatment temperature is 1000 °C to 1100 °C.

[0038] Correspondingly, the present invention also discloses a Micro-LED, which includes the above-mentioned Micro-LED epitaxial wafer. Based on this Micro-LED epitaxial wafer, the reliability of the Micro-LED can be improved; at the same time, the light emission efficiency and the light emission uniformity can also be improved.

[0039] The following further illustrates the present invention with specific examples: Example 1 This example provides a Micro-LED epitaxial wafer, which includes a substrate, a buffer layer, an undoped GaN layer, an N-type semiconductor layer, a multi-quantum well layer, and a P-type GaN layer that are sequentially stacked on the substrate.

[0040] Among them, the substrate is a sapphire substrate, the buffer layer is an AlN layer with a thickness of 40 nm, and the thickness of the undoped GaN layer is 2 μm.

[0041] Among them, the N-type semiconductor layer includes a first superlattice layer and a second superlattice layer that are sequentially stacked on the undoped GaN layer; the first superlattice layer is a periodic structure with 10 periods. Each period includes a first Si-doped GaN layer, a Si3N4 layer, a second Si-doped GaN layer, and an InN annihilation layer that are sequentially stacked; the thickness of the first Si-doped GaN layer is 40 nm, and the Si doping concentration is 2.3×10 18 cm -3 ⁻³. The thickness of the Si3N4 layer is 3.5 nm. The thickness of the second Si-doped GaN layer is 40 nm, and the Si doping concentration is 2.3×10 18 cm -3 ⁻³. The thickness of the InN annihilation layer is 2.8 nm, and it forms multiple holes through a photolithography etching process.

[0042] Among them, the second superlattice layer is a periodic structure with 5 periods, and each period includes a third Si-doped GaN layer and an AlInGaN layer that are sequentially stacked. The thickness of the third Si-doped GaN layer is 25 nm, and its Si doping concentration is 2.2×10 19 cm -3 ⁻³. The thickness of the AlInGaN layer is 12 nm, and the proportion of its In component is 0.02, and the proportion of its Al component is 0.08.

[0043] Among them, the multiple quantum well layer includes an InGaN quantum well layer and a GaN quantum barrier layer that are alternately stacked, and its period number is 10. Among them, the proportion of the In component in the InGaN quantum well layer is 0.18, and its thickness is 3 nm. The thickness of the GaN quantum barrier layer is 10 nm.

[0044] Among them, the Mg doping concentration in the P-type GaN layer is 8×10 19 cm -3 ⁻³, and its thickness is 100 nm.

[0045] Example 2 This example provides a Micro-LED epitaxial wafer, and the difference from Example 1 is that: In the first superlattice layer, as the number of its periods increases, the Si doping concentrations of the first Si-doped GaN layer and the second Si-doped GaN layer increase from 1×10 18 cm -3 ⁻³ to 2.8×10 18 cm -3 ⁻³ at an increasing rate of 20%.

[0046] In the second superlattice layer, as the number of its periods increases, the Si doping concentration of the third Si-doped GaN layer increases from 1.8×10 19 cm -3 ⁻³ to 2.52×10 19 cm-3 。

[0047] The rest is the same as that in Example 1.

[0048] Example 3 This example provides a Micro-LED epitaxial wafer, and the difference from Example 2 is as follows: The preparation method of the InN annihilation layer is to grow an InN layer, and then perform heat treatment in an H2 atmosphere to form holes, thereby obtaining the InN annihilation layer; wherein, the growth temperature of the InN layer is 720 °C, the heat treatment temperature is 1050 °C, and the heat treatment time is 20 s.

[0049] The rest is the same as that in Example 2.

[0050] Example 4 This example provides a Micro-LED epitaxial wafer, and the difference from Example 3 is as follows: The N-type semiconductor layer further includes a third superlattice layer disposed between the first superlattice layer and the second superlattice layer; The third superlattice layer is a periodic structure with a period number of 10, and each period includes an AlN layer, a fourth Si-doped GaN layer, a porous InGaN layer, and an intrinsic GaN layer stacked in sequence. The thickness of the AlN layer is 4.5 nm. The thickness of the fourth Si-doped GaN layer is 35 nm, and the Si doping concentration is 6.5×10 18 cm -3 . The thickness of the porous InGaN layer is 3.5 nm, the proportion of the In component is 0.05, and a plurality of holes are formed inside it through a photolithography and etching process and are filled with the intrinsic GaN layer. The thickness of the intrinsic GaN layer is 35 nm.

[0051] The rest is the same as that in Example 3.

[0052] Example 5 This example provides a Micro-LED epitaxial wafer, and the difference from Example 4 is as follows: In the third superlattice layer, as the period number increases, the Si doping concentration of the fourth Si-doped GaN layer increases from 5×10 18 cm -3 to 9.5×10 18 cm -3 .

[0053] The rest is the same as that in Example 4.

[0054] Example 6 This example provides a Micro-LED epitaxial wafer, and the difference from Example 5 is as follows: The preparation method of the porous InGaN layer is as follows: grow the InGaN layer, and then perform heat treatment in an H2 atmosphere to form pores, thus obtaining the porous InGaN layer; Among them, the growth temperature of the InGaN layer is 840 °C, the heat treatment temperature is 1100 °C, and the heat treatment time is 15 s.

[0055] The rest are the same as in Example 5.

[0056] Comparative Example 1 This comparative example provides a Micro-LED epitaxial wafer, which is different from Example 1 in that: The N-type semiconductor layer is an N-type GaN layer, and its doping concentration is 1.3×10 19 cm -3 .

[0057] The rest are the same as in Example 1.

[0058] Comparative Example 2 This comparative example provides a Micro-LED epitaxial wafer, which is different from Example 1 in that: The N-type semiconductor layer does not include the first superlattice layer.

[0059] The rest are the same as in Example 1.

[0060] Comparative Example 3 This comparative example provides a Micro-LED epitaxial wafer, which is different from Example 1 in that: The N-type semiconductor layer does not include the second superlattice layer.

[0061] The rest are the same as in Example 1.

[0062] Comparative Example 4 This comparative example provides a Micro-LED epitaxial wafer, which is different from Example 1 in that: The first superlattice layer does not include the Si3N4 layer.

[0063] The rest are the same as in Example 1.

[0064] Comparative Example 5 This comparative example provides a Micro-LED epitaxial wafer, which is different from Example 1 in that: The first superlattice layer does not include the InN annihilation layer.

[0065] The rest are the same as in Example 1.

[0066] Comparative Example 6 This comparative example provides a Micro-LED epitaxial wafer, which is different from Example 1 in that: The first superlattice layer of each period includes a Si3N4 layer, a first Si-doped GaN layer, a second Si-doped GaN layer, and an InN annihilation layer stacked in sequence. The thickness of the Si3N4 layer is 3.5 nm. The thickness of the first Si-doped GaN layer is 40 nm, and the Si doping concentration is 2.3×10 18 cm -3 . The thickness of the second Si-doped GaN layer is 40 nm, and the Si doping concentration is 2.3×10 18 cm -3 . The thickness of the InN annihilation layer is 2.8 nm, and it forms a plurality of holes through a photolithography etching process.

[0067] The rest are the same as in Example 1.

[0068] The Micro-LED epitaxial wafers obtained in Examples 1 to 6 and Comparative Examples 1 to 6 were fabricated into Micro-LEDs with a horizontal structure and a size of 3 mil × 5 mil, and then tested as follows; (1) The luminous brightness was tested at a current density of 0.2 A / cm 2 , and the luminous brightness improvement rate was calculated based on the data of Comparative Example 1.

[0069] (2) Electrofluorescence tests were performed at current densities of 0.2 A / cm 2 and 1 A / cm 2 to obtain the wavelengths at different current densities. The wavelength shift was calculated according to the following formula: Wavelength shift = |Test wavelength 1 (0.2 A / cm 2 ) - Test wavelength 2 (1 A / cm 2 )|.

[0070]

[0071] As can be seen from the above table, when the Micro-LED epitaxial wafer of the present invention is used, the luminous efficiency of the Micro-LED can be greatly improved, and the wavelength uniformity can be optimized.

[0072] The above are the preferred embodiments of the invention. It should be noted that for those of ordinary skill in the art, without departing from the principle of the present invention, several improvements and refinements can be made, and these improvements and refinements are also regarded as the protection scope of the present invention.

Claims

1. A Micro-LED epitaxial wafer, characterized in that, It includes a substrate, a buffer layer, an undoped GaN layer, an N-type semiconductor layer, a multi-quantum well layer, and a P-type GaN layer that are sequentially stacked on the substrate; Among them, the N-type semiconductor layer includes a first superlattice layer and a second superlattice layer that are sequentially stacked on the undoped GaN layer; the first superlattice layer is a periodic structure, and each period includes a first Si-doped GaN layer, a Si3N4 layer, a second Si-doped GaN layer, and an InN annihilation layer that are sequentially stacked; a plurality of holes are provided in the InN annihilation layer; The second superlattice layer is a periodic structure, and each period includes a third Si-doped GaN layer and an AlInGaN layer stacked in sequence; the Si doping concentrations of the first Si-doped GaN layer and the second Si-doped GaN layer are less than the Si doping concentration of the third Si-doped GaN layer; the Si doping concentration of the third Si-doped GaN layer ≥ 1×10 19 cm -3 .

2. The Micro-LED epitaxial wafer according to claim 1, wherein In the first superlattice layer, the Si doping concentrations of the first Si-doped GaN layer and the second Si-doped GaN layer in the Nth period are respectively greater than the Si doping concentrations of the first Si-doped GaN layer and the second Si-doped GaN layer in the (N-1)th period; where N is a positive integer and N≥2; and / or In the second superlattice layer, the Si doping concentration of the third Si-doped GaN layer in the Mth period is greater than the Si doping concentration of the third Si-doped GaN layer in the (M-1)th period; where M is a positive integer and M≥2.

3. The Micro-LED epitaxial wafer according to claim 1, wherein, In the first superlattice layer, the Si doping concentrations of the first Si-doped GaN layer and the second Si-doped GaN layer in the Nth period are respectively 2% to 20% greater than the Si doping concentrations of the first Si-doped GaN layer and the second Si-doped GaN layer in the (N-1)th period; where N is a positive integer and N≥2; and / or In the second superlattice layer, the Si doping concentration of the third Si-doped GaN layer in the Mth period is 10% to 50% greater than the Si doping concentration of the third Si-doped GaN layer in the (M-1)th period; where M is a positive integer and M≥2.

4. The Micro-LED epitaxial wafer according to claim 1, wherein, The preparation method of the InN annihilation layer includes: growing an InN layer, and then performing heat treatment in an H2-containing atmosphere to form holes, that is, obtaining the InN annihilation layer; Among them, the growth temperature of the InN layer is 700°C to 800°C, and the heat treatment temperature is 1000°C to 1100°C.

5. The Micro-LED epitaxial wafer according to any one of claims 1 to 4, characterized in that, The number of periods of the first superlattice layer is 2 to 20; and / or The thickness of the first Si-doped GaN layer is 10 nm to 60 nm, and its Si doping concentration is 1×10 18 cm -3 ~1×10 19 cm -3 ; and / or The thickness of the Si3N4 layer is 1 nm to 10 nm; and / or The thickness of the second Si-doped GaN layer is 10 nm to 60 nm, and its Si doping concentration is 1×10 18 cm -3 ~1×10 19 cm -3 ; and / or The thickness of the InN annihilation layer is 0.5 nm to 5 nm; and / or The number of periods of the second superlattice layer is 2 to 15; and / or The thickness of the third Si-doped GaN layer is 5 nm to 30 nm, and its Si doping concentration is 1×10 19 cm -3 ~5×10 20 cm -3 ; The thickness of the AlInGaN layer is 5 nm to 50 nm, the In component ratio is 0.01 to 0.1, and the Al component ratio is 0.01 to 0.

1.

6. The Micro-LED epitaxial wafer according to any one of claims 1 to 4, characterized in that The N-type semiconductor layer further includes a third superlattice layer provided between the first superlattice layer and the second superlattice layer; The third superlattice layer is a periodic structure, and each period includes an AlN layer, a fourth Si-doped GaN layer, a porous InGaN layer, and an intrinsic GaN layer that are sequentially stacked; a plurality of holes are formed in the porous InGaN layer and are filled by the intrinsic GaN layer; Among them, the doping concentration of the fourth Si-doped GaN layer is less than the Si doping concentration of the third Si-doped GaN layer, and the Si doping concentrations of the first Si-doped GaN layer and the second Si-doped GaN layer are less than the Si doping concentration of the fourth Si-doped GaN layer.

7. The Micro-LED epitaxial wafer according to claim 6, wherein The number of periods of the third superlattice layer is 2 to 20; and / or The thickness of the AlN layer is 1 nm to 10 nm; and / or The thickness of the fourth Si-doped GaN layer is 10 nm to 50 nm, and its Si doping concentration is 5×10 18 cm -3 ~5×10 19 cm -3 ; and / or The thickness of the porous InGaN layer is 0.5 nm to 5 nm, and the proportion of its In component is 0.01 to 0.1; and / or The thickness of the intrinsic GaN layer is 10 nm to 50 nm.

8. The Micro-LED epitaxial wafer according to claim 6, wherein, In the third superlattice layer, the Si doping concentration of the fourth Si-doped GaN layer in the Oth period is greater than the Si doping concentration of the fourth Si-doped GaN layer in the (O-1)th period; where O is a positive integer and O≥2.

9. The Micro-LED epitaxial wafer according to claim 6, wherein The preparation method of the porous InGaN layer includes: growing an InGaN layer, and then performing heat treatment in an atmosphere containing H2 to form pores, thus obtaining the porous InGaN layer; Among them, the growth temperature of the InGaN layer is 800 °C to 900 °C, and the heat treatment temperature is 1000 °C to 1100 °C.

10. A Micro-LED, characterized in that, Including the Micro-LED epitaxial wafer according to any one of claims 1 to 9.

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