Data processing apparatus, method, NPU, device and storage medium

Abstract

The application provides a data processing device, method, NPU, equipment and storage medium. The device comprises: an off-chip memory configured to store a plurality of data; a read-write module configured to read k data from the off-chip memory for the (i+1)th reading; an on-chip memory configured to store the k data; a processor configured to obtain k first differences based on the k data; obtain an (i+1)th intermediate mean based on the k first differences and an ith intermediate mean; obtain k second differences; each second difference indicates a difference between a data and the (i+1)th intermediate mean; obtain an (i+1)th intermediate variance based on the k first differences, the k second differences and the ith intermediate variance; and the on-chip memory is further configured to store the (i+1)th intermediate mean and the (i+1)th intermediate variance. The technical scheme of the application can batch read data, batch process data and facilitate hardware implementation.

Description

Technical Field

[0001] This application relates to the field of artificial intelligence technology, and in particular to a data processing apparatus, method, NPU, device, and storage medium. Background Technology

[0002] Currently, in the field of artificial intelligence technology, when performing calculations on large amounts of data, the data cannot be fully loaded into the chip's on-chip memory and must be read from external memory before calculations can be performed.

[0003] In related technologies, both the mean and variance are calculated using defined formulas. This requires first reading the data to calculate the mean, then reading the data again to calculate the variance. This necessitates reading external memory twice, meaning multiple data reads are required when processing large amounts of data, leading to low processing efficiency. Alternatively, variance calculation using E(X^2)-(EX)^2 allows for reading the data only once to calculate the mean and the mean of the squares of the data, followed by variance calculation. While this method only requires one data read, when the actual variance is small, systematic errors in the calculation can lead to large errors in the final result, resulting in highly unstable values. Summary of the Invention

[0004] This application provides a data processing apparatus, method, NPU, device, and storage medium capable of batch reading and processing of data, thereby reducing the number of times data is read from off-chip memory, and providing stable data values ​​that are easy to implement in hardware, thus improving the data processing efficiency and stability of the processor or chip. The technical solution is as follows: According to a first aspect of the embodiments of this application, a data processing apparatus is provided, the apparatus comprising: Off-chip memory is used to store multiple data items; The read / write module is used to read k data items from the off-chip memory for the (i+1)th read. On-chip memory for storing k of the data; A processor is configured to: obtain k first differences based on k data points; each first difference indicating the difference between a data point and an i-th intermediate mean; obtain an (i+1)-th intermediate mean based on the k first differences and the i-th intermediate mean; obtain k second differences; each second difference indicating the difference between a data point and the (i+1)-th intermediate mean; and obtain an (i+1)-th intermediate variance based on the k first differences, the k second differences, and the i-th intermediate variance; where k and i are integers greater than or equal to 1. The on-chip memory is also used to store the (i+1)th intermediate mean and the (i+1)th intermediate variance.

[0005] In one possible implementation, obtaining the (i+1)th intermediate mean based on the k first differences and the i-th intermediate mean includes: Obtain the (i+1)th first difference sum; the (i+1)th first difference sum is the sum of the k first differences; Obtain the (i+1)th average difference; the (i+1)th average difference is obtained based on the first difference and ((i+1)×k); Obtain the i-th intermediate mean from the on-chip memory; Based on the i-th intermediate mean and the (i+1)-th average difference, the (i+1)-th intermediate mean is obtained; Write the (i+1)th intermediate mean into the on-chip memory.

[0006] In one possible implementation, obtaining the (i+1)th intermediate mean based on the i-th intermediate mean and the (i+1)th average difference includes: The (i+1)th intermediate mean is obtained based on the i-th intermediate mean and the (i+1)-th first difference sum.

[0007] In one possible implementation, obtaining the (i+1)th intermediate variance based on k first differences, k second differences, and the i-th intermediate variance includes: Obtain k product of differences; each product of differences is the product of a first difference and a second difference; Obtain the (i+1)th sum of difference products; the (i+1)th sum of difference products is the sum of the k sums of difference products; Read the i-th intermediate variance from the on-chip memory; The (i+1)th intermediate variance is obtained based on the sum of the products of the i-th intermediate variance and the (i+1)-th difference. Write the (i+1)th intermediate variance into the on-chip memory.

[0008] In one possible implementation, obtaining the (i+1)th intermediate variance based on the sum of the products of the i-th intermediate variance and the (i+1)th difference includes: The intermediate variance of the (i+1)th term is obtained by summing the products of the i-th intermediate variance and the (i+1)-th difference.

[0009] In one possible implementation, the processor is further configured to: Based on the intermediate variance described in (i+1), the target intermediate variance is obtained; The target variance is obtained by dividing the target intermediate variance by the total quantity; the total quantity indicates the total quantity of the data.

[0010] In one possible implementation, the processor is further configured to write the target mean and the target variance into the on-chip memory; The read / write module is further configured to read the target variance and the target mean from the on-chip memory, and write the target variance and the target mean into the off-chip memory.

[0011] According to a second aspect of the embodiments of this application, a data processing method is provided, the method comprising: For the (i+1)th read, read k data items from the off-chip memory; write the k data items into the on-chip memory; Based on k data points, obtain k first differences; each first difference indicates the difference between a data point and the i-th median mean; based on the k first differences and the i-th median mean, obtain the (i+1)-th median mean; obtain k second differences; each second difference indicates the difference between a data point and the (i+1)-th median mean; based on the k first differences, the k second differences, and the i-th median variance, obtain the (i+1)-th median variance; k and i are integers greater than or equal to 1; The (i+1)th intermediate mean and the (i+1)th intermediate variance are stored in the on-chip memory.

[0012] According to a third aspect of the embodiments of this application, an NPU is provided, the NPU comprising: The read / write module is used to read k data from off-chip memory for the (i+1)th read. On-chip memory for storing k of the data; A processor is configured to: obtain k first differences based on k data points; each first difference indicating the difference between a data point and an i-th intermediate mean; obtain an (i+1)-th intermediate mean based on the k first differences and the i-th intermediate mean; obtain k second differences; each second difference indicating the difference between a data point and the (i+1)-th intermediate mean; and obtain an (i+1)-th intermediate variance based on the k first differences, the k second differences, and the i-th intermediate variance; where k and i are integers greater than or equal to 1. The on-chip memory is also used to store the (i+1)th intermediate mean and the (i+1)th intermediate variance.

[0013] According to a fourth aspect of the present application, a computer device is provided, the computer device including a processor and a memory, the memory being used to store at least one program, the at least one program being loaded by the processor and executing a data processing method.

[0014] According to a fifth aspect of the embodiments of this application, a computer-readable storage medium is provided, wherein at least one program is stored in the computer-readable storage medium, the at least one program being loaded and executed by a processor to implement a data processing method.

[0015] In this embodiment, a data processing method is provided. A batch of data is read from off-chip memory and loaded into on-chip memory each time. The processor retrieves k data points from on-chip memory each time and processes these k data points stably to obtain a stable mean and variance. This allows for batch reading and processing of data, and iterative processing of data indefinitely, reducing the number of times data is read from off-chip memory and processed, thus improving the processor's data processing efficiency while ensuring that the number of operation instructions does not increase. Furthermore, since the values ​​in the iterative process are stable, the error of the final result is within an acceptable range. In addition, this embodiment calculates the variance of a batch of data iteratively each time, eliminating the need for calculation using the variance formula E(X^2)-(EX)^2, thereby solving the problem of large system errors, improving the stability of the calculated target variance, facilitating hardware implementation, and improving the computing performance and stability of the processor or chip. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a schematic diagram of an implementation environment provided according to an embodiment of this application; Figure 2 This is a schematic diagram of the structure of a data processing device according to an embodiment of this application; Figure 3 This is a flowchart illustrating a data processing method according to an embodiment of this application; Figure 4 This is a schematic diagram of the structure of an NPU according to an embodiment of this application; Figure 5 This is a schematic diagram of the structure of a terminal according to an embodiment of this application; Figure 6 This is a schematic diagram of the structure of a server according to an embodiment of this application. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0019] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application.

[0020] In this application, the terms "first," "second," etc., are used to distinguish identical or similar items that have essentially the same function. It should be understood that there is no logical or temporal dependency between "first," "second," and "nth," nor does it limit the quantity or execution order. It should also be understood that although the following description uses the terms "first," "second," etc., to describe various elements, these elements should not be limited by the terms.

[0021] These terms are simply used to distinguish one element from another. For example, without departing from the scope of various examples, the first action can be called the second action, and similarly, the second action can be called the first action. Both the first and second actions can be actions, and in some cases, they can be separate and distinct actions.

[0022] "At least one" refers to one or more actions. For example, at least one action can be one action, two actions, three actions, or any integer number of actions greater than or equal to one. "Multiple" refers to two or more actions. For example, multiple actions can be two actions, three actions, or any integer number of actions greater than or equal to two.

[0023] Figure 1 This is a schematic diagram of an implementation environment provided according to an embodiment of this application. The implementation environment may include a terminal 101 and a server 102.

[0024] Each terminal 101 is equipped with a data processing device. The data processing device includes at least on-chip memory, off-chip memory, read / write modules, and a processor.

[0025] Terminal 101 can be a smartphone with a data processing device, wearable device, personal computer, laptop computer, tablet computer, smart TV, and vehicle terminal, etc.

[0026] Server 102 can be a single server, a server cluster consisting of multiple servers, or a cloud processing center.

[0027] Terminal 101 is connected to server 102 via wired or wireless network.

[0028] In some embodiments, the wireless or wired network uses standard communication technologies and / or protocols. The network is typically the Internet, but can be any network, including but not limited to Local Area Networks (LANs), Metropolitan Area Networks (MANs), Wide Area Networks (WANs), mobile, wired or wireless networks, private networks, or any combination of virtual private networks. In some embodiments, technologies and / or formats, including Hyper Text Markup Language (HTML), Extensible Markup Language (XML), etc., are used to represent data exchanged over the network. Furthermore, conventional encryption technologies such as Secure Socket Layer (SSL), Transport Layer Security (TLS), Virtual Private Networks (VPNs), and Internet Protocol Security (IPsec) can be used to encrypt all or some links. In other embodiments, custom and / or dedicated data communication technologies may be used to replace or supplement the aforementioned data communication technologies.

[0029] In related technologies, the median mean is mainly calculated using the following two methods. The first method is based on the definition, which involves calculating the sum of all data points and dividing by the data size to obtain the median mean. The second method uses the Welford algorithm, which iteratively updates the median mean during the calculation process, processing one data point at a time.

[0030] In addition, the intermediate variance is mainly calculated using the following methods: The first is calculation based on the definition; the second is calculation based on the variance formula E(X^2)-(EX)^2; and the third is iterative calculation using the Welford algorithm, processing one data point at a time. While the Welford algorithm, when numerically stable, can calculate the median mean and median variance with only one data point read, it can only incrementally calculate one data point per iteration, making it unsuitable for computation by a Neural Processing Unit (NPU).

[0031] To address the aforementioned technical problems, this application provides a data processing apparatus, the specific technical solution of which is as follows: Figure 2 This is a schematic diagram of a data processing apparatus 200 according to an embodiment of this application. The apparatus includes: The external memory 201, read / write module 202, on-chip memory, and processor 204 are connected in sequence. Among them, the external memory 201, read / write module 202, on-chip memory, and processor 204 are all hardware structures.

[0032] In one example, on-chip memory 203 refers to memory integrated within the processor 204 or the chip, characterized by high-speed access and low latency. For example, in embodiments of this application, on-chip memory 203 is implemented based on static random access memory (SRAM).

[0033] In one example, off-chip memory 201 refers to storage devices that are separate from the main processor 204 or main memory, and are typically used to expand the system's storage capacity or to store data that needs to be retained for a long time. For example, in an embodiment of this application, off-chip memory 201 is implemented based on a hard disk.

[0034] In one example, the read / write module 202 is used to read data from the off-chip memory 201 and write the data to the on-chip memory. Alternatively, the read / write module 202 is used to read data from the on-chip memory and write the data to the off-chip memory 201. In the embodiments of this application, the read / write module 202 is hardware with read / write functionality.

[0035] In one example, processor 204 is used for streaming computation. Streaming computation can be understood as calculating k data points in the order they flow through processor 204. The specific functions of processor 204 include arithmetic operations and accumulation functions. Processor 204 is used to read data from on-chip memory, process the data, and write the processed data results back to on-chip memory. In the embodiments of this application, processor 204 is hardware that supports arithmetic operations and accumulation functions.

[0036] In some embodiments, since the large amount of data stored in the off-chip memory 201 cannot be completely loaded into the on-chip memory, it is necessary to read a portion of the data from the off-chip memory 201 each time. Specifically, the read / write module 202 is used to read k data from the off-chip memory 201 for the (i+1)th read and store the k data to the on-chip memory. The processor 204 is used to obtain k first differences based on the k data; each first difference indicates the difference between a data and the i-th intermediate mean; obtain the (i+1)-th intermediate mean based on the k first differences and the i-th intermediate mean; obtain k second differences; each second difference indicates the difference between a data and the (i+1)-th intermediate mean; obtain the (i+1)-th intermediate variance based on the k first differences, the k second differences, and the i-th intermediate variance; and store the (i+1)-th intermediate mean and the (i+1)-th intermediate variance to the on-chip memory. k and i are integers greater than or equal to 1. Here, the i-th median mean can be understood as the mean of the first i×k data points. The i-th median variance can be understood as the variance of the first i×k data points. As can be seen from the above embodiments, due to the technical solution of this application, batch data is read and processed each time, which greatly reduces the number of data reads compared to related technologies where one data point is read and processed at a time, thereby improving data processing efficiency. For example, k is 1000 or 10000.

[0037] In one example, the data processing device is started, and the intermediate mean, intermediate variance, and i are initialized to 0. For example, the data involved in the embodiments of this application are image data, audio data, or video data, etc.

[0038] In some embodiments, the (i+1)th intermediate mean is obtained based on the k first differences and the i-th intermediate mean, which can be achieved as follows: Obtain the (i+1)th sum of first differences; the (i+1)th sum of first differences is the sum of k first differences. Obtain the (i+1)th average difference; the (i+1)th average difference is obtained based on the sum of first differences and ((i+1)×k). Obtain the i-th intermediate mean from on-chip memory. Based on the i-th intermediate mean and the (i+1)th average difference, obtain the (i+1)th intermediate mean. Write the (i+1)th intermediate mean to on-chip memory. Wherein, the (i+1)th average difference = sum of first differences / ((i+1)×k).

[0039] Based on the above implementation, it can be seen that the processor 204 acquires k data points each time and processes these k data points stably to obtain a stable mean, thus iterating through the data indefinitely. Since the values ​​during the iteration process are stable, the error of the final result is within an acceptable range.

[0040] In some embodiments, the (i+1)th intermediate mean is obtained based on the i-th intermediate mean and the (i+1)-th average difference, which can be achieved as follows: Based on the i-th intermediate mean and the (i+1)-th first difference sum, the (i+1)-th intermediate mean is obtained.

[0041] In one example, the (i+1)th intermediate mean can be calculated using the following formula: The (i+1)th median mean = the i-th median mean + .

[0042] In the above formula, This is the m-th data point; This is the i-th intermediate mean; This is the sum of the first differences for the (i+1)th time. This is a first difference; This is the (i+1)th average difference.

[0043] In some embodiments, the (i+1)th intermediate variance is obtained based on k first differences, k second differences, and the i-th intermediate variance, which can be achieved as follows: Obtain k difference products; each difference product is the product of a first difference and a second difference. Obtain the (i+1)th difference product sum; the (i+1)th difference product sum is the sum of the k difference products. Read the i-th intermediate variance from on-chip memory. Based on the i-th intermediate variance and the (i+1)th difference product sum, obtain the (i+1)th intermediate variance. Write the (i+1)th intermediate variance to on-chip memory. Optionally, each difference product is the product of a first difference and a second difference for the same data.

[0044] In some embodiments, the (i+1)th intermediate variance is obtained based on the sum of the products of the i-th intermediate variance and the (i+1)-th difference, which can be achieved as follows: The (i+1)th intermediate variance is obtained by summing the products of the i-th intermediate variance and the (i+1)-th difference.

[0045] In one example, the (i+1)th intermediate variance can be calculated using the following formula: The (i+1)th intermediate variance = the i-th intermediate variance + .

[0046] In the above formula, This is the (i+1)th intermediate mean. It is a product of differences; The sum of the (i+1)th difference products; This is a second difference.

[0047] As can be seen from the above analysis, the embodiments of this application calculate the variance of a batch of data each time by means of iteration, so that it does not need to be calculated by the variance formula E(X^2)-(EX)^2, thereby solving the problem of large system error and improving the stability of the target variance calculated by the processor or chip.

[0048] In some embodiments, the processor 204 is further configured to: Based on the (i+1)th intermediate variance, the target intermediate variance is obtained; The target variance is obtained by dividing the target intermediate variance by the total quantity; the total quantity indicates the total number of data.

[0049] In one example, after calculating the variance of the last batch of data, the final intermediate variance, also known as the target intermediate variance, is obtained. The target variance is then calculated by dividing this target intermediate variance by the total number of data. In other words, the embodiments of this application only perform the calculation of the target intermediate variance divided by the total number of data once.

[0050] In one example, the target variance can be calculated using the following formula.

[0051] Target variance = Target midpoint variance / Total number

[0052] In one example, for the last data read, if the number of data to be read is less than k, then after reading the remaining data, "0"s are added to make the number of data read equal to k. However, during the calculation of the mean and variance of this batch of data, the number of data involved is calculated according to the actual number of data, that is, the number of "0"s is not considered, thus ensuring the accuracy and stability of the mean and variance.

[0053] In some embodiments, the processor 204 is further configured to write the target mean and the target variance into on-chip memory; The read / write module 202 is also used to read the target variance and target mean from the on-chip memory and write the target variance and target mean to the off-chip memory 201. The target mean is the mean obtained after calculating the mean of all data.

[0054] In one example, the read / write module 202 writes the last batch of data to the on-chip memory and waits for a preset time. The processor 204 calculates the target mean and target variance and writes them to the on-chip memory. After the read / write module 202 has waited for the preset time, it reads the target mean and target variance from the on-chip memory and writes them to the off-chip memory 201.

[0055] It should be noted that the data processing device provided in the above embodiments is only illustrated by the division of the above functional modules when performing the corresponding steps. In actual applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above.

[0056] In this embodiment, a batch of data is read from off-chip memory and loaded into on-chip memory each time. The processor retrieves k data points from on-chip memory each time and processes these k data points stably to obtain a stable mean and variance. This allows for batch reading and batch processing of data, and iterative processing of data indefinitely, reducing the number of times data is read from and processed from off-chip memory, improving the processor's data processing efficiency, and ensuring that the number of operation instructions does not increase. Moreover, since the values ​​in the iteration process are stable, the error of the final result is within an acceptable range. Furthermore, this embodiment calculates the variance of a batch of data iteratively each time, thus eliminating the need to calculate it using the variance formula E(X^2)-(EX)^2, thereby solving the problem of large system errors, improving the stability of the calculated target variance, facilitating hardware implementation, and improving the computing performance and stability of the processor or chip.

[0057] Figure 3 This is a flowchart illustrating a data processing method according to an embodiment of this application, such as... Figure 3 As shown, this embodiment of the application takes an application to a terminal with a data processing device as an example. The method includes the following steps: In step 301, for the (i+1)th read, the terminal reads k data from the off-chip memory and writes the k data to the on-chip memory.

[0058] In step 302, the terminal obtains k first differences based on k data points; each first difference indicates the difference between a data point and the i-th median mean; k second differences are obtained; and the (i+1)-th median variance is obtained based on the k first differences, the k second differences, and the i-th median variance.

[0059] Here, the (i+1)th intermediate mean is obtained based on the k first differences and the i-th intermediate mean; each second difference indicates the difference between a data point and the (i+1)-th intermediate mean; k and i are integers greater than or equal to 1.

[0060] In step 303, the terminal stores the (i+1)th intermediate mean and the (i+1)th intermediate variance into the on-chip memory.

[0061] In some embodiments, the (i+1)th intermediate mean is obtained based on the k first differences and the i-th intermediate mean, including: Get the (i+1)th first difference sum; the (i+1)th first difference sum is the sum of the k first differences; Obtain the (i+1)th average difference; the (i+1)th average difference is obtained based on the sum of the first difference and ((i+1)×k); Retrieve the i-th intermediate mean from on-chip memory; Based on the i-th intermediate mean and the (i+1)-th average difference, the (i+1)-th intermediate mean is obtained; Write the (i+1)th intermediate mean into the on-chip memory.

[0062] In some embodiments, the (i+1)th intermediate mean is obtained based on the i-th intermediate mean and the (i+1)-th average difference, including: Based on the i-th intermediate mean and the (i+1)-th first difference sum, the (i+1)-th intermediate mean is obtained.

[0063] In some embodiments, the (i+1)th intermediate variance is obtained based on k first differences, k second differences, and the i-th intermediate variance, including: Obtain the product of k differences; each product of differences is the product of a first difference and a second difference; Obtain the sum of the (i+1)th difference product; the sum of the (i+1)th difference product is the sum of the k difference products; Read the i-th intermediate variance from the on-chip memory; The (i+1)th intermediate variance is obtained based on the sum of the products of the i-th intermediate variance and the (i+1)-th difference. Write the (i+1)th intermediate variance into the on-chip memory.

[0064] In some embodiments, the (i+1)th intermediate variance is obtained based on the sum of the products of the i-th intermediate variance and the (i+1)-th difference, including: The (i+1)th intermediate variance is obtained by summing the products of the i-th intermediate variance and the (i+1)-th difference.

[0065] In some embodiments, the method further includes: Based on the (i+1)th intermediate variance, the target intermediate variance is obtained; The target variance is obtained by dividing the target intermediate variance by the total quantity; the total quantity indicates the total number of data.

[0066] In some embodiments, the method further includes: Write the target mean and target variance into the on-chip memory; Read the target variance and target mean from the on-chip memory, and write the target variance and target mean to the off-chip memory.

[0067] It should be noted that the data processing method and the data processing device embodiment provided in the above embodiments belong to the same concept, and their specific implementation process can be found in the device embodiment, which will not be repeated here.

[0068] In this embodiment, a batch of data is read from off-chip memory and loaded into on-chip memory each time. The processor retrieves k data points from on-chip memory each time and processes these k data points stably to obtain a stable mean and variance. This allows for batch reading and batch processing of data, and iterative processing of data indefinitely, reducing the number of times data is read from and processed from off-chip memory, improving the processor's data processing efficiency, and ensuring that the number of operation instructions does not increase. Moreover, since the values ​​in the iteration process are stable, the error of the final result is within an acceptable range. Furthermore, this embodiment calculates the variance of a batch of data iteratively each time, thus eliminating the need to calculate it using the variance formula E(X^2)-(EX)^2, thereby solving the problem of large system errors, improving the stability of the calculated target variance, facilitating hardware implementation, and improving the computing performance and stability of the processor or chip.

[0069] Figure 4 This is a schematic diagram of an NPU 400 according to an embodiment of this application. The NPU 400 includes: The read / write module 202 is used to read k data from the external memory 201 for the (i+1)th read; On-chip memory 203 is used to store k data items; Processor 204 is configured to: obtain k first differences based on k data points; each first difference indicates the difference between a data point and the i-th median mean; obtain the (i+1)-th median mean based on the k first differences and the i-th median mean; obtain k second differences; each second difference indicates the difference between a data point and the (i+1)-th median mean; obtain the (i+1)-th median variance based on the k first differences, the k second differences, and the i-th median variance; where k and i are integers greater than or equal to 1. The on-chip memory 203 is also used to store the (i+1)th intermediate mean and the (i+1)th intermediate variance.

[0070] In some embodiments, the (i+1)th intermediate mean is obtained based on the k first differences and the i-th intermediate mean, including: Get the (i+1)th first difference sum; the (i+1)th first difference sum is the sum of the k first differences; Obtain the (i+1)th average difference; the (i+1)th average difference is obtained based on the sum of the first difference and ((i+1)×k); Retrieve the i-th intermediate mean from on-chip memory; Based on the i-th intermediate mean and the (i+1)-th average difference, the (i+1)-th intermediate mean is obtained; Write the (i+1)th intermediate mean into the on-chip memory.

[0071] In some embodiments, the (i+1)th intermediate mean is obtained based on the i-th intermediate mean and the (i+1)-th average difference, including: Based on the i-th intermediate mean and the (i+1)-th first difference sum, the (i+1)-th intermediate mean is obtained.

[0072] In some embodiments, the (i+1)th intermediate variance is obtained based on k first differences, k second differences, and the i-th intermediate variance, including: Obtain the product of k differences; each product of differences is the product of a first difference and a second difference; Obtain the sum of the (i+1)th difference product; the sum of the (i+1)th difference product is the sum of the k difference products; Read the i-th intermediate variance from the on-chip memory; The (i+1)th intermediate variance is obtained based on the sum of the products of the i-th intermediate variance and the (i+1)-th difference. Write the (i+1)th intermediate variance into the on-chip memory.

[0073] In some embodiments, the (i+1)th intermediate variance is obtained based on the sum of the products of the i-th intermediate variance and the (i+1)-th difference, including: The (i+1)th intermediate variance is obtained by summing the products of the i-th intermediate variance and the (i+1)-th difference.

[0074] In some embodiments, the processor is further configured to: Based on the (i+1)th intermediate variance, the target intermediate variance is obtained; The target variance is obtained by dividing the target intermediate variance by the total quantity; the total quantity indicates the total number of data.

[0075] In some embodiments, the processor is further configured to write the target mean and the target variance into on-chip memory; The read / write module is also used to read the target variance and target mean from the on-chip memory and write the target variance and target mean to the off-chip memory.

[0076] It should be noted that the NPU provided in the above embodiments and the data processing device embodiments belong to the same concept, and the specific implementation process can be found in the device embodiments, which will not be repeated here.

[0077] In this embodiment, a batch of data is read from off-chip memory and loaded into on-chip memory each time. The processor retrieves k data points from on-chip memory each time and processes these k data points stably to obtain a stable mean and variance. This allows for batch reading and batch processing of data, and iterative processing of data indefinitely, reducing the number of times data is read from and processed from off-chip memory, improving the processor's data processing efficiency, and ensuring that the number of operation instructions does not increase. Moreover, since the values ​​in the iteration process are stable, the error of the final result is within an acceptable range. Furthermore, this embodiment calculates the variance of a batch of data iteratively each time, thus eliminating the need to calculate it using the variance formula E(X^2)-(EX)^2, thereby solving the problem of large system errors, improving the stability of the calculated target variance, facilitating hardware implementation, and improving the computing performance and stability of the processor or chip.

[0078] Embodiments of this application also provide a computer device, including a processor, a memory, and a computer program stored in the memory and configured to be executed by the processor, wherein the processor executes the computer program to implement the method described above.

[0079] Taking computer devices as terminals as an example, Figure 5 This is a schematic diagram of the structure of a terminal provided in an embodiment of this application. See also... Figure 5Terminal 500 can be: a smartphone, tablet computer, MP3 player (Moving Picture Experts Group Audio Layer III), MP4 player (Moving Picture Experts Group Audio Layer IV), laptop computer, or desktop computer. Terminal 500 may also be referred to as user equipment, portable terminal, laptop terminal, desktop terminal, or other names.

[0080] Typically, terminal 500 includes a processor 501 and a memory 502.

[0081] Processor 501 may include one or more processing cores, such as a quad-core processor, a penta-core processor, etc. Processor 501 may be implemented using at least one hardware form selected from DSP (Digital Signal Processing), FPGA (Field-Programmable Gate Array), and PLA (Programmable Logic Array). Processor 501 may also include a main processor and a coprocessor. The main processor, also known as a CPU (Central Processing Unit), is used to process data in the wake-up state; the coprocessor is a low-power processor used to process data in the standby state. In some embodiments, processor 501 may integrate a GPU (Graphics Processing Unit), which is responsible for rendering and drawing the content required to be displayed on the screen. In some embodiments, processor 501 may also include an AI (Artificial Intelligence) processor, which is used to handle computational operations related to machine learning.

[0082] The memory 502 may include one or more computer-readable storage media, which may be non-transitory. The memory 502 may also include high-speed random access memory and non-volatile memory, such as one or more disk storage devices or flash memory devices. In some embodiments, the non-transitory computer-readable storage media in the memory 502 are used to store at least one program code, which is executed by the processor 501 to implement the process of terminal execution in the method embodiments of this application.

[0083] In some embodiments, the terminal 500 may also optionally include a peripheral device interface 503 and at least one peripheral device. The processor 501, memory 502, and peripheral device interface 503 can be connected via a bus or signal line. Each peripheral device can be connected to the peripheral device interface 503 via a bus, signal line, or circuit board. Specifically, the peripheral device includes at least one of a display screen 504, a camera assembly 505, an audio circuit 506, and a power supply 507.

[0084] Peripheral device interface 503 can be used to connect at least one I / O (Input / Output) related peripheral device to processor 501 and memory 502. In some embodiments, processor 501, memory 502 and peripheral device interface 503 are integrated on the same chip or circuit board; in some other embodiments, any one or two of processor 501, memory 502 and peripheral device interface 503 can be implemented on separate chips or circuit boards, and this application embodiment does not limit this.

[0085] Display screen 504 is used to display a UI (User Interface). This UI may include graphics, text, icons, videos, and any combination thereof. When display screen 504 is a touch display screen, it also has the ability to collect touch signals on or above its surface. These touch signals can be input as control signals to processor 501 for processing. In this case, display screen 504 can also be used to provide virtual buttons and / or a virtual keyboard, also known as soft buttons and / or a soft keyboard. In some embodiments, there may be one display screen 504, disposed on the front panel of terminal 500; in other embodiments, there may be at least two display screens, disposed on different surfaces of terminal 500 or in a folded design; in still other embodiments, display screen 504 may be a flexible display screen, disposed on a curved or folded surface of terminal 500. Furthermore, display screen 504 may be configured as a non-rectangular, irregular shape, i.e., a non-rectangular screen. Display screen 504 may be made of materials such as LCD (Liquid Crystal Display) or OLED (Organic Light-Emitting Diode).

[0086] The camera assembly 505 is used to acquire images or videos. In some embodiments, the camera assembly 505 includes a front-facing camera and a rear-facing camera. Typically, the front-facing camera is located on the front panel of the terminal, and the rear-facing camera is located on the back of the terminal. In some embodiments, there are at least two rear-facing cameras, which are any one of a main camera, a depth-sensing camera, a wide-angle camera, and a telephoto camera, to achieve background blurring by fusion of the main camera and the depth-sensing camera, panoramic shooting by fusion of the main camera and the wide-angle camera, VR (Virtual Reality) shooting, or other fusion shooting functions. In some embodiments, the camera assembly 505 may also include a flash. The flash can be a single-color temperature flash or a dual-color temperature flash. A dual-color temperature flash is a combination of a warm-light flash and a cool-light flash, which can be used for light compensation at different color temperatures.

[0087] The audio circuit 506 may include a microphone and a speaker. The microphone is used to collect sound waves from the user and the environment, and convert the sound waves into electrical signals which are then input to the processor 501 for processing. For stereo sound acquisition or noise reduction purposes, multiple microphones may be used, each positioned at a different location on the terminal 500. The microphone may also be an array microphone or an omnidirectional microphone. The speaker is used to convert the electrical signals from the processor 501 into sound waves. The speaker may be a conventional diaphragm speaker or a piezoelectric ceramic speaker. When the speaker is a piezoelectric ceramic speaker, it can convert electrical signals not only into audible sound waves but also into inaudible sound waves for purposes such as distance measurement. In some embodiments, the audio circuit 506 may also include a headphone jack.

[0088] Power supply 507 is used to power the various components in terminal 500. Power supply 507 can be AC ​​power, DC power, a disposable battery, or a rechargeable battery. When power supply 507 includes a rechargeable battery, the rechargeable battery can support wired or wireless charging. The rechargeable battery can also be used to support fast charging technology.

[0089] Those skilled in the art will understand that Figure 5 The structure shown does not constitute a limitation on terminal 500, and may include more or fewer components than shown, or combine certain components, or use different component arrangements.

[0090] Taking computer equipment as a server as an example, Figure 6This is a schematic diagram of a server structure provided in an embodiment of this application. The server 600 can vary significantly due to differences in configuration or performance. It may include one or more Central Processing Units (CPUs) 601 and one or more memories 602. Each memory 602 stores at least one computer program, which is loaded and executed by the one or more processors 601 to implement the aforementioned data processing method. Of course, the server 600 may also have wired or wireless network interfaces, a keyboard, and input / output interfaces for input and output. The server 600 may also include other components for implementing device functions, which will not be elaborated upon here.

[0091] Embodiments of this application also provide a computer-readable storage medium, which includes a stored computer program, wherein the computer program, when running, controls the device where the computer-readable storage medium is located to perform the method described above. Optionally, the computer-readable storage medium may be read-only memory (ROM), random access memory (RAM), compact-disc read-only memory (CD-ROM), magnetic tape, floppy disk, and optical data storage device, etc.

[0092] Those skilled in the art will understand that all or part of the steps of the above embodiments can be implemented by hardware or by a program instructing related hardware. The program can be stored in a computer-readable storage medium, such as a read-only memory, a disk, or an optical disk.

[0093] The above description is merely an optional embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A data processing apparatus, characterized in that, include: Off-chip memory is used to store multiple data items; The read / write module is used to read k data items in batches from the off-chip memory for the (i+1)th read; On-chip memory for storing k of the data; A processor is configured to: obtain k first differences based on k data points; each first difference indicating a difference between a data point and an i-th intermediate mean; obtain an (i+1)-th intermediate mean based on the k first differences and the i-th intermediate mean; obtain k second differences; each second difference indicating a difference between a data point and the (i+1)-th intermediate mean; obtain an (i+1)-th intermediate variance based on the k first differences, the k second differences, and the i-th intermediate variance; where i is an integer greater than or equal to 1, k is an integer greater than 1, the i-th intermediate mean is the mean of i×k data points read from the first to the i-th read, and the i-th intermediate variance is the intermediate variance of i×k data points read from the first to the i-th read. The on-chip memory is also used to store the (i+1)th intermediate mean and the (i+1)th intermediate variance; The step of obtaining the (i+1)th intermediate mean based on the k first differences and the i-th intermediate mean includes: Obtain the (i+1)th first difference sum; obtain the (i+1)th average difference; obtain the i-th intermediate mean from the on-chip memory; Based on the i-th intermediate mean and the (i+1)-th average difference, the (i+1)-th intermediate mean is obtained, which is calculated using the following formula: The (i+1)th median mean = the i-th median mean + ; in, This is the m-th data point; Let be the i-th intermediate mean. For the (i+1)th first difference sum, For a first difference, This is the (i+1)th average difference; Write the (i+1)th intermediate mean into the on-chip memory; The process of obtaining the (i+1)th intermediate variance based on k first differences, k second differences, and the i-th intermediate variance includes: Obtain the k product of differences; obtain the sum of the (i+1)th product of differences; read the i-th intermediate variance from the on-chip memory; Based on the sum of the products of the i-th intermediate variance and the (i+1)-th difference, the (i+1)-th intermediate variance is obtained, which is calculated using the following formula: The (i+1)th intermediate variance = the i-th intermediate variance + ; in, This is the (i+1)th intermediate mean. It is a product of differences. For the sum of the products of the (i+1)th difference, It is a second difference; Write the (i+1)th intermediate variance into the on-chip memory.

2. The apparatus according to claim 1, characterized in that, The processor is also used for: Based on the (i+1)th intermediate variance, the target intermediate variance is obtained, which is the last intermediate variance obtained by calculating the variance of the last batch of data. The target variance is obtained by dividing the target intermediate variance by the total number. The total quantity indicates the total amount of data.

3. The apparatus according to claim 2, characterized in that, The processor is further configured to write the target mean and the target variance into the on-chip memory; The read / write module is further configured to read the target variance and the target mean from the on-chip memory, and write the target variance and the target mean into the off-chip memory.

4. A data processing method, characterized in that, include: For the (i+1)th read, read k data items in batch from off-chip memory; write the k data items into on-chip memory; Based on k data points, obtain k first differences; each first difference indicates the difference between a data point and the i-th intermediate mean; based on the k first differences and the i-th intermediate mean, obtain the (i+1)-th intermediate mean; obtain k second differences; each second difference indicates the difference between a data point and the (i+1)-th intermediate mean; based on the k first differences, the k second differences, and the i-th intermediate variance, obtain the (i+1)-th intermediate variance; i is an integer greater than or equal to 1, k is an integer greater than 1, the i-th intermediate mean is the mean of the i×k data points read from the 1st to the i-th time, and the i-th intermediate variance is the intermediate variance of the i×k data points read from the 1st to the i-th time. The (i+1)th intermediate mean and the (i+1)th intermediate variance are stored in the on-chip memory; The step of obtaining the (i+1)th intermediate mean based on the k first differences and the i-th intermediate mean includes: Obtain the (i+1)th first difference sum; obtain the (i+1)th average difference; obtain the i-th intermediate mean from the on-chip memory; Based on the i-th intermediate mean and the (i+1)-th average difference, the (i+1)-th intermediate mean is obtained, which is calculated using the following formula: The (i+1)th median mean = the i-th median mean + ; in, This is the m-th data point; Let be the i-th intermediate mean. For the (i+1)th first difference sum, For a first difference, This is the (i+1)th average difference; Write the (i+1)th intermediate mean into the on-chip memory; The process of obtaining the (i+1)th intermediate variance based on k first differences, k second differences, and the i-th intermediate variance includes: Obtain the k product of differences; obtain the sum of the (i+1)th product of differences; read the i-th intermediate variance from the on-chip memory; Based on the sum of the products of the i-th intermediate variance and the (i+1)-th difference, the (i+1)-th intermediate variance is obtained, which is calculated using the following formula: The (i+1)th intermediate variance = the i-th intermediate variance + ; in, This is the (i+1)th intermediate mean. It is a product of differences. For the sum of the products of the (i+1)th difference, It is a second difference; Write the (i+1)th intermediate variance into the on-chip memory.

5. An NPU, characterized in that, include: The read / write module is used to read k data items in batches from off-chip memory for the (i+1)th read. On-chip memory for storing k of the data; A processor is configured to: obtain k first differences based on k data points; each first difference indicating a difference between a data point and an i-th intermediate mean; obtain an (i+1)-th intermediate mean based on the k first differences and the i-th intermediate mean; obtain k second differences; each second difference indicating a difference between a data point and the (i+1)-th intermediate mean; and obtain an (i+1)-th intermediate variance based on the k first differences, the k second differences, and the i-th intermediate variance; where i is an integer greater than or equal to 1, k is an integer greater than 1, the i-th intermediate mean is the mean of i×k data points read from the first to the i-th read, and the i-th intermediate variance is the intermediate variance of i×k data points read from the first to the i-th read. The on-chip memory is also used to store the (i+1)th intermediate mean and the (i+1)th intermediate variance; The step of obtaining the (i+1)th intermediate mean based on the k first differences and the i-th intermediate mean includes: Obtain the (i+1)th first difference sum; obtain the (i+1)th average difference; obtain the i-th intermediate mean from the on-chip memory; Based on the i-th intermediate mean and the (i+1)-th average difference, the (i+1)-th intermediate mean is obtained, which is calculated using the following formula: The (i+1)th median mean = the i-th median mean + ; in, This is the m-th data point; Let be the i-th intermediate mean. For the (i+1)th first difference sum, For a first difference, This is the (i+1)th average difference; Write the (i+1)th intermediate mean into the on-chip memory; The process of obtaining the (i+1)th intermediate variance based on k first differences, k second differences, and the i-th intermediate variance includes: Obtain the k product of differences; obtain the sum of the (i+1)th product of differences; read the i-th intermediate variance from the on-chip memory; Based on the sum of the products of the i-th intermediate variance and the (i+1)-th difference, the (i+1)-th intermediate variance is obtained, which is calculated using the following formula: The (i+1)th intermediate variance = the i-th intermediate variance + ; in, This is the (i+1)th intermediate mean. It is a product of differences. For the sum of the products of the (i+1)th difference, It is a second difference; Write the (i+1)th intermediate variance into the on-chip memory.

6. A computer device, characterized in that, The computer device includes a processor and a memory, the memory being used to store at least one program, the at least one program being loaded by the processor and executed as described in claim 4.

7. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores at least one program, which is loaded and executed by a processor to implement the data processing method as described in claim 4.

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