Quenching circuit and imaging system of avalanche diode

Abstract

This invention proposes a quenching circuit and imaging system for an avalanche diode. The quenching circuit for the avalanche diode includes a quenching reset circuit, a delay circuit, a comparator circuit, and a detection and control circuit. The detection and control circuit outputs a quenching signal during the output period of the first level signal of the first clock signal, so that the quenching circuit operates in the quenching stage. During the second level signal, i.e., the reset stage of the quenching circuit, if the avalanche diode is triggered by a photon, the comparator circuit or the delay circuit will generate a corresponding first change signal or a second change signal. When the detection and control circuit detects the first change signal or the second change signal of the comparator circuit or the delay circuit, it can determine that the avalanche diode has been triggered in the reset stage. At this time, it outputs a quenching signal, so that the quenching reset circuit enters the quenching stage in advance, reducing the power consumption of the quenching circuit when it is triggered in the reset stage.

Description

Technical Field

[0001] This invention belongs to the field of imaging system technology, and particularly relates to a quenching circuit and imaging system for an avalanche diode. Background Technology

[0002] SPAD (Single Photon Avalanche Diode) imaging systems use SPAD arrays as light receivers to obtain input light intensity by sensing information such as photon count rate, thereby achieving imaging.

[0003] When a SPAD is over-biased, it generates a self-sustained current due to photon triggering. Without any suppression measures, the avalanche process will continue until the device is permanently damaged. Therefore, a quenching circuit is needed to suppress avalanche and quench the avalanche current. To achieve high resolution in the imaging system, the SPAD array is relatively large, thus requiring the quenching circuit to have low power consumption characteristics.

[0004] The quenching circuit operates in the quenching stage and the reset stage. In the reset stage, the quenching switch in the quenching circuit is in the on state. The avalanche diode may be photon triggered, causing the quenching circuit and the avalanche diode to form a current loop. At this time, the avalanche diode can be simplified to a small load resistor. The quenching tube is fully turned on, resulting in a large DC power consumption in the circuit.

[0005] like Figure 1 As shown, a conventional quenching circuit consists of a quenching diode, a capacitor, and a comparator. Assuming that the avalanche diode is forward biased, the gate voltage of the quenching diode is controlled by a clock signal. The comparator compares the anode voltage of the avalanche diode and outputs a pulse signal. The back-end signal processing circuit determines information such as the photon count rate based on the pulse signal and the clock signal, and then determines the image information.

[0006] The quenching circuit operates in the quenching phase and the reset phase, such as Figure 2 As shown, when the avalanche diode is forward biased, the quenching period is the low-level period of the clock signal, and the reset period is the high-level period of the clock signal. Assuming a photon triggers the avalanche diode when CK=0, the circuit enters the quenching stage: at this time, the quenching diode is turned off, acting as an "infinitely large" quenching resistor. The avalanche current charges the parasitic capacitance Cpar, and VA0 rapidly rises to Vex, making the voltage across the avalanche diode ≤ VBK, thus achieving rapid quenching. Here, VBK is the avalanche voltage of the avalanche diode, and Vex is the overbias voltage of the avalanche diode. Afterward, while CK remains at 0, VA0 remains at Vex, and even if other photons are incident, the avalanche diode cannot be triggered. Therefore, the maximum photon count rate achievable by the quenching circuit is the frequency of the clock signal.

[0007] However, as Figure 3 As shown, if a photon triggers during the reset phase, the voltage across the avalanche diode is higher than VBK due to the decrease in VA0. If a photon is incident at this time, the avalanche diode is triggered. Since the quencher is still conducting and its on-resistance is small, the avalanche current of the avalanche diode is insufficient to increase VA0 to Vex, therefore the avalanche diode cannot be quenched. In this case, the avalanche diode can be simplified to a small load resistor, and the quencher is fully conducting, resulting in a large DC power dissipation in the circuit.

[0008] The maximum duration of high power consumption is equal to the high-level pulse width of the clock signal. The quenching diode turns off after the clock signal is reset to 0 again, and the avalanche current charges Cpar, increasing VA0 to Vex. This causes the avalanche diode to enter the quenching phase, awaiting the next reset.

[0009] When the incident light is strong, the probability of photons being triggered during the reset phase increases. This problem of high power consumption becomes even more serious when the array size of avalanche diodes is large. Summary of the Invention

[0010] The purpose of this invention is to provide a quenching circuit for an avalanche diode, which aims to solve the problem of high power consumption in traditional quenching circuits.

[0011] A first aspect of this invention provides a quenching circuit for an avalanche diode, comprising:

[0012] A bias voltage circuit is connected to the first terminal of the avalanche diode, and the bias voltage circuit is used to provide a bias voltage;

[0013] A quenching and reset circuit is connected to the second terminal of the avalanche diode. The quenching and reset circuit is used to quench or reset the avalanche diode according to a quenching signal or a reset signal.

[0014] The delay circuit is used to delay the input first clock signal for a preset time and output it as a second clock signal. The first clock signal is composed of alternating first-level signals and second-level signals with opposite levels.

[0015] A comparator circuit is connected to the second terminal of the avalanche diode. The comparator circuit is used to output a third level signal when the input voltage is greater than or equal to a preset threshold voltage, and to output a fourth level signal with the opposite level to the third level signal when the input voltage is less than the preset threshold voltage.

[0016] The detection control circuit is connected to the comparison circuit, the delay circuit, and the quenching reset circuit, respectively. The detection control circuit is used for:

[0017] The reset signal is output during the output period of each of the second level signals, and the quenching signal is output when the first change signal generated by the comparison circuit is detected, or when the second change signal generated by the delay circuit is detected but the second change signal generated by the comparison circuit is not detected.

[0018] The quenching signal is output during the output period of the first level signal, wherein the first change signal and the second change signal are each other's rising edge and falling edge.

[0019] A second aspect of the present invention provides an imaging system, including a pixel array and an image processing circuit, wherein the pixel array includes pixel units arranged in an array, and each pixel unit includes an avalanche diode connected in series and a quenching circuit for the avalanche diode as described above.

[0020] The image processing circuit is connected to the quenching circuit of each avalanche diode. The image processing circuit is used to process the photon count rate output by the quenching circuit of the avalanche diode and determine the image information.

[0021] The beneficial effects of the embodiments of the present invention compared with the prior art are as follows: The quenching circuit of the avalanche diode mentioned above includes a quenching reset circuit, a delay circuit, a comparator circuit, and a detection control circuit. The detection control circuit outputs a quenching signal during the output period of the first level signal of the first clock signal, so that the quenching circuit works in the quenching stage. In the second level signal, i.e., the reset stage of the quenching circuit, if the avalanche diode is triggered by a photon, the comparator circuit or the delay circuit will generate a corresponding first change signal or a second change signal. When the detection control circuit detects the first change signal or the second change signal of the comparator circuit or the delay circuit, it can determine that the avalanche diode is triggered in the reset stage. At this time, it outputs a quenching signal, so that the quenching reset circuit enters the quenching stage in advance, reducing the power consumption of the quenching circuit when it is triggered in the reset stage. Attached Figure Description

[0022] Figure 1 This is a circuit diagram of a traditional quenching circuit;

[0023] Figure 2 This is a schematic diagram of the first type of signal waveforms for the quenching and reset phases of a traditional quenching circuit.

[0024] Figure 3 This is a schematic diagram of the signal waveform of a photon-triggered circuit during the reset phase.

[0025] Figure 4 This is a schematic diagram of the signal waveform of a traditional quenching circuit without photon triggering during the reset phase.

[0026] Figure 5This is a schematic diagram of the first signal waveform in the reset phase of a traditional quenching circuit.

[0027] Figure 6 This is a schematic diagram of the first signal waveform in Case 2 of the traditional quenching circuit during the reset phase.

[0028] Figure 7 This is a schematic diagram of a first structure of the quenching circuit provided in an embodiment of the present invention;

[0029] Figure 8 This is a schematic diagram of the first signal waveform of the quenching circuit provided in an embodiment of the present invention in the absence of photon triggering;

[0030] Figure 9 This is a schematic diagram of the first signal waveform of the quenching circuit in the reset phase according to an embodiment of the present invention;

[0031] Figure 10 This is a schematic diagram of the second signal waveform of the quenching circuit in the reset phase according to an embodiment of the present invention;

[0032] Figure 11 This is a schematic diagram of the first signal waveform in the second case of the quenching circuit during the reset phase provided in an embodiment of the present invention;

[0033] Figure 12 This is a schematic diagram of the second signal waveform of the quenching circuit in case two during the reset phase, provided in an embodiment of the present invention.

[0034] Figure 13 This is a schematic diagram of the third signal waveform in case two of the quenching circuit provided in the embodiment of the present invention during the reset phase;

[0035] Figure 14 This is a schematic diagram of the fourth signal waveform in case two of the quenching circuit provided in the embodiment of the present invention during the reset phase;

[0036] Figure 15 This is a schematic diagram of the second type of signal waveforms for the quenching and reset phases of a traditional quenching circuit.

[0037] Figure 16 This is a schematic diagram of the second signal waveform in the reset phase of a traditional quenching circuit.

[0038] Figure 17 This is a schematic diagram of the second signal waveform in case two of the traditional quenching circuit during the reset phase;

[0039] Figure 18 This is a schematic diagram of a second structure of the quenching circuit provided in an embodiment of the present invention;

[0040] Figure 19This is a schematic diagram of the second signal waveform of the quenching circuit provided in an embodiment of the present invention in the absence of photon triggering;

[0041] Figure 20 This is a schematic diagram of the third signal waveform of the quenching circuit in the reset phase according to an embodiment of the present invention;

[0042] Figure 21 A schematic diagram of the fifth signal waveform of the quenching circuit in the reset phase of the embodiment of the present invention;

[0043] Figure 22 A schematic diagram of the sixth signal waveform in case two during the reset phase of the quenching circuit provided in an embodiment of the present invention;

[0044] Figure 23 This is a schematic diagram of a third structure of the quenching circuit provided in an embodiment of the present invention;

[0045] Figure 24 This is a schematic diagram of the third signal waveform of the quenching circuit provided in an embodiment of the present invention in the absence of photon triggering;

[0046] Figure 25 This is a schematic diagram of the fourth signal waveform of the quenching circuit in the reset phase according to an embodiment of the present invention;

[0047] Figure 26 A schematic diagram of the seventh signal waveform in case two during the reset phase of the quenching circuit provided in an embodiment of the present invention;

[0048] Figure 27 A schematic diagram of the eighth signal waveform in case two during the reset phase of the quenching circuit provided in an embodiment of the present invention;

[0049] Figure 28 This is a schematic diagram of the fourth signal waveform of the quenching circuit provided in an embodiment of the present invention in the absence of photon triggering;

[0050] Figure 29 A schematic diagram of the fifth signal waveform of the quenching circuit in the reset phase according to an embodiment of the present invention;

[0051] Figure 30 A schematic diagram of the ninth signal waveform in case two during the reset phase of the quenching circuit provided in an embodiment of the present invention;

[0052] Figure 31 A schematic diagram of ten signal waveforms in Case 2 of the quenching circuit provided in the embodiment of the present invention during the reset phase;

[0053] Figure 32 This is a schematic diagram of the fourth structure of the quenching circuit provided in an embodiment of the present invention;

[0054] Figure 33 This is a schematic diagram of a first type of quenching circuit provided in an embodiment of the present invention;

[0055] Figure 34 This is a second circuit diagram of the quenching circuit provided in an embodiment of the present invention;

[0056] Figure 35 This is a third circuit diagram of the quenching circuit provided in an embodiment of the present invention;

[0057] Figure 36 This is a circuit diagram of a quenching switch provided in an embodiment of the present invention;

[0058] Figure 37 This is a schematic diagram of the fifth structure of the quenching circuit provided in an embodiment of the present invention;

[0059] Figure 38 A waveform diagram of the output clock of the quenching circuit provided in an embodiment of the present invention;

[0060] Figure 39 This is a schematic diagram of the imaging system provided in an embodiment of the present invention.

[0061] The figures in the diagram are labeled as follows:

[0062] 1. Quenching circuit; 2. Image processing circuit; 10. Quenching and reset circuit; 20. Delay circuit; 30. Comparison circuit; 40. Detection and control circuit; 50. Bias voltage circuit; 60. Clock generation circuit; 11. Quenching switch; 41. First detection circuit; 42. Second detection circuit; 43. Logic control circuit; 100. Pixel array; 101. Pixel unit; 431. First logic gate circuit; 432. Second logic gate circuit; 433. Third logic gate circuit;

[0063] SPAD, avalanche diode; M1, quench diode; Cpar, capacitor; DFF1, first D flip-flop; DFF2, second D flip-flop; DFF3, third D flip-flop; DFF4, fourth D flip-flop; DFF5, fifth D flip-flop; DFF6, sixth D flip-flop; U1, first inverter; U2, second inverter; U3, third inverter; U4, fourth inverter; U5, non-inverting inverter; AND1, AND gate; OR1, first OR gate; OR2, second OR gate;

[0064] CK1, first clock signal; CK2, second clock signal; CK0, output clock of the detection control circuit; VA0, anode voltage of the avalanche diode; VC0, cathode voltage of the avalanche diode; VC1, output signal of the comparator circuit; Q1, output signal of the first detection circuit; Q2, output signal of the second detection circuit. Detailed Implementation

[0065] To make the technical problems to be solved, the technical solutions, and the beneficial effects of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present invention and are not intended to limit the present invention.

[0066] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0067] A typical SPAD avalanche diode's quenching circuit consists of a quenching diode M1, a capacitor Cpar, and a comparator U0. The capacitor Cpar is generally a parasitic capacitance. Figure 1 As shown, assuming the avalanche diode SPAD is forward biased, the gate voltage of the quenching transistor M1 is controlled by the clock signal CK. The comparator U0 compares the anode voltage of the avalanche diode SPAD and outputs a pulse signal. The image processing circuit 2 at the back end determines information such as the photon count rate based on the pulse signal and the clock signal, and then determines the image information.

[0068] The quenching circuit operates in the quenching phase and the reset phase, such as Figure 2 As shown, when the avalanche diode SPAD is forward biased, the quenching period is the low-level period of the clock signal, and the reset period is the high-level period of the clock signal CK. Assuming a photon triggers the avalanche diode SPAD when CK=0, the circuit enters the quenching stage: at this time, the quenching transistor M1 is turned off, acting as an "infinitely large" quenching resistor. The avalanche current charges the parasitic capacitance Cpar, and VA0 rapidly rises to Vex, making the voltage across the avalanche diode SPAD ≤ VBK, thus achieving rapid quenching. Here, Vex is the over-bias voltage of the avalanche diode SPAD, and VBK is the avalanche voltage of the avalanche diode SPAD. Afterward, while CK remains at 0, VA0 remains at Vex, and even if other photons are incident, the avalanche diode SPAD cannot be triggered. Therefore, the maximum photon count rate achievable by the quenching circuit is the frequency of the clock signal.

[0069] However, as Figure 3As shown, if a photon triggers during the reset phase, the voltage across the avalanche diode SPAD is higher than VBK due to the decrease in VA0. If a photon is incident at this time, the avalanche diode SPAD is triggered. Since the quencher M1 is still conducting and its on-resistance is small, the avalanche current of the avalanche diode SPAD is insufficient to increase VA0 to Vex, therefore the avalanche diode SPAD cannot be quenched. In this case, the avalanche diode SPAD can be simplified to a small load resistor, and the quencher M1 is fully conducting, resulting in a large DC power consumption in the circuit.

[0070] The maximum duration of high power consumption is equal to the high-level pulse width of the clock signal CK. Until the clock signal is reset to 0 again, the quenching transistor M1 turns off, and the avalanche current charges Cpar, increasing VA0 to Vex. This causes the avalanche diode SPAD to enter the quenching phase, awaiting the next reset.

[0071] When the incident light is strong, the probability of photons being triggered during the reset phase increases. This problem of high power consumption becomes even more serious when the array size of avalanche diodes (SPADs) is large.

[0072] The first aspect of this invention provides a quenching circuit 1 for an avalanche diode (SPAD) to reduce the power consumption of the quenching circuit 1 and the overall power consumption of the imaging system.

[0073] SPAD avalanche diodes can be positively or negatively biased, depending on the specific circuit design.

[0074] Taking a forward-biased avalanche diode (SPAD) as an example, the cathode of the SPAD is connected to a forward bias voltage, and the anode of the SPAD is connected to the quenching and reset circuit 10. Figure 4 As shown, during the reset phase, i.e., when the clock signal is high and there is no photon trigger, the anode voltage VA0 of the avalanche diode SPAD decreases. When it drops to the preset threshold voltage Vth, the output signal VA1 of the comparator circuit 30 flips from low to high. That is, the output signal VA1 of the comparator circuit 30 only has a rising edge, where Vth is the preset threshold voltage.

[0075] During the reset phase, if a photon triggers the process, the following two scenarios may occur.

[0076] Firstly, such as Figure 5 As shown, the output signal VA1 of the comparator circuit 30 has a falling edge in addition to the rising edge. That is, after the voltage at the second terminal of the avalanche diode SPAD drops to the preset threshold voltage Vth, there is photon triggering, and the anode voltage VA0 of the avalanche diode SPAD rises. When it rises to the preset threshold voltage Vth, the output signal VA1 of the comparator circuit 30 will generate a falling edge.

[0077] Secondly, such as Figure 6 As shown, the voltage at the second terminal of the avalanche diode SPAD remains high, and the output signal VA1 of the comparator circuit 30 has neither a rising edge nor a falling edge. This is because the anode voltage VA0 of the avalanche diode SPAD is photon-triggered before it drops to the preset threshold voltage Vth. Subsequently, the voltage at the second terminal of the avalanche diode SPAD remains higher than the preset threshold voltage Vth. At this time, the output signal VA1 of the comparator circuit 30 remains at a low level.

[0078] Alternatively, assume the avalanche diode SPAD is negatively biased, with the anode of the SPAD connected to the negative bias voltage, and the cathode of the SPAD connected to the quenching and reset circuit 10. Figure 15 As shown, the avalanche diode SPAD is in the quenching stage when the clock signal is high and in the reset stage when the clock signal is low.

[0079] During the reset phase, if a photon triggers the process, the following two scenarios may occur.

[0080] Firstly, such as Figure 16 As shown, the output signal VA1 of the comparator circuit 30 has a rising edge in addition to the falling edge. That is, after the voltage at the second terminal of the avalanche diode SPAD rises to the preset threshold voltage Vth during the reset phase, there is photon triggering, and the anode voltage VA0 of the avalanche diode SPAD drops. When it drops to the preset threshold voltage Vth, the output signal VA1 of the comparator circuit 30 will generate a rising edge.

[0081] Secondly, such as Figure 17 As shown, the cathode voltage VC0 of the avalanche diode SPAD remains low, and the output signal VA1 of the comparator circuit 30 has neither a rising edge nor a falling edge. This is because the cathode voltage VC0 of the avalanche diode SPAD is photon-triggered before rising to the preset threshold voltage Vth. Subsequently, the voltage at the second terminal of the avalanche diode SPAD remains below the preset threshold voltage Vth. At this time, the output signal VA1 of the comparator circuit 30 remains at a high level.

[0082] Therefore, to avoid additional power consumption caused by the quenching circuit 1 being triggered during the reset phase, this embodiment proposes a quenching circuit 1 for an avalanche diode SPAD, such as... Figure 7 or Figure 18 As shown, the quenching circuit 1 of the avalanche diode SPAD includes:

[0083] The bias voltage circuit 50 is connected to the first terminal of the avalanche diode SPAD and is used to provide a bias voltage.

[0084] Quenching and reset circuit 10 is connected to the second terminal of avalanche diode SPAD. Quenching and reset circuit 10 is used to quench or reset avalanche diode SPAD according to quenching signal or reset signal.

[0085] Delay circuit 20 is used to delay the input first clock signal CK1 for a preset time and output it as a second clock signal CK2. The first clock signal CK1 is composed of alternating first level signals and second level signals with opposite levels.

[0086] The comparator circuit 30 is connected to the second terminal of the avalanche diode SPAD. The comparator circuit 30 is used to output a third level signal when the input voltage is greater than or equal to a preset threshold voltage Vth, and to output a fourth level signal with the opposite level to the third level signal when the input voltage is less than the preset threshold voltage Vth.

[0087] The detection control circuit 40 is connected to the comparator circuit 30, the delay circuit 20, and the quenching and reset circuit 10, respectively. The detection control circuit 40 is used for:

[0088] A reset signal is output during the output period of each second level signal, and a quenching signal is output when the first change signal generated by the comparison circuit 30 is detected, or when the second change signal generated by the delay circuit 20 is detected but the second change signal generated by the comparison circuit 30 is not detected.

[0089] A quenching signal is output during the output period of the first level signal, and the first change signal and the second change signal are each other's rising edge and falling edge.

[0090] In this embodiment, firstly... Figure 7 The quenching circuit 1 shown is explained using the forward bias of the avalanche diode SPAD.

[0091] like Figure 7 As shown, the cathode of the avalanche diode SPAD is positively biased, and the anode of the avalanche diode SPAD is connected to the quenching reset circuit 10 and the comparator circuit 30. The detection control circuit 40 is connected to the output terminal of the comparator circuit 30 and detects the change signal of the output of the comparator circuit 30. The output signal VA1 of the comparator circuit 30 can be used as the output signal of the quenching circuit 1. The signal processing circuit at the back end can determine the photon count rate and image information based on the output signal of the quenching circuit 1.

[0092] like Figure 8As shown, the quenching signal and the reset signal are high and low level signals, respectively, and form the output clock CK0 of the detection and control circuit 40. At this time, the second level signal is high level and the first level signal is low level. When the quenching circuit 1 is working in the quenching stage, the quenching transistor M1 in the quenching and reset circuit 10 receives the low level quenching signal and turns off. The anode voltage VA0 of the avalanche diode SPAD rises and changes until it stabilizes at Vex, and then enters the reset stage. The detection and control circuit 40 first outputs a high level reset signal. The quenching transistor M1 of the quenching and reset circuit 10 receives the high level signal and is triggered to conduct. At this time, the anode voltage VA0 of the avalanche diode SPAD begins to decrease. When it drops to the preset threshold voltage Vth, the comparator circuit 30... The output signal VA1 flips, switching from low level to high level. If there is no photon trigger during the reset phase, the voltage of the avalanche diode SPAD will start to rise in the next quenching phase until it stabilizes at Vex. The output signal VA1 of the comparator circuit 30 will switch to low level when the voltage of the avalanche diode SPAD rises to the preset threshold voltage Vth in the next quenching phase. In this state, the quenching signal and the reset signal are high and low level signals respectively and form the output clock CK0 of the detection control circuit 40. The output clock CK0 of the detection control circuit 40 is in phase with the high and low levels of the first clock signal CK1. Vex is the over-bias voltage of the avalanche diode SPAD, and VBK is the avalanche voltage of the avalanche diode SPAD.

[0093] When the above situation occurs, such as Figure 9 As shown, during the reset phase, when the anode voltage VA0 of the avalanche diode SPAD is triggered by a photon after dropping to the preset threshold voltage Vth, the voltage of the avalanche diode SPAD will rise after the drop, causing the comparator circuit 30 to have a rising edge and a falling edge. The first change signal is the falling edge, and the second change signal is the rising edge.

[0094] In this situation, such as Figure 10 As shown, during the output period of the second level signal, which is the reset period, after the reset signal is output, the detection control circuit 40 will detect the falling edge generated by the comparison circuit 30. At this time, the detection control circuit 40 outputs a quenching signal, that is, the output clock CK0 of the detection control circuit 40 switches to a low level signal and controls the quenching transistor M1 in the quenching reset circuit 10 to turn off. The anode voltage VA0 of the avalanche diode SPAD increases rapidly to Vex, so the avalanche diode SPAD can be quickly quenched and no longer respond to subsequent photons.

[0095] And such as Figure 11As shown, when the avalanche diode SPAD switches from the quenching stage to the reset stage, the input clock of the quenching and reset circuit 10 switches from low level to high level. At this time, the anode voltage VA0 of the avalanche diode SPAD starts to decrease, and when it decreases to the preset threshold voltage Vth, the output signal VA1 of the comparator circuit 30 switches from low level to high level. The time for the anode voltage VA0 of the avalanche diode SPAD to decrease from Vex to the preset threshold voltage Vth is limited to td1. In this embodiment, the preset delay time of the delay circuit 20 is set to td2, where td2>td1.

[0096] like Figure 12 As shown, when the above-mentioned situation two occurs during the reset phase, the voltage at the second terminal of the avalanche diode SPAD remains high, and the output signal VA1 of the comparator circuit 30 has neither a rising edge nor a falling edge. This is because the anode voltage VA0 of the avalanche diode SPAD is photon-triggered before it drops to the preset threshold voltage Vth. Subsequently, the voltage at the second terminal of the avalanche diode SPAD remains above the preset threshold voltage Vth. At this time, the output signal VA1 of the comparator circuit 30 remains at a low level.

[0097] like Figure 13 As shown, assuming that during the reset phase, i.e. the output period of the second level signal of the first clock signal CK1, if there is no photon trigger, the anode voltage VA0 of the avalanche diode SPAD will drop, and when it drops to the preset threshold voltage Vth, the output signal VA1 of the comparator circuit 30 switches to the high level. At this time, the detection control circuit 40 first detects the second change signal, the detection control circuit 40 maintains the output reset signal, and controls the quenching reset circuit 10 to remain in the reset state.

[0098] And when the above-mentioned situation two occurs during the reset phase, that is, during the reset phase, there is photon triggering before the anode voltage VA0 of the avalanche diode SPAD drops to the preset threshold voltage Vth, causing the anode voltage VA0 of the avalanche diode SPAD to remain greater than the preset threshold voltage Vth, and the output signal VA1 of the comparator circuit 30 remains at a low level.

[0099] In this case, such as Figure 14As shown, after the detection control circuit 40 outputs the reset signal, it does not detect the second change signal generated by the comparison circuit 30. At the same time, since the second clock signal CK2 is in phase with the first clock signal CK1, the detection control circuit 40 can detect the rising edge of the second clock signal CK2. When the rising edge of the second clock signal CK2 is detected, the detection control circuit 40 outputs a quenching signal, that is, the output clock CK0 of the detection control circuit 40 switches to a low level signal and controls the quenching transistor M1 in the quenching reset circuit 10 to turn off. The anode voltage VA0 of the avalanche diode SPAD increases rapidly to Vex, so the avalanche diode SPAD can be quickly quenched and no longer respond to subsequent photons.

[0100] Meanwhile, when entering the quenching stage, that is, when the first clock signal CK1 switches to output the first level signal, the detection control circuit 40 outputs a quenching signal, the quenching tube M1 in the quenching reset circuit 10 receives a low level signal and turns off, and the anode voltage VA0 of the avalanche diode SPAD changes from rising to stabilizing at Vex.

[0101] By detecting the falling edge of the comparison circuit 30 and the rising edge generated by the delay circuit 20 during the reset phase, it can be determined whether the avalanche diode SPAD is triggered during the reset phase. When it is determined that the avalanche diode SPAD is triggered during the reset phase, a quenching signal is output to quickly turn off the quenching transistor M1 in the quenching reset circuit 10 in advance. Since the quenching transistor M1 is in the off state, it will not form a path with the avalanche diode SPAD, that is, no power consumption is generated, thereby reducing the DC power consumption generated by the quenching circuit 1 and reducing the overall power consumption of the imaging system.

[0102] And such as Figure 18 As shown, the explanation uses the avalanche diode SPAD with negative bias.

[0103] like Figure 18 As shown, the anode of the avalanche diode SPAD is negatively biased, and the cathode of the avalanche diode SPAD is connected to the quenching reset circuit 10 and the comparator circuit 30. At this time, the second level signal is low and the first level signal is high.

[0104] like Figure 19As shown, the quenching signal and the reset signal are high and low level signals, respectively, forming the output clock CK0 of the detection and control circuit 40. When the quenching circuit 1 is working in the quenching stage, that is, during the output period of the first level signal, the detection and control circuit 40 outputs a high-level quenching signal. The quenching transistor M1 in the quenching and reset circuit 10 receives the high-level quenching signal and turns off. The cathode voltage VC0 of the avalanche diode SPAD stabilizes at 0 after a decrease, and then enters the reset stage, that is, during the output period of the second level signal. The detection and control circuit 40 outputs a low-level reset signal, and the quenching transistor M1 in the quenching and reset circuit 10 receives the low-level signal and is triggered to conduct. At this time, the avalanche diode SPAD... The cathode voltage VC0 of D starts to rise. When it rises to the preset threshold voltage Vth, the output signal VA1 of the comparator circuit 30 flips and switches from high level to low level. If there is no photon trigger during the reset phase, the voltage of the avalanche diode SPAD will start to drop in the next quenching phase until it stabilizes at 0. The output signal VA1 of the comparator circuit 30 will switch to high level when the voltage of the avalanche diode SPAD drops to the preset threshold voltage Vth in the next quenching phase. In this state, the output clock CK0 of the detection control circuit 40 is in phase with the high and low levels of the first clock signal CK1. Vex is the stable voltage of the avalanche diode SPAD when it is reset.

[0105] When the above situation occurs, such as Figure 20 As shown, during the reset phase, when the cathode voltage VCO of the avalanche diode SPAD is triggered by a photon after rising to the preset threshold voltage Vth, the voltage of the avalanche diode SPAD will drop after rising, causing the comparator circuit 30 to have a falling edge and a rising edge. The first change signal is the rising edge, and the second change signal is the falling edge.

[0106] In this situation, such as Figure 20 As shown, during the output period of the second level signal, which is also the reset period, after the reset signal is output, the second level signal is low. The detection control circuit 40 will detect the rising edge generated by the comparison circuit 30. At this time, the detection control circuit 40 outputs a quenching signal, that is, the output clock CK0 of the detection control circuit 40 switches to a high level signal and controls the quenching transistor M1 in the quenching reset circuit 10 to turn off. The cathode voltage VC0 of the avalanche diode SPAD drops rapidly to 0, so the avalanche diode SPAD can be quickly quenched and no longer respond to subsequent photons.

[0107] And such as Figure 21As shown, when the avalanche diode SPAD switches from the quenching stage to the reset stage, the input clock of the quenching and reset circuit 10 switches from high level to low level. At this time, the cathode voltage VCO of the avalanche diode SPAD starts to rise, and when it rises to the preset threshold voltage Vth, the output signal VA1 of the comparator circuit 30 switches from high level to low level. The time for the cathode voltage VCO of the avalanche diode SPAD to rise from 0 to the preset threshold voltage Vth is limited to td1. In this embodiment, the preset delay time of the delay circuit 20 is set to td2, where td2>td1.

[0108] like Figure 22 As shown, when the above-mentioned situation two occurs during the reset phase, the cathode voltage VC0 of the avalanche diode SPAD remains high, and the output signal VA1 of the comparator circuit 30 has neither rising edge nor falling edge. The reason is that there is photon triggering before the cathode voltage VC0 of the avalanche diode SPAD rises to the preset threshold voltage Vth. Subsequently, the cathode voltage VC0 of the avalanche diode SPAD remains in a state lower than the preset threshold voltage Vth. At this time, the output signal VA1 of the comparator circuit 30 remains in a high level state.

[0109] like Figure 21 As shown, assuming that during the reset phase, i.e. the output period of the second level signal of the first clock signal CK1, if there is no photon trigger, the cathode voltage VC0 of the avalanche diode SPAD will rise, and when it rises to the preset threshold voltage Vth, the output signal VA1 of the comparator circuit 30 switches to a low level. At this time, the detection control circuit 40 first detects the second change signal, the detection control circuit 40 maintains the output reset signal, and controls the quenching reset circuit 10 to remain in the reset state.

[0110] And when the above-mentioned situation two occurs during the reset phase, that is, during the reset phase, there is photon triggering before the cathode voltage VC0 of the avalanche diode SPAD rises to the preset threshold voltage Vth, causing the cathode voltage VC0 of the avalanche diode SPAD to remain below the preset threshold voltage Vth, and the output signal VA1 of the comparator circuit 30 remains at a high level.

[0111] In this case, such as Figure 22As shown, after the detection control circuit 40 outputs the reset signal, it does not detect the second change signal generated by the comparison circuit 30. At the same time, since the second clock signal CK2 is in phase with the first clock signal CK1, the detection control circuit 40 can detect the falling edge of the second clock signal CK2. When the falling edge of the second clock signal CK2 is detected, the detection control circuit 40 outputs a quenching signal, that is, the output clock CK0 of the detection control circuit 40 switches to a high level signal and controls the quenching transistor M1 in the quenching reset circuit 10 to turn off. The cathode voltage VC0 of the avalanche diode SPAD decreases rapidly to 0, so the avalanche diode SPAD can be quickly quenched and no longer respond to subsequent photons.

[0112] Meanwhile, when entering the quenching stage, that is, when the first clock signal CK1 switches to output the first level signal, the detection control circuit 40 outputs a quenching signal, the quenching tube M1 in the quenching reset circuit 10 receives a high-level signal and turns off, and the cathode voltage VCO of the avalanche diode SPAD stabilizes at 0 after a decrease.

[0113] By detecting the rising edge of the comparator circuit 30 and the falling edge generated by the delay circuit 20 during the reset phase, it can be determined whether the avalanche diode SPAD is triggered during the reset phase. When it is determined that the avalanche diode SPAD is triggered during the reset phase, a quenching signal is output to quickly turn off the quenching transistor M1 in the quenching reset circuit 10 in advance. Since the quenching transistor M1 is in the off state, it will not form a path with the avalanche diode SPAD, that is, no power consumption is generated, thereby reducing the DC power consumption generated by the quenching circuit 1 and reducing the overall power consumption of the imaging system.

[0114] The detection and control circuit 40 can be configured based on the biasing method of the avalanche diode SPAD and the direction of change of the output voltage of the avalanche diode SPAD. In an optional embodiment, such as... Figure 23 As shown, the detection control circuit 40 includes:

[0115] The first detection circuit 41 is connected to the output terminal of the comparison circuit 30. The first detection circuit 41 is used to output a first detection signal when a first change signal is detected or to trigger the output of a second detection signal when no first change signal is detected during the output period of each second level signal.

[0116] The second detection circuit 42 is connected to the output terminal of the comparison circuit 30 and the output terminal of the delay circuit 20 respectively. The second detection circuit 42 is used to output a third detection signal when the second change signal generated by the delay circuit 20 is detected during the output period of each second level signal and the second change signal generated by the comparison circuit 30 is not detected; otherwise, it outputs a fourth detection signal.

[0117] The logic control circuit 43 is connected to the first detection circuit 41, the second detection circuit 42, and the quenching and reset circuit 10, respectively. The logic control circuit 43 is used for:

[0118] A reset signal is output during the output period of each second level signal, and a quench signal is output when the first detection signal or the third detection signal is received, or a reset signal is output when the second detection signal or the fourth detection signal is received;

[0119] A quenching signal is output during the output period of the first level signal.

[0120] In this embodiment, firstly... Figure 23 The quenching circuit 1 shown is explained using the forward bias of the avalanche diode SPAD.

[0121] like Figure 23 As shown, the cathode of the avalanche diode SPAD is forward biased, and the anode of the avalanche diode SPAD is connected to the quenching reset circuit 10 and the comparator circuit 30. The output terminal of the comparator circuit 30 is connected to the first detection circuit 41 and the second detection circuit 42 respectively. The first detection circuit 41 is used to detect whether the output signal VA1 of the comparator circuit 30 has a falling edge, and the second detection circuit 42 is used to detect whether the output signal VA1 of the comparator circuit 30 has a rising edge. The second detection circuit 42 is also used to detect whether the second clock signal CK2 of the delay circuit 20 has a rising edge.

[0122] like Figure 24 As shown, when the quenching circuit 1 is working in the quenching stage, the quenching transistor M1 in the quenching reset circuit 10 receives a low-level signal and turns off. The anode voltage VA0 of the avalanche diode SPAD rises and changes until it stabilizes at Vex, and then enters the reset stage. The logic control circuit 43 first outputs a high-level reset signal. The quenching transistor M1 in the quenching reset circuit 10 receives a high-level signal and is triggered to turn on. At this time, the anode voltage VA0 of the avalanche diode SPAD begins to decrease. When it drops to the preset threshold voltage Vth, the output signal VA1 of the comparator circuit 30 flips and switches from low level to high level. If there is no photon triggering during the reset stage, the voltage of the avalanche diode SPAD will start to rise in the next quenching stage until it stabilizes at Vex. Here, Vex is the overbias voltage of the avalanche diode SPAD, and VBK is the avalanche voltage of the avalanche diode SPAD.

[0123] When the above situation occurs, such as Figure 25As shown, during the reset phase, when the anode voltage VA0 of the avalanche diode SPAD is triggered by a photon after dropping to the preset threshold voltage Vth, the voltage of the avalanche diode SPAD will rise after the drop, causing the comparator circuit 30 to have a rising edge and a falling edge. The first change signal is the falling edge, and the second change signal is the rising edge.

[0124] In this situation, such as Figure 25 As shown, during the output period of the second level signal, i.e. the reset period, when the logic control circuit 43 outputs a high-level reset signal, the first detection circuit 41 will detect the falling edge generated by the comparator circuit 30. At this time, the first detection circuit 41 outputs a first detection signal, which can be a low-level signal. When the logic control circuit 43 receives the low-level signal, it triggers the output quenching signal, i.e., the output clock CK0 of the logic control circuit 43 switches to a low-level signal and controls the quenching transistor M1 in the quenching reset circuit 10 to turn off. The anode voltage VA0 of the avalanche diode SPAD rapidly increases to Vex, and the avalanche diode SPAD can thus be quickly quenched and no longer respond to subsequent photons.

[0125] Similarly, during the reset period, if there is no photon trigger and the first detection circuit 41 does not detect a falling edge, the first detection circuit 41 outputs a second detection signal. The second detection signal can be an opposite level signal to the first detection signal, such as a high level signal. Here, Q1 represents the output signal of the first detection circuit 41.

[0126] And such as Figure 26 As shown, when the avalanche diode SPAD switches from the quenching stage to the reset stage, the input clock of the quenching and reset circuit 10 switches from low level to high level. At this time, the anode voltage VA0 of the avalanche diode SPAD starts to decrease, and when it decreases to the preset threshold voltage Vth, the output signal VA1 of the comparator circuit 30 switches from low level to high level. The time for the anode voltage VA0 of the avalanche diode SPAD to decrease from Vex to the preset threshold voltage Vth is limited to td1. In this embodiment, the preset delay time of the delay circuit 20 is set to td2, where td2>td1.

[0127] like Figure 26 As shown, assuming that during the reset phase, i.e. the output period of the second level signal of the first clock signal CK1, if there is no photon trigger, the anode voltage VA0 of the avalanche diode SPAD will drop, and when it drops to the preset threshold voltage Vth, the output signal VA1 of the comparator circuit 30 switches to the high level. At this time, the second change signal is detected first, the detection control circuit 40 maintains the output reset signal, and controls the quenching reset circuit 10 to remain in the reset state.

[0128] And when the above-mentioned situation two occurs during the reset phase, that is, during the reset phase, there is photon triggering before the anode voltage VA0 of the avalanche diode SPAD drops to the preset threshold voltage Vth, causing the anode voltage VA0 of the avalanche diode SPAD to remain greater than the preset threshold voltage Vth, and the output signal VA1 of the comparator circuit 30 remains at a low level.

[0129] In this case, such as Figure 27 As shown, after the logic control circuit 43 outputs a reset signal, the second detection circuit 42 does not detect the second change signal generated by the comparison circuit 30. At the same time, since the second clock signal CK2 is in phase with the first clock signal CK1, the second detection circuit 42 can detect the rising edge of the second clock signal CK2. When the rising edge of the second clock signal CK2 is detected, the second detection circuit 42 outputs a third detection signal and triggers the logic control circuit 43 to output a quenching signal. That is, the output clock CK0 of the logic control circuit 43 switches to a low level signal and controls the quenching transistor M1 in the quenching reset circuit 10 to turn off. The anode voltage VA0 of the avalanche diode SPAD increases rapidly to Vex, so the avalanche diode SPAD can be quickly quenched and no longer respond to subsequent photons.

[0130] When the second detection circuit 42 detects the second change signal generated by the comparison circuit 30, the second detection circuit 42 outputs a fourth detection signal. The third detection signal and the fourth detection signal can be high and low level signals respectively. At this time, the logic control circuit 43 can maintain the output of a reset signal, where Q2 represents the output signal of the second detection circuit 42.

[0131] Meanwhile, when entering the quenching stage, that is, when the first clock signal CK1 switches to output the first level signal, the detection control circuit 40 outputs a quenching signal, the quenching tube M1 in the quenching reset circuit 10 receives a low level signal and turns off, and the anode voltage VA0 of the avalanche diode SPAD changes from rising to stabilizing at Vex.

[0132] During the reset phase, by using the first detection circuit 41 and the second detection circuit 42 to detect the falling edge of the comparison circuit 30 and the rising edge generated by the detection delay circuit 20 respectively, it is possible to detect and determine whether the avalanche diode SPAD is triggered during the reset phase. When it is determined that the avalanche diode SPAD is triggered during the reset phase, the logic control circuit 43 can output a quenching signal to quickly turn off the quenching transistor M1 in the quenching reset circuit 10 in advance. Since the quenching transistor M1 is in the off state, it will not form a path with the avalanche diode SPAD, that is, no power consumption is generated, thereby reducing the DC power consumption generated by the quenching circuit 1 and reducing the overall power consumption of the imaging system.

[0133] And such as Figure 18 and Figure 23As shown, the avalanche diode SPAD negative is used for illustration.

[0134] like Figure 18 As shown, the anode of the avalanche diode SPAD is negatively biased, and the cathode of the avalanche diode SPAD is connected to the quenching reset circuit 10 and the comparator circuit 30. The output terminal of the comparator circuit 30 is connected to the first detection circuit 41 and the second detection circuit 42 respectively. The first detection circuit 41 is used to detect whether the output signal VA1 of the comparator circuit 30 has a rising edge, and the second detection circuit 42 is used to detect whether the output signal VA1 of the comparator circuit 30 has a falling edge. The second detection circuit 42 is also used to detect whether the second clock signal CK2 of the delay circuit 20 has a rising edge.

[0135] like Figure 28 As shown, when the quenching circuit 1 is working in the quenching stage, the logic control circuit 43 outputs a high-level quenching signal. The quenching transistor M1 in the quenching reset circuit 10 receives the high-level signal and turns off. The cathode voltage VC0 of the avalanche diode SPAD stabilizes at 0 after a decrease and then enters the reset stage. The logic control circuit 43 outputs a low-level reset signal. The quenching transistor M1 in the quenching reset circuit 10 receives the low-level signal and is triggered to turn on. At this time, the cathode voltage VC0 of the avalanche diode SPAD begins to rise. When it rises to the preset threshold voltage Vth, the output signal VA1 of the comparator circuit 30 flips and switches from high level to low level.

[0136] When the above situation occurs, such as Figure 29 As shown, during the reset phase, when the cathode voltage VCO of the avalanche diode SPAD is triggered by a photon after rising to the preset threshold voltage Vth, the voltage of the avalanche diode SPAD will drop after rising, causing the comparator circuit 30 to have a falling edge and a rising edge. The first change signal is the rising edge, and the second change signal is the falling edge.

[0137] In this situation, such as Figure 29 As shown, after the logic control circuit 43 outputs a low-level reset signal, the first detection circuit 41 will detect the rising edge generated by the comparator circuit 30. At this time, the first detection circuit 41 outputs a first detection signal, which can be a high-level signal. When the logic control circuit 43 receives the high-level signal, it triggers the output quenching signal, that is, the output clock CK0 of the logic control circuit 43 switches to a high-level signal and controls the quenching transistor M1 in the quenching reset circuit 10 to turn off. The cathode voltage VC0 of the avalanche diode SPAD drops rapidly to 0, so the avalanche diode SPAD can be quickly quenched and no longer respond to subsequent photons.

[0138] Similarly, during the reset period, if there is no photon trigger and the first detection circuit 41 does not detect a rising edge, the first detection circuit 41 outputs a second detection signal. The second detection signal can be an opposite level signal to the first detection signal, such as a low level signal. Here, Q1 represents the output signal of the first detection circuit 41.

[0139] And such as Figure 30 As shown, when the avalanche diode SPAD switches from the quenching stage to the reset stage, the input clock of the quenching and reset circuit 10 switches from high level to low level. At this time, the cathode voltage VCO of the avalanche diode SPAD starts to rise, and when it rises to the preset threshold voltage Vth, the output signal VA1 of the comparator circuit 30 switches from high level to low level. The time for the cathode voltage VCO of the avalanche diode SPAD to rise from 0 to the preset threshold voltage Vth is limited to td1. In this embodiment, the preset delay time of the delay circuit 20 is set to td2, where td2>td1.

[0140] like Figure 30 As shown, assuming that during the reset phase, i.e. the output period of the second level signal of the first clock signal CK1, if there is no photon trigger, the cathode voltage VC0 of the avalanche diode SPAD will rise, and when it rises to the preset threshold voltage Vth, the output signal VA1 of the comparator circuit 30 switches to the low level. At this time, the second change signal is detected first, the detection control circuit 40 maintains the output reset signal, and controls the quenching reset circuit 10 to remain in the reset state.

[0141] And when the above-mentioned situation two occurs during the reset phase, that is, during the reset phase, there is photon triggering before the cathode voltage VC0 of the avalanche diode SPAD rises to the preset threshold voltage Vth, causing the cathode voltage VC0 of the avalanche diode SPAD to remain below the preset threshold voltage Vth, and the output signal VA1 of the comparator circuit 30 remains at a high level.

[0142] In this case, such as Figure 31 As shown, after the logic control circuit 43 outputs a reset signal, the second detection circuit 42 does not detect the second change signal generated by the comparison circuit 30. At the same time, since the second clock signal CK2 is in phase with the first clock signal CK1, the second detection circuit 42 can detect the falling edge of the second clock signal CK2. When the falling edge of the second clock signal CK2 is detected, the second detection circuit 42 outputs a third detection signal and triggers the logic control circuit 43 to output a quenching signal. That is, the output clock CK0 of the logic control circuit 43 switches to a high level signal and controls the quenching transistor M1 in the quenching reset circuit 10 to turn off. The cathode voltage VC0 of the avalanche diode SPAD drops rapidly to 0, so the avalanche diode SPAD can be quickly quenched and no longer respond to subsequent photons.

[0143] When the second detection circuit 42 detects the second change signal generated by the comparison circuit 30, the second detection circuit 42 outputs a fourth detection signal. The third detection signal and the fourth detection signal can be high and low level signals respectively. At this time, the logic control circuit 43 can maintain the output of a reset signal, where Q2 represents the output signal of the second detection circuit 42.

[0144] Meanwhile, when entering the quenching stage, that is, when the first clock signal CK1 switches to output the first level signal, the detection control circuit 40 outputs a quenching signal, the quenching tube M1 in the quenching reset circuit 10 receives a high-level signal and turns off, and the cathode voltage VCO of the avalanche diode SPAD stabilizes at 0 after a decrease.

[0145] During the reset phase, by using the first detection circuit 41 and the second detection circuit 42 to detect the rising edge of the comparison circuit 30 and the falling edge generated by the detection delay circuit 20 respectively, it is possible to detect and determine whether the avalanche diode SPAD is triggered during the reset phase. When it is determined that the avalanche diode SPAD is triggered during the reset phase, the logic control circuit 43 can output a quenching signal to quickly turn off the quenching transistor M1 in the quenching reset circuit 10 in advance. Since the quenching transistor M1 is in the off state, it will not form a path with the avalanche diode SPAD, that is, no power consumption is generated, thereby reducing the DC power consumption generated by the quenching circuit 1 and reducing the overall power consumption of the imaging system.

[0146] Furthermore, to improve the trigger detection efficiency during the reset phase, different preset threshold voltages Vth can be set, thereby quickly detecting the trigger event when the avalanche diode SPAD is triggered during the reset phase, such as... Figure 32 As shown, in an optional embodiment, the delay circuit 20 includes multiple delay circuits. Each delay circuit 20 is used to delay the input first clock signal CK1 for a preset time and then output a second clock signal CK2. The delay times of each delay circuit 20 are not equal.

[0147] The comparator circuit 30 includes multiple circuits. Each comparator circuit 30 is used to compare the input voltage with a preset threshold voltage Vth respectively, and outputs a third level signal when the input voltage is greater than or equal to the preset threshold voltage Vth, or outputs a fourth level signal when the input voltage is less than or equal to the preset threshold voltage Vth. The preset threshold voltage Vth corresponding to each comparator circuit 30 is not equal.

[0148] The first detection circuit 41 includes multiple circuits, and each first detection circuit 41 is connected to the comparison circuit 30 in a corresponding manner.

[0149] The second detection circuit 42 includes multiple circuits, and each second detection circuit 42 is connected to the output terminal of a comparison circuit 30 and the output terminal of a delay circuit 20 respectively.

[0150] The logic control circuit 43 is connected to multiple first detection circuits 41 and multiple second detection circuits 42 respectively. The logic control circuit 43 is used for:

[0151] A reset signal is output during the output period of each second level signal, and a quench signal is output when one of the first detection signals or the third detection signal is received first, or a reset signal is output when one of the second detection signals or the fourth detection signal is received first.

[0152] A quenching signal is output during the output period of the first level signal.

[0153] In this embodiment, a multi-threshold detection strategy is adopted. The preset threshold voltage Vth corresponding to each comparison circuit 30 is not equal, thus allowing the voltage change at the second terminal of the avalanche diode SPAD from the reset phase to the quenching circuit 1 (0~Vex) to be divided into multiple segments for refined detection. For example, taking the forward bias voltage of the avalanche diode SPAD as an example, during the quenching phase, such as... Figure 24 As shown, the quenching transistor M1 in the quenching reset circuit 10 is turned off when it receives a low-level signal. The anode voltage VA0 of the avalanche diode SPAD rises and then stabilizes at Vex before entering the reset stage. The quenching transistor M1 in the quenching reset circuit 10 is triggered to turn on when it receives a high-level signal. At this time, the anode voltage VA0 of the avalanche diode SPAD begins to drop until it drops to 0. Assume that the preset threshold voltages Vth of the multiple comparator circuits 30 are 0.4Vex and 0.6Vex, respectively.

[0154] When the above situation occurs, such as Figure 25 As shown, during the output period of the second level signal, i.e. the reset period, the anode voltage VA0 of the avalanche diode SPAD first drops to 0.6Vex. The comparator circuit 30 corresponding to the preset threshold voltage Vth of 0.6Vex first outputs a falling edge. The first detection circuit 41 connected to the comparator circuit 30 will first detect the falling edge. At this time, the first detection circuit 41 first outputs a first detection signal. When the logic control circuit 43 receives the first detection signal, it triggers the output quenching signal in advance and controls the quenching tube M1 in the quenching reset circuit 10 to turn off. The anode voltage VA0 of the avalanche diode SPAD quickly increases to Vex, so the avalanche diode SPAD can be quickly quenched and no longer respond to subsequent photons.

[0155] Furthermore, multiple delay circuits 20 can delay the first clock signal CK1 for different preset durations. For example, if the original preset duration is 0.5ns, and then two delay circuits 20 are set, assuming that there are two comparator circuits 30, and the preset threshold voltages Vth corresponding to the two comparator circuits 30 are not equal, and the anode voltage VA0 of the avalanche diode SPAD drops to 0.4Vex and 0.6Vex at times td1_1 and td1_2 respectively during the reset phase, then the preset durations of the corresponding delay circuits 20 are td2_1 and td2_2 respectively. Therefore, td2_1 > td1_1 and td2_2 > td1_2. For example, if td1_1 and td1_2 are 0.5ns and 0.3ns respectively, then td2_1 and td2_2 can be set to 0.6ns and 0.4ns respectively.

[0156] And when situation two occurs during the reset phase, such as Figure 27 As shown, the second detection circuit 42 did not detect the second change signal generated by the comparison circuit 30. At the same time, since the second clock signal CK2 and the first clock signal CK1 are in phase, the second detection circuit 42 can first detect the rising edge of the second clock signal CK2 with a preset delay of 0.4ns. When the rising edge of the second clock signal CK2 is detected, the second detection circuit 42 first outputs the third detection signal and triggers the logic control circuit 43 to first output the quenching signal and control the quenching tube M1 in the quenching reset circuit 10 to turn off. The anode voltage VA0 of the avalanche diode SPAD increases rapidly to Vex, so the avalanche diode SPAD can be quickly quenched and no longer respond to subsequent photons.

[0157] During the reset phase, by setting multiple delay circuits 20, multiple comparison circuits 30, multiple first detection circuits 41 and multiple second detection circuits 42, different threshold comparison and preset duration settings can be set, thereby enabling earlier control of the quenching tube M1, further reducing the power consumption of the quenching circuit 1 and the overall power consumption of the imaging system.

[0158] The quenching and reset circuit 10 can adopt the corresponding quenching transistor M1 and capacitor Cpar structure. The comparison circuit 30 can adopt the corresponding comparator, inverter, etc. The delay circuit 20 can adopt multiple inverters, non-inverters, or delay circuits. The first detection circuit 41 and the second detection circuit 42 can adopt the corresponding flip-flop, latch, etc. structure. The logic control circuit 43 can adopt the corresponding logic gate, controller, etc. structure.

[0159] In an optional embodiment, the quench reset circuit 10 includes a quench switch 11 and a capacitor Cpar;

[0160] The first terminal of the quenching switch 11, the first terminal of the capacitor Cpar, and the second terminal of the avalanche diode SPAD are connected. The second terminal of the quenching switch 11 is grounded or connected to the first positive voltage terminal Vbias.

[0161] The first detection circuit 41 includes a first D flip-flop DFF1;

[0162] The data terminal of the first D flip-flop DFF1 is connected to the second positive voltage terminal VCC. The corresponding clock terminal of the first D flip-flop DFF1 is connected to the output terminal of the comparator circuit 30. The corresponding reset terminal of the first D flip-flop DFF1 is used to input the first clock signal CK1. The output terminal of the first D flip-flop DFF1 constitutes the output terminal of the first detection circuit 41.

[0163] The second detection circuit 42 includes a second D flip-flop DFF2 and a third D flip-flop DFF3;

[0164] The data terminal of the second D flip-flop DFF2 is connected to the second positive voltage terminal VCC. The corresponding clock terminal of the second D flip-flop DFF2 is connected to the output terminal of the comparator circuit 30. The corresponding reset terminals of the second D flip-flop DFF2 and the third D flip-flop DFF3 are used to input the first clock signal CK1. The corresponding clock terminal of the third D flip-flop DFF3 is used to input the corresponding second clock signal CK2. The corresponding output terminal of the second D flip-flop DFF2 is connected to the data terminal of the third D flip-flop DFF3. The corresponding output terminal of the third D flip-flop DFF3 constitutes the output terminal of the second detection circuit 42.

[0165] When the first detection circuit 41 and the second detection circuit 42 are included, the logic control circuit 43 includes a first logic gate circuit 431. The two input terminals of the first logic gate circuit 431 are respectively connected to the output terminal of the first detection circuit 41 and the output terminal of the second detection circuit 42. The other input terminal of the first logic gate circuit 431 is also used to input the first clock signal CK1. The output terminal of the first logic gate circuit 431 constitutes the output terminal of the logic control circuit 43.

[0166] Depending on the different biasing methods of the avalanche diode SPAD, the connection method between the quenching switch 11 and the avalanche diode SPAD varies, such as... Figure 33 As shown, in an optional embodiment, the avalanche diode SPAD is forward biased, the cathode of the avalanche diode SPAD is connected to the first positive voltage terminal Vbias, the anode of the avalanche diode SPAD, the first terminal of the quenching switch 11 and the first terminal of the capacitor Cpar are connected to form the output terminal of the quenching reset circuit 10, and the second terminal of the quenching switch 11 and the second terminal of the capacitor Cpar are grounded.

[0167] Quenching switch 11 includes a quenching tube M1.

[0168] Corresponding to the forward bias of the avalanche diode SPAD, the data terminal D of the first D flip-flop DFF1 is connected to the second positive voltage terminal VCC, the inverting clock terminal CN of the first D flip-flop DFF1 is connected to the output terminal of the comparator circuit 30, the inverting reset terminal RN of the first D flip-flop DFF1 is used to input the first clock signal CK1, and the output terminal Q of the first D flip-flop DFF1 constitutes the output terminal of the first detection circuit 41.

[0169] The data terminal D of the second D flip-flop DFF2 is connected to the second positive voltage terminal VCC. The clock terminal C of the second D flip-flop DFF2 is connected to the output terminal of the comparator circuit 30. The inverted reset terminals RN of the second D flip-flop DFF2 and the third D flip-flop DFF3 are used to input the first clock signal CK1. The clock terminal C of the third D flip-flop DFF3 is used to input the corresponding second clock signal CK2. The inverted output terminal QN of the second D flip-flop DFF2 is connected to the data terminal D of the third D flip-flop DFF3. The output terminal Q of the third D flip-flop DFF3 constitutes the output terminal of the second detection circuit 42.

[0170] The first logic gate circuit 431 includes a second inverter U2, a third inverter U3, and an AND gate AND1;

[0171] The input terminal of the second inverter U2 is connected to the output terminal of the first detection circuit 41, the input terminal of the third inverter U3 is connected to the output terminal of the second detection circuit 42, the output terminal of the second inverter U2 is connected to the first input terminal of the AND gate AND1, the output terminal of the third inverter U3 is connected to the second input terminal of the AND gate AND1, the third input terminal of the AND gate AND1 is used to input the first clock signal CK1, and the output terminal of the AND gate AND1 constitutes the output terminal of the logic control circuit 43.

[0172] Each delay circuit 20 includes an inverter U5;

[0173] The input terminal of the inverter U5 is used to input the first clock signal CK1, and the output terminal of the inverter U5 is used to output the second clock signal CK2.

[0174] Comparator circuit 30 includes a first inverter U1;

[0175] The input terminal of the first inverter U1 is connected to the second terminal of the avalanche diode SPAD, and the output terminal of the first inverter U1 constitutes the output terminal of the comparator circuit 30.

[0176] In this embodiment, the comparator circuit 30 adopts an inverter structure. The inverter has a corresponding threshold voltage Vth. For example, the threshold voltage Vth of a CMOS inverter is half of the power supply voltage, and the threshold voltage Vth of a TTL inverter can be 0.8V, etc. When the anode voltage VA0 of the avalanche diode SPAD is greater than the threshold voltage Vth corresponding to the first inverter U1, the first inverter U1 outputs a high level, and when the anode voltage VA0 of the avalanche diode SPAD is less than the threshold voltage Vth corresponding to the first inverter U1, the first inverter U1 outputs a low level. By using inverters of different models and types, the comparator circuit 30 can obtain first inverters U1 with different threshold voltages Vth, realize threshold comparison, and eliminate the need for a comparator structure and additional reference voltage source for outputting the threshold voltage Vth, thus simplifying the circuit structure.

[0177] like Figure 33 As shown, the cathode of the avalanche diode SPAD is forward biased, and the anode of the avalanche diode SPAD is connected to the quenching transistor M1, capacitor Cpar, and the first inverter U1 of the comparator circuit 30. The output of the first inverter U1 is connected to the first D flip-flop DFF1 and the second D flip-flop DFF2. The first D flip-flop DFF1 is used to detect whether the output signal of the first inverter U1 has a falling edge, the second D flip-flop DFF2 is used to detect whether the output signal VA1 of the comparator circuit 30 has a rising edge, and the third D flip-flop DFF3 is used to detect whether the second clock signal CK2 of the delay circuit 20 has a rising edge. The first D flip-flop DFF1 is triggered by a falling edge, and the second D flip-flop DFF2 and the third D flip-flop DFF3 are triggered by a rising edge.

[0178] like Figure 24 As shown, when the quenching circuit 1 is working in the quenching stage, the AND gate AND1 first outputs a low-level quenching signal. The quenching transistor M1 receives the low-level signal and turns off. The anode voltage VA0 of the avalanche diode SPAD rises and changes until it stabilizes at Vex. Then it enters the reset stage. The quenching transistor M1 receives a high-level signal and is triggered to turn on. At this time, the anode voltage VA0 of the avalanche diode SPAD begins to decrease. When it drops to the preset threshold voltage Vth, the output signal of the first inverter U1 flips and switches from low level to high level. If there is no photon trigger during the reset stage, the voltage of the avalanche diode SPAD will start to rise in the next quenching stage until it stabilizes at Vex.

[0179] When the above situation occurs, such as Figure 25As shown, during the output period of the second level signal, i.e. the reset period, AND gate AND1 first outputs a high-level reset signal. The first D flip-flop DFF1 will detect the falling edge generated by the first inverter U1. At this time, the first D flip-flop DFF1 outputs a high-level signal. When AND gate AND1 receives a low-level signal through the second inverter U2, the first clock signal CK1 is high. AND gate AND1 outputs a low-level quenching signal, i.e., the output clock CK0 of logic control circuit 43 switches to a low-level signal and controls the quenching transistor M1 in the quenching reset circuit 10 to turn off. The anode voltage VA0 of the avalanche diode SPAD rapidly increases to Vex, so the avalanche diode SPAD can be quickly quenched and no longer respond to subsequent photons.

[0180] And when the above-mentioned situation two occurs during the reset phase, that is, during the reset phase, there is photon triggering before the anode voltage VA0 of the avalanche diode SPAD drops to the preset threshold voltage Vth, causing the anode voltage VA0 of the avalanche diode SPAD to remain greater than the preset threshold voltage Vth, and the output signal of the first inverter U1 remains at a low level.

[0181] In this case, such as Figure 27 As shown, the second D flip-flop DFF2 does not detect the second change signal generated by the comparator circuit 30, and the second D flip-flop DFF2 maintains a high output level. Since the second clock signal CK2 is in phase with the first clock signal CK1, the third D flip-flop DFF3 samples the high level and can detect the rising edge of the second clock signal CK2. When the rising edge of the second clock signal CK2 is detected, the third D flip-flop DFF3 outputs a high level signal. The third D flip-flop DFF3 outputs a low level through the third inverter U3. At this time, the first clock signal CK1 is high, and the AND gate AND1 outputs a low-level quenching signal. That is, the output clock CK0 of the logic control circuit 43 switches to a low-level signal and controls the quenching transistor M1 in the quenching reset circuit 10 to turn off. The anode voltage VA0 of the avalanche diode SPAD rapidly increases to Vex, and the avalanche diode SPAD can thus be quickly quenched and no longer respond to subsequent photons.

[0182] During the reset phase, by using the first D flip-flop DFF1 to detect the falling edge of the comparator circuit 30, the second D flip-flop DFF2 to detect the falling edge of the comparator circuit 30, and the third D flip-flop DFF3 to detect the falling edge of the delay circuit 20, it is possible to detect and determine whether the avalanche diode SPAD is triggered during the reset phase. When it is determined that the avalanche diode SPAD is triggered during the reset phase, the AND gate AND1 can output a quenching signal to quickly turn off the quenching transistor M1 in the quenching reset circuit 10 in advance. Since the quenching transistor M1 is in the off state, it will not form a path with the avalanche diode SPAD, that is, no power consumption is generated, reducing the DC power consumption generated by the quenching circuit 1 and reducing the overall power consumption of the imaging system.

[0183] In another alternative embodiment, such as Figure 34 As shown, the avalanche diode SPAD is negatively biased. The anode of the avalanche diode SPAD is connected to the negative voltage terminal -VBK. The cathode of the avalanche diode SPAD, the first terminal of the quenching switch 11, and the first terminal of the capacitor Cpar are connected to form the output terminal of the quenching reset circuit 10. The second terminal of the quenching switch 11 is connected to the third positive voltage terminal Vex, and the second terminal of the capacitor Cpar is grounded.

[0184] Quenching switch 11 includes a quenching tube M1;

[0185] The data terminal D of the first D flip-flop DFF1 is connected to the second positive voltage terminal VCC. The clock terminal C of the first D flip-flop DFF1 is connected to the output terminal of the comparator circuit 30. The reset terminal R of the first D flip-flop DFF1 is used to input the first clock signal CK1. The output terminal Q of the first D flip-flop DFF1 constitutes the output terminal of the first detection circuit 41.

[0186] The data terminal D of the second D flip-flop DFF2 is connected to the second positive voltage terminal VCC. The inverted clock terminal CN of the second D flip-flop DFF2 is connected to the output terminal of the comparator circuit 30. The reset terminals R of the second D flip-flop DFF2 and the third D flip-flop DFF3 are used to input the first clock signal CK1. The inverted clock terminal CN of the third D flip-flop DFF3 is used to input the corresponding second clock signal CK2. The inverted output terminal QN of the second D flip-flop DFF2 is connected to the data terminal D of the third D flip-flop DFF3. The output terminal Q of the third D flip-flop DFF3 constitutes the output terminal of the fifth detection unit.

[0187] When the first detection circuit 41 and the second detection circuit 42 are included, the first logic gate circuit 431 includes a first OR gate OR1;

[0188] The first input terminal of the first OR gate OR1 is connected to the output terminal of the first detection circuit 41, the second input terminal of the first OR gate OR1 is connected to the output terminal of the second detection circuit 42, the third input terminal of the first OR gate OR1 is used to input the first clock signal CK1, and the output terminal of the first OR gate OR1 constitutes the output terminal of the logic control circuit 43.

[0189] Each delay circuit 20 includes an inverter U5;

[0190] The input terminal of the inverter U5 is used to input the first clock signal CK1, and the output terminal of the inverter U5 is used to output the second clock signal CK2.

[0191] Comparator circuit 30 includes a first inverter U1;

[0192] The input terminal of the first inverter U1 is connected to the second terminal of the avalanche diode SPAD, and the output terminal of the first inverter U1 constitutes the output terminal of the comparator circuit 30.

[0193] In this embodiment, the comparator circuit 30 adopts an inverter structure. The inverter has a corresponding threshold voltage. For example, the threshold voltage of a CMOS inverter is half of the power supply voltage, and the threshold voltage of a TTL inverter can be 0.8V, etc. When the cathode voltage VC0 of the avalanche diode SPAD is greater than the threshold voltage corresponding to the first inverter U1, the first inverter U1 outputs a high level, and when the cathode voltage VC0 of the avalanche diode SPAD is less than the threshold voltage corresponding to the first inverter U1, the first inverter U1 outputs a low level. By using inverters of different models and types, the comparator circuit 30 can obtain inverters with different threshold voltages to achieve threshold comparison. There is no need to use a comparator structure, and there is no need to set an additional reference voltage source for outputting the threshold voltage, which simplifies the circuit structure.

[0194] like Figure 34 As shown, the anode of the avalanche diode SPAD is negatively biased by input voltage -VBK. The cathode of the avalanche diode SPAD is connected to the quenching transistor M1, capacitor Cpar, and the first inverter U1 of the comparator circuit 30. The second terminal of the quenching transistor M1 is input to Vex. The output terminal of the first inverter U1 is connected to the first D flip-flop DFF1 and the second D flip-flop DFF2 respectively. The first D flip-flop DFF1 is used to detect whether the output signal of the first inverter U1 has a rising edge. The second D flip-flop DFF2 is used to detect whether the output signal VA1 of the comparator circuit 30 has a falling edge. The third D flip-flop DFF3 is used to detect whether the second clock signal CK2 of the delay circuit 20 has a falling edge. The first D flip-flop DFF1 is triggered by a rising edge, and the second D flip-flop DFF2 and the third D flip-flop DFF3 are triggered by a rising edge.

[0195] like Figure 28As shown, when the quenching circuit 1 is working in the quenching stage, the first OR gate OR1 first outputs a high-level quenching signal. The quenching tube M1 receives the high-level signal and turns off. The cathode voltage VC0 of the avalanche diode SPAD stabilizes at 0 after a decrease and then enters the reset stage. The quenching tube M1 receives a low-level signal and is triggered to turn on. At this time, the cathode voltage VC0 of the avalanche diode SPAD begins to rise. When it rises to the preset threshold voltage Vth, the output signal of the first inverter U1 flips and switches from high level to low level.

[0196] When the above situation occurs, such as Figure 29 As shown, during the output period of the second level signal, i.e. the reset period, the first D flip-flop DFF1 will detect the rising edge generated by the first inverter U1. At this time, the first D flip-flop DFF1 outputs a low level signal. When the first OR gate OR1 receives the low level signal, the first clock signal CK1 is high. The first OR gate OR1 outputs a high level quenching signal, i.e., the output clock CK0 of the logic control circuit 43 switches to a high level signal and controls the quenching transistor M1 in the quenching reset circuit 10 to turn off. The anode voltage VA0 of the avalanche diode SPAD drops rapidly to 0, so the avalanche diode SPAD can be quickly quenched and no longer respond to subsequent photons.

[0197] And when the above-mentioned situation two occurs during the reset phase, that is, during the reset phase, there is photon triggering before the cathode voltage VC0 of the avalanche diode SPAD rises to the preset threshold voltage Vth, causing the cathode voltage VC0 of the avalanche diode SPAD to remain below the preset threshold voltage Vth, and the output signal of the first inverter U1 remains at a high level.

[0198] In this case, such as Figure 31 As shown, the second D flip-flop DFF2 does not detect the second change signal generated by the comparator circuit 30, and the second D flip-flop DFF2 maintains a high output level. Since the second clock signal CK2 is in phase with the first clock signal CK1, the third D flip-flop DFF3 can detect the falling edge of the second clock signal CK2. When the falling edge of the second clock signal CK2 is detected, the third D flip-flop DFF3 outputs a high-level signal, the first OR gate OR1 outputs a high-level signal, and controls the quenching transistor M1 in the quenching reset circuit 10 to turn off. The cathode voltage VC0 of the avalanche diode SPAD drops rapidly to 0, and the avalanche diode SPAD can thus be quickly quenched and no longer respond to subsequent photons.

[0199] Similarly, as Figure 35As shown, when multiple comparison circuits 30, delay circuits 20, first detection circuits 41 and second detection circuits 42 are provided, the logic control circuit 43 can adopt different logic gate circuits. In an optional embodiment, the logic control circuit 43 includes a second logic gate circuit 432 and a third logic gate circuit 433.

[0200] Multiple input terminals of the second logic gate circuit 432 are respectively connected to the output terminals of multiple first detection circuits 41. Multiple input terminals of the third logic gate circuit 433 are respectively connected to the output terminals of multiple second detection circuits 42 and the output terminal of the second logic gate circuit 432. Another input terminal of the third logic gate circuit 433 is used to input the first clock signal CK1. The output terminal of the third logic gate circuit 433 constitutes the output terminal of the logic control circuit.

[0201] When the biasing mode of the avalanche diode SPAD is different, the second logic gate circuit 432 and the third logic gate circuit 433 can adopt different circuit structures. In an optional embodiment, when the avalanche diode SPAD is forward biased, such as Figure 35 As shown, the second logic gate circuit 432 includes a first OR gate OR1, and the third logic gate circuit 433 includes multiple fourth inverters U4 and an AND gate AND1. Multiple input terminals of the first OR gate OR1 are respectively connected to the output terminals of multiple first detection circuits 41. The output terminals of multiple second detection circuits 42 and the output terminal of the first OR gate OR1 are respectively connected through a fourth inverter U4 and multiple input terminals of the AND gate AND1. Another input terminal of the AND gate AND1 is also used to input the first clock signal CK1. The output terminal of the AND gate AND1 constitutes the output terminal of the logic control circuit 43.

[0202] The first OR gate OR1 performs an OR operation on the output signals of multiple first detection circuits 41 and outputs a high level when at least one high level is received. Multiple fourth inverters U4 invert the output signals of the first OR gate OR1 and multiple second detection circuits 42. The inverted signals are ANDed by the AND gate AND1. When the above situation occurs, it is assumed that the preset threshold voltages Vth of the multiple first inverters are 0.4Vex and 0.6Vex, respectively.

[0203] When the above situation occurs, such as Figure 25As shown, during the output period of the second level signal, i.e. the reset period, the anode voltage VA0 of the avalanche diode SPAD first drops to 0.6Vex. The first inverter U1 corresponding to the preset threshold voltage Vth of 0.6Vex first outputs a falling edge. The first D flip-flop DFF1 connected to the first inverter U1 will first detect the falling edge. At this time, the first D flip-flop DFF1 first outputs a high-level signal, the first OR gate OR1 outputs a high level, and receives a low-level signal through the fourth inverter U4. At this time, the first clock signal CK1 is high, the AND gate AND1 outputs a low-level quenching signal, and controls the quenching transistor M1 in the quenching reset circuit 10 to turn off. The anode voltage VA0 of the avalanche diode SPAD quickly increases to Vex, so the avalanche diode SPAD can be quickly quenched and no longer respond to subsequent photons.

[0204] And when the above-mentioned situation two occurs during the reset phase, assuming that td1_1 and td1_2 are 0.5ns and 0.3ns respectively, then td2_1 and td2_2 can be set to 0.6ns and 0.4ns respectively.

[0205] like Figure 27 As shown, the second D flip-flop DFF2 does not detect the second change signal generated by the comparator circuit 30, and the second D flip-flop DFF2 maintains a high output level. At the same time, since the second clock signal CK2 is in phase with the first clock signal CK1, the third D flip-flop DFF3 can detect the rising edge of the second clock signal CK2 with a preset delay of 0.4ns first. When the rising edge of the second clock signal CK2 is detected, the corresponding third D flip-flop DFF3 first outputs a high-level signal. The third D flip-flop DFF3 outputs a low level through the fourth inverter U4. At this time, the first clock signal CK1 is high, and the AND gate AND1 outputs a low-level quenching signal. That is, the output clock CK0 of the logic control circuit 43 switches to a low-level signal and controls the quenching transistor M1 in the quenching reset circuit 10 to turn off. The anode voltage VA0 of the avalanche diode SPAD rapidly increases to Vex, and the avalanche diode SPAD can thus be quickly quenched and no longer respond to subsequent photons.

[0206] When the avalanche diode SPAD is negatively biased, the second logic gate circuit 432 includes a second OR gate, and the third logic gate circuit 433 includes a third OR gate.

[0207] Assume that the preset threshold voltages Vth of the multiple first inverters U1 are 0.4Vex and 0.6Vex, respectively.

[0208] When the above situation occurs, such as Figure 25As shown, during the output period of the second level signal, i.e. the reset period, the anode voltage VA0 of the avalanche diode SPAD first drops to 0.4Vex. The first inverter U1 corresponding to the preset threshold voltage Vth of 0.4Vex first outputs a rising edge. The first D flip-flop DFF1 connected to the first inverter U1 will first detect the rising edge. At this time, the first D flip-flop DFF1 first outputs a low level signal, and the second OR gate OR2 outputs a low level. At this time, the first clock signal CK1 is high level, and the third OR gate OR3 outputs a high level quenching signal and controls the quenching transistor M1 in the quenching reset circuit 10 to turn off. The anode voltage VA0 of the avalanche diode SPAD quickly increases to Vex, so the avalanche diode SPAD can be quickly quenched and no longer respond to subsequent photons.

[0209] And when situation two occurs during the reset phase, assuming td1_1 and td1_2 are 0.5ns and 0.3ns respectively, then td2_1 and td2_2 can be set to 0.6ns and 0.4ns respectively. Figure 27 As shown, the second D flip-flop DFF2 does not detect the second change signal generated by the comparator circuit 30, and the second D flip-flop DFF2 maintains a high output level. At the same time, since the second clock signal CK2 is in phase with the first clock signal CK1, the third D flip-flop DFF3 can detect the falling edge of the second clock signal CK2 with a preset delay of 0.4ns. When the falling edge of the second clock signal CK2 is detected, the corresponding third D flip-flop DFF3 first outputs a high-level signal, and the second OR gate outputs a high-level signal. At this time, the first clock signal CK1 is high, and the third OR gate outputs a high-level quenching signal, that is, the output clock CK0 of the logic control circuit 43 switches to a high-level signal and controls the quenching transistor M1 in the quenching reset circuit 10 to turn off. The anode voltage VA0 of the avalanche diode SPAD rapidly increases to Vex, and the avalanche diode SPAD can thus be quickly quenched and no longer respond to subsequent photons.

[0210] Among them, when photon triggering exists during the reset phase, there may be a third situation. Taking the positive bias voltage of the avalanche diode SPAD as an example, the comparator circuit 30 will only have a falling edge when the quench reset circuit 10 outputs a quench signal. Or, taking the negative bias voltage of the avalanche diode SPAD as an example, the comparator circuit 30 will only have a rising edge when the quench reset circuit 10 outputs a quench signal.

[0211] The reason is that after the voltage at the second terminal of the avalanche diode SPAD drops to or rises to the preset threshold voltage Vth during the reset phase, there is photon triggering. However, due to the small on-resistance of the quenching diode M1, although the voltage at the second terminal of the avalanche diode SPAD rises or falls, it is still lower or higher than the preset threshold voltage Vth, resulting in the inability to produce the falling edge or rising edge of Case 1.

[0212] Therefore, it is necessary to ensure that the on-resistance of the quenching tube M1 reaches a preset resistance value. In an optional embodiment, such as... Figure 36 As shown, the quenching switch 11 includes multiple parallel quenching branches. Each quenching branch includes a series selection switch S and a quenching tube M1. The control terminal of each quenching tube M1 is used to receive a quenching signal or a reset signal. Each selection switch S is used to receive a data switch selection signal and correspondingly turn on and off.

[0213] By setting multiple parallel quenching branches, different selection switches S can be turned on according to the required on-resistance, thereby generating different on-resistances in parallel. This makes the on-resistance of the quenching switch 11 reach the preset on-resistance, so that when the voltage at the second terminal of the avalanche diode SPAD drops to or rises to the preset threshold voltage Vth during the reset phase and photon triggering occurs, a rising or falling edge of condition one can appear, ensuring the accuracy of signal detection and the reliability of the on / off control of the quenching tube.

[0214] Among them, the smaller the width-to-length ratio of each quenching tube M1, the fewer the selector switches S are closed, the smaller the width-to-length ratio of the quenching switch 11, and the greater the on-resistance.

[0215] Furthermore, the on-resistance of the quenching switch 11 can be changed by altering the output clock CK0 of the detection control circuit 40. In an optional embodiment, such as... Figure 37 As shown, the quenching circuit 1 also includes:

[0216] The signal attenuation circuit 60 is connected between the quenching and reset circuit 10 and the detection and control circuit 40. The signal attenuation circuit 60 is used to attenuate the output signal of the detection and control circuit 40 and output it to the quenching and reset circuit 10.

[0217] In this embodiment, the signal attenuation circuit 60 reduces the amplitude of the output clock CK0 of the detection control circuit 40, thereby increasing the on-resistance of the quenching switch 11. This makes the on-resistance of the quenching switch 11 reach the preset on-resistance, so that when the voltage at the second terminal of the avalanche diode SPAD drops to or rises to the preset threshold voltage Vth during the reset phase and photon triggering occurs, a rising edge or falling edge of condition one can occur, ensuring the accuracy of signal detection and the reliability of the on / off control of the quenching tube.

[0218] The signal attenuation circuit 60 can adopt structures such as attenuators and voltage dividers, and the specific structure is not limited.

[0219] The aforementioned quenching circuit 1 includes an avalanche diode SPAD, a quenching reset circuit 10, a delay circuit 20, a comparator circuit 30, and a detection and control circuit 40. The detection and control circuit 40 outputs a quenching signal when the first clock signal CK1 reaches its first level, causing the quenching circuit 1 to operate in the quenching stage. During the second level signal, i.e., the reset stage of the quenching circuit 1, if the avalanche diode SPAD is triggered by a photon, the comparator circuit 30 or the delay circuit 20 will generate a corresponding first change signal or a second change signal. When the detection and control circuit 40 detects the first change signal or the second change signal of the comparator circuit 30 or the delay circuit 20, it can determine that the avalanche diode SPAD has been triggered in the reset stage. At this time, it outputs a quenching signal, causing the quenching reset circuit 10 to enter the quenching stage in advance, thereby reducing the power consumption of the quenching circuit 1 when it is triggered in the reset stage.

[0220] Furthermore, the quenching circuit 1 uses clock-controlled active quenching without changing the clock frequency of the first clock signal CK1. Therefore, the quenching circuit 1 can measure a high photon count rate, giving it a low dead time characteristic. Simultaneously, to ensure the accuracy of the intensity information sensed by the system, the photon count rate output by the quenching circuit 1 can exhibit a "non-decreasing" trend with light intensity, thus guaranteeing the accuracy of the light intensity information sensed by the system.

[0221] The present invention also proposes an imaging system, such as Figure 39 As shown, the imaging system includes a pixel array 100 and an image processing circuit 2. The pixel array 100 includes pixel units 101 arranged in an array. Each pixel unit 101 includes an avalanche diode (SPAD) connected to the above-described quenching circuit 1. The specific structure of the quenching circuit 1 is as described in the above embodiments. Since this imaging system adopts all the technical solutions of all the above embodiments, it has at least all the beneficial effects brought about by the technical solutions of the above embodiments, which will not be described in detail here. The image processing circuit 2 is connected to the quenching circuit 1 of each avalanche diode (SPAD). The image processing circuit 2 is used to process the photon count rate output by the quenching circuit 1 of the avalanche diode (SPAD) and determine the image information.

[0222] In this embodiment, the image processing circuit 2 can use corresponding logic gates and signal processing circuits, and obtain the output signal VA1 of the comparison circuit 30 in the quenching circuit and the clock signal received by the quenching reset circuit 10. The photon count rate and image information are determined according to the clock signal and the output signal VA1 of the comparison circuit 30.

[0223] The signal processing circuit may include a counter, a memory, and other signal processing circuits. By counting, storing, and processing the photon count rate, the corresponding image information can be obtained.

[0224] The above-described embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included within the protection scope of the present invention.

Claims

1. A quenching circuit for an avalanche diode, characterized in that, include: A bias voltage circuit is connected to the first terminal of the avalanche diode, and the bias voltage circuit is used to provide a bias voltage; A quenching and reset circuit is connected to the second terminal of the avalanche diode. The quenching and reset circuit is used to quench or reset the avalanche diode according to a quenching signal or a reset signal. The voltage at the second terminal of the avalanche diode changes to a first voltage when photon triggering occurs during quenching, and changes to a second voltage when there is no photon triggering during reset. The delay circuit is used to delay the input first clock signal for a preset time and output it as a second clock signal. The first clock signal is composed of alternating first-level signals and second-level signals with opposite levels. A comparator circuit is connected to the second terminal of the avalanche diode. The comparator circuit is used to output a third level signal when the input voltage is greater than or equal to a preset threshold voltage, and to output a fourth level signal with the opposite level to the third level signal when the input voltage is less than the preset threshold voltage. The detection control circuit is connected to the comparison circuit, the delay circuit, and the quenching reset circuit, respectively. The detection control circuit is used for: The reset signal is output during the output period of each of the second level signals, and the quenching signal is output when the first change signal generated by the comparison circuit is detected, or when the second change signal generated by the delay circuit is detected but the second change signal generated by the comparison circuit is not detected. The quenching signal is output during the output period of the first level signal, wherein the first change signal and the second change signal are each other's rising edge and falling edge; Wherein, td2>td1, td2 is the preset duration of the delay circuit, and td1 is the duration of the avalanche diode changing from the first voltage to the preset threshold voltage when the output period of the first level signal switches to the output period of the second level signal. The preset threshold voltage is between the first voltage and the second voltage.

2. The quenching circuit of the avalanche diode as described in claim 1, characterized in that, The detection control circuit includes: A first detection circuit is connected to the output terminal of the comparison circuit. The first detection circuit is used to output a first detection signal when the first change signal is detected or to trigger the output of a second detection signal when the first change signal is not detected during the output period of each second level signal. The second detection circuit is connected to the output terminal of the comparison circuit and the output terminal of the delay circuit respectively. The second detection circuit is used to output a third detection signal when the second change signal generated by the delay circuit is detected and the second change signal generated by the comparison circuit is not detected during the output period of each second level signal; otherwise, it outputs a fourth detection signal. A logic control circuit is connected to the first detection circuit, the second detection circuit, and the quenching and reset circuit, respectively. The logic control circuit is used for: The reset signal is output during the output period of each of the second level signals, and the quenching signal is output when the first detection signal or the third detection signal is received, or the reset signal is output when the second detection signal or the fourth detection signal is received; The quenching signal is output during the output period of the first level signal.

3. The quenching circuit of the avalanche diode as described in claim 2, characterized in that, The delay circuit includes multiple delay circuits. Each delay circuit is used to delay the input first clock signal for a preset time and then output a second clock signal. The delay times of each delay circuit are not equal. The comparison circuit includes multiple circuits. Each comparison circuit is used to compare the input voltage with a preset threshold voltage, and output the third level signal when the input voltage is greater than or equal to the preset threshold voltage, or output the fourth level signal when the input voltage is less than or equal to the preset threshold voltage. The preset threshold voltages corresponding to each comparison circuit are not equal. The first detection circuit includes multiple circuits, and each of the first detection circuits is connected to the comparison circuit one by one. The second detection circuit includes multiple circuits, each of which is connected to the output terminal of one of the comparison circuits and the output terminal of one of the delay circuits. The logic control circuit is connected to a plurality of the first detection circuits and a plurality of the second detection circuits respectively, and the logic control circuit is used for: The reset signal is output during the output period of each of the second level signals, and the quenching signal is output when one of the first detection signals or the third detection signal is received first, or the reset signal is output when one of the second detection signals or the fourth detection signal is received first. The quenching signal is output during the output period of the first level signal.

4. The quenching circuit of the avalanche diode as described in claim 3, characterized in that, The first detection circuit includes a first D flip-flop; The data terminal of the first D flip-flop is connected to the second positive voltage terminal, the corresponding clock terminal of the first D flip-flop is connected to the output terminal of the comparator circuit, the corresponding reset terminal of the first D flip-flop is used to input the first clock signal, and the corresponding output terminal of the first D flip-flop constitutes the output terminal of the first detection circuit.

5. The quenching circuit of the avalanche diode as described in claim 4, characterized in that, The second detection circuit includes a second D flip-flop and a third D flip-flop; The data terminal of the second D flip-flop is connected to the second positive voltage terminal, the clock terminal of the second D flip-flop is connected to the output terminal of the comparator circuit, the corresponding reset terminals of the second D flip-flop and the third D flip-flop are used to input the first clock signal, the corresponding clock terminal of the third D flip-flop is used to input the corresponding second clock signal, the corresponding output terminal of the second D flip-flop is connected to the data terminal of the third D flip-flop, and the corresponding output terminal of the third D flip-flop constitutes the output terminal of the second detection circuit.

6. The quenching circuit of the avalanche diode as described in claim 3, characterized in that, When the first detection circuit and the second detection circuit are included, the logic control circuit includes a first logic gate circuit. The two input terminals of the first logic gate circuit are respectively connected to the output terminal of the first detection circuit and the output terminal of the second detection circuit. The other input terminal of the first logic gate circuit is also used to input the first clock signal. The output terminal of the first logic gate circuit constitutes the output terminal of the logic control circuit. Alternatively, when the first detection circuit and the second detection circuit include multiple circuits, the logic control circuit includes a second logic gate circuit and a third logic gate circuit; Multiple input terminals of the second logic gate circuit are respectively connected to multiple output terminals of the first detection circuit, multiple input terminals of the third logic gate circuit are respectively connected to multiple output terminals of the second detection circuit and the output terminal of the second logic gate circuit, another input terminal of the third logic gate circuit is used to input the first clock signal, and the output terminal of the third logic gate circuit constitutes the output terminal of the logic control circuit.

7. The quenching circuit of the avalanche diode as described in claim 1, characterized in that, The comparison circuit includes a first inverter; The input terminal of the first inverter is connected to the second terminal of the avalanche diode, and the output terminal of the first inverter constitutes the output terminal of the comparator circuit.

8. The quenching circuit of the avalanche diode as described in claim 1, characterized in that, The quenching and reset circuit includes a quenching switch and a capacitor; The first terminal of the quenching switch, the first terminal of the capacitor, and the second terminal of the avalanche diode are connected, and the second terminal of the quenching switch is grounded or connected to the first positive voltage terminal. The quenching switch includes a quenching tube; Alternatively, the quenching switch may include multiple quenching branches connected in parallel; Each of the quenching branches includes a selection switch and a quenching tube connected in series. The control terminal of each quenching tube is used to receive the quenching signal or the reset signal. Each selection switch is used to receive a selection signal from the switch and correspondingly turn it on and off.

9. The quenching circuit of the avalanche diode as described in any one of claims 1 to 8, characterized in that, The quenching circuit of the avalanche diode also includes: A signal attenuation circuit is connected between the quenching and reset circuit and the detection and control circuit. The signal attenuation circuit is used to attenuate the output signal of the detection and control circuit and output it to the quenching and reset circuit.

10. An imaging system, characterized in that, It includes a pixel array and an image processing circuit. The pixel array includes pixel units arranged in an array, and each pixel unit includes an avalanche diode connected in series and a quenching circuit for the avalanche diode as described in any one of claims 1 to 9. The image processing circuit is connected to the quenching circuit of each avalanche diode. The image processing circuit is used to process the photon count rate output by the quenching circuit of the avalanche diode and determine the image information.

Images