A trench-type silicon carbide MOSFET device and its preparation method

Abstract

The invention discloses a trench-type silicon carbide MOSFET device and a preparation method thereof, belonging to the field of semiconductors. The device introduces a P-type deep doped region and a Schottky trench, so that: when the device is in a reverse withstand voltage state, the P-type buried layer, the N-type first silicon carbide epitaxial layer, the P-type deep doped region, and the N-type second silicon carbide epitaxial layer are used as a gate oxide protection structure, and the lateral and vertical gate oxide protection structures are depleted together to protect the gate oxide layer, thereby reducing the electric field strength at the gate corner; when the device undergoes avalanche breakdown, the current flows through the P-type deep doped region and then flows into the source through the source metal inside the Schottky trench, and the avalanche current hardly flows through the first P-type body region and then enters the N+ type source region and finally enters the source metal, thereby reducing the risk of parasitic transistor turning on; the source metal at the bottom of the Schottky trench forms a Schottky contact with the N-type second silicon carbide epitaxial layer, so that the device integrates the Schottky structure and improves the reverse recovery performance of the device.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor technology, and in particular relates to a trench-type silicon carbide MOSFET device and a preparation method thereof. Background Art

[0002] As a wide-bandgap semiconductor material, silicon carbide (SiC) boasts advantages such as high critical breakdown electric field strength, high saturated electron mobility, and high thermal conductivity, offering significant material advantages in the field of power electronics. Compared to planar VDMOS (Vertical Double-diffused Metal-Oxide-Semiconductor) devices, trench SiC MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors) feature a vertically oriented conductive channel, eliminating the parasitic junction field-effect transistor (JFET) resistance of planar VDMOS. This reduces cell size and increases cell density, significantly increasing current density and significantly reducing the device's on-resistance.

[0003] Compared to planar structures, trench silicon carbide has a higher cell density per unit area, resulting in a reduction in the device's avalanche capability. This is particularly evident at low inductances, where parasitic transistor conduction issues in the cell region of the silicon carbide device become more pronounced. Currently, asymmetric trench MOSFET devices and dual-trench MOSFET devices are commonly used. In an asymmetric trench MOSFET device, one side of the gate trench is used for conduction, while the other side is used to create a P+ shielding region. However, when the asymmetric trench MOSFET device is turned on, the P+ shielding region and the N-type epitaxial layer form a depletion region, significantly reducing the electron current flow path and increasing the on-resistance of the MOSFET device. Dual-trench MOSFET devices incorporate gate and source trenches, but the gate oxide electric field strength remains high in the center of the gate trench, providing insufficient electric field protection for the gate oxide. In particular, the gate oxide at the corners is susceptible to electric field breakdown. Summary of the Invention

[0004] In order to solve the above problems existing in the prior art, the present invention provides a trench silicon carbide MOSFET device and a method for manufacturing the same. The technical problem to be solved by the present invention is achieved through the following technical solutions:

[0005] In a first aspect, an embodiment of the present invention provides a trench silicon carbide MOSFET device, wherein the trench silicon carbide MOSFET device comprises:

[0006] Silicon carbide substrate;

[0007] An N-type first silicon carbide epitaxial layer is located on the upper surface of the silicon carbide substrate;

[0008] A P-type buried layer is located within the N-type first silicon carbide epitaxial layer at both ends of the device;

[0009] An N-type second silicon carbide epitaxial layer is located on the P-type buried layer and the remaining N-type first silicon carbide epitaxial layer;

[0010] Two gate trenches, respectively penetrating the N-type second silicon carbide epitaxial layer near both ends of the device and extending into the corresponding P-type buried layer; a gate oxide layer is provided on the inner wall of each gate trench, and P-type polysilicon is provided on the gate oxide layer and in the gate trench;

[0011] Two N+ type source regions are located in the N-type second silicon carbide epitaxial layer between the two gate trenches and are respectively in contact with the gate oxide layer in one gate trench;

[0012] Two first P-type body regions are respectively located in the N-type second silicon carbide epitaxial layer below an N+ type source region and in contact with the corresponding N+ type source region;

[0013] Two second P-type body regions are located in the N-type second silicon carbide epitaxial layer between the two N+ type source regions and are in contact with adjacent N+ type source regions respectively;

[0014] Two P-type deep doped regions are respectively located in the N-type second silicon carbide epitaxial layer below a second P-type body region, and are in contact with the corresponding second P-type body region and with an adjacent first P-type body region; the second P-type body region and the first P-type body region are connected and are diagonally distributed, and the depth of the P-type deep doped region in the N-type second silicon carbide epitaxial layer is greater than the depth of the first P-type body region in the N-type second silicon carbide epitaxial layer;

[0015] An interlayer insulating dielectric is respectively located on the N-type second silicon carbide epitaxial layer, the gate trench, and a portion of the N+ type source region at both ends of the device;

[0016] A Schottky trench is located in the N-type second silicon carbide epitaxial layer between two P-type deep doped regions; the depth of the Schottky trench in the N-type second silicon carbide epitaxial layer is less than the depth of the P-type deep doped region in the N-type second silicon carbide epitaxial layer, and is greater than the depth of the first P-type body region in the N-type second silicon carbide epitaxial layer;

[0017] A source metal is located in the Schottky trench, on all interlayer insulating dielectrics, on all second P-type body regions, and on all remaining N+-type source regions;

[0018] The drain metal is located on the lower surface of the silicon carbide substrate.

[0019] In a second aspect, an embodiment of the present invention provides a method for preparing a trench silicon carbide MOSFET device, the method comprising:

[0020] obtaining a silicon carbide substrate;

[0021] Depositing an N-type first silicon carbide epitaxial layer on the upper surface of the silicon carbide substrate;

[0022] Ion implantation is performed on the N-type first silicon carbide epitaxial layer at both ends of the device to form a P-type buried layer;

[0023] Depositing an N-type second silicon carbide epitaxial layer on the P-type buried layer and the N-type first silicon carbide epitaxial layer;

[0024] Performing ion implantation on the N-type second silicon carbide epitaxial layer to form two first P-type body regions;

[0025] Performing ion implantation on a portion of each first P-type body region to form a corresponding N+-type source region;

[0026] Ion implantation is performed on another portion of each first P-type body region to form a second P-type body region and a P-type deep doped region from top to bottom; the second P-type body region is connected to the first P-type body region and is diagonally distributed, and the depth of the P-type deep doped region in the N-type second silicon carbide epitaxial layer is greater than the depth of the first P-type body region in the N-type second silicon carbide epitaxial layer;

[0027] Etching the N-type second silicon carbide epitaxial layer near both ends of the device until it reaches the corresponding P-type buried layer to form two gate trenches, growing a gate oxide layer in each gate trench, and depositing P-type polysilicon on the gate oxide layer and in the gate trenches;

[0028] forming an interlayer insulating dielectric on the N-type second silicon carbide epitaxial layer, the gate trench, and a portion of the N+ type source region at both ends of the device;

[0029] Etching the N-type second silicon carbide epitaxial layer in the middle region to form a Schottky trench; the depth of the Schottky trench in the N-type second silicon carbide epitaxial layer is less than the depth of the P-type deep doped region in the N-type second silicon carbide epitaxial layer, and is greater than the depth of the first P-type body region in the N-type second silicon carbide epitaxial layer;

[0030] Depositing source metal in the Schottky trench, on all interlayer insulating dielectrics, on all second P-type body regions, and on all remaining N+-type source regions;

[0031] A drain metal is deposited on the lower surface of the silicon carbide substrate.

[0032] Beneficial effects of the present invention:

[0033] The trench-type silicon carbide MOSFET device proposed in the present invention innovatively introduces a P-type deep doped region and a Schottky trench based on the device structure. The depth of the Schottky trench in the N-type second silicon carbide epitaxial layer is designed to be smaller than the depth of the P-type deep doped region in the N-type second silicon carbide epitaxial layer, and larger than the depth of the first P-type body region in the N-type second silicon carbide epitaxial layer. This allows the P-type buried layer, the N-type first silicon carbide epitaxial layer, the P-type deep doped region, and the N-type second silicon carbide epitaxial layer to serve as a gate oxide protection structure when the device is in a reverse withstand voltage state. The horizontal and vertical gate oxide protection structures are depleted together to protect the gate oxide layer in the gate trench and reduce the electric field strength at the gate corner; when the device undergoes avalanche breakdown, the avalanche current flows through the P-type deep doped region and then flows into the source through the source metal inside the Schottky trench. The avalanche current almost never flows through the first P-type body region and then enters the N+ type source region and finally enters the source metal, thereby reducing the risk of parasitic transistor turning on; the source metal at the bottom of the Schottky trench forms a Schottky contact with the N-type second silicon carbide epitaxial layer, so that the device integrates a Schottky structure, which can improve the reverse recovery performance of the device.

[0034] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 Schematic diagram of the structure of a trench silicon carbide MOSFET device provided by an embodiment of the present invention;

[0036] Figure 2 is a schematic diagram of the cross-sectional structure of gate trenches located in different areas of a chip provided by an embodiment of the present invention;

[0037] Figure 3 This is a top view of the P-type deep doped region of the discontinuous structure provided by an embodiment of the present invention, and a schematic diagram of the corresponding cross-sectional structure when cut in different directions;

[0038] Figure 4(a) to Figure 4(b) Schematic diagram of the simulated structure and electric field strength of the gate oxide layer in the gate trench in the edge region under the reverse withstand voltage state provided by an embodiment of the present invention;

[0039] Figure 5(a) to Figure 5(b) Schematic diagram of avalanche current paths for a conventional trench structure and the trench structure proposed by the present invention;

[0040] Figure 6 The embodiment of the present invention provides Figure 1 Schematic diagram of the process of preparing a trench silicon carbide MOSFET device;

[0041] Figure 7(a) to Figure 7(r) The embodiment of the present invention provides Figure 1 Schematic diagram of the structure corresponding to each step in the preparation process of the trench silicon carbide MOSFET device shown.

[0042] Description of reference numerals:

[0043] 01-Silicon carbide substrate; 02-N-type first silicon carbide epitaxial layer; 03-P-type buried layer; 04-N-type second silicon carbide epitaxial layer; 051-First P-type body region; 052-Second P-type body region; 06-P-type deep doped region; 07-N+ type source region; 08-Gate trench; 09-Gate oxide layer; 10-P-type polysilicon; 11-Interlayer insulating dielectric; 12-Schottky trench; 13-Source metal; 14-Drain metal. DETAILED DESCRIPTION

[0044] The present invention will be further described in detail below with reference to specific examples, but the embodiments of the present invention are not limited thereto.

[0045] First, see Figure 1 An embodiment of the present invention provides a trench silicon carbide MOSFET device, the trench silicon carbide MOSFET device comprising:

[0046] Silicon carbide substrate 01;

[0047] The N-type first silicon carbide epitaxial layer 02 is located on the upper surface of the silicon carbide substrate 01;

[0048] The P-type buried layer 03 is located inside the N-type first silicon carbide epitaxial layer 02 at both ends;

[0049] The N-type second silicon carbide epitaxial layer 04 is located on the P-type buried layer 03 and the remaining N-type first silicon carbide epitaxial layer 02;

[0050] Two gate trenches 08 penetrate the N-type second silicon carbide epitaxial layer 04 near the two ends of the device and extend into the corresponding P-type buried layer 03; a gate oxide layer 09 is provided on the inner wall of each gate trench 08, and P-type polysilicon 10 is provided on the gate oxide layer 09 and in the gate trench 08;

[0051] Two N+ type source regions 07 are located in the N-type second silicon carbide epitaxial layer 04 between the two gate trenches 08 and are in contact with the gate oxide layer 09 in one gate trench 08 respectively;

[0052] Two first P-type body regions 051 are respectively located in the N-type second silicon carbide epitaxial layer 04 below an N+ type source region 07 and in contact with the corresponding N+ type source region 07;

[0053] Two second P-type body regions 052 are located in the N-type second silicon carbide epitaxial layer 04 between the two N+ type source regions 07 and are in contact with one N+ type source region 07 respectively;

[0054] Two P-type deep doped regions 06 are respectively located in the N-type second silicon carbide epitaxial layer 04 below a second P-type body region 052 and in contact with the corresponding second P-type body region 052 and the adjacent first P-type body region 051. At this time, the second P-type body region 052 and the first P-type body region 051 are connected and arranged diagonally.

[0055] Interlayer insulating dielectric 11 is located on the N-type second silicon carbide epitaxial layer 04, gate trench 08, and part of the N+ type source region 07 at both ends of the device;

[0056] The Schottky trench 12 is located in the N-type second silicon carbide epitaxial layer 04 between the two P-type deep doped regions 06. The depth of the Schottky trench 12 in the N-type second silicon carbide epitaxial layer 04 is less than the depth of the P-type deep doped region 06 in the N-type second silicon carbide epitaxial layer 04, and is greater than the depth of the first P-type body region 051 in the N-type second silicon carbide epitaxial layer 04.

[0057] The source metal 13 is located in the Schottky trench 12, on all interlayer insulating dielectrics 11, on all second P-type body regions 052, and on all remaining N+-type source regions 07;

[0058] The drain metal 14 is located on the lower surface of the silicon carbide substrate 01 .

[0059] The silicon carbide substrate 01 of the embodiment of the present invention is an N+ type silicon carbide substrate, and the specific material can be 4H-SiC; the thickness of the silicon carbide substrate 01 is 200μm~350μm, and the doping concentration is 6e17cm -3 ~8e17cm -3 .

[0060] The thickness of the N-type first silicon carbide epitaxial layer 02 in the embodiment of the present invention is 2 μm to 10 μm, and the doping concentration is 4e15 cm -3 ~8e15cm -3 .

[0061] In the embodiment of the present invention, the depth of the P-type buried layer 03 in the N-type first silicon carbide epitaxial layer 02 is 0.3 μm to 0.8 μm, and the doping concentration is 5e17 cm -3 ~1e18cm -3 .

[0062] The thickness of the N-type second silicon carbide epitaxial layer 04 in the embodiment of the present invention is 1.5 μm to 2 μm, and the doping concentration is 4e15 cm -3 ~8e15cm -3 .

[0063] In this embodiment of the present invention, the width of the gate trench 08 is 0.8 μm to 1.2 μm. The gate oxide layer 09 disposed within the gate trench 08 can be made of materials such as SiO2 (silicon dioxide) and SiN (silicon nitride). The bottom of the gate trench 08 is an arc-shaped structure, and the P-type buried layer 03 covers the bottom of the gate trench 08. If the P-type buried layer 03 covers too little of the gate trench 08, the gate oxide layer 09 within the gate trench 08 will not be adequately protected. If it covers too much of the gate trench 08, the on-resistance of the device will increase. The width of the P-type buried layer 03 on both sides of the gate trench 08 is 0.3 μm to 0.6 μm.

[0064] In the embodiment of the present invention, the depth of the N+ type source region 07 in the N-type second silicon carbide epitaxial layer 04 is 0.3 μm to 0.5 μm, the width is 0.6 μm to 1.2 μm, and the doping concentration is 8e18 cm -3 ~2e19cm -3 .

[0065] In the embodiment of the present invention, the deepest depth of the first P-type body region 051 in the N-type second silicon carbide epitaxial layer 04 is 0.5 μm to 1.2 μm, the width of the first P-type body region 051 is 0.5 μm to 1.2 μm, and the doping concentration is 1e16 cm -3 ~5e16cm -3 .

[0066] The width of the second P-type body region 052 in the N-type second silicon carbide epitaxial layer 04 is 0.6 μm to 0.9 μm. The doping concentration of the second P-type body region 052 is greater than that of the first P-type body region 051, depending on the doping conditions during the process.

[0067] In the embodiment of the present invention, the deepest depth of the P-type deep doping region 06 in the N-type second silicon carbide epitaxial layer 04 is 1.0μm~1.5μm, and the width of the P-type deep doping region 06 is 0.5μm~0.8μm. In the embodiment of the present invention, the doping concentration of the P-type deep doping region 06 decreases vertically from bottom to top, and the doping concentration at the bottom of the P-type deep doping region 06 is 5 times~10 times the doping concentration of the first P-type body region 051, and the doping concentration at the top of the P-type deep doping region 06 is 2.5 times~5 times the doping concentration of the first P-type body region 051. Preferably, according to the doping condition of the first P-type body region 051, the doping concentration at the bottom of the P-type deep doping region 06 is 5e16cm -3 ~5e17cm -3 The doping concentration of the top of the P-type deep doped region 06 is 2.5e16cm -3 ~2.5e17cm -3 Here, vertical refers to Figure 1The vertical direction from the silicon carbide substrate 01 to the source metal 13 is shown.

[0068] In the embodiment of the present invention, the horizontal distance between the P-type deep doped region 06 and the P-type buried layer 03 is 0.5 μm to 0.9 μm. If the horizontal distance between the P-type deep doped region 06 and the P-type buried layer 03 is too close, the on-resistance of the device will increase; if the horizontal distance is too far, the protection effect of the gate oxide layer 09 in the gate trench 08 will be affected.

[0069] In the embodiment of the present invention, the material of the interlayer insulating dielectric 11 can be SiO 2 , SiN, etc., and the thickness is 1.0 μm to 1.2 μm.

[0070] In the embodiment of the present invention, the material of the source metal 13 can be a metal combination of titanium / titanium nitride / aluminum stacked sequentially from bottom to top, and the thickness of the source metal 13 on the interlayer insulating dielectric 11 is 3.0μm~5.0μm; the material of the drain metal 14 can be a metal combination of titanium / nickel / silver stacked sequentially from inside to outside, with a thickness of 0.1μm~0.3μm.

[0071] Usually the trench silicon carbide MOSFET device is located in the center area of the chip. Figure 2 As shown, Figure 2 In the dotted box, the source metal 13 forms ohmic contacts with the second P-type body region 052 and the P-type deep doped region 06, and the source metal 13 forms a Schottky contact with the N-type second silicon carbide epitaxial layer 04. However, there will also be trench silicon carbide MOSFET devices located at the edge of the chip, that is, Figure 2 Outside the dotted box, the P-type polysilicon 10 at the bottom of the gate trench 08 penetrates the gate oxide layer 09 to form an ohmic contact with the P-type buried layer 03. Simultaneously, the source metal 13 penetrates the interlayer insulating dielectric 11 to contact the portion of the P-type polysilicon 10 within the recessed structure 8. Here, the P-type polysilicon 10 in the edge region forms an ohmic contact with the P-type buried layer 03. This contact around the edge ensures that the source potential is consistent with the P-type buried layer 03. When the device is in the reverse withstand voltage state, only when the potential of the P-type buried layer 03 and the source metal 13 are consistent can the trench gate oxide corners be protected.

[0072] In order to increase the area ratio of the Schottky region and reduce the on-resistance of the device, the P-type deep doped region 06 in the embodiment of the present invention has a discontinuous structure, such as Figure 3 As shown in the top view, the P-type deep doped region 06 may be discontinuous and present a periodic discontinuous structure. Figure 3, the trench-type silicon carbide MOSFET device is cut along the AA direction and the AB direction respectively: when cutting in the AA direction, the P-type deep doped region 06 is passed through, and its cross-sectional structure shows that the device structure cut along the AA direction is the same as the device structure located in the central area; when cutting along the AB direction, the P-type deep doped region 06 is not passed through, and its cross-sectional structure shows that the device structure cut along the AB direction does not have the P-type deep doped region 06 and the second P-type body region 052, but it still has to meet the requirement that the depth of the Schottky trench 12 in the N-type second silicon carbide epitaxial layer 04 is greater than the depth of the first P-type body region 051 in the N-type second silicon carbide epitaxial layer 04.

[0073] The trench silicon carbide MOSFET device provided by the embodiments of the present invention can solve the problem of insufficient electric field protection of the gate oxide layer 09 at the bottom of the trench in conventional trench MOSFET devices, especially the problem that the gate oxide layer 09 at the corner is easily broken down by the electric field. It also improves the problem of long reverse recovery time and diode performance degradation of the silicon carbide body diode, and improves the problem of parasitic transistor turn-on in silicon carbide devices. Specifically:

[0074] To solve the above technical problems, the corresponding mechanism is:

[0075] A: The trench MOSFET device proposed in the present invention solves the problem that the traditional trench MOSFET device has insufficient electric field protection for the gate oxide layer at the bottom of the gate trench, especially the gate oxide layer at the corner of the gate trench is easily broken down by the electric field.

[0076] Mechanism: When the device is in reverse withstand voltage, the P-type deep doped region 06 and the P-type buried layer 03 form a depletion region together with the N-type first silicon carbide epitaxial layer 02 and the N-type second silicon carbide epitaxial layer 04. A space charge region is formed between the P-type buried layer 03 and the P-type deep doped region 06, which shields the electric field passing through the gate oxide layer 09, thereby reducing the electric field strength and protecting the gate oxide layer 09 at the corner of the gate trench 08. It can be seen that the trench silicon carbide MOSFET device proposed in the embodiment of the present invention has the effect of shielding and protecting the gate oxide layer 09. When the trench silicon carbide MOSFET device is in a reverse withstand voltage state, the P-type buried layer 03, the N-type first silicon carbide epitaxial layer 02, the P-type deep doped region 06 and the N-type second silicon carbide epitaxial layer 04 are specifically used as gate oxide protection structures. The horizontal and vertical gate oxide protection structures are depleted together to protect the gate oxide layer 09 in the gate trench 08, reducing the electric field strength at the corner of the gate trench 08. Specifically, Figure 4(a) to Figure 4(b) As shown in FIG4 (a), FIG4 (a) is a schematic diagram of the simulation structure of the gate oxide layer in the gate trench along the AC direction in the edge region under the reverse withstand voltage state. The horizontal axis in FIG4 (a) represents the structure of the present invention corresponding to the edge region from left to right. Figure 2The structure length in the AC direction is in μm, and the vertical axis represents the structure depth of the structure of the present invention corresponding to the edge region, in μm. 4(b) is a schematic diagram of the electric field strength of the gate oxide layer along the AC direction in the gate trench under the reverse withstand voltage state in the edge region. The horizontal axis in Figure 4(b) represents the structure of the present invention corresponding to the edge region from left to right. Figure 2 The structure length in the AC direction is in μm, and the vertical axis represents the electric field strength of the gate oxide layer in the AC direction within the gate trench under reverse withstand voltage conditions, in MV / μm. Figures 4(a) and 4(b) show that in a trench-type SiC MOSFET device cut along the AC direction, the electric field strength of the gate oxide layer 09 at the corner of the gate trench 08 drops below 1.7 MV / cm, far below the safe electric field strength of less than 3 MV / cm.

[0077] B: The trench MOSFET device proposed in the present invention improves the problem of parasitic transistor turn-on in silicon carbide devices.

[0078] Mechanism: By introducing a Schottky trench 12 between the P-type deep doped regions 06, the depth of the Schottky trench 12 in the N-type second silicon carbide epitaxial layer 04 is less than the depth of the P-type deep doped region 06 in the N-type second silicon carbide epitaxial layer 04 but greater than the depth of the first P-type body region 051 in the N-type second silicon carbide epitaxial layer 04, the sidewall of the Schottky trench 12 forms an ohmic contact with the P-type deep doped region 06, and the bottom of the Schottky trench 12 forms a Schottky contact with the N-type second silicon carbide epitaxial layer 04. The doping concentration of the P-type deep doped region 06 is higher than the doping concentration of the first P-type body region 051 and the second P-type body region 052. When the device undergoes avalanche breakdown, the avalanche current preferentially flows through the P-type deep doped region 06 (this region has a high doping concentration and a low on-resistance) and then flows into the source metal 13 inside the Schottky trench 12. The specific avalanche current route is shown by the dotted arrow in Figure 5(a). That is to say, when the device structure proposed by the present invention undergoes avalanche breakdown, the avalanche current will hardly flow through the first P-type body region 051 and the N+ type source region 07, but will directly flow through the P-type deep doped region 06 into the source metal 13, thereby reducing the risk of the parasitic transistor being turned on (the parasitic transistor formed by the N+ type source region 07, the first P-type body region 051, the second P-type body region 052, and the N-type second silicon carbide epitaxial layer 04). The avalanche current path of the traditional structure is shown by the dotted arrow in Figure 5(b). When avalanche breakdown occurs, the avalanche current flows through the P-type body region and part of the current enters the source metal 13, and part of the current flows through the N+ type source region 07 and then enters the source metal 13. When the avalanche current flows through the P-type body region, the P-type body region will cause a voltage drop, thereby causing the parasitic transistor to turn on, and then burn the device.

[0079] C: The trench MOSFET device proposed in the present invention improves the problem of long reverse recovery time and diode performance degradation of the silicon carbide body diode.

[0080] Mechanism: The source metal 13 at the bottom of the Schottky trench 12 forms a Schottky contact with the N-type second SiC epitaxial layer 04. The Schottky junction barrier is much lower than that of a typical SiC PN junction. During the freewheeling phase of the SiC device, the Schottky diode preferentially conducts. As the current continues to increase, the SiC PN junction begins to conduct, while the Schottky diode relies on single-carrier conduction, resulting in a shorter reverse recovery time. The device structure proposed in this invention improves its reverse recovery performance by integrating the Schottky structure.

[0081] In summary, the trench-type silicon carbide MOSFET device proposed in the embodiment of the present invention innovatively introduces the P-type deep doped region 06 and the Schottky trench 12 from the perspective of the device structure, and at the same time designs the depth of the Schottky trench 12 in the N-type second silicon carbide epitaxial layer 04 to be less than the depth of the P-type deep doped region 06 in the N-type second silicon carbide epitaxial layer 04, and greater than the depth of the first P-type body region 051 in the N-type second silicon carbide epitaxial layer 04, so that: when the device is in a reverse withstand voltage state, the P-type buried layer 03, the N-type first silicon carbide epitaxial layer 02, the P-type deep doped region 06 and the N-type second silicon carbide epitaxial layer 04 can be used as a gate oxide protection structure, and the lateral and The vertical gate oxide protection structure is depleted together to protect the gate oxide layer 09 in the gate trench 08, reducing the electric field strength at the gate corner; when the device undergoes avalanche breakdown, it flows through the P-type deep doped region 06 and then flows into the source through the source metal 13 inside the Schottky trench 12. The avalanche current hardly flows through the P-type body region (the first P-type body region 051 and the second P-type body region 052) and then enters the N+ type source region 07 and finally enters the source metal 13, thereby reducing the risk of the parasitic transistor being turned on; the source metal 13 at the bottom of the Schottky trench 12 forms a Schottky contact with the N-type second silicon carbide epitaxial layer 04, so that the device integrates a Schottky structure, which can improve the reverse recovery performance of the device.

[0082] Second, see Figure 6 An embodiment of the present invention provides a method for preparing a trench silicon carbide MOSFET device, the method comprising:

[0083] S10: Obtain a silicon carbide substrate 01.

[0084] The material obtained in the embodiment of the present invention is N+ type 4H-SiC, with a thickness of 200μm~350μm and a doping concentration of 6e17cm -3 ~8e17cm -3 The N+ type 4H-silicon carbide substrate 01 is cleaned.

[0085] S20 , depositing an N-type first silicon carbide epitaxial layer 02 on the upper surface of the silicon carbide substrate 01 .

[0086] As shown in FIG7 (a), the embodiment of the present invention uses the MOCVD (Metal-Organic Chemical Vapor Deposition) process to deposit a 2 μm to 10 μm thick and a doping concentration of 4e15 cm on the upper surface of the silicon carbide substrate 01. -3 ~8e15cm -3 N-type first silicon carbide epitaxial layer 02.

[0087] S30 , performing ion implantation on the N-type first silicon carbide epitaxial layer 02 at both ends of the device to form a P-type buried layer 03 .

[0088] As shown in FIG7(b), in an embodiment of the present invention, an oxide layer is deposited on the surface of the device obtained in S20. The oxide layer material may be SiO2. A portion of the oxide layer is etched away on the N-type first silicon carbide epitaxial layer 02 by photolithography and etching to form a P-type buried layer ion implantation window. P-type ions such as aluminum ions are selectively implanted in the P-type buried layer ion implantation window. The energy of the ion implantation is 50KeV~150KeV, so as to form a depth of 0.3μm~0.8μm and a doping concentration of 5e17cm in the N-type first silicon carbide epitaxial layer 02 at both ends of the device. -3 ~1e18cm -3 The P-type buried layer 03 is then etched away, and all remaining oxide layers are etched away.

[0089] S40 , depositing an N-type second silicon carbide epitaxial layer 04 on the P-type buried layer 03 and the N-type first silicon carbide epitaxial layer 02 .

[0090] As shown in FIG7 (c), the embodiment of the present invention uses MOCVD process to deposit a thickness of 1.5 μm to 2 μm and a doping concentration of 4e15 cm on the P-type buried layer 03 and the N-type first silicon carbide epitaxial layer 02. -3 ~8e15cm -3 N-type second silicon carbide epitaxial layer 04.

[0091] S50 , performing ion implantation on the N-type second silicon carbide epitaxial layer 04 to form two first P-type body regions 051 .

[0092] As shown in FIG7(d), in the embodiment of the present invention, an oxide layer is deposited on the surface of the device obtained in S40, and a portion of the oxide layer is etched away on the N-type second silicon carbide epitaxial layer 04 through a photolithography process and an etching process to form a first P-type body region ion implantation window, and P-type ions such as aluminum ions are selectively implanted in the first P-type body region ion implantation window. The ion implantation energy is 50KeV~150KeV, so as to form a depth of 0.5μm~1.2μm, a width of 0.5μm~1.2μm, and a doping concentration of 1e16cm in the N-type second silicon carbide epitaxial layer 04 at both ends of the device. -3 ~5e16cm -3 The first P-type body region 051 is formed, and all remaining oxide layers are etched away.

[0093] S60 , performing ion implantation on a portion of each first P-type body region 051 to form a corresponding N+-type source region 07 .

[0094] As shown in FIG7(e), in an embodiment of the present invention, an oxide layer is deposited on the surface of the device obtained in S50, and a portion of the oxide layer is etched away on each first P-type body region 051 through a photolithography process and an etching process to form an N+ type source region ion implantation window, and N-type ions such as nitrogen ions are selectively implanted in the N+ type source region ion implantation window. The ion implantation energy is 50KeV~120KeV, so as to form a corresponding depth of 0.3μm~0.5μm, a width of 0.6μm~1.2μm, and a doping concentration of 8e18cm in each first P-type body region 051. -3 ~2e19cm -3 The N+ type source region 07 is in contact with the N-type second silicon carbide epitaxial layer 04, and all remaining oxide layers are etched away.

[0095] S70, perform ion implantation on another part of each first P-type body region 051 to form a second P-type body region 052 and a P-type deep doped region 06 from top to bottom; at this time, the second P-type body region 052 and the first P-type body region 051 are connected and diagonally distributed.

[0096] As shown in FIG7(f), in an embodiment of the present invention, an oxide layer is deposited on the surface of the device obtained in S60, and a P-type deep doping region ion implantation window is formed on each first P-type body region 051 through a photolithography process and an etching process. P-type ions such as aluminum ions are selectively implanted in the P-type deep doping region ion implantation window. The energy of the ion implantation is 100KeV~800KeV, and more preferably the energy of the ion implantation is 500KeV, so as to form a P-type deep doping region 06 in the first P-type body region 051 and the N-type second silicon carbide epitaxial layer 04. A portion of the first P-type body region 051 forms a second P-type body region 052 due to the influence of the ion implantation. The ion doping of the second P-type body region 052 is The impurity concentration is greater than the impurity concentration of the first P-type body region 051, the second P-type body region 052 and the first P-type body region 051 are connected and diagonally distributed, and at the same time, the deepest depth of the P-type deep doping region 06 in the N-type second silicon carbide epitaxial layer 04 is greater than the deepest depth of the first P-type body region 051 in the N-type second silicon carbide epitaxial layer 04, and the impurity concentration of the formed P-type deep doping region 06 decreases vertically from bottom to top, and the impurity concentration at the bottom of the P-type deep doping region 06 is 5 times to 10 times the impurity concentration of the first P-type body region 051, and the impurity concentration at the top of the P-type deep doping region 06 is 2.5 times to 5 times the impurity concentration of the first P-type body region 051. Preferably, the deepest depth of the P-type deep doped region 06 in the N-type second silicon carbide epitaxial layer 04 is 1.0 μm to 1.5 μm, and the width of the P-type deep doped region 06 is 0.5 μm to 0.8 μm; according to the doping condition of the first P-type body region 051, the doping concentration at the bottom of the P-type deep doped region 06 is 5e16 cm -3 ~5e17cm -3 The doping concentration of the top of the P-type deep doped region 06 is 2.5e16cm -3 ~2.5e17cm -3 At the same time, the horizontal distance between the P-type deep doped region 06 and the P-type buried layer 03 is 0.5 μm to 0.9 μm.

[0097] S80, the N-type second silicon carbide epitaxial layer 04 near both ends of the device is etched until two gate trenches 08 are formed in the corresponding P-type buried layer 03, a gate oxide layer 09 is grown in each gate trench 08, and P-type polysilicon 10 is deposited on the gate oxide layer 09 and in the gate trench 08.

[0098] In the embodiment of the present invention, an oxide layer is deposited on the surface of the device obtained in S70, and two gate trenches 08 are formed by etching the N-type second silicon carbide epitaxial layer 04 near the two ends of the device through photolithography and etching processes. Each gate trench 08 penetrates the N-type second silicon carbide epitaxial layer 04 and extends into the corresponding P-type buried layer 03. Then, as shown in FIG7(g), SiO2 is formed as a gate oxide layer 09 in each gate trench 08 using a high-temperature furnace tube method. Finally, as shown in FIG7(h), the deposition material is deposited on the gate oxide layer 09 and in the gate trench 08 using LPCVD (Low Pressure Chemical Vapor Deposition) process. At this time, the width of the P-type buried layer 03 on both sides of the gate trench 08 is 0.3μm to 0.6μm.

[0099] It should be noted here that Figures 7(g) and 7(h) are conventional cases where the device structure proposed in the present invention is designed in the central area of the chip. For the case where the device structure proposed in the present invention is designed in the edge area, based on Figure 7(g), first, as shown in Figure 7(i), part of the gate oxide layer 09 at the bottom of the two gate trenches 08 is etched away, and then, as shown in Figure 7(j), the LPCVD process is used to deposit P-type polysilicon 10 on the remaining gate oxide layer 09 and in the gate trench 08. At this time, the P-type polysilicon 10 at the bottom of the gate trench 08 forms an ohmic contact with the P-type buried layer 03.

[0100] S90 , forming an interlayer insulating dielectric 11 on the N-type second silicon carbide epitaxial layer 04 , the gate trench 08 , and a portion of the N+ type source region 07 at both ends of the device.

[0101] As shown in FIG7(k), the embodiment of the present invention first uses a PECVD (Plasma Enhanced Chemical Vapor Deposition) process to deposit a layer of interlayer insulating dielectric 11 of a material such as SiO2 with a thickness of 1.0 μm to 1.2 μm on the surface of the device obtained in S80; then, as shown in FIG7(l), the interlayer insulating dielectric 11 in the middle area including all P second-type body regions, N-type second silicon carbide epitaxial layer 04, and part of the N+ type source region 07 is etched away through a photolithography process and an etching process.

[0102] It should be noted here that, for the case where the device structure proposed in the present invention is designed in the edge area, based on Figure 7(j), the PECVD process is first used to deposit an interlayer insulating dielectric 11 on the device surface, and then etching is performed similar to Figure 7(l), while continuing to etch away part of the interlayer insulating dielectric 11 on the gate trench 08. Finally, for the case where the device structure is designed in the edge area, the device structure formed after S90 is shown in Figure 7(m).

[0103] S100, etching the N-type second silicon carbide epitaxial layer 04 in the middle area to form a Schottky trench 12; the depth of the Schottky trench 12 in the N-type second silicon carbide epitaxial layer 04 is less than the depth of the P-type deep doped region 06 in the N-type second silicon carbide epitaxial layer 04, and is greater than the depth of the first P-type body region 051 in the N-type second silicon carbide epitaxial layer 04.

[0104] As shown in FIG7(n), in an embodiment of the present invention, an oxide layer is deposited on the surface of the device obtained in S90, and the N-type second silicon carbide epitaxial layer 04 in the middle area is etched through a photolithography process and an etching process to form a Schottky trench 12. The depth of the Schottky trench 12 in the N-type second silicon carbide epitaxial layer 04 is less than the depth of the P-type deep doped region 06 in the N-type second silicon carbide epitaxial layer 04, and is greater than the depth of the first P-type body region 051 in the N-type second silicon carbide epitaxial layer 04.

[0105] It should be noted here that, in the case where the device structure proposed in the present invention is designed in the edge region, based on FIG. 7( m ), as shown in FIG. 7( o ), the N-type second silicon carbide epitaxial layer 04 in the middle region is etched to form a Schottky trench 12 .

[0106] S101 , depositing source metal 13 in the Schottky trench 12 , on all interlayer insulating dielectrics 11 , on all second P-type body regions 052 , and on all remaining N+-type source regions 07 .

[0107] As shown in FIG7(p), the embodiment of the present invention uses an electron beam evaporation process to deposit source metal 13 within Schottky trench 12, on all interlayer insulating dielectrics 11, on all second P-type body regions 052, and on all remaining N+ source regions 07. Source metal 13 can be made of a metal combination of titanium / titanium nitride / aluminum stacked sequentially from bottom to top. At this point, source metal 13 forms ohmic contacts with second P-type body regions 052 and P-type deep doped regions 06, respectively; and forms a Schottky contact with the N-type second silicon carbide epitaxial layer 04.

[0108] It should be noted here that, in the case where the device structure proposed in the present invention is designed in the edge area, as shown in Figure 7(q), the source metal 13 is also deposited on part of the groove structure, so that the P-type polysilicon 10 in contact with the P-type buried layer 03 is connected to the source metal 13.

[0109] S102 , depositing a drain metal 14 on the lower surface of the silicon carbide substrate 01 .

[0110] As shown in FIG7(r), the embodiment of the present invention uses an electron beam evaporation process to deposit a drain metal 14 with a thickness of 0.1 μm to 0.3 μm on the lower surface of the silicon carbide substrate 01. The material of the drain metal 14 can be a metal combination of titanium / nickel / silver stacked sequentially from the inside to the outside.

[0111] As for the preparation method embodiment of the second aspect, since it is basically similar to the device embodiment of the first aspect, the description is relatively simple, and the relevant parts can be referred to the partial description of the device embodiment of the first aspect.

[0112] In the description of the present invention, it should be understood that the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature specified as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, "plurality" means two or more, unless otherwise specifically defined.

[0113] Although the present invention is described herein in conjunction with various embodiments, those skilled in the art may understand and implement other variations of the disclosed embodiments by reviewing the specification and accompanying drawings in the process of implementing the claimed invention. In the specification, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude multiple components or steps. The fact that certain measures are described in different embodiments does not mean that these measures cannot be combined to produce good results.

[0114] The above is a further detailed description of the present invention in conjunction with specific preferred embodiments, and the specific implementation of the present invention should not be considered to be limited to these descriptions. For those skilled in the art of the present invention, without departing from the concept of the present invention, several simple deductions or substitutions can be made, which should be considered to fall within the scope of protection of the present invention.

Claims

1. A trench silicon carbide MOSFET device, characterized in that: The trench silicon carbide MOSFET device comprises: Silicon carbide substrate (01); An N-type first silicon carbide epitaxial layer (02) is located on the upper surface of the silicon carbide substrate (01); A P-type buried layer (03) is located within the N-type first silicon carbide epitaxial layer (02) at both ends of the device; An N-type second silicon carbide epitaxial layer (04) is located on the P-type buried layer (03) and the remaining N-type first silicon carbide epitaxial layer (02); Two gate trenches (08) respectively penetrate the N-type second silicon carbide epitaxial layer (04) near the two ends of the device and extend into the corresponding P-type buried layer (03); a gate oxide layer (09) is provided on the inner wall of each gate trench (08), and P-type polysilicon (10) is provided on the gate oxide layer (09) and in the gate trench (08); Two N+ type source regions (07) are located in the N-type second silicon carbide epitaxial layer (04) between the two gate trenches (08) and are in contact with the gate oxide layer (09) in one gate trench (08) respectively; Two first P-type body regions (051) are respectively located in an N-type second silicon carbide epitaxial layer (04) below an N+ type source region (07) and in contact with the corresponding N+ type source region (07); Two second P-type body regions (052) are located in the N-type second silicon carbide epitaxial layer (04) between the two N+ type source regions (07) and are in contact with adjacent N+ type source regions (07) respectively; Two P-type deep doped regions (06) are respectively located in the N-type second silicon carbide epitaxial layer (04) below a second P-type body region (052), and are in contact with the corresponding second P-type body region (052) and with the adjacent first P-type body region (051); at this time, the second P-type body region (052) and the first P-type body region (051) are in a connected structure and are diagonally distributed; An interlayer insulating dielectric (11) is respectively located on the N-type second silicon carbide epitaxial layer (04), the gate trench (08), and a portion of the N+ type source region (07) at both ends of the device; A Schottky trench (12) is located in the N-type second silicon carbide epitaxial layer (04) between two P-type deep doping regions (06); the depth of the Schottky trench (12) in the N-type second silicon carbide epitaxial layer (04) is less than the depth of the P-type deep doping region (06) in the N-type second silicon carbide epitaxial layer (04), and is greater than the depth of the first P-type body region (051) in the N-type second silicon carbide epitaxial layer (04); A source metal (13) is located in the Schottky trench (12), on all interlayer insulating dielectrics (11), on all second P-type body regions (052), and on all remaining N+-type source regions (07); The drain metal (14) is located on the lower surface of the silicon carbide substrate (01).

2. The trench silicon carbide MOSFET device according to claim 1, characterized in that: The P-type deep doping region (06) has a discontinuous structure.

3. The trench silicon carbide MOSFET device according to claim 1 or 2, characterized in that: The doping concentration of the P-type deep doping region (06) decreases vertically from bottom to top, and the doping concentration at the bottom of the P-type deep doping region (06) is 5 to 10 times the doping concentration of the first P-type body region (051), and the doping concentration at the top of the P-type deep doping region (06) is 2.5 to 5 times the doping concentration of the first P-type body region (051).

4. The trench silicon carbide MOSFET device according to claim 1 or 2, characterized in that: The doping concentration of the first P-type body region (051) is 1e16 cm -3 ~5e16cm -3 .

5. The trench silicon carbide MOSFET device according to claim 1 or 2, characterized in that: The doping concentration of the second P-type body region (052) is greater than the doping concentration of the first P-type body region (051).

6. The trench silicon carbide MOSFET device according to claim 1 or 2, characterized in that: The deepest depth of the P-type deep doping region (06) in the N-type second silicon carbide epitaxial layer (04) is 1.0 μm to 1.5 μm, and the width of the P-type deep doping region (06) is 0.5 μm to 0.8 μm.

7. The trench silicon carbide MOSFET device according to claim 1 or 2, characterized in that: The horizontal distance between the P-type deep doping region (06) and the P-type buried layer (03) is 0.5 μm to 0.9 μm; and the width of the P-type buried layer (03) on both sides of the gate trench (08) is 0.3 μm to 0.6 μm.

8. The trench silicon carbide MOSFET device according to claim 1 or 2, characterized in that: The source metal (13) forms an ohmic contact with the second P-type body region (052) and the P-type deep doping region (06), respectively; and the source metal (13) forms a Schottky contact with the N-type second silicon carbide epitaxial layer (04).

9. The trench silicon carbide MOSFET device according to claim 1 or 2, characterized in that: If the trench-type silicon carbide MOSFET device is located in the edge area of the chip, the P-type polysilicon (10) at the bottom of the gate trench (08) penetrates the gate oxide layer (09) and forms an ohmic contact with the P-type buried layer (03); and the source metal (13) penetrates the interlayer insulating medium (11) and contacts the P-type polysilicon (10) in the gate trench (08).

10. A method for preparing a trench silicon carbide MOSFET device, characterized in that: The preparation method comprises: obtaining a silicon carbide substrate (01); Depositing an N-type first silicon carbide epitaxial layer (02) on the upper surface of the silicon carbide substrate (01); Ion implantation is performed on the N-type first silicon carbide epitaxial layer (02) at both ends of the device to form a P-type buried layer (03); Depositing an N-type second silicon carbide epitaxial layer (04) on the P-type buried layer (03) and the N-type first silicon carbide epitaxial layer (02); Performing ion implantation on the N-type second silicon carbide epitaxial layer (04) to form two first P-type body regions (051); Performing ion implantation on a portion of each first P-type body region (051) to form a corresponding N+-type source region (07); Ion implantation is performed on another part of each first P-type body region (051) to form a second P-type body region (052) and a P-type deep doping region (06) from top to bottom; at this time, the second P-type body region (052) and the first P-type body region (051) are in a connected structure and are diagonally distributed, and the depth of the P-type deep doping region (06) in the N-type second silicon carbide epitaxial layer (04) is greater than the depth of the first P-type body region (051) in the N-type second silicon carbide epitaxial layer (04); Etching the N-type second silicon carbide epitaxial layer (04) near both ends of the device until two gate trenches (08) are formed in the corresponding P-type buried layer (03), growing a gate oxide layer (09) in each gate trench (08), and depositing P-type polysilicon (10) on the gate oxide layer (09) and in the gate trench (08); forming an interlayer insulating dielectric (11) on the N-type second silicon carbide epitaxial layer (04), the gate trench (08), and a portion of the N+ type source region (07) at both ends of the device; The N-type second silicon carbide epitaxial layer (04) in the middle region is etched to form a Schottky trench (12); the depth of the Schottky trench (12) in the N-type second silicon carbide epitaxial layer (04) is less than the depth of the P-type deep doped region (06) in the N-type second silicon carbide epitaxial layer (04), and is greater than the depth of the first P-type body region (051) in the N-type second silicon carbide epitaxial layer (04); Depositing source metal (13) in the Schottky trench (12), on all interlayer insulating dielectrics (11), on all second P-type body regions (052), and on all remaining N+-type source regions (07); A drain metal (14) is deposited on the lower surface of the silicon carbide substrate (01).

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