Chip, electronic device, and power consumption control method of chip

Abstract

The application relates to a chip, an electronic device and a power consumption control method of the chip, and belongs to the field of electronic circuits.The chip comprises a plurality of functional modules and an interconnection module;the plurality of functional modules comprise a power consumption management module;any two functional modules in the plurality of functional modules are connected through the interconnection module; the interconnection module is used for monitoring the channel bandwidth between the interconnection module and a target module connected with the interconnection module within a period of time; and the power consumption management module is used for acquiring each channel bandwidth monitored by the interconnection module and adjusting the working frequency of the interconnection module according to each channel bandwidth.The application reduces the power consumption of the interconnection module by adjusting the working frequency of the interconnection module in the data channel, so that the overall power consumption of the chip is reduced.

Description

Technical Field

[0001] This application belongs to the field of electronic circuits, specifically relating to a chip, an electronic device, and a method for controlling the power consumption of the chip. Background Technology

[0002] As chip computing power increases, chip power consumption also rises. If this power consumption growth cannot be effectively controlled, chip energy efficiency will become a bottleneck restricting further computing power improvements. Therefore, reducing chip power consumption has become a crucial direction for chip development. Currently, chip power management mainly relies on technologies such as dynamic voltage and frequency adjustment and low-power mode switching. Among these, the software and hardware collaborative management framework centered on the ACPI (Advanced Configuration and Power Management Interface) protocol is widely used in modern processors, such as CPUs (Central Processing Units). Under this framework, the operating system (OS) monitors the CPU core load in real time and, combined with the power consumption strategies of the ACPI protocol, controls the CPU core to enter different operating modes to achieve a balance between power consumption and performance.

[0003] Although dynamic power management technology based on the ACPI protocol has played a key role in chip energy efficiency optimization, there is still considerable room for optimization in the overall power consumption of chips as chip computing power increases and energy efficiency requirements grow. Summary of the Invention

[0004] Therefore, the purpose of this application is to provide a chip, an electronic device, and a method for controlling the power consumption of the chip, which reduces the power consumption of the interconnect module by adjusting the operating frequency of the interconnect module in the data path, thereby reducing the overall power consumption of the chip.

[0005] The embodiments of this application are implemented as follows:

[0006] In a first aspect, embodiments of this application provide a chip, including: multiple functional modules and an interconnect module; the multiple functional modules include a power management module; any two functional modules are connected through the interconnect module; the interconnect module is used to monitor the path bandwidth between the interconnect module and the target module connected to the interconnect module over a period of time; the power management module is used to acquire the path bandwidths monitored by the interconnect module and adjust the operating frequency of the interconnect module according to the path bandwidths.

[0007] In the above embodiments, given that the ACPI protocol does not define the working state of the interconnect modules connecting various functional modules within the chip, and that the interconnect bus in the data path is transparent to software such as the operating system, the software sends an address, the address is routed to a predetermined location, and accesses the corresponding device. The software does not care which modules this address passes through to reach the target device, resulting in poor management of the power consumption of the data path, leading to high chip power consumption and wasted power. This application monitors the path bandwidth between the interconnect module and the target module over a period of time to dynamically adjust the operating frequency of the interconnect module in the data path, thereby reducing the power consumption of the interconnect module and the overall power consumption of the chip. At the same time, hardware control (power management module) has a faster response speed than software control.

[0008] In one possible implementation of the first aspect embodiment, the power management module is configured to obtain the maximum path bandwidth among the various path bandwidths monitored by the interconnect module, and adjust the operating frequency of the interconnect module according to the maximum path bandwidth.

[0009] In the above embodiments, by obtaining the maximum path bandwidth among the various path bandwidths and adjusting the operating frequency of the interconnect module according to the maximum path bandwidth, it is beneficial to better control the power consumption of the interconnect module, so as to reduce power consumption while being compatible with the bandwidth requirements of the target module with high bandwidth requirements.

[0010] In one possible implementation of the first aspect embodiment, the path bandwidth includes the number of transmission cycles within a preset time window, and the power management module is configured to: determine the required minimum frequency based on the number of transmission cycles in the maximum path bandwidth, and adjust the operating frequency of the interconnect module based on the minimum frequency.

[0011] In the above embodiments, the minimum required frequency is determined based on the number of transmission cycles in the maximum path bandwidth, and the operating frequency of the interconnect module is adjusted accordingly. This can minimize power consumption while ensuring that data can be transmitted within a specified time. For example, assuming the current clock frequency of the interconnect module is 1 GHz, the corresponding time period is 1 nanosecond, and the preset time window is 1 microsecond (corresponding to 1000 cycles). Among them, 10 cycles (corresponding to a time period of 10 nanoseconds) are used to transmit data. Therefore, the minimum frequency of the interconnect module required to transmit 10 cycles within the preset time window (1 microsecond) is determined to be 10 MHz. After adjusting the clock frequency of the interconnect module to 10 MHz by configuration, there are 10 cycles in the same time period, all of which are used to transmit data. The data can still be transmitted within the specified time (e.g., 1 microsecond), but the power consumption will be reduced due to the slower frequency.

[0012] In one possible implementation of the first aspect embodiment, the path bandwidth includes the number of transmission cycles within a preset time window, and the power management module is configured to: obtain the number of available cycles at different frequencies; select a target available cycle whose available cycle number is greater than the number of transmission cycles in the maximum path bandwidth and has the smallest difference with the number of transmission cycles in the maximum path bandwidth; and adjust the operating frequency of the interconnect module according to the frequency corresponding to the target available cycle.

[0013] In the above embodiments, the number of available cycles at different frequencies can be obtained, and a target available cycle can be selected. Then, the operating frequency of the interconnect module can be adjusted according to the frequency corresponding to the target available cycle. Since the target available cycle is selected when the number of available cycles is greater than the number of transmission cycles in the maximum path bandwidth and the difference between the number of available cycles and the number of transmission cycles in the maximum path bandwidth is the smallest, the number of idle cycles (i.e., the number of cycles without data transmission) can be reduced as much as possible. This can also ensure that the data is transmitted within the specified time and reduce the power consumption of the interconnect module to the greatest extent.

[0014] In one possible implementation of the first aspect embodiment, the chip includes multiple interconnect modules operating in the same clock domain; the power management module is further configured to acquire a target path bandwidth and adjust the operating frequency of the multiple interconnect modules according to the target path bandwidth; wherein the target path bandwidth is the maximum path bandwidth among the maximum path bandwidths of the multiple interconnect modules.

[0015] In the above embodiments, when the chip contains multiple interconnect modules operating in the same clock domain, the maximum path bandwidth among the maximum path bandwidths of each of the multiple interconnect modules is selected as the target path bandwidth, and the operating frequency of these multiple interconnect modules is adjusted accordingly. This ensures that interconnect modules with high bandwidth requirements always have sufficient bandwidth, avoids data transmission blockage due to insufficient frequency, and achieves the goal of reducing power consumption while meeting the bandwidth requirements of interconnect modules with high bandwidth requirements.

[0016] In one possible implementation of the first aspect embodiment, the interconnect module includes an AON unit; the power management module is configured to control other units in the interconnect module, except for the AON unit, to be in a power-down state when the interconnect module is in an idle state, so that the interconnect module is in a low-power mode.

[0017] In the above embodiments, when the interconnect module is in an idle state, the power management module controls the other units in the interconnect module, except for the AON unit, to be in a power-down state. By turning off the power supply to most of the logic in the interconnect module and only retaining a small amount of logic power supply for wake-up, power consumption can be saved as much as possible.

[0018] In one possible implementation of the first aspect embodiment, the AON unit in the interconnect module is used to control other units in the interconnect module, except for the AON unit, to be in a power-down state when the interconnect module is in an idle state, so that the interconnect module is in a low-power mode.

[0019] In the above embodiments, when the interconnect module is in an idle state, the AON unit in the interconnect module controls other units in the interconnect module to be in a power-off state. By turning off the power supply to most of the logic in the interconnect module and only retaining a small amount of logic power supply for wake-up, power consumption can be saved as much as possible.

[0020] In one possible implementation of the first aspect embodiment, the AON unit is configured to control the other unit to reset when the interconnect module is in an idle state, and to isolate the other unit from the AON unit after the reset is completed, and to control the other unit to power off after the isolation is completed.

[0021] In the above embodiments, when the interconnect module is in an idle state, the power-off of other units is controlled in the order of first resetting → then isolating → then powering off. This can balance functional safety and power consumption optimization. Resetting can ensure that the module state is controllable, and isolation can prevent electrical interference and current backflow. It can reduce the logic state confusion and leakage safety caused by not resetting or isolating, and ensure the logical correctness of the interconnect module.

[0022] In one possible implementation of the first aspect embodiment, the AON unit in the interconnect module is further configured to, upon receiving a data request from the target module, if it is detected that the interconnect module is currently in a low-power mode, control other units in the interconnect module to power on, release the isolation between the other units and the AON unit after power-on, and control the other units to release the reset state and resume the operating state after the isolation is released.

[0023] In the above embodiments, upon receiving a data request from the target module, the power-on of other units is controlled in the order of power-on → de-isolation → de-reset. This balances functional safety and power consumption optimization, and prevents the power-down area from affecting the normal operation of the non-power-down area during the power-on process.

[0024] Secondly, embodiments of this application also provide an electronic device, including: a chip provided as described in the first aspect embodiments and / or in any possible implementation of the first aspect embodiments.

[0025] Thirdly, embodiments of this application also provide a power consumption control method for a chip, comprising: acquiring the path bandwidth between an interconnect module in the chip and a target module connected to the interconnect module over a period of time; and adjusting the operating frequency of the interconnect module according to the various path bandwidths of the interconnect module.

[0026] In a possible implementation of the third aspect embodiment, the method further includes: when the interconnect module is in an idle state, controlling other units in the interconnect module except for the AON unit to be in a power-down state, so that the interconnect module is in a low-power mode.

[0027] In one possible implementation of the third aspect embodiment, the method further includes: upon receiving a data request from the target module, if it is detected that the interconnect module is currently in a low-power mode, controlling other units in the interconnect module to power on, releasing the isolation between the other units and the AON unit after power-on, and controlling the other units to release the reset state and resume the operating state after releasing the isolation.

[0028] The effectiveness of the third aspect embodiment described above can be referred to the effectiveness of the same part in the first aspect embodiment.

[0029] Other features and advantages of this application will be set forth in the following description. The objectives and other advantages of this application can be realized and obtained through the structures specifically pointed out in the written description and the accompanying drawings. Attached Figure Description

[0030] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the accompanying drawings used in the embodiments will be briefly described below. Obviously, the drawings described below are only some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings. The above and other objects, features, and advantages of this application will become clearer through the accompanying drawings.

[0031] Figure 1 A schematic diagram of the structure of a chip provided in an embodiment of this application is shown.

[0032] Figure 2 This illustration shows a schematic diagram of a chip connected to other modules or devices according to an embodiment of this application.

[0033] Figure 3 This illustration shows a schematic diagram of the principle of adjusting the operating frequency of an interconnect module using a chip according to an embodiment of this application.

[0034] Figure 4 This illustration shows a schematic diagram of the power-on and power-off principle of an interconnect module in a control chip according to an embodiment of this application.

[0035] Figure 5 A schematic diagram of the structure of an electronic device provided in an embodiment of this application is shown.

[0036] Figure 6 A schematic flowchart of a chip power consumption control method provided in an embodiment of this application is shown. Detailed Implementation

[0037] The technical solutions of the embodiments of this application will now be described with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. The following embodiments are provided as examples to more clearly illustrate the technical solutions of this application, and should not be used to limit the scope of protection of this application. Those skilled in the art will understand that, without conflict, the following embodiments and features can be combined with each other.

[0038] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. Furthermore, relational terms such as "first," "second," etc., in the description of this application are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus.

[0039] Furthermore, the term "and / or" in this application is merely a description of the relationship between related objects, indicating that there can be three relationships. For example, A and / or B can represent three situations: A exists alone, A and B exist simultaneously, and B exists alone.

[0040] In the description of the embodiments of this application, unless otherwise expressly specified and limited, the technical term "connection" can be a direct connection or an indirect connection through an intermediate medium.

[0041] As chip computing power increases, data throughput grows, data path area expands, and power consumption rises. To reduce chip power consumption, this application provides a chip power consumption control method. This method monitors the bandwidth of the interconnect module in the chip and adjusts the operating frequency of the interconnect module based on the monitored bandwidth to reduce power consumption.

[0042] The following is combined with Figure 1 The chip provided in the embodiments of this application will be described. For example... Figure 1 As shown, the chip includes multiple functional modules and interconnect modules, among which the functional modules include a power management module.

[0043] Any two functional modules in a chip are connected through at least one interconnect module. For example, functional module A can be connected to functional module B through multiple interconnect modules in series. Functional modules in a chip refer to independent hardware modules designed to perform specific functions within an integrated circuit. These functional modules work together to complete the overall task of the chip. Different chips may contain different types of functional modules.

[0044] In addition to the power management module mentioned above, the functional modules may, in some possible implementations, include, but are not limited to, at least one of the following modules: CPU core, GPU (Graphics Processing Unit) core, System Management Processor (SMP), Memory Controller (MC), Multimedia Hub, and I / O Hub. These modules are all connected via a Data Fabric Cross Bus (a type of interconnect module), as illustrated in the diagram below. Figure 2 As shown. The MC can connect to memory, such as DDR (Double Data Rate) memory. The multimedia connector can be used to connect multimedia units or devices, such as audio and display units or devices. The IO (Input / Output) connector is used to connect I / O devices. In some implementations, DDR can also be a chip.

[0045] Of the aforementioned functional modules, some can act as request initiators, some as request receivers, and a few can act as both. Request initiators and receivers communicate via an interconnect module.

[0046] Interconnect modules are fundamental modules responsible for coordinating communication between various functional modules within a chip, connecting these modules. As chip complexity increases, the area and power consumption of interconnect modules also increase. Managing the power consumption of interconnect modules helps reduce overall power consumption. Interconnect modules include, but are not limited to, Network-on-Chip (NoC), Crossbars, and Data Fabrics.

[0047] The interconnect module is used to monitor the bandwidth of the path between the interconnect module and the target module over a configurable period of time. The time window for monitoring the bandwidth of the path is configurable; for example, it can monitor the bandwidth of the path flowing through the interconnect module within 1 second. The bandwidth of the path measures the amount of information transmitted in a communication link or data path per unit time. For example, the bandwidth can include the transmitted data flow or the number of transmission cycles within a preset time window.

[0048] The target module is the module connected to the interconnect module. The target module can be a functional module or an interconnect module. Since one interconnect module can interconnect many target modules, the interconnect module can monitor multiple path bandwidths. For example, for Figure 1 The interconnect module located on the left has four channel ports and connects to four target modules. Each channel port corresponds to a channel bandwidth.

[0049] The power management module acquires the bandwidth of each path monitored by the interconnect module and adjusts the operating frequency of the interconnect module based on the bandwidth of each path. The power management module can dynamically adjust the operating frequency of the interconnect modules in the data path according to power consumption strategies (such as power-priority strategies, efficiency-priority strategies, etc.) and the current path bandwidth. That is, when the path bandwidth requirement of the interconnect module decreases, the operating frequency of the interconnect module can be appropriately reduced; when the path bandwidth requirement of the interconnect module increases, the operating frequency of the interconnect module can be appropriately increased to meet the bandwidth requirement. The operating frequency of the interconnect module can be the clock frequency at which the interconnect module operates.

[0050] In some implementations, the interconnect module can record the monitored bandwidth of each path into a register or memory, and the power management module can obtain the bandwidth of each path monitored by the interconnect module by reading the data in the register or memory.

[0051] A bandwidth monitoring module (which can be firmware) can be added to the interconnect module to monitor the bandwidth of the interconnect modules in the data path in real time. Since the ACPI protocol does not define the operating status of the interconnect modules connecting various functional modules within the chip, and the interconnect bus in the data path is transparent to software such as the operating system, the software sends an address, the address is routed to a predetermined location, and accesses the corresponding device. The software does not care which modules this address passes through to reach the target device, resulting in poor management of power consumption in the data path, leading to high chip power consumption and wasted power. This application addresses this issue by adding a bandwidth monitoring module to the data path to monitor the bandwidth in real time and dynamically adjust the operating frequency of the interconnect modules in the data path based on the current bandwidth.

[0052] In one possible implementation, the power management module is used to obtain the maximum path bandwidth among the various path bandwidths monitored by the interconnect module, and adjust the operating frequency of the interconnect module according to the maximum path bandwidth. In this implementation, the process of the power management module adjusting the operating frequency of the interconnect module according to the various path bandwidths may include: obtaining the maximum path bandwidth among the various path bandwidths monitored by the interconnect module, and adjusting the operating frequency of the interconnect module according to the maximum path bandwidth.

[0053] In some other implementations, when the power management module adjusts the operating frequency of the interconnect module according to the bandwidth of each path, the process may include: obtaining the sum of the bandwidths of each path monitored by the interconnect module, and adjusting the operating frequency of the interconnect module according to the total bandwidth of the path.

[0054] The path bandwidth includes the number of transmission cycles within a preset time window. When adjusting the operating frequency of the interconnect module based on the maximum path bandwidth, the process may include: determining the required minimum frequency based on the number of transmission cycles in the maximum path bandwidth, and adjusting the operating frequency of the interconnect module based on the minimum frequency. For example, setting the operating frequency of the interconnect module to the minimum frequency. In this implementation, the power management module is used to: determine the required minimum frequency based on the number of transmission cycles in the maximum path bandwidth, and adjust the operating frequency of the interconnect module based on the minimum frequency.

[0055] For example, assuming the current interconnect module's clock frequency is 1 GHz, the corresponding time period is 1 nanosecond, and the preset time window is 1 microsecond (corresponding to 1000 cycles), with 10 cycles (corresponding to a time period of 10 nanoseconds) for data transmission. Therefore, the minimum frequency of the interconnect module required to transmit 10 cycles within the preset time window (1 microsecond) is 10 MHz. Since 10 MHz corresponds to a clock period of 100 nanoseconds, there are 10 cycles within the same time (i.e., 1 microsecond), meaning 1 GHz (corresponding to a time of 1 nanosecond) * 1000 cycles = 10 MHz (corresponding to a time of 100 nanoseconds) * 10 cycles. By configuring the interconnect module's clock frequency to 10 MHz, power consumption is reduced due to the slower frequency, but data can still be transmitted within the specified time (e.g., 1 microsecond).

[0056] When adjusting the operating frequency of the interconnect module based on the minimum frequency, the operating frequency of the interconnect module can also be set to a frequency higher than the minimum frequency. For example, if the clock frequency of the interconnect module is adjusted to 500MHz, there are 500 cycles in the same time period, but only 10 cycles are used for data transmission; if the clock frequency of the interconnect module is adjusted to 100MHz, there are 100 cycles in the same time period, but only 10 cycles are used for data transmission; if the clock frequency of the interconnect module is adjusted to 10MHz, there are 10 cycles in the same time period, and 10 cycles are used for data transmission. Thus, when the clock frequency of the interconnect module is reduced, such as adjusting the clock frequency of the interconnect module to 100MHz, there are 100 cycles in the same time period, and only 10 cycles are used for data transmission. It can be seen that within the same time period, as the frequency decreases, the power consumption decreases, the number of cycles required for data transmission remains the same (10 cycles), and the data can still be transmitted within the specified time (e.g., 1 microsecond), but the number of idle cycles (i.e., the number of cycles without data transmission) decreases.

[0057] In some possible implementations, when the path bandwidth includes the number of transmission cycles within a preset time window, the process of adjusting the operating frequency of the interconnect module according to the maximum path bandwidth may further include: calculating the number of available cycles at different frequencies within the preset time window; selecting a target available cycle whose available cycle number is greater than the number of transmission cycles in the maximum path bandwidth and has the smallest difference between the two; and adjusting the operating frequency of the interconnect module according to the frequency corresponding to the target available cycle. For example, the operating frequency of the interconnect module is adjusted to the frequency corresponding to the target available cycle. In this implementation, the power management module is used to: obtain the number of available cycles at different frequencies; select a target available cycle whose available cycle number is greater than the number of transmission cycles in the maximum path bandwidth and has the smallest difference between the two; and adjust the operating frequency of the interconnect module according to the frequency corresponding to the target available cycle.

[0058] Assuming a preset time window of 1 microsecond and a current interconnect module clock frequency of 1 GHz, only 10 out of 1000 cycles (corresponding to 1 microsecond) will transmit data. If the interconnect module's clock frequency is adjusted to 500 MHz, 500 cycles will be available; if adjusted to 100 MHz, 100 cycles will be available; if adjusted to 10 MHz, 10 cycles will be available; if adjusted to 5 MHz, 5 cycles will be available; and if adjusted to 1 MHz, 1 cycle will be available. When selecting the target available cycle according to the above rules, the 10 available cycles in the example above can be chosen as the target available cycle, thus the frequency corresponding to the target available cycle is 10 MHz.

[0059] In some possible implementations, the power management module can also adjust the operating frequency of the interconnect module by combining historical path bandwidth information. For example, when adjusting the operating frequency of the interconnect module based on the maximum path bandwidth, the power management module can: if the maximum path bandwidth is greater than the maximum path bandwidth at a historical time, adjust the operating frequency of the interconnect module from the current first frequency to the second frequency; wherein the first frequency is less than the second frequency; if the maximum path bandwidth is less than the maximum path bandwidth at a historical time, adjust the operating frequency of the interconnect module from the current first frequency to the third frequency; wherein the first frequency is greater than the third frequency.

[0060] The operating frequency of the interconnect module is adjusted by combining the historical maximum path bandwidth to avoid affecting efficiency if the frequency is set too low or too high. The first frequency, second frequency, and third frequency mentioned above are all clock frequencies used by the interconnect module during operation.

[0061] The maximum path bandwidth at the aforementioned historical moment can be the maximum path bandwidth recorded over a period of time. For example, it can be the path bandwidth recorded every 1 ms within the first 10 ms (configurable), and the highest path bandwidth within these 10 ms can be used as the basis for frequency adjustment. In some implementations, when adjusting the operating frequency of the interconnect module by combining the path bandwidth information from historical records, it can also be based on the maximum path bandwidth of the previous preset number of times (e.g., 5 times). If the difference in the maximum path bandwidth of these preset number of times is relatively large, it indicates large bandwidth jitter, and the frequency can be temporarily not adjusted; or the frequency can be adjusted according to the maximum path bandwidth in the preset number of times; in addition, if the maximum path bandwidth in the preset number of times shows a downward trend, the frequency can be adjusted as soon as possible, etc.

[0062] Specifically, when recording the maximum bandwidth for each preset number of times, different recording precisions can be used based on the time interval. For example, for the first 10ms, only the maximum 1ms bandwidth record is retained every 10ms, and this 1ms record is used as the recording result for that 10ms. Similarly, for the first 100ms, only the maximum 1ms bandwidth record is retained every 100ms, and this 1ms record is used as the recording result for that 100ms. For the first 90ms, since there is one recording result every 10ms, there are 9 maximum bandwidth records. When the time reaches the first 100ms, the maximum bandwidth is selected from the maximum bandwidth corresponding to the first 90ms and the maximum bandwidth corresponding to the last 10ms, and used as the recording result for that 100ms.

[0063] In some possible implementations, the chip includes multiple interconnect modules operating in the same clock domain. In this case, the power management module is also used to obtain a target path bandwidth and adjust the operating frequency of the multiple interconnect modules according to the target path bandwidth. The target path bandwidth is the maximum path bandwidth among the maximum path bandwidths of the multiple interconnect modules. For example, assuming there are three interconnect modules operating in the same clock domain, namely interconnect module 1, interconnect module 2, and interconnect module 3, each interconnect module has a corresponding maximum path bandwidth. Then, the target path bandwidth is the maximum path bandwidth among the three maximum path bandwidths corresponding to these three interconnect modules.

[0064] In this case, when adjusting the operating frequency of multiple interconnect modules according to the target path bandwidth, the operating frequencies of multiple interconnect modules can be adjusted to the same operating frequency. The adjustment process can be the same as the process of adjusting the operating frequency of interconnect modules according to the maximum path bandwidth, which will not be repeated here.

[0065] In some possible implementations, the power management module, when controlling the power consumption of the interconnect module, can operate on the principle of... Figure 3 As shown, the power management module monitors the effective data traffic of the interconnect module over a period of time and determines whether its clock frequency needs to be adjusted based on the monitored data traffic and the current clock frequency of the interconnect module. If so, the clock frequency of the interconnect module is adjusted while meeting the bandwidth requirements. After the clock frequency is adjusted, the effective path bandwidth of the interconnect module continues to be monitored, that is, the effective data traffic of the interconnect module continues to be monitored over a period of time.

[0066] When determining whether to adjust the clock frequency of an interconnect module based on monitored data traffic and the current clock frequency, this can be done using power consumption strategies (such as power-priority strategies or efficiency-priority strategies) and the current clock frequency of the interconnect module. When calculating the required clock frequency adjustment, various algorithms, such as machine learning, can be used based on historical data of effective bandwidth to calculate a suitable clock frequency that meets both bandwidth requirements and optimizes power consumption. Furthermore, adjustments can be made using the methods described above. For example, if only 10 out of 1000 cycles transmit data, the clock frequency can be configured to be adjusted to 1 / 10 of its original frequency.

[0067] In some possible implementations, the power management module is also used to control the interconnect modules to enter a low-power mode when they are idle. If an interconnect module in the data path is idle, it can be powered down via hardware control, retaining only a small amount of wake-up logic. When there is a data request, it can be automatically powered on. Hardware-controlled power-down and power-on do not require software intervention, resulting in fast response and further power savings. This avoids interconnect modules operating even when idle, thus preventing power waste.

[0068] For example, some application devices occasionally initiate DMA (Direct Memory Access) access. At this time, there is only a small amount of data transmission in the data path, but it still works in full-speed mode, resulting in wasted power consumption. Another example is CPU memory access scenarios, where the I / O device does not access data, but the entire interconnect module is still working, resulting in wasted power consumption. In this case, the interconnect module can be powered down by hardware control, with only a small amount of wake-up logic retained. When there is a data request, it can be automatically powered on, which can save power consumption as much as possible.

[0069] The interconnect module includes an AON (Always On Domain) unit. The AON unit is not a single module, but a collection of core modules that maintain basic functions in a low-power system. For example, it may include a real-time clock, interrupt controller, power management unit, communication interface, etc. It is a key module in the embedded system, mainly used to maintain the continuous operation of specific functions when the main system is in sleep or off, and to ensure that critical tasks are uninterrupted. For example, it maintains time synchronization when the system is in sleep, is responsible for handling wake-up events, and maintains basic functions.

[0070] In some possible implementations, the AON unit can be powered independently, and the AON unit and other units in the interconnect module can be in different power domains, such as... Figure 2 The AON unit is powered from power domain 2, while other units are powered from power domain 1. The AON unit can control the power supply from power domain 1 to other units. For example, a switch can be installed on the power supply line of other units, and the power supply to other units can be controlled by controlling the on / off state of the switch. Alternatively, the AON unit and other units can be in the same power domain, rather than being powered independently. However, the AON unit is always powered on by default, and the power supply to other units is controlled by the AON unit. For example, a switch can be installed on the power supply line of other units, and the power supply to other units can be controlled by controlling the on / off state of the switch.

[0071] When the interconnect module is in a low-power mode, the power management module controls all units in the interconnect module except for the AON unit to be powered down, thus putting the interconnect module in a low-power mode. In other words, when the interconnect module is idle, it shuts off power to most of the logic within the interconnect module, retaining only a small amount of power for wake-up. For example, when the interconnect module is idle, the power management module can send a power-down command to the AON unit in the interconnect module to control the interconnect module to enter a low-power mode.

[0072] It is possible that the AON unit in the interconnect module, upon receiving a power-down command from the power management module, controls all other units in the interconnect module except the AON unit to be in a power-down state. In some other possible implementations, the AON unit in the interconnect module itself can control all other units in the interconnect module except the AON unit to be in a power-down state when the interconnect module is in an idle state, thereby putting the interconnect module into a low-power mode.

[0073] The AON unit can control other units to reset when the interconnect module is idle, isolate other units from the AON unit after the reset, and control other units to power down after isolation. For example, the AON unit can send a reset signal to other units to reset them to a reset state, and after the reset is complete, send an isolation valid signal to other units to isolate them from the AON unit, and then control other units to power down.

[0074] The AON unit is also used to, upon receiving a data request from the target module, if it detects that the interconnect module is currently in a low-power mode, control other units in the interconnect module to power on, release the isolation between the other units and the AON unit after power-on, and control the other units to unreset and resume operation after releasing the isolation. For example, when the interconnect module is in a low-power state, the AON unit monitors the data request from the target module in real time. Upon receiving a data request from the target module, if it detects that the interconnect module is currently in a low-power mode, the AON unit controls other units in the interconnect module to power on, then sends an isolation invalidation signal to the other units to release the isolation between the other units and the AON unit, and finally sends a de-reset signal to the other units to unreset and resume operation.

[0075] Among them, the idle state of the interconnect module can be determined by the channel bandwidth monitored over a period of time. If the channel bandwidth indicates no or very little data transmission over a period of time, the interconnect module can be considered to be in an idle state.

[0076] The power-on or power-off principles of the units other than the AON unit in the aforementioned control interconnection module can be found in [reference needed]. Figure 4 The process is as follows: By monitoring the bandwidth of the interconnect module over a period of time, when the interconnect module is determined to be in an idle state based on the monitored bandwidth, the power supply to most of the interconnect module's logic is turned off, leaving only a small amount of power supply for wake-up. In other words, the interconnect module is controlled to be in a power-off state except for the AON unit. Then, when a data request is received from the target module, the power supply to most of the interconnect module's logic (i.e., other units) is restored and the configuration is restored. In this way, the interconnect module returns to the working state and can process the data request.

[0077] The aforementioned chip can be, but is not limited to, a processor. It can be a general-purpose processor, including a Central Processing Unit (CPU), a Network Processor (NP), a Graphics Processing Unit (GPU), an Accelerated Processing Unit (ACCU), a Multimedia Application Processor (MAP), a microprocessor, etc.; it can also be a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. It can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this application. Alternatively, the processor can also be any conventional processor.

[0078] In addition, chips that include the aforementioned interconnect modules and power management modules can also include memory controller chips, wireless communication chips, Internet of Things chips, and automotive electronic control units.

[0079] This application also provides an electronic device that includes the aforementioned chip. When the chip is a processor, one possible implementation is as follows: Figure 5 As shown, the electronic device includes: a transceiver, a memory, a communication bus, and a processor.

[0080] The transceiver, memory, and processor are electrically connected directly or indirectly to achieve data transmission or interaction. For example, these components can be electrically connected to each other through one or more communication buses or signal lines. The transceiver is used to send and receive data. The memory stores computer programs, and the processor executes the software functional modules or computer programs stored in the memory.

[0081] The memory can be, but is not limited to, Random Access Memory (RAM), Read Only Memory (ROM), Programmable Read-Only Memory (PROM), Erasable Programmable Read-Only Memory (EPROM), Electrically Erasable Programmable Read-Only Memory (EEPRO), etc.

[0082] The aforementioned electronic devices include, but are not limited to, mobile phones, tablets, computers, network devices, in-vehicle devices, servers, etc.

[0083] This application also provides a chip power consumption control method, which will be described below in conjunction with... Figure 6 The principle behind it is explained. This power consumption control method includes: S1 and S2.

[0084] S1: Obtain the path bandwidth between the interconnect module in the chip and the target module connected to the interconnect module within a certain period of time.

[0085] Since an interconnect module can interconnect many target modules, when obtaining the path bandwidth between the interconnect module and the target module connected to the interconnect module in the chip over a period of time, multiple path bandwidths of the interconnect module can be obtained.

[0086] In some possible implementations, the power management module in the chip can obtain the path bandwidth between the interconnect module in the chip and the target module connected to the interconnect module over a period of time.

[0087] S2: Adjust the operating frequency of the interconnect module according to the bandwidth of each path of the interconnect module.

[0088] After obtaining the bandwidth of each path of the interconnect module, the operating frequency of the interconnect module can be adjusted based on the bandwidth of each path and the power consumption strategy.

[0089] In some possible implementations, the power management module in the chip can adjust the operating frequency of the interconnect module according to the bandwidth of each path of the interconnect module.

[0090] In some possible implementations, the process of S2 may include: obtaining the maximum path bandwidth among the various path bandwidths, and adjusting the operating frequency of the interconnect module according to the maximum path bandwidth.

[0091] In some possible implementations, when adjusting the operating frequency of the interconnect module according to the maximum path bandwidth, the process may include: determining the required minimum frequency based on the number of transmission cycles in the maximum path bandwidth, and adjusting the operating frequency of the interconnect module according to the minimum frequency.

[0092] In some possible implementations, when adjusting the operating frequency of the interconnect module according to the maximum path bandwidth, the process may include: obtaining the number of available cycles at different frequencies; selecting a target available cycle whose number of available cycles is greater than the number of transmission cycles in the maximum path bandwidth and whose difference from the number of transmission cycles in the maximum path bandwidth is the smallest; and adjusting the operating frequency of the interconnect module according to the frequency corresponding to the target available cycle.

[0093] In some possible implementations, the chip includes multiple interconnect modules operating in the same clock domain. The implementation process of S2 may include: selecting a target path bandwidth from the various path bandwidths of the multiple interconnect modules operating in the same clock domain, and adjusting the operating frequency of the multiple interconnect modules operating in the same clock domain according to the target path bandwidth. The target path bandwidth is the maximum path bandwidth among the maximum path bandwidths of each of these multiple interconnect modules.

[0094] In some possible implementations, the above method further includes: when the interconnect module is in an idle state, controlling other units in the interconnect module except for the AON unit to be in a power-off state, so that the interconnect module is in a low-power mode.

[0095] In some possible implementations, the power management module in the chip can control the other units in the interconnect module, except for the AON unit, to be in a power-down state, so that the interconnect module is in a low-power mode. In other possible implementations, the AON unit in the interconnect module can control the other units, except for the AON unit, to be in a power-down state, so that the interconnect module is in a low-power mode.

[0096] In some possible implementations, when other units in the control interconnect module, except for the AON unit, are in a power-off state, the process may include: controlling other units to reset, isolating other units from the AON unit after the reset is completed, and controlling other units to power off after the isolation is completed.

[0097] In some possible implementations, the above method further includes: upon receiving a data request from the target module, if it is detected that the interconnect module is currently in a low-power mode, controlling other units in the interconnect module to power on, releasing the isolation between the other units and the AON unit after powering on, and controlling the other units to release the reset state and resume operation after releasing the isolation.

[0098] In some possible implementations, the AON unit in the interconnect module can control other units in the interconnect module to power on when it detects that the interconnect module is currently in a low-power mode and receives a data request from the target module. After powering on, the isolation between other units and the AON unit is released, and after the isolation is released, the other units are controlled to release the reset state and resume the operating state.

[0099] The implementation principle and technical effects of the method embodiment are the same as those of the aforementioned chip embodiment. For the sake of brevity, any parts not mentioned in the method embodiment can be referred to the corresponding content in the aforementioned chip embodiment.

[0100] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0101] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can also be implemented in other ways. The apparatus embodiments described above are merely illustrative. For example, the flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions marked in the blocks may occur in a different order than those marked in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram and / or flowchart, and combinations of blocks in block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0102] In addition, the functional modules in the various embodiments of this application can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0103] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A chip, characterized in that, include: Multiple functional modules, including a power management module; An interconnect module is provided, through which any two functional modules are connected. The interconnect module is used to monitor the path bandwidth between the interconnect module and the target module connected to the interconnect module within a certain period of time. The path bandwidth includes the number of transmission cycles of the interconnect module for data transmission within a preset time window. The power management module is used to obtain the bandwidth of each path monitored by the interconnect module, and adjust the operating frequency of the interconnect module according to the number of transmission cycles in the maximum bandwidth of each path.

2. The chip according to claim 1, characterized in that, The power management module is used for: The required minimum frequency is determined based on the number of transmission cycles in the maximum path bandwidth, and the operating frequency of the interconnect module is adjusted based on the minimum frequency.

3. The chip according to claim 1, characterized in that, The power management module is used for: Obtain the number of available cycles at different frequencies; Select the target available period whose number of available periods is greater than the number of transmission periods in the maximum path bandwidth and whose difference from the number of transmission periods in the maximum path bandwidth is the smallest; The operating frequency of the interconnect module is adjusted according to the frequency corresponding to the available period of the target.

4. The chip according to claim 1, characterized in that, The chip includes multiple interconnect modules operating in the same clock domain; the power management module is also used to obtain the target path bandwidth and adjust the operating frequency of the multiple interconnect modules according to the target path bandwidth. The target path bandwidth is the maximum path bandwidth among the maximum path bandwidths of the plurality of interconnected modules.

5. The chip according to claim 1, characterized in that, The interconnect module includes an AON unit; The power management module is used to control other units in the interconnect module, except for the AON unit, to be in a power-down state when the interconnect module is in an idle state, so that the interconnect module is in a low-power mode.

6. The chip according to claim 1, characterized in that, The AON unit in the interconnect module is used to control other units in the interconnect module, except for the AON unit, to be in a power-down state when the interconnect module is in an idle state, so that the interconnect module is in a low-power mode.

7. The chip according to claim 6, characterized in that, The AON unit is used to control the other units to reset when the interconnect module is in an idle state, and to isolate the other units from the AON unit after the reset is completed, and to control the other units to power off after the isolation is completed.

8. The chip according to claim 6 or 7, characterized in that, The AON unit in the interconnect module is also used to, upon receiving a data request from the target module, if it detects that the interconnect module is currently in a low-power mode, control other units in the interconnect module to power on, release the isolation between the other units and the AON unit after power-on, and control the other units to release the reset state and resume operation after the isolation is released.

9. An electronic device, characterized in that, include: The chip as described in any one of claims 1-8.

10. A method for controlling the power consumption of a chip, characterized in that, include: The path bandwidth between the interconnect module in the chip and the target module connected to the interconnect module is obtained within a certain period of time, wherein the path bandwidth includes the number of transmission cycles of the interconnect module for data transmission within a preset time window; The operating frequency of the interconnect module is adjusted according to the number of transmission cycles in the maximum bandwidth of each path of the interconnect module.

11. The method according to claim 10, characterized in that, The method further includes: When the interconnect module is in an idle state, control all units in the interconnect module except for the AON unit to be in a power-down state, so that the interconnect module is in a low-power mode.

12. The method according to claim 11, characterized in that, The method further includes: Upon receiving a data request from the target module, if it is detected that the interconnect module is currently in a low-power mode, the system controls other units in the interconnect module to power on. After powering on, the isolation between the other units and the AON unit is released, and after the isolation is released, the system controls the other units to release the reset state and resume operation.

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