A pointer-based dynamic control method and system for data filling

Abstract

This application discloses a pointer-based dynamic data filling control method and system. By using a built-in mapping table in the flash cache, the number of times the flash controller calls the preset interface is reduced. In addition, by adopting the setting of writing a small amount of data to the first flash storage area cache first and then writing a large amount of data to the second flash storage area, the amount of filling data required in the data filling operation of a single write operation is greatly reduced, thereby reducing the amount of data written from the host cache to the flash storage area, improving the utilization rate of the bandwidth resources of the preset interface, and effectively controlling the write amplification problem.

Description

Technical Field

[0001] This application belongs to the field of flash memory technology, specifically relating to a pointer-based dynamic data filling control method and system. Background Technology

[0002] Currently, some flash memory products use Host Memory Buffer (HMB) technology to balance cost and performance requirements. HMB technology refers to the use of host-allocated target memory as memory for flash memory devices.

[0003] In practical applications, the inventors found that in high-frequency request scenarios for front-end data services, such flash memory products cause delays and instability in data services due to excessively frequent calls to the flash memory controller interface, which urgently needs improvement and optimization. Summary of the Invention

[0004] This application provides a pointer-based dynamic data filling control method and system to improve the latency and instability issues in high-frequency data service request scenarios of existing flash memory products using HMB technology, caused by excessively frequent calls to the flash controller interface. By reducing the number of times the flash controller calls the preset interface through the built-in mapping table of the flash cache, and by adopting the setting of writing small amounts of data to the first flash storage area cache first and large amounts of data to the second flash storage area, the amount of filling data required in the data filling operation of a single write operation is greatly reduced, thereby reducing the amount of data written from the host cache to the flash storage area, improving the utilization rate of the bandwidth resources of the preset interface, and effectively controlling the write amplification problem.

[0005] In a first aspect, embodiments of this application provide a pointer-based dynamic data filling control method applied to a flash memory device. The flash memory controller is communicatively connected to the host controller of a host. The flash memory device includes the flash memory controller, a flash memory cache module, and a flash memory storage module. The host includes the host controller and a host memory module.

[0006] The host memory module is configured as a cache area for the flash memory device. The flash memory module is configured with a first flash memory area and a second flash memory area. The capacity of the first minimum write block of the first flash memory area is smaller than the capacity of the second minimum write block of the second flash memory area. The flash memory controller accesses the first host memory area through a preset interface.

[0007] The flash memory cache module is used to cache the host memory mapping table and address mapping table of the flash memory device. The host memory mapping table includes address information of the first host memory region and a first pointer. The first pointer is used to indicate the starting offset address of the next data to be cached in the first host memory region. The address mapping table includes the mapping relationship between the physical address of the data stored in the flash memory cache module and the logical address of the data, as well as a second pointer and a third pointer. The second pointer is used to indicate the starting offset address of the next data to be written in the first flash memory region, and the third pointer is used to indicate the starting offset address of the next data to be written in the second flash memory region.

[0008] The method includes:

[0009] Receive a first data write instruction from the host;

[0010] Parse the first data write instruction to obtain the first data to be written;

[0011] The first pointer is obtained by querying the host memory mapping table in the flash memory cache module, and the first data is cached in the first host memory range according to the first pointer by calling the preset interface.

[0012] The second pointer and the third pointer are obtained by querying the address mapping table in the flash memory cache module;

[0013] The preset interface is invoked to perform a first data filling operation to obtain second data that can fill the first minimum write block; and the first pointer of the host memory mapping table is updated;

[0014] The system calls the preset interface to write the second data into the first flash memory storage area according to the second pointer; updates the second pointer in the address mapping table; and creates a mapping relationship between the first physical address and the first logical address of the first data in the address mapping table.

[0015] If it is determined that the size of the third data already written in the first flash memory storage area is equal to the capacity of the second minimum write block, the third data is written to the second flash memory storage area according to the third pointer; and the third pointer in the address mapping table is updated; and the mapping relationship between the physical address and logical address of the third data is updated.

[0016] Secondly, embodiments of this application provide a pointer-based data filling dynamic control system, including a host and a flash memory device. The flash memory device is communicatively connected to the host and includes a flash memory controller, a flash memory cache module, and a flash memory storage module. The host includes a host controller and a host memory module.

[0017] The host memory module is configured as a cache area for the flash memory device. The flash memory module is configured with a first flash memory area and a second flash memory area. The capacity of the first minimum write block of the first flash memory area is smaller than the capacity of the second minimum write block of the second flash memory area. The flash memory controller accesses the first host memory area through a preset interface.

[0018] The flash memory cache module is used to cache the host memory mapping table and address mapping table of the flash memory device. The host memory mapping table includes address information of the first host memory region and a first pointer. The first pointer is used to indicate the starting offset address of the next data to be cached in the first host memory region. The address mapping table includes the mapping relationship between logical addresses and physical addresses, as well as a second pointer and a third pointer. The second pointer is used to indicate the starting offset address of the next data to be written in the first flash memory region, and the third pointer is used to indicate the starting offset address of the next data to be written in the second flash memory region.

[0019] The flash memory controller is configured to perform the following operations:

[0020] Receive a first data write instruction from the host;

[0021] Parse the first data write instruction to obtain the first data to be written;

[0022] The first pointer is obtained by querying the host memory mapping table in the flash memory cache module, and the first data is cached in the first host memory range according to the first pointer by calling the preset interface.

[0023] The second pointer and the third pointer are obtained by querying the address mapping table in the flash memory cache module;

[0024] The preset interface is invoked to perform a first data filling operation to obtain second data that can fill the first minimum write block; and the first pointer of the host memory mapping table is updated;

[0025] The system calls the preset interface to write the second data into the first flash memory storage area according to the second pointer; updates the second pointer in the address mapping table; and creates a mapping relationship between the first physical address and the first logical address of the first data in the address mapping table.

[0026] If it is determined that the size of the third data already written in the first flash memory storage area is equal to the capacity of the second minimum write block, the third data is written to the second flash memory storage area according to the third pointer; and the third pointer in the address mapping table is updated; and the mapping relationship between the physical address and logical address of the third data is updated.

[0027] As can be seen from the embodiments of this application, in the case of existing flash memory products using HMB technology, which suffer from latency and instability in high-frequency front-end data service request scenarios due to excessively frequent calls to the flash controller interface, the number of times the flash controller calls the preset interface is reduced by using a built-in mapping table in the flash cache. In addition, by adopting the setting of writing a small amount of data to the first flash storage area cache first and then writing a large amount of data to the second flash storage area, the amount of data to be filled in the data filling operation of a single write operation is greatly reduced, thereby reducing the amount of data written from the host cache to the flash storage area, improving the utilization rate of the bandwidth resources of the preset interface, and effectively controlling the write amplification problem. Attached Figure Description

[0028] Figure 1 This is a schematic diagram of a pointer-based data filling dynamic control system 100 provided in an embodiment of this application.

[0029] Figure 2 This is a schematic diagram of the processing flow of a pointer-based dynamic data filling control method provided in an embodiment of this application. Detailed Implementation

[0030] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present application.

[0031] The terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish different objects, not to describe a specific order. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or apparatuses.

[0032] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0033] In the embodiments of this application, "and / or" describes the relationship between associated objects, indicating that three relationships can exist. For example, A and / or B can represent the following three situations: A exists alone; A and B exist simultaneously; B exists alone. Among them, A and B can be singular or plural.

[0034] In this embodiment, the symbol " / " can indicate that the preceding and following objects are in an "or" relationship. Alternatively, the symbol " / " can also represent a division sign, i.e., performing a division operation. For example, A / B can mean A divided by B.

[0035] In the embodiments of this application, "at least one item" or its similar expression refers to any combination of these items, including any combination of a single item or a plurality of items. "One or more" means one or more, while "multiple" means two or more. For example, "at least one item" of a, b, or c can represent the following seven cases: a, b, c; a and b; a and c; b and c; a, b, and c. Each of a, b, and c can be an element or a set containing one or more elements.

[0036] In the embodiments of this application, "equal to" can be used with "greater than" and is applicable to technical solutions used when "greater than" is used; it can also be used with "less than" and is applicable to technical solutions used when "less than" is used. When "equal to" is used with "greater than", it is not used with "less than"; when "equal to" is used with "less than", it is not used with "greater than".

[0037] First, a basic explanation of the key concepts involved in this application will be given.

[0038] (1) High-speed peripheral component interconnect (PCIe)

[0039] PCIe is a high-speed serial computer expansion bus standard used to connect various internal computer components, such as graphics cards, solid-state drives, and network cards, to achieve high-speed data transmission and communication.

[0040] (2) Solid State Drive (SSD)

[0041] SSDs are non-volatile storage devices based on storage media such as flash memory chips or DRAM, used to store and retrieve data in computers and other electronic devices. They feature high-speed read / write speeds, low power consumption, and strong shock resistance.

[0042] (3) Host Memory Buffer (HMB) technology

[0043] In HMB technology, a portion of the address space managed by the host is allocated to the flash controller. The host controller calls the NVMe driver to synchronize the base address and length data of the target memory to the flash controller. The flash controller updates its own address mapping table (such as the FTL mapping table) based on this data list for looking up the physical address of its own storage blocks. The host controller can store the address mapping table in the host's target memory region. When the flash controller processes data operation commands, it can access the host's target memory via the PCIe bus to retrieve the target physical address corresponding to the target logical address in the address mapping table.

[0044] (4) Non-Volatile Memory Express (NVMe) driver

[0045] An NVMe driver is a software program that enables a host system to communicate and interact with storage devices that support the NVMe protocol. It acts as a bridge between the operating system and the NVMe storage device, translating the operating system's instructions and requests into a format that the storage device can understand, and relaying the storage device's responses and data back to the operating system, thus enabling efficient data transfer and processing between the host and the storage device.

[0046] (5) Dynamic Random Access Memory (DRAM)

[0047] DRAM is a type of random access memory, meaning it allows a computer processor to directly access data in any memory cell, offering fast data read and write speeds. The term "dynamic" emphasizes its storage characteristic, meaning the stored data needs to be constantly refreshed to maintain its validity. Compared to static random access memory (SRAM), DRAM offers higher integration density and lower cost, but is relatively slower.

[0048] Currently, some flash memory products use Host Memory Buffer (HMB) technology to balance cost and performance requirements.

[0049] In practical applications, the inventors found that in high-frequency request scenarios for front-end data services, such flash memory products cause delays and instability in data services due to excessively frequent calls to the flash memory controller interface, which urgently needs improvement and optimization.

[0050] To address the aforementioned issues, this application provides a pointer-based dynamic data filling control method and system. By using a built-in mapping table in the flash cache, the number of times the flash controller calls the preset interface is reduced. Furthermore, by employing a setting that first writes a small amount of data to the first flash storage area cache and then writes a large amount of data to the second flash storage area, the amount of filling data required in a single write operation is significantly reduced. This reduces the amount of data written from the host cache to the flash storage area, improves the utilization rate of the preset interface bandwidth resources, and effectively controls write amplification. This is beneficial for improving the stability and responsiveness of flash devices using HMB technology in data service processing.

[0051] Please see Figure 1 , Figure 1 This is a schematic diagram of a pointer-based data filling dynamic control system 100 provided in an embodiment of this application. Figure 1 As shown, the pointer-based data filling dynamic control system 100 includes a flash memory device 1 and a host 2. The flash memory controller 10 is communicatively connected to the host controller 20 of the host 2. The flash memory device 1 includes the flash memory controller 10, a flash memory cache module 30, and a flash memory storage module 50. The host 2 includes the host controller 20 and a host memory module 40.

[0052] The host memory module 40 has a first host memory region 41 configured as a cache region for the flash memory device 1. The flash memory storage module 50 is configured with a first flash memory storage region 51 and a second flash memory storage region 52. The capacity of the first minimum write block of the first flash memory storage region 51 is smaller than the capacity of the second minimum write block of the second flash memory storage region 52. The flash memory controller 10 accesses the first host memory region 41 through a preset interface (such as a PCIe interface).

[0053] The capacity of the second minimum write block is an integer multiple of the capacity of the first minimum write block. For example, the capacity of the first minimum write block could be 16KB, and the capacity of the second minimum write block could be 96KB.

[0054] Among them, the host memory module 40 can use the first DRAM, and the flash memory cache module 30 can use the second DRAM. The cost and performance of the first DRAM are higher than those of the second DRAM.

[0055] In one possible example, the configuration process for the first host memory region includes the following steps:

[0056] After the flash memory device 1 is detected to be powered on, a self-test operation is performed and the remaining capacity of the storage space of the flash memory storage module 50 that has not stored data is obtained;

[0057] A memory configuration request message carrying the remaining capacity is sent to the host controller 20. The memory configuration request message is used to instruct the host controller 20 to perform the following operations: determine a target capacity based on the remaining capacity and the current usage status of the host memory module; mark the usage status of multiple host free cache units in the host free cache units of the host memory module 40 whose sum of capacity is the target capacity as flash cache usage status; create the host memory mapping table based on the memory addresses of the multiple host free cache units; and call the preset interface to send a memory configuration response message carrying the host memory mapping table to the flash controller.

[0058] Receive the memory configuration response message from the host controller 20;

[0059] The host memory mapping table is cached in the flash memory cache module 30 and stored in the flash memory storage module 50.

[0060] The current usage status of the host memory module 40 can be the ratio of its used space capacity to its total space capacity, or the total space capacity. The more remaining capacity, the smaller the ratio, and the larger the total space capacity, the larger the configurable target capacity. A larger configurable target capacity results in better stability and performance of the flash memory device's data processing.

[0061] In one implementation, a parameter table can be pre-configured and stored in the storage module of host 2. Host controller 20 queries the parameter table to obtain the parameter group entry to which the current parameter value belongs. In addition to the aforementioned numerical ranges of remaining capacity, ratio, and total space capacity, the parameter entry also includes the numerical value or numerical range of the suggested allocated capacity. Host controller 20 determines the target capacity based on the numerical value or numerical range of the suggested allocated capacity in the parameter group entry.

[0062] In another implementation, a calculation formula can be set in advance based on the relationship between parameters. Subsequently, the host controller 20 substitutes the values ​​of the currently acquired parameters into the calculation formula to perform the calculation, and the result can be used as the target capacity.

[0063] This application does not impose a single limitation on the specific implementation method of the target capacity.

[0064] As can be seen in this example, the host controller determines the target capacity of the host memory range allocated to the flash memory device by taking into account the remaining storage space of the flash memory device itself and the usage status of the host memory. This can avoid affecting the stability and performance requirements of the host or flash memory device due to the allocation of the host memory range being too large or too small, which is beneficial to improving the operational stability of the flash memory device.

[0065] The flash memory cache module 30 is used to cache the host memory mapping table 71 and the address mapping table 72 of the flash memory device 1. The host memory mapping table 71 includes address information of the first host memory interval 41 and a first pointer. The first pointer is used to indicate the starting offset address of the next data to be cached in the first host memory interval 41. The address mapping table 72 includes the mapping relationship between logical addresses and physical addresses, as well as a second pointer and a third pointer. The second pointer is used to indicate the starting offset address of the next data to be written in the first flash memory storage area 51, and the third pointer is used to indicate the starting offset address of the next data to be written in the second flash memory storage area 52.

[0066] In practical implementations, flash memory devices can use unsigned integer types to store pointers. For example, `uint32_t` (32-bit unsigned integer) or `uint64_t` (64-bit unsigned integer) can be used to represent pointers, thus covering different ranges of address space. When pointers need to contain more information, structure types may be used. For instance, in addition to address information, it may be necessary to record the status of the cache or memory unit pointed to by that address (such as whether it is valid, whether it has been deleted, etc.), which can be achieved by defining a structure:

[0067] typedef struct {

[0068] uint64_t address; / / Storage address

[0069] uint8_t status; / / Stores status information

[0070] FlashPointer;

[0071] like Figure 2 As shown in the diagram, this application provides a schematic flowchart of a pointer-based dynamic data filling control method, which can be applied to, for example... Figure 1 The flash controller 10 of the flash memory device 1 shown herein includes the following steps:

[0072] Step 201: Receive a first data write instruction from the host;

[0073] The first data write instruction may be associated with data paste task, data transfer task, text editing task, etc. in the front-end data task, and is not limited to one here.

[0074] Step 202: Parse the first data write instruction to obtain the first data to be written;

[0075] Step 203: Query the host memory mapping table in the flash memory cache module to obtain the first pointer, and call the preset interface to cache the first data in the first host memory range according to the first pointer;

[0076] Step 204: Query the address mapping table in the flash memory cache module to obtain the second pointer and the third pointer;

[0077] The first flash memory area of ​​the flash memory module can be used to store the host memory mapping table, and the second flash memory area of ​​the flash memory module can be used to store the address mapping table.

[0078] Step 205: Call the preset interface to perform a first data filling operation to obtain second data that can fill the first minimum write block; and update the first pointer of the host memory mapping table;

[0079] The purpose of the data filling operation is to reduce the probability of instability in the minimum write block of flash memory caused by incomplete data flushing of flash memory cells, thereby improving stability.

[0080] In the specific implementation, the data filled in by the first data filling operation can be preset dummy data, such as all 0s, all 1s, or a specific byte sequence, without being uniquely limited here.

[0081] Step 206: Call the preset interface to write the second data into the first flash memory storage area according to the second pointer; and update the second pointer in the address mapping table; and create a mapping relationship between the first physical address and the first logical address of the first data in the address mapping table.

[0082] Step 207: If it is determined that the size of the third data already written in the first flash memory storage area is equal to the capacity of the second minimum write block, the third data is written to the second flash memory storage area according to the third pointer; and the third pointer in the address mapping table is updated; and the mapping relationship between the physical address and logical address of the third data is updated.

[0083] In a specific implementation, the flash memory controller writes the third data into the second flash memory storage area according to the third pointer, including: detecting whether the third data is retained in the data cached in the first host memory area;

[0084] If no data is detected, the third data is first read from the first flash memory storage area into the first host memory area, and then the storage cells in the second flash memory storage area indicated by the third pointer are sequentially flushed to write the third data; and a garbage collection operation is performed on the first flash memory storage area to reclaim the first flash memory storage area.

[0085] If any data is detected, the third data is written by sequentially flushing the storage cells in the second flash memory area indicated by the third pointer; and a garbage collection operation is performed on the first flash memory area to reclaim the first flash memory area.

[0086] As can be seen, this example fully considers the performance and space redundancy of host memory, makes full use of host memory, accurately detects and identifies the subdivision of the first host memory range where third data is retained and not retained, and performs dedicated write operations to adapt to the subdivision to improve flexibility and applicability.

[0087] In one possible example, the method also includes:

[0088] If it is determined that the size of the third data already written in the first flash memory storage area is less than the capacity of the second minimum write block, a second data write instruction is received from the host.

[0089] Parse the second data write instruction to obtain the fifth data to be written;

[0090] The first pointer is obtained by querying the host memory mapping table in the flash memory cache module, and the fifth data is cached in the first host memory range according to the first pointer by calling the preset interface.

[0091] The second pointer and the third pointer are obtained by querying the address mapping table in the flash memory cache module;

[0092] The preset interface is invoked to perform a second data filling operation to obtain sixth data that can fill the first minimum write block; and the first pointer of the host memory mapping table is updated.

[0093] The system calls the preset interface to write the sixth data into the first flash memory storage area according to the second pointer; updates the second pointer in the address mapping table; and creates a mapping relationship between the first physical address and the first logical address of the first data in the address mapping table.

[0094] If it is determined that the size of the seventh data already written in the first flash memory storage area is equal to the capacity of the second minimum write block, the seventh data is written to the second flash memory storage area according to the third pointer; and the third pointer in the address mapping table is updated; and the mapping relationship between the physical address and logical address of the seventh data is updated.

[0095] As can be seen in this example, the flash memory device can aggregate multiple data from multiple write commands in the first flash memory storage area until the sum of the aggregated data equals the capacity of the second smallest write unit in the second flash memory storage area, and then write the entire data into the second flash memory storage area. By using the first flash memory storage area as a temporary storage area and the second flash memory storage area as the main storage area, the design can effectively reduce the amount of data that needs to be filled when performing data filling operations in a single data write operation. This reduces the amount of data transmitted between the flash memory device and the host in a single call to the preset interface, avoiding the problem of wasted bandwidth and storage space resources caused by transmitting large amounts of redundant data.

[0096] As can be seen, in this embodiment of the application, the flash memory device using HMB technology reduces the number of times the flash controller calls the preset interface by using the built-in mapping table of the flash cache. In addition, by using the setting of writing a small amount of data to the first flash memory storage area cache first and then writing a large amount of data to the second flash memory storage area, the amount of data to be filled in the data filling operation of a single write operation is greatly reduced, thereby reducing the amount of data written from the host cache to the flash memory storage area, improving the utilization rate of the bandwidth resources of the preset interface, and effectively controlling the write amplification problem. This is beneficial to improving the stability and responsiveness of the flash memory device using HMB technology in data service processing.

[0097] In one possible example, before calling the preset interface to perform the first data filling operation to obtain second data capable of filling the first minimum write block, the method further includes: performing a modulo operation on the size of the first data relative to the capacity of the first minimum write block to obtain a calculation result; and detecting that the calculation result is not zero;

[0098] The method further includes:

[0099] The calculation result was detected to be zero;

[0100] The system calls the preset interface to write the first data into the first flash memory storage area according to the second pointer; updates the second pointer in the address mapping table; and creates a mapping relationship between the first physical address and the first logical address of the first data in the address mapping table.

[0101] If it is determined that the size of the fourth data already written in the first flash memory storage area is equal to the capacity of the second minimum write block, the fourth data is written to the second flash memory storage area according to the third pointer; and the third pointer in the address mapping table is updated; and the mapping relationship between the physical address and logical address of the fourth data is updated.

[0102] As can be seen, in this example, the flash memory device dynamically calculates whether to perform a data filling operation, making the data processing process more accurate and stable.

[0103] like Figure 1 As shown, in the pointer-based data filling dynamic control system 100 disclosed in this application embodiment, the flash memory controller 10 is used to perform the following operations:

[0104] Receive a first data write instruction from the host;

[0105] Parse the first data write instruction to obtain the first data to be written;

[0106] The first pointer is obtained by querying the host memory mapping table in the flash memory cache module, and the first data is cached in the first host memory range according to the first pointer by calling the preset interface.

[0107] The second pointer and the third pointer are obtained by querying the address mapping table in the flash memory cache module;

[0108] The preset interface is invoked to perform a first data filling operation to obtain second data that can fill the first minimum write block; and the first pointer of the host memory mapping table is updated;

[0109] The system calls the preset interface to write the second data into the first flash memory storage area according to the second pointer; updates the second pointer in the address mapping table; and creates a mapping relationship between the first physical address and the first logical address of the first data in the address mapping table.

[0110] If it is determined that the size of the third data already written in the first flash memory storage area is equal to the capacity of the second minimum write block, the third data is written to the second flash memory storage area according to the third pointer; and the third pointer in the address mapping table is updated; and the mapping relationship between the physical address and logical address of the third data is updated.

[0111] In one possible example, the capacity of the second minimum write block is an integer multiple of the capacity of the first minimum write block.

[0112] In one possible example, the configuration process for the first host memory region includes the following steps:

[0113] After the flash memory controller 10 detects that the flash memory device is powered on, it performs a self-test operation and obtains the remaining capacity of the storage space of the flash memory storage module that has not stored data.

[0114] The flash memory controller 10 sends a memory configuration request message carrying the remaining capacity to the host controller. The memory configuration request message instructs the host controller to perform the following operations: determine a target capacity based on the remaining capacity and the current usage status of the host memory module; mark the usage status of multiple host free cache units in the host free cache units of the host memory module whose sum of capacity equals the target capacity as flash cache usage status; create the host memory mapping table based on the memory addresses of the multiple host free cache units; and call the preset interface to send a memory configuration response message carrying the host memory mapping table to the flash memory controller 10.

[0115] The flash memory controller 10 receives the memory configuration response message from the host controller;

[0116] The flash memory controller 10 caches the host memory mapping table in the flash memory cache module and stores the host memory mapping table in the flash memory storage module.

[0117] In one possible example, before calling the preset interface to perform a first data filling operation to obtain second data capable of filling the first minimum write block, the flash controller 10 is further configured to: perform a modulo calculation on the size of the first data relative to the capacity of the first minimum write block to obtain a calculation result; and detect that the calculation result is not zero;

[0118] The flash memory controller 10 is also used for:

[0119] The calculation result was detected to be zero;

[0120] The system calls the preset interface to write the first data into the first flash memory storage area according to the second pointer; updates the second pointer in the address mapping table; and creates a mapping relationship between the first physical address and the first logical address of the first data in the address mapping table.

[0121] If it is determined that the size of the fourth data already written in the first flash memory storage area is equal to the capacity of the second minimum write block, the fourth data is written to the second flash memory storage area according to the third pointer; and the third pointer in the address mapping table is updated; and the mapping relationship between the physical address and logical address of the fourth data is updated.

[0122] In one possible example, the flash controller 10 is also used for:

[0123] If it is determined that the size of the third data already written in the first flash memory storage area is less than the capacity of the second minimum write block, a second data write instruction is received from the host.

[0124] Parse the second data write instruction to obtain the fifth data to be written;

[0125] The first pointer is obtained by querying the host memory mapping table in the flash memory cache module, and the fifth data is cached in the first host memory range according to the first pointer by calling the preset interface.

[0126] The second pointer and the third pointer are obtained by querying the address mapping table in the flash memory cache module;

[0127] The preset interface is invoked to perform a second data filling operation to obtain sixth data that can fill the first minimum write block; and the first pointer of the host memory mapping table is updated.

[0128] The system calls the preset interface to write the sixth data into the first flash memory storage area according to the second pointer; updates the second pointer in the address mapping table; and creates a mapping relationship between the first physical address and the first logical address of the first data in the address mapping table.

[0129] If it is determined that the size of the seventh data already written in the first flash memory storage area is equal to the capacity of the second minimum write block, the seventh data is written to the second flash memory storage area according to the third pointer; and the third pointer in the address mapping table is updated; and the mapping relationship between the physical address and logical address of the seventh data is updated.

[0130] It should be noted that, for the sake of simplicity, the foregoing method embodiments are all described as a series of actions. However, those skilled in the art should understand that this application is not limited to the described order of actions, as some steps may be performed in other orders or simultaneously according to this application. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are preferred embodiments, and the actions and modules involved are not necessarily essential to this application.

[0131] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0132] In the several embodiments provided in this application, it should be understood that the disclosed apparatus can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of the units described above is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or units may be electrical or other forms.

[0133] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0134] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0135] If the integrated units described above are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage device (CMD). Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a memory and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned memory includes various media capable of storing program code, such as USB flash drives, read-only memory (ROM), random access memory (RAM), portable hard drives, magnetic disks, or optical disks.

[0136] Those skilled in the art will understand that all or part of the steps in the various methods of the above embodiments can be implemented by a program instructing related hardware. The program can be stored in a computer-readable storage medium, which may include: flash drive, read-only memory (ROM), random access memory (RAM), disk or optical disk, etc.

[0137] The embodiments of this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A pointer-based dynamic data filling control method, characterized in that, The invention is applied to a flash memory device, which is used to communicate with a host. The flash memory device includes a flash memory controller, a flash memory cache module, and a flash memory storage module. The host includes a host controller and a host memory module. The host memory module is configured as a cache area for the flash memory device. The flash memory module is configured with a first flash memory area and a second flash memory area. The capacity of the first minimum write block of the first flash memory area is smaller than the capacity of the second minimum write block of the second flash memory area. The flash memory controller accesses the first host memory area through a preset interface. The flash memory cache module is used to cache the host memory mapping table and address mapping table of the flash memory device. The host memory mapping table includes address information of the first host memory region and a first pointer. The first pointer is used to indicate the starting offset address of the next data to be cached in the first host memory region. The address mapping table includes the mapping relationship between the physical address of the data stored in the flash memory cache module and the logical address of the data, as well as a second pointer and a third pointer. The second pointer is used to indicate the starting offset address of the next data to be written in the first flash memory region, and the third pointer is used to indicate the starting offset address of the next data to be written in the second flash memory region. The method includes: Receive a first data write instruction from the host; Parse the first data write instruction to obtain the first data to be written; The first pointer is obtained by querying the host memory mapping table in the flash memory cache module, and the first data is cached in the first host memory range according to the first pointer by calling the preset interface. The second pointer and the third pointer are obtained by querying the address mapping table in the flash memory cache module; The preset interface is invoked to perform a first data filling operation to obtain second data that can fill the first minimum write block; and the first pointer of the host memory mapping table is updated; The system calls the preset interface to write the second data into the first flash memory storage area according to the second pointer; updates the second pointer in the address mapping table; and creates a mapping relationship between the first physical address and the first logical address of the first data in the address mapping table. If it is determined that the size of the third data already written in the first flash memory storage area is equal to the capacity of the second minimum write block, the third data is written to the second flash memory storage area according to the third pointer; and the third pointer in the address mapping table is updated; and the mapping relationship between the physical address and logical address of the third data is updated.

2. The method according to claim 1, characterized in that, The capacity of the second minimum write block is an integer multiple of the capacity of the first minimum write block.

3. The method according to claim 2, characterized in that, The configuration process for the first host memory region includes the following steps: After the flash memory device is powered on, a self-test operation is performed and the remaining capacity of the storage space where no data is stored in the flash memory module is obtained; Send a memory configuration request message carrying the remaining capacity to the host controller. The memory configuration request message is used to instruct the host controller to perform the following operation: determine the target capacity based on the remaining capacity and the current usage status of the host memory module; Furthermore, the usage status of multiple host free cache units in the host memory module whose sum of capacity equals the target capacity is marked as flash cache usage status; In addition, the host memory mapping table is created based on the memory addresses of the plurality of host free cache units; and the memory configuration response message carrying the host memory mapping table is sent to the flash controller by calling the preset interface; Receive the memory configuration response message from the host controller; The host memory mapping table is cached in the flash cache module and stored in the flash storage module.

4. The method according to claim 3, characterized in that, Before calling the preset interface to perform the first data filling operation to obtain second data that can fill the first minimum write block, the method further includes: performing a modulo calculation on the size of the first data relative to the capacity of the first minimum write block to obtain a calculation result; and detecting that the calculation result is not zero; The method further includes: The calculation result was detected to be zero; The system calls the preset interface to write the first data into the first flash memory storage area according to the second pointer; updates the second pointer in the address mapping table; and creates a mapping relationship between the first physical address and the first logical address of the first data in the address mapping table. If it is determined that the size of the fourth data already written in the first flash memory storage area is equal to the capacity of the second minimum write block, the fourth data is written to the second flash memory storage area according to the third pointer; and the third pointer in the address mapping table is updated; and the mapping relationship between the physical address and logical address of the fourth data is updated.

5. The method according to any one of claims 1-4, characterized in that, The method further includes: If it is determined that the size of the third data already written in the first flash memory storage area is less than the capacity of the second minimum write block, a second data write instruction is received from the host. Parse the second data write instruction to obtain the fifth data to be written; The first pointer is obtained by querying the host memory mapping table in the flash memory cache module, and the fifth data is cached in the first host memory range according to the first pointer by calling the preset interface. The second pointer and the third pointer are obtained by querying the address mapping table in the flash memory cache module; The preset interface is invoked to perform a second data filling operation to obtain sixth data that can fill the first minimum write block; and the first pointer of the host memory mapping table is updated. The system calls the preset interface to write the sixth data into the first flash memory storage area according to the second pointer; updates the second pointer in the address mapping table; and creates a mapping relationship between the first physical address and the first logical address of the first data in the address mapping table. If it is determined that the size of the seventh data already written in the first flash memory storage area is equal to the capacity of the second minimum write block, the seventh data is written to the second flash memory storage area according to the third pointer; and the third pointer in the address mapping table is updated; and the mapping relationship between the physical address and logical address of the seventh data is updated.

6. A pointer-based dynamic data filling control system, characterized in that, The system includes a host and a flash memory device, the flash memory device being used to communicate with the host, the flash memory device including a flash memory controller, a flash memory cache module and a flash memory storage module, and the host including a host controller and a host memory module; The host memory module is configured as a cache area for the flash memory device. The flash memory module is configured with a first flash memory area and a second flash memory area. The capacity of the first minimum write block of the first flash memory area is smaller than the capacity of the second minimum write block of the second flash memory area. The flash memory controller accesses the first host memory area through a preset interface. The flash memory cache module is used to cache the host memory mapping table and address mapping table of the flash memory device. The host memory mapping table includes address information of the first host memory region and a first pointer. The first pointer is used to indicate the starting offset address of the next data to be cached in the first host memory region. The address mapping table includes the mapping relationship between the physical address of the data stored in the flash memory cache module and the logical address of the data, as well as a second pointer and a third pointer. The second pointer is used to indicate the starting offset address of the next data to be written in the first flash memory region, and the third pointer is used to indicate the starting offset address of the next data to be written in the second flash memory region. The flash memory controller is configured to perform the following operations: Receive a first data write instruction from the host; Parse the first data write instruction to obtain the first data to be written; The first pointer is obtained by querying the host memory mapping table in the flash memory cache module, and the first data is cached in the first host memory range according to the first pointer by calling the preset interface. The second pointer and the third pointer are obtained by querying the address mapping table in the flash memory cache module; The preset interface is invoked to perform a first data filling operation to obtain second data that can fill the first minimum write block; and the first pointer of the host memory mapping table is updated; The system calls the preset interface to write the second data into the first flash memory storage area according to the second pointer; updates the second pointer in the address mapping table; and creates a mapping relationship between the first physical address and the first logical address of the first data in the address mapping table. If it is determined that the size of the third data already written in the first flash memory storage area is equal to the capacity of the second minimum write block, the third data is written to the second flash memory storage area according to the third pointer; and the third pointer in the address mapping table is updated; and the mapping relationship between the physical address and logical address of the third data is updated.

7. The system according to claim 6, characterized in that, The capacity of the second minimum write block is an integer multiple of the capacity of the first minimum write block.

8. The system according to claim 7, characterized in that, The configuration process for the first host memory region includes the following steps: After the flash memory controller detects that the flash memory device is powered on, it performs a self-test operation and obtains the remaining capacity of the storage space of the flash memory storage module that has not stored data. The flash memory controller sends a memory configuration request message carrying the remaining capacity to the host controller. The memory configuration request message is used to instruct the host controller to perform the following operation: determine the target capacity based on the remaining capacity and the current usage status of the host memory module; Furthermore, the usage status of multiple host free cache units in the host memory module whose sum of capacity equals the target capacity is marked as flash cache usage status; In addition, the host memory mapping table is created based on the memory addresses of the plurality of host free cache units; and the memory configuration response message carrying the host memory mapping table is sent to the flash controller by calling the preset interface; The flash memory controller receives the memory configuration response message from the host controller; The flash memory controller caches the host memory mapping table in the flash memory cache module and stores the host memory mapping table in the flash memory storage module.

9. The system according to claim 8, characterized in that, Before calling the preset interface to perform the first data filling operation to obtain second data that can fill the first minimum write block, the flash memory controller is further configured to: perform a modulo calculation on the size of the first data relative to the capacity of the first minimum write block to obtain a calculation result; and detect that the calculation result is not zero; The flash memory controller is also used for: The calculation result was detected to be zero; The system calls the preset interface to write the first data into the first flash memory storage area according to the second pointer; and updates the second pointer in the address mapping table. In addition, a mapping relationship between the first physical address and the first logical address of the first data is created in the address mapping table; If it is determined that the size of the fourth data already written in the first flash memory storage area is equal to the capacity of the second minimum write block, the fourth data is written to the second flash memory storage area according to the third pointer; and the third pointer in the address mapping table is updated. In addition, update the mapping relationship between the physical address and logical address of the fourth data.

10. The system according to any one of claims 6-9, characterized in that, The flash memory controller is also used for: If it is determined that the size of the third data already written in the first flash memory storage area is less than the capacity of the second minimum write block, a second data write instruction is received from the host. Parse the second data write instruction to obtain the fifth data to be written; The first pointer is obtained by querying the host memory mapping table in the flash memory cache module, and the fifth data is cached in the first host memory range according to the first pointer by calling the preset interface. The second pointer and the third pointer are obtained by querying the address mapping table in the flash memory cache module; The preset interface is invoked to perform a second data filling operation to obtain sixth data that can fill the first minimum write block; and the first pointer of the host memory mapping table is updated. The preset interface is invoked to write the sixth data into the first flash memory storage area according to the second pointer; and the second pointer in the address mapping table is updated. In addition, a mapping relationship between the first physical address and the first logical address of the first data is created in the address mapping table; If it is determined that the size of the seventh data already written in the first flash memory storage area is equal to the capacity of the second minimum write block, the seventh data is written to the second flash memory storage area according to the third pointer; and the third pointer in the address mapping table is updated. In addition, update the mapping relationship between the physical address and logical address of the seventh data.

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