Sampling method, sampling device, computer storage medium and laser ranging device

Abstract

A sampling method, sampling device, computer storage medium, and laser ranging device are disclosed. The sampling method includes: sampling an electrical signal output by a detection unit at a sampling rate of N*f0 to generate an initial sampling signal; wherein f0 is the clock frequency of a first clock signal, and N is a positive integer greater than 1; sampling K*N sampling data of K adjacent clock cycles of the initial sampling signal at a sampling rate of f0 / K to generate a first sampling signal to a K*Nth sampling signal; wherein K is a positive integer greater than 1. This application can improve the sampling rate of the sampling circuit, thereby improving the ranging accuracy of time-of-flight, while reducing the clock speed requirements for subsequent sampling signal processing.

Description

Technical Field

[0001] This application relates to the field of laser ranging, and more particularly to a sampling method, a sampling device, a computer storage medium, and a laser ranging device. Background Technology

[0002] Laser ranging technology has important applications in fields such as autonomous driving, facial recognition, and 3D gesture recognition. Laser ranging systems typically utilize time-of-flight (TOF) measurement technology to determine the distance to obstacles. TOF technology usually uses a laser to emit pulsed light signals into a detection area, and a detector detects the echo signals returned after the pulsed light signals are reflected by obstacles within the detection area. When the detector receives a light signal, it outputs a high-level pulsed electrical signal; when it does not receive a light signal, it outputs a low-level electrical signal, meaning the detector outputs a digital signal. A sampling circuit then samples the detector's output signal to generate a sampled signal. This sampled signal is used to determine the time of flight, allowing the calculation of the distance between the laser and the object.

[0003] Currently, the accuracy of time-of-flight measurement usually depends on the sampling rate of the sampling circuit. The higher the sampling rate of the sampling circuit, the shorter the time interval between two adjacent sampling moments in the sampled signal, that is, the shorter the duration of each flight moment within the flight time statistical period, and the higher the accuracy of flight time measurement.

[0004] To improve the accuracy of time-of-flight measurement, related technologies typically increase the sampling rate of the sampling circuit. However, increasing the sampling rate of the sampling circuit leads to higher clock speed requirements for subsequent processing of the sampled signals, easily consuming significant computational resources. Therefore, how to improve the sampling rate of the sampling circuit, thereby enhancing the accuracy of time-of-flight ranging, while simultaneously reducing the clock speed requirements for subsequent processing of the sampled signals, has become a technical problem that needs to be solved by those skilled in the art. Summary of the Invention

[0005] To address the aforementioned issues, this application provides a sampling method, sampling device, computer storage medium, and laser ranging device. The method samples the electrical signal output by the detection unit at a sampling rate of N*f0, thereby increasing the sampling rate and thus improving the accuracy of time-of-flight measurement. Simultaneously, the initial sampling signal is sampled at a sampling rate of f0 / K to generate the first to K*Nth sampling signals. This converts the initial sampling signal in the fast clock domain into the first to K*Nth sampling signals in the slow clock domain, reducing the clock speed requirements for subsequent sampling signal processing and computation. This reduces the computational resources required for subsequent sampling signal processing, thereby increasing the sampling rate of the sampling circuit and improving the ranging accuracy of time-of-flight while reducing the clock speed requirements for subsequent sampling signal processing.

[0006] Firstly, this application provides a sampling method, including:

[0007] The electrical signal output by the detection unit is sampled at a sampling rate of N*f0 to generate an initial sampling signal; where f0 is the clock frequency of the first clock signal and N is a positive integer greater than 1.

[0008] The K*N sampled data of the initial sampled signal for K adjacent clock cycles are sampled at a sampling rate of f0 / K to generate the first sampled signal to the K*Nth sampled signal; where K is a positive integer greater than 1.

[0009] Secondly, this application also provides a sampling device, comprising:

[0010] The first sampling unit is used to sample the electrical signal output by the detection unit at a sampling rate of N*f0 to generate an initial sampling signal; where f0 is the clock frequency of the first clock signal and N is a positive integer greater than 1.

[0011] The second sampling unit is used to sample K*N sampled data of adjacent K clock cycles of the initial sampled signal at a sampling rate of f0 / K, to generate the first sampled signal to the K*Nth sampled signal; where K is a positive integer greater than 1.

[0012] Thirdly, this application also provides a computer-readable storage medium storing at least one executable instruction that, when executed by a processor, implements the method described in any of the above-mentioned embodiments.

[0013] Fourthly, this application also provides a laser ranging device, characterized in that it includes: a transmitter, a detector, a processor, a communication interface, a memory, and a communication bus; the processor communicates with the transmitter and the detector through the communication interface; the processor, the communication interface, and the memory communicate with each other through the communication bus.

[0014] The transmitter includes one or more light-emitting units for emitting pulsed light signals;

[0015] The detector includes one or more detection units for receiving optical signals;

[0016] The memory is used to store computer programs or instructions;

[0017] The processor is used to execute computer programs or instructions in the memory to implement the method as described in any of the above.

[0018] This application also provides another laser ranging device, including a transmitter, a detector, and a sampling module;

[0019] The transmitter includes one or more light-emitting units for emitting pulsed light signals;

[0020] The detector includes one or more detection units for receiving optical signals;

[0021] The sampling module includes one or more sampling units, and the sampling units employ the sampling device described in any of the above descriptions.

[0022] The advantages of this application compared to the prior art are:

[0023] The electrical signal output by the detection unit is sampled at a sampling rate of N*f0, which increases the sampling rate and thus improves the accuracy of time-of-flight measurement. At the same time, the initial sampling signal is sampled at a sampling rate of f0 / K to generate the first to K*Nth sampling signals. This converts the initial sampling signal in the fast clock domain into the first to K*Nth sampling signals in the slow clock domain, thereby reducing the clock speed requirements for subsequent sampling signal processing and reducing the computational resources required for subsequent sampling signal processing. This improves the sampling rate of the sampling circuit, thereby improving the ranging accuracy of time-of-flight while reducing the clock speed requirements for subsequent sampling signal processing. Attached Figure Description

[0024] Figure 1 This is a schematic flowchart of a sampling method provided in an embodiment of this application;

[0025] Figure 2 yes Figure 1A flowchart illustrating step S110 in the provided sampling method;

[0026] Figure 3 yes Figure 2 A flowchart illustrating step S110 in the provided sampling method;

[0027] Figure 4 This is a timing diagram showing the waveform changes of each signal in the sampling method provided in the embodiments of this application;

[0028] Figure 5 This is another schematic flowchart of the sampling method provided in the embodiments of this application;

[0029] Figure 6 This is a schematic diagram of a sampling device provided in an embodiment of this application;

[0030] Figure 7 yes Figure 6 A schematic diagram of a specific structure of the provided sampling device;

[0031] Figure 8 yes Figure 7 A schematic diagram of a specific structure of the provided sampling device;

[0032] Figure 9 This is another schematic diagram of the sampling device provided in the embodiments of this application;

[0033] Figure 10 yes Figure 9 A schematic diagram of a specific structure of the determination unit and output unit in the provided sampling device;

[0034] Figure 11 yes Figure 10 A schematic diagram of a specific structure of the sampling determination unit and the output unit is provided;

[0035] Figure 12 This is a schematic diagram of a laser ranging device provided in an embodiment of this application. Detailed Implementation

[0036] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings.

[0037] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of this application. However, those skilled in the art will understand that this application may also be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods have been omitted so as not to obscure the description of this application with unnecessary detail.

[0038] It should be noted that when a unit is referred to as being "connected to" another unit, it can be directly connected to the other unit or indirectly connected to it. It should be understood that the term "and / or" as used in this specification and the appended claims refers to any combination and all possible combinations of one or more of the associated listed items, and includes such combinations. Furthermore, in the description of this specification and the appended claims, the terms "first," "second," "third," "fourth," etc., are used only for distinguishing descriptions and should not be construed as indicating or implying relative importance. Unless otherwise stated, " / " means "division," and "*" means "multiplication."

[0039] It should also be understood that references to "one embodiment" or "some embodiments" in this specification mean that one or more embodiments of this application include the specific features, structures, or characteristics described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0040] like Figure 1 As shown, in a first aspect, embodiments of this application provide a sampling method that samples the electrical signal output by the detection unit at a sampling rate of N*f0, thereby improving the sampling rate and thus improving the measurement accuracy of the time of flight. At the same time, the sampling method provided by embodiments of this application samples the initial sampling signal at a sampling rate of f0 / K to generate the first sampling signal to the K*Nth sampling signal, thereby converting the initial sampling signal under the fast clock domain into the first sampling signal to the K*Nth sampling signal under the slow clock domain, so as to reduce the clock speed requirement when processing and calculating the subsequent sampling signals (i.e., time of flight data) and reduce the computing resources required when processing and calculating the subsequent sampling signals.

[0041] Please see Figure 1 The sampling method provided in this application includes, but is not limited to, the following steps:

[0042] S110, the electrical signal output by the detection unit is sampled at a sampling rate of N*f0 to generate an initial sampling signal; where f0 is the clock frequency of the first clock signal and N is a positive integer greater than 1.

[0043] In some specific embodiments, the detection unit employs a silicon photomultiplier (SIPM). A SIPM is a novel photodetector device, composed of an array of avalanche diodes operating in Geiger mode, and features high gain, high sensitivity, low bias voltage, insensitivity to magnetic fields, and a compact structure. In other optional embodiments, the detection unit 101 may also employ a single-photon avalanche diode (SPAD). This application does not limit the specific type of the detection unit 101.

[0044] like Figure 4 As shown, the electrical signal output by the detection unit is a digital signal. When the electrical signal output by the detection unit 101 is high, it means that the detection unit 101 has received an optical signal (including an echo optical signal). When the electrical signal output by the detection unit 101 is low, it means that the detection unit 101 has not received an optical signal.

[0045] The sampling method provided in this application sample the electrical signal output by the detection unit at a sampling rate of N*f0. Specifically, it performs N samples within each clock cycle of the first clock signal. The initial sampling signal includes N sampled data points (i.e., N time-of-flight data points) within each clock cycle of the first clock signal. These N sampled data points include N sampling moments (i.e., N time-of-flight times) within each clock cycle of the first clock signal and the corresponding sampled values ​​(the number of photons corresponding to each of the N time-of-flight times). Compared to related technologies that sample the electrical signal output by the detection unit at a sampling rate of f0, this method improves the sampling rate. In related technologies, when sampling the electrical signal output by the detection unit at a sampling rate of f0, the phase difference between two adjacent sampled data points... The time interval Δt0 = T0 between two adjacent sampled data points, and the measurement accuracy of the time of flight is equal to Δt0 = T0; where T0 is the clock period of the first clock signal, T0 = 1 / f0, and the initial sampled signal obtained by the sampling method provided in this application sampling the electrical signal output by the detection unit at a sampling rate of N*f0, has a phase difference between two adjacent sampled data points. The time interval between two adjacent sampled data points is Δt1 = T0 / N; the measurement accuracy of flight time is equal to Δt1 = T0 / N, which improves the measurement accuracy of flight time.

[0046] S120, sample the K*N sampled data of the adjacent K clock cycles of the initial sampled signal at a sampling rate of f0 / K to generate the first sampled signal to the K*Nth sampled signal; where K is a positive integer greater than 1.

[0047] Wherein, the (k-1)*N+1th sampled signal to the k*Nth sampled signal are the N sampled data corresponding to the initial sampled signal in the kth clock cycle, where k is a positive integer and 1≤k≤K; when k=1, the (k-1)*N+1th sampled signal to the k*Nth sampled signal are the first sampled signal to the Nth sampled signal, the first sampled signal to the Nth sampled signal are the N sampled data corresponding to the initial sampled signal in the 1st clock cycle... when k=K, the (k-1)*N+1th sampled signal to the k*Nth sampled signal are the (K-1)*N+1th sampled signal to the K*Nth sampled signal, the (K-1)*N+1th sampled signal to the K*Nth sampled signal are the N sampled data corresponding to the initial sampled signal in the Kth clock cycle.

[0048] The sampling method provided in this application samples the initial sampling signal at a sampling rate of f0 / K to generate the first sampling signal to the K*Nth sampling signal. The initial clock signal is a signal in the clock domain with a frequency of f0, and the first sampling signal to the K*Nth sampling signal is a signal in the clock domain with a frequency of f0 / K. This method converts the initial sampling signal in the fast clock domain into the first sampling signal to the K*Nth sampling signal in the slow clock domain, thereby reducing the clock speed requirements for processing subsequent sampling signals (i.e., time-of-flight data) and reducing the computational resources required for processing subsequent sampling signals.

[0049] In some specific implementations, N=2, that is, sampling is performed twice within each clock cycle of the first clock signal, and the initial sampled signal includes two sampled data within each clock cycle of the first clock signal; such as Figure 2 As shown, step S110, sampling the electrical signal output by the detection unit at a sampling rate of N*f0 to generate the initial sampling signal includes:

[0050] S111, the rising edge of the first clock signal is used to sample the electrical signal output by the detection unit to generate the first initial sampling signal;

[0051] S112, the falling edge of the first clock signal is used to sample the electrical signal output by the detection unit to generate a second initial sampling signal; wherein, the first initial sampling signal and the second initial sampling clock signal constitute the initial clock signal; the first initial sampling signal is the first sampled data of the initial clock signal in each clock cycle of the first clock signal, and the second initial sampling signal is the second sampled data of the initial clock signal in each clock cycle of the first clock signal.

[0052] like Figure 4 As shown, the first clock signal is CLK1; it can be understood that the electrical signal output by the detection unit is sampled by the rising and falling edges of the first clock signal CLK1, which doubles the sampling rate and doubles the measurement accuracy of the time of flight.

[0053] like Figure 4 As shown, the first initial sampling signal is denoted as sample1; the second initial sampling signal is denoted as sample2. When the rising edge of the first clock signal CLK1 is used to sample the electrical signal output by the detection unit 101, if a pulse high level is sampled at a certain rising edge of the first clock signal CLK1, then the first initial sampling signal sample1 is high at the sampling time corresponding to that rising edge. Correspondingly, the flight time corresponding to that sampling time is the generation time of the pulse high level of the detection unit, that is, the time when the optical signal arrives at the detection unit. The level value of the first initial sampling signal sample1 at the sampling time corresponding to that rising edge is used to indicate the number of photons received by the detection unit 101 at the corresponding flight time. If a pulse high level is not sampled at a certain rising edge of the first clock signal CLK1, then the first initial sampling signal sample1 is low at the sampling time corresponding to that rising edge. Correspondingly, the detection unit does not generate a pulse high level at the flight time corresponding to that sampling time, that is, the detection unit does not receive an optical signal at that flight time.

[0054] Similarly, when the falling edge of the first clock signal CLK1 is used to sample the electrical signal output by the detection unit, if a high-level pulse is sampled at a certain falling edge of the first clock signal CLK1, the first initial sampling signal sample1 is high at the sampling time corresponding to that falling edge. Accordingly, the flight time corresponding to that sampling time is the generation time of the high-level pulse of the detection unit, that is, the time when the optical signal arrives at the detection unit. The level value of the first initial sampling signal sample1 at the sampling time corresponding to that falling edge is used to indicate the number of photons received by the detection unit at the corresponding flight time. If a high-level pulse is not sampled at a certain falling edge of the first clock signal CLK1, the first initial sampling signal sample1 is low at the sampling time corresponding to that falling edge. Accordingly, the detection unit does not generate a high-level pulse at the flight time corresponding to that sampling time, that is, the detection unit does not receive an optical signal at that flight time.

[0055] In one specific implementation, the frequency of the first clock signal CLK1 is 1GHz, and the clock period of the first clock signal CLK1 is 10. -9The sampling method provided in this application uses both the rising and falling edges of the first clock signal CLK1 to sample the electrical signal output by the detection unit, with a sampling rate of 2 GHz. Simultaneously, the time interval between the first initial sampling signal sample1 and the second initial sampling signal sample2 is equal to (1 / 2 GHz) = 5 * 10^- ... -10 s, that is, the time interval between two adjacent sampled data in the initial sampled signal is equal to (1 / 2 GHz) = 5 * 10 -10 s, correspondingly, the accuracy of the flight time measurement is 5*10 -10 s.

[0056] Further, K=2; N=2, sampling the K*N sampled data of the initial sampled signal in the K adjacent clock cycles with a sampling rate of f0 / K is equivalent to sampling the initial sampled signal in the 2*2, i.e., 4 sampled data in the two adjacent clock cycles with a sampling rate of f0 / 2; the first sampled signal to the K*Nth sampled signal includes the first sampled signal, the second sampled signal, the third sampled signal and the fourth sampled signal; the first sampled signal is the first sampled data of the initial sampled signal in the first clock cycle of the two adjacent clock cycles of the first clock signal CLK1, the second sampled signal is the second sampled data of the initial sampled signal in the first clock cycle of the two adjacent clock cycles of the first clock signal CLK1, the third sampled signal is the first sampled data of the initial sampled signal in the second clock cycle of the two adjacent clock cycles of the first clock signal CLK1, and the fourth sampled signal is the second sampled data of the initial sampled signal in the second clock cycle of the two adjacent clock cycles of the second clock signal CLK1.

[0057] like Figure 3 As shown, in some specific embodiments, step S120, sampling K*N sampled data of the initial sampled signal for K adjacent clock cycles at a sampling rate of f0 / K to generate the first sampled signal to the K*Nth sampled signal, includes:

[0058] S121, synchronize the first initial sampling signal with the first clock signal to generate a first synchronization signal; synchronize the second initial sampling signal with the first clock signal to generate a second synchronization signal;

[0059] like Figure 4As shown, the first synchronization signal is sync1; the second synchronization signal is sync2. Since the first initial sampling signal sample1 is obtained by sampling the rising edge of the first clock signal CLK1, and the second initial sampling signal sample2 is obtained by sampling the falling edge of the first clock signal CLK1, the first initial sampling signal sample1 and the second initial sampling signal sample2 are asynchronous signals; step S12 is used to synchronize the first synchronization signal sync1 and the second synchronization signal sync2 with the first clock signal CLK1.

[0060] Furthermore, synchronizing the first initial sampling signal with the first clock signal to generate the first synchronization signal includes: synchronizing the first initial sampling signal with the rising edge of the first clock signal to generate the first synchronization signal.

[0061] Specifically, the first synchronization signal sync1 is synchronized with the rising edge of the first clock signal CLK1.

[0062] Furthermore, synchronizing the second initial sampling signal with the first clock signal to generate the second synchronization signal includes: synchronizing the second initial sampling signal with the rising edge of the first clock signal to generate the second synchronization signal.

[0063] Specifically, the second synchronization signal sync2 is synchronized with the rising edge of the first clock signal CLK1.

[0064] S122, after delaying the first synchronization signal by T0, generate the third synchronization signal; after delaying the second synchronization signal by T0, generate the fourth synchronization signal.

[0065] like Figure 4 As shown, the third synchronization signal is sync3; the second synchronization signal is sync4; since the third synchronization signal sync3 is delayed by one clock cycle T0 compared to the first synchronization signal sync1, the third synchronization signal sync3 is used to represent the data of the next clock cycle of the first synchronization signal sync1; since the fourth synchronization signal sync4 is delayed by one clock cycle T0 compared to the second synchronization signal sync2, the fourth synchronization signal sync4 is used to represent the data of the next clock cycle of the second synchronization signal sync2.

[0066] like Figure 4As shown, when sampling the electrical signal output by the detection unit using the rising and falling edges of the first clock signal CLK1, the sampling rate is 2*f1. This means the electrical signal output by the detection unit is sampled four times in every two adjacent clock cycles T0 of the first clock signal CLK1, and twice in each clock cycle T0. Specifically, the sampling data obtained by sampling the electrical signal output by the detection unit in the first clock cycle of the two adjacent clock cycles of the first clock signal CLK1 are the first synchronization signal sync1 and the second synchronization signal sync1, respectively. The sampling data obtained by sampling the electrical signal output by the detection unit in the second clock cycle of the two adjacent clock cycles of the first clock signal CLK1 are... The sampling data from the two sampling sessions are the third synchronization signal sync3 and the fourth synchronization signal sync4, respectively. The sampling time corresponding to the first synchronization signal sync1 is the sampling time corresponding to the rising edge of the previous clock cycle between two adjacent clock cycles; the sampling time corresponding to the second synchronization signal sync2 is the sampling time corresponding to the falling edge of the previous clock cycle between two adjacent clock cycles; the sampling time corresponding to the third synchronization signal sync3 is the sampling time corresponding to the rising edge of the next clock cycle between two adjacent clock cycles; and the sampling time corresponding to the fourth synchronization signal sync4 is the sampling time corresponding to the falling edge of the next clock cycle between two adjacent clock cycles. That is, the first synchronization signal sync1, the second synchronization signal sync2, the third synchronization signal sync3, and the fourth synchronization signal sync4 are equivalent to the sampling data corresponding to each of the four time units when the clock cycle of the second clock signal CLK2 with frequency f0 / 2 is divided into four equal time units.

[0067] S123, the first synchronization signal is sampled using the rising edge of the second clock signal and delayed by T2 to generate the first sampled signal; the second synchronization signal is sampled using the rising edge of the second clock signal and delayed by T2 to generate the second sampled signal; the third synchronization signal is sampled using the rising edge of the second clock signal to generate the third sampled signal; the fourth synchronization signal is sampled using the rising edge of the second clock signal to generate the fourth sampled signal; wherein, the clock frequency of the second clock signal is f0 / 2, and T2 is the period of the second clock signal, T2=2 / f0.

[0068] In one specific implementation, the clock frequency f0 of the first clock signal CLK1 is 1 GHz, and the frequency of the second clock signal CLK2 is 500 MHz; the clock period of the first clock signal CLK1 is 10. -9The sampling method provided in this application uses both the rising and falling edges of the first clock signal CLK1 to sample the electrical signal output by the detection unit, with a sampling rate of 2 GHz. Simultaneously, the time interval between the first initial sampling signal sample1 and the second initial sampling signal sample2 is equal to (1 / 2 GHz) = 5 * 10^- ... -10 s, that is, the time interval between two adjacent sampled data in the initial sampled signal is equal to (1 / 2 GHz) = 5 * 10 -10 s, correspondingly, the accuracy of the flight time measurement is 5*10 -10 The sampling rates of the first sampled signal res1, the second sampled signal res2, the third sampled signal res3, and the fourth sampled signal res4 are all 500MHz. Compared with the initial sampled signal with a sampling rate of 3GHz, the clock speed requirement for subsequent processing of the first sampled signal res1, the second sampled signal res2, the third sampled signal res3, and the fourth sampled signal res4 is reduced, thereby reducing the computational resources required for processing the subsequent sampled signals.

[0069] The sampling method provided in this application, through steps S121 to S123, converts the initial clock signal under the clock domain of the first clock signal CLK1 at frequency f0 to the first sampling clock signal, the second sampling clock signal, the third sampling clock signal, and the fourth sampling clock signal under the clock domain of the second clock signal CLK2 at frequency f0 / 2. This achieves the conversion of the initial sampling signal under the fast clock domain into the first to fourth sampling signals under the slow clock domain, which can reduce the clock speed requirements when processing and calculating the subsequent sampling signals (i.e., time-of-flight data), thereby reducing the computational resources required when processing and calculating the subsequent sampling signals.

[0070] like Figure 4As shown, the signal obtained by sampling the first synchronization signal sync1 using the second clock signal CLK2 is res01. After a delay of T2, res01 is used to obtain the first sampled signal res1. The signal obtained by sampling the second synchronization signal sync2 using the second clock signal CLK2 is res02. After a delay of T2, res02 is used to obtain the second sampled signal res1. The third sampled signal is res3. The fourth sampled signal is res4. The first sampling signal res1, the second sampling signal res2, the third sampling signal res3, and the fourth sampling signal res4 are the four sampled data corresponding to each rising edge of the second clock signal CLK2. These are the four sampled data of the initial sampling signal composed of the first initial sampling signal sample1 and the second initial sampling signal sample2 within two adjacent clock cycles of the first clock signal CLK1. That is, the first sampling signal res1 is the first time-of-flight data P0 within each clock cycle of the second clock signal CLK2, the second sampling signal res2 is the second time-of-flight data P1 within each clock cycle of the second clock signal CLK2, the third sampling signal res3 is the third time-of-flight data P2 within each clock cycle of the second clock signal CLK2, and the fourth sampling signal res4 is the fourth time-of-flight data P3 within each clock cycle of the second clock signal CLK2.

[0071] like Figure 5 As shown, in some other embodiments, the sampling method further includes:

[0072] S130, determine whether a transition from 0 to 1 occurs between any two adjacent sampled signals from the first sampled signal to the K*Nth sampled signal, and generate the first judgment result to the K*Nth judgment result;

[0073] The first judgment result is generated by judging whether a transition from 0 to 1 occurs between the K*Nth sampled signal and the first sampled signal; the second judgment result is generated by judging whether a transition from 0 to 1 occurs between the first sampled signal and the second sampled signal; the xth judgment result is generated by judging whether a transition from 0 to 1 occurs between the xth sampled signal and the x+1th sampled signal, where x is a positive integer and 2≤x≤K*N-1;

[0074] S140, Output the first judgment result to the K*Nth judgment result;

[0075] S150: Obtain the first judgment result to the K*Nth judgment result, and determine whether the first sampling signal to the K*Nth sampling signal is a normal sampling signal based on the first judgment result to the K*Nth judgment result; if so, proceed to step S160.

[0076] S160, output the first sampled signal to the K*Nth sampled signal. That is, when the first sampled signal to the K*Nth sampled signal are normal sampled signals, output the first sampled signal to the K*Nth sampled signal.

[0077] Specifically, when the first sampling signal to the K*Nth sampling signal are normal sampling signals, there is no transition from 0 to 1 between the first sampling signal and the K*Nth sampling signal, or there is only a transition from 0 to 1 between two sampling signals; if, based on the first judgment result to the K*Nth judgment result, it is determined that there are two or more transitions from 0 to 1 between the first sampling signal and the K*Nth sampling signal, then it indicates that there is a sampling abnormality between the first sampling signal and the K*Nth sampling signal.

[0078] The sampling method provided in this application determines whether the first sampling signal to the K*Nth sampling signal is a normal sampling signal by judging the number of times a transition from 0 to 1 occurs between any two adjacent sampling signals in the first sampling signal to the K*Nth sampling signal, thereby avoiding the output of abnormal first sampling signal to the K*Nth sampling signal, which would affect the measurement results of flight time.

[0079] In one specific implementation, K = 2, N = 2.

[0080] Step S130, determining whether a transition from 0 to 1 occurs between any two adjacent sampled signals from the first sampled signal to the K*Nth sampled signal, and generating the first judgment result to the K*Nth judgment result includes:

[0081] The system determines whether a transition from 0 to 1 occurs between any two adjacent sampled signals from the first to the fourth sampled signals, generating a first judgment result to a fourth judgment result. Specifically, the first judgment result is the judgment result generated based on whether a transition from 0 to 1 occurs between the fourth and first sampled signals; the second judgment result is the judgment result generated based on whether a transition from 0 to 1 occurs between the first and second sampled signals; the third judgment result is the judgment result generated based on whether a transition from 0 to 1 occurs between the second and third sampled signals; and the fourth judgment result is the judgment result generated based on whether a transition from 0 to 1 occurs between the third and fourth sampled signals.

[0082] Step S140, outputting the first judgment result to the K*Nth judgment result includes:

[0083] Output the results of the first to the fourth judgment.

[0084] Step S150: Obtain the first judgment result to the K*Nth judgment result; determine whether the first sampling signal to the K*Nth sampling signal is a normal sampling signal based on the first judgment result to the K*Nth judgment result; if so, proceed to step S160, which includes:

[0085] Based on the first to fourth judgment results, determine whether the first to fourth sampling signals are normal sampling signals. If so, proceed to step S160.

[0086] Step S160, outputting the first sampled signal to the K*Nth sampled signal includes:

[0087] Output the first sampled signal to the fourth sampled signal.

[0088] The foregoing has detailed a sampling method according to an embodiment of this application. Below, a sampling apparatus according to an embodiment of this application is provided. Secondly, please refer to... Figure 6 As shown, Figure 6 The sampling device shown can achieve Figure 1 The sampling method shown includes a first sampling unit 210 and a second sampling unit 220.

[0089] The first sampling unit 210 is used to sample the electrical signal output by the detection unit at a sampling rate of N*f0 to generate an initial sampling signal; where f0 is the clock frequency of the first clock signal and N is a positive integer greater than 1.

[0090] The second sampling unit 220 is used to sample K*N sampled data of adjacent K clock cycles of the initial sampled signal at a sampling rate of f0 / K, to generate the first sampled signal to the K*Nth sampled signal; where K is a positive integer greater than 1.

[0091] Figure 6 The sampling device shown and Figure 1 The method implementations are based on the same concept and bring about the same technical effects. The specific process can be referred to Figure 1 The method embodiments described herein will not be repeated here.

[0092] In some specific implementations, N=2, such as Figure 7 As shown, the first sampling unit 210 includes a first sub-sampling unit 211 and a second sub-sampling unit 212.

[0093] The first sub-sampling unit 211 uses the rising edge of the first clock signal to sample the electrical signal output by the detection unit to generate a first initial sampling signal;

[0094] The second sub-sampling unit 212 uses the falling edge of the first clock signal to sample the electrical signal output by the detection unit to generate a second initial sampling signal.

[0095] Furthermore, K = 2; as Figure 7 As shown, in some specific embodiments, the second sampling unit 220 includes a first synchronization unit 221, a second synchronization unit 222, a first delay unit 223, a second delay unit 224, a first sampling and delay unit 2251, a second sampling and delay unit 2252, a fifth sub-sampling unit 2253, a sixth sub-sampling unit 2254, a third delay unit 226, and a fourth delay unit 227.

[0096] The first synchronization unit 221 is used to synchronize the first initial sampling signal with the first clock signal to generate a first synchronization signal;

[0097] The second synchronization unit 222 is used to synchronize the second initial sampling signal with the first clock signal to generate a second synchronization signal;

[0098] The first delay unit 223 is used to delay the first synchronization signal by T0 and then generate the third synchronization signal.

[0099] The second delay unit 224 is used to delay the second synchronization signal by T0 to generate the fourth synchronization signal;

[0100] The first sampling and delay unit 2251 is used to sample the first synchronization signal using the rising edge of the second clock signal and delay it for T2 to generate the first sampled signal.

[0101] The second sampling and delay unit 2252 is used to sample the second synchronization signal using the rising edge of the second clock signal and delay it for T2 to generate the second sampled signal;

[0102] The third sub-sampling unit 2253 is used to sample the third synchronization signal using the rising edge of the second clock signal to generate the third sampling signal;

[0103] The fourth sub-sampling unit 2254 is used to sample the fourth synchronization signal using the rising edge of the second clock signal to generate the fourth sampling signal.

[0104] Figure 7 The first sampling unit 210 shown and Figure 2 The method implementations are based on the same concept and bring about the same technical effects. The specific process can be referred to Figure 2 The method embodiments described herein will not be repeated here. Figure 7 The second sampling unit 220 shown and Figure 3 The method implementations are based on the same concept and bring about the same technical effects. The specific process can be referred to Figure 3 The method embodiments described herein will not be repeated here.

[0105] Please see Figure 8 , Figure 8 This is a schematic diagram of the structure of the first sampling unit 210 and the second sampling unit 220 provided in an embodiment of this application. Figure 8 As shown, the first sub-sampling unit 211 includes a first flip-flop D1, which is a rising-edge triggered D flip-flop. The first flip-flop D1 includes a data input terminal (also called the D terminal), a data output terminal (also called the Q terminal), and a clock input terminal (also called the C terminal). The data input terminal of the first flip-flop D1 is used to receive the electrical signal output by the detection unit, the clock input terminal of the first flip-flop D1 is used to receive the first clock signal CLK1, and the data output terminal of the first flip-flop D1 is used to output the first initial sampling signal sample1. The second sub-sampling unit 212 includes a second flip-flop D2, which is a falling-edge triggered D flip-flop. The second flip-flop D2 includes a data input terminal (D terminal), a data output terminal (Q terminal), and a clock input terminal (C terminal). The data input terminal of the second flip-flop D2 is used to receive the electrical signal output by the detection unit, the clock input terminal of the second flip-flop D2 is used to receive the first clock signal CLK1, and the data output terminal of the second flip-flop D2 is used to output the second initial sampling signal sample2. The first flip-flop D1 samples the electrical signal output by the detection unit at the rising edge of the first clock signal CLK1 to generate the first initial sampling signal sample1; the second flip-flop D2 samples the electrical signal output by the detection unit at the falling edge of the first clock signal CLK1 to generate the second initial sampling signal sample2.

[0106] like Figure 8As shown, the first synchronization unit 221 includes a third flip-flop D3, which is a rising-edge triggered D flip-flop; the first flip-flop D1 includes a data input terminal (D terminal), a data output terminal (Q terminal), and a clock input terminal (C terminal); the data input terminal of the third flip-flop D3 is used to receive the first preliminary sampling signal sample1, the clock input terminal of the third flip-flop D3 is used to receive the first clock signal CLK1, and the data output terminal of the third flip-flop D3 is used to output the first synchronization signal sync1; the second synchronization unit 222 includes a fourth flip-flop D4, which is a rising-edge triggered D flip-flop; the fourth flip-flop D4 includes a data input terminal (D terminal), a data output terminal (Q terminal), and a clock input terminal (C terminal). The system has one input terminal (D terminal), one data output terminal (Q terminal), and one clock input terminal (C terminal). The data input terminal of the fourth flip-flop D4 is used to receive the second preliminary sampling signal sample2, the clock input terminal of the fourth flip-flop D4 is used to receive the first clock signal CLK1, and the data output terminal of the fourth flip-flop D4 is used to output the second synchronization signal sync2. The third flip-flop D3 is used to synchronize the first initial sampling signal sample1 with the first clock signal CLK1 to generate the first synchronization signal sync1. The fourth flip-flop D4 is used to synchronize the second initial sampling signal sample2 with the first clock signal CLK1 to generate the second synchronization signal sync2.

[0107] like Figure 8 As shown, the first delay unit 223 includes a fifth flip-flop D5, which is a rising-edge triggered D flip-flop. The fifth flip-flop D5 includes a data input terminal (D terminal), a data output terminal (Q terminal), and a clock input terminal (C terminal). The data input terminal of the fifth flip-flop D5 is used to receive the first synchronization signal sync1, the clock input terminal of the fifth flip-flop D5 is used to receive the first clock signal CLK1, and the data output terminal of the fifth flip-flop D5 is used to output the third synchronization signal sync3. The second delay unit 224 includes a sixth flip-flop D6, which is a rising-edge triggered D flip-flop. It includes a data input terminal (also called the D terminal), a data output terminal (also called the Q terminal), and a clock input terminal (also called the C terminal). The data input terminal of the sixth flip-flop D6 is used to receive the second synchronization signal sync2, the clock input terminal of the sixth flip-flop D6 is used to receive the first clock signal CLK1, and the data output terminal of the sixth flip-flop D6 is used to output the fourth synchronization signal sync4. The fifth flip-flop D5 is used to delay the first synchronization signal sync1 by T0 to generate the third synchronization signal sync3. The sixth flip-flop D6 is used to delay the second synchronization signal sync2 by T0 to generate the fourth synchronization signal sync4.

[0108] like Figure 8As shown, the first sampling and delay unit 2251 includes a seventh flip-flop D7 and an eighth flip-flop D8, both of which are rising-edge triggered D flip-flops. Each of the seventh and eighth flip-flops includes a data input terminal (D terminal), a data output terminal (Q terminal), and a clock input terminal (C terminal). The data input terminal of the seventh flip-flop D7 is used to receive the first synchronization signal sync1, and the clock input terminal of the seventh flip-flop D7 is used to receive the second clock signal CLK2. The data output terminal of the seventh flip-flop D7 is connected to the data input terminal of the eighth flip-flop D8. The clock input terminal of the eighth flip-flop D8 is used to receive the second clock signal CLK2, and the data output terminal of the eighth flip-flop D8 is used to output the first sampling signal res1. The seventh flip-flop D7 is used to sample the first synchronization signal sync1 using the rising edge of the second clock signal CLK2, and the eighth flip-flop D8 is used to delay the data output by the seventh flip-flop D7 by T2 to generate the first sampling signal res1.

[0109] like Figure 8 As shown, the second sampling and delay unit 2252 includes a ninth flip-flop D9 and a tenth flip-flop D10, both of which are rising-edge triggered D flip-flops. Each of the ninth and tenth flip-flops includes a data input terminal (D terminal), a data output terminal (Q terminal), and a clock input terminal (C terminal). The data input terminal of the ninth flip-flop D9 is used to receive the second synchronization signal sync2, and the clock input terminal of the ninth flip-flop D9 is used to receive the second clock signal CLK2. The data output terminal of the ninth flip-flop D9 is connected to the data input terminal of the tenth flip-flop D10. The clock input terminal of the tenth flip-flop D10 is used to receive the second clock signal CLK2, and the data output terminal of the tenth flip-flop D10 is used to output the second sampling signal res2. The ninth flip-flop D9 is used to sample the second synchronization signal sync2 using the rising edge of the second clock signal CLK2, and the tenth flip-flop D10 is used to delay the data output by the ninth flip-flop D9 by T2 to generate the second sampling signal res2.

[0110] like Figure 8As shown, the third sub-sampling unit 2253 includes an eleventh flip-flop D11, which is a rising-edge triggered D flip-flop. The eleventh flip-flop D11 includes a data input terminal (D terminal), a data output terminal (Q terminal), and a clock input terminal (C terminal). The data input terminal of the eleventh flip-flop D11 is used to receive the third synchronization signal sync3, the clock input terminal of the eleventh flip-flop D11 is used to receive the second clock signal CLK2, and the data output terminal of the eleventh flip-flop D11 is used to output the third sampling signal res3. The fourth sub-sampling unit 2254 includes a twelfth flip-flop D12, which is a rising-edge triggered D flip-flop. The twelfth flip-flop D12 includes a... The 12th flip-flop D12 has one data input terminal (D terminal), one data output terminal (Q terminal), and one clock input terminal (C terminal). The data input terminal of the 12th flip-flop D12 is used to receive the fourth synchronization signal sync4, and the clock input terminal of the 12th flip-flop D12 is used to receive the second clock signal CLK2. The data output terminal of the 12th flip-flop D12 is used to output the fourth sampling signal res4. The 11th flip-flop D11 is used to sample the third synchronization signal sync3 using the rising edge of the second clock signal CLK2 to generate the third sampling signal res3. The 12th flip-flop D12 is used to sample the fourth synchronization signal sync4 using the rising edge of the second clock signal CLK2 to generate the fourth sampling signal res4.

[0111] The sampling device provided in this application embodiment can sample the electrical signal output by the detection unit at a sampling rate of 2*f0 using the first sampling unit 210 to generate an initial sampling signal, thereby improving the sampling rate and thus improving the measurement accuracy of the time of flight. The sampling device provided in this application embodiment can sample the initial sampling signal at a sampling rate of f0 / 2 using the second sampling unit 220 to generate the first to fourth sampling signals. The initial clock signal is a signal in the clock domain of the first clock signal (frequency f0), and the first to fourth sampling signals are signals in the clock domain of the second clock signal (frequency f0 / 2). This converts the initial sampling signal in the fast clock domain into the first to fourth sampling signals in the slow clock domain, reducing the clock speed requirements for processing subsequent sampling signals (i.e., time of flight data) and reducing the computational resources required for processing subsequent sampling signals.

[0112] Furthermore, such as Figure 9 The sampling device provided in this application further includes a judgment unit 230, an output unit 240, and a determination unit (not shown);

[0113] The judgment unit 230 is used to judge whether a transition from 0 to 1 occurs between every two adjacent sampled signals from the first sampled signal to the K*Nth sampled signal, and to generate the first judgment result to the K*Nth judgment result.

[0114] Output unit 240 is used to output the first judgment result to the K*Nth judgment result;

[0115] The determining unit is used to acquire the first judgment result to the K*Nth judgment result, and determine whether the first sampling signal to the K*Nth sampling signal is a normal sampling signal based on the first judgment result to the K*Nth judgment result.

[0116] The output unit 240 is also used to output the first sampling signal to the K*Nth sampling signal when the first sampling signal to the K*Nth sampling signal are normal sampling signals.

[0117] In one specific implementation, K=2, N=2. The judgment unit 230 is used to determine whether a transition from 0 to 1 occurs between any two adjacent sampled signals in the first to fourth sampled signals, generating a first judgment result to a fourth judgment result; the determination unit is used to acquire the first to fourth judgment results and determine whether the first to fourth sampled signals are normal sampled signals based on the first to fourth judgment results; the output unit 240 is used to output the first to fourth judgment results, and also to output the first to fourth sampled signals when the first to fourth sampled signals are normal sampled signals.

[0118] Figure 8 The sampling device shown and Figure 5 The method implementations are based on the same concept and bring about the same technical effects. The specific process can be referred to Figure 5 The method embodiments described herein will not be repeated here.

[0119] In one specific implementation, see Figure 10 , Figure 10 This is a schematic diagram of a judgment unit 230 and an output unit 240 provided in an embodiment of this application.

[0120] like Figure 10 As shown, the judgment unit 230 includes a first sub-judgment unit 231, a second sub-judgment unit 232, a third sub-judgment unit 233, and a fourth sub-judgment unit 234. The first sub-judgment unit 231 is used to determine whether a transition from 0 to 1 occurs between the fourth sampled signal res4 and the first sampled signal res1. The second sub-judgment unit 231 is used to determine whether a transition from 0 to 1 occurs between the first sampled signal res1 and the second sampled signal res2. The third sub-judgment unit 233 is used to determine whether a transition from 0 to 1 occurs between the second sampled signal res2 and the third sampled signal res3. The fourth sub-judgment unit 234 is used to determine whether a transition from 0 to 1 occurs between the third sampled signal res3 and the fourth sampled signal res4.

[0121] like Figure 10 As shown, the first sub-judgment unit 231 includes a thirteenth flip-flop D13, a first inverter N, and a first AND gate A1; the thirteenth flip-flop D13 is a rising-edge triggered D flip-flop; the thirteenth flip-flop D13 includes a data input terminal (D terminal), a data output terminal (Q terminal), and a clock input terminal (C terminal). The data input terminal of the thirteenth flip-flop D13 is used to receive the fourth sampling signal res4, the clock input terminal of the thirteenth flip-flop D13 is used to receive the second clock signal CLK2, and the data output terminal of the thirteenth flip-flop D13 is connected to the input terminal of the first inverter N; one input terminal of the first AND gate A1 is used to receive the first sampling signal res1. The other input of the first AND gate A1 is connected to the output of the first inverter N. The output of the first AND gate A1 is used to output the fourth judgment result. When there is a transition from 0 to 1 between the fourth sampled signal res4 and the first sampled signal res1, the fourth judgment result output by the first AND gate A1 is equal to the value 1. When there is no transition from 0 to 1 between the fourth sampled signal res3 and the first sampled signal res1, the fourth judgment result output by the first AND gate A1 is equal to the value 0. The value of the fourth judgment result output by the first AND gate A1 can be used to determine whether there is a transition from 0 to 1 between the fourth sampled signal res4 and the first sampled signal res1.

[0122] like Figure 10 As shown, the second sub-judgment unit 232 includes a second inverter N2 and a second AND gate A2; the input terminal of the second inverter N2 is used to receive the second sampled signal res2; one input terminal of the second AND gate A2 is used to receive the first sampled signal res1, the other input terminal of the second AND gate A2 is connected to the output terminal of the second inverter N2, and the output terminal of the second AND gate A2 is used to output the first judgment result; when there is a transition from 0 to 1 between the first sampled signal res1 and the second sampled signal res2, the first judgment result output by the second AND gate A2 is equal to the value 1, and when there is no transition from 0 to 1 between the first sampled signal res1 and the second sampled signal res2, the first judgment result output by the second AND gate A2 is equal to the value 0; whether there is a transition from 0 to 1 between the first sampled signal res1 and the second sampled signal res2 can be obtained according to the value of the first judgment result output by the second AND gate A2.

[0123] like Figure 10As shown, the third sub-judgment unit 233 includes a third inverter N3 and a third AND gate A3; the input terminal of the third inverter N3 is used to receive the third sampled signal res3; one input terminal of the third AND gate A3 is used to receive the second sampled signal res2, the other input terminal of the third AND gate A3 is connected to the output terminal of the third inverter N3, and the output terminal of the third AND gate A3 is used to output the second judgment result; when there is a transition from 0 to 1 between the second sampled signal res2 and the third sampled signal res3, the second judgment result output by the third AND gate A3 is equal to the value 1, and when there is no transition from 0 to 1 between the second sampled signal res2 and the third sampled signal res3, the second judgment result output by the third AND gate A3 is equal to the value 0; based on the value of the second judgment result output by the third AND gate A3, it can be determined whether there is a transition from 0 to 1 between the second sampled signal res2 and the third sampled signal res3.

[0124] like Figure 10 As shown, the fourth sub-judgment unit 234 includes a fourth inverter N4 and a fourth AND gate A4; the input of the fourth inverter N4 is used to receive the fourth sampled signal res4; one input of the fourth AND gate A4 is used to receive the third sampled signal res3, the other input of the fourth AND gate A4 is connected to the output of the fourth inverter N4, and the output of the fourth AND gate A4 is used to output the third judgment result; when there is a transition from 0 to 1 between the third sampled signal res3 and the fourth sampled signal res4, the third judgment result output by the fourth AND gate A4 is equal to the value 1, and when there is no transition from 0 to 1 between the third sampled signal res3 and the fourth sampled signal res4, the third judgment result output by the fourth AND gate A4 is equal to the value 0; based on the value of the third judgment result output by the fourth AND gate A4, it can be determined whether there is a transition from 0 to 1 between the third sampled signal res2 and the fourth sampled signal res3.

[0125] like Figure 10 As shown, the output unit 240 includes a first sub-output unit 241, a second sub-output unit 242, a third sub-output unit 243, and a fourth sub-output unit 244. When it is necessary to output the first judgment result, the second judgment result, the third judgment result, and the fourth judgment result, the first sub-output unit 241, the second sub-output unit 242, the third sub-output unit 243, and the fourth sub-output unit 244 are respectively used to output the first sampling signal res1, the second sampling signal res2, the third sampling signal res3, and the fourth sampling signal res4.

[0126] like Figure 11 As shown, the first sub-output unit 241 includes a first data selector M1 and a fourteenth flip-flop D14. The first data selector M1 includes two data input terminals, one data output terminal, and one control signal input terminal. One data input terminal of the first data selector M1 is connected to the output terminal of the first AND gate A1 to receive the first judgment result. The other data input terminal of the first data selector M1 is connected to the output terminal of the fourteenth flip-flop D14 to receive the first sampling signal res1. The control signal input terminal of the first data selector M1 receives a control signal. The first data selector M1 is used to control the signal... Below, the first selection result or the first sampling signal res1 is output through the output terminal; the fourteenth flip-flop D14 is a rising edge triggered D flip-flop; the fourteenth flip-flop D14 includes a data input terminal (D terminal), a data output terminal (Q terminal) and a clock input terminal (C terminal). The data input terminal of the fourteenth flip-flop D14 is connected to the output terminal of the first data selector M1. The clock input terminal of the fourteenth flip-flop D14 is used to receive the second clock signal CLK2. The data output terminal of the fourteenth flip-flop D14 is used to output the first judgment result or the first sampling signal res1 synchronized with the second clock signal CLK2.

[0127] like Figure 11 As shown, the second sub-output unit 242 includes a second data selector M2 and a fifteenth flip-flop D15. The second data selector M2 includes two data input terminals, one data output terminal, and one control signal input terminal. One data input terminal of the second data selector M2 is connected to the output terminal of the second AND gate A2 to receive the second judgment result. The other data input terminal of the second data selector M2 is connected to the output terminal of the fifteenth flip-flop D15 to receive the second sampling signal res2. The control signal input terminal of the second data selector M2 receives the control signal. The second data selector M2 is used to control the signal... Below, the second selection result or the second sampling signal res2 is output through the output terminal; the fifteenth flip-flop D15 is a rising edge triggered D flip-flop; the fifteenth flip-flop D15 includes a data input terminal (D terminal), a data output terminal (Q terminal) and a clock input terminal (C terminal). The data input terminal of the fifteenth flip-flop D15 is connected to the output terminal of the second data selector M2. The clock input terminal of the fifteenth flip-flop D15 is used to receive the second clock signal CLK2. The data output terminal of the fifteenth flip-flop D15 is used to output the second judgment result or the second sampling signal res2 synchronized with the second clock signal CLK2.

[0128] like Figure 11As shown, the third sub-output unit 243 includes a third data selector M3 and a sixteenth flip-flop D16. The third data selector M3 includes two data input terminals, one data output terminal, and one control signal input terminal. One data input terminal of the third data selector M3 is connected to the output terminal of the third AND gate A3 to receive the third judgment result. The other data input terminal of the third data selector M3 is connected to the output terminal of the sixteenth flip-flop D16 to receive the third sampling signal res3. The control signal input terminal of the third data selector M3 receives the control signal. The third data selector M3 is used to control the signal... Below, the third selection result or the third sampling signal res3 is output through the output terminal; the sixteenth flip-flop D16 is a rising edge triggered D flip-flop; the sixteenth flip-flop D16 includes a data input terminal (D terminal), a data output terminal (Q terminal) and a clock input terminal (C terminal). The data input terminal of the sixteenth flip-flop D16 is connected to the output terminal of the third data selector M3. The clock input terminal of the sixteenth flip-flop D16 is used to receive the second clock signal CLK2. The data output terminal of the sixteenth flip-flop D16 is used to output the third judgment result or the third sampling signal res3 synchronized with the second clock signal CLK2.

[0129] like Figure 11 As shown, the fourth sub-output unit 244 includes a third data selector M4 and a seventeenth flip-flop D17. The fourth data selector M4 includes two data input terminals, one data output terminal, and one control signal input terminal. One data input terminal of the fourth data selector M4 is connected to the output terminal of the fourth AND gate A4 to receive the fourth judgment result. The other data input terminal of the fourth data selector M4 is connected to the output terminal of the seventeenth flip-flop D17 to receive the fourth sampling signal res4. The control signal input terminal of the fourth data selector M4 receives the control signal. The fourth data selector M4 is used to control the signal... Below, the fourth selection result or the fourth sampling signal res4 is output through the output terminal; the seventeenth flip-flop D17 is a rising edge triggered D flip-flop; the seventeenth flip-flop D17 includes a data input terminal (D terminal), a data output terminal (Q terminal) and a clock input terminal (C terminal). The data input terminal of the seventeenth flip-flop D17 is connected to the output terminal of the fourth data selector M4. The clock input terminal of the seventeenth flip-flop D17 is used to receive the second clock signal CLK2. The data output terminal of the seventeenth flip-flop D17 is used to output the fourth judgment result or the fourth sampling signal res4 synchronized with the second clock signal CLK2.

[0130] Specifically, when the confirmation unit 250 needs to determine whether the first sampling signal to the K*Nth sampling signal is a normal sampling signal based on the first judgment result to the K*Nth judgment result, the control signal is in the first state (e.g., high level) to control the first data selector M1, the second data addresser M2, the third data selector M3 and the fourth data selector M4 to output the first selection result, the second selection result, the third selection result and the fourth selection result respectively, and output the first judgment result, the second judgment result, the third judgment result and the fourth judgment result synchronized with the second clock signal CLK2 to the determination unit through the fourteenth flip-flop D14, the fifteenth flip-flop D15, the sixteenth flip-flop D16 and the seventeenth flip-flop D17 respectively. When the determining unit determines that the first sampling signal res1, the second sampling signal res2, the third sampling signal res3, and the fourth sampling signal res4 are normal sampling signals based on the first judgment result, the second judgment result, the third judgment result, and the fourth judgment result, the control signal is in the second state (e.g., low level) to control the first data selector M1, the second data addresser M2, the third data selector M3, and the fourth data selector M4 to output the first sampling signal res1, the second sampling signal res2, the third sampling signal res3, and the fourth sampling signal res4, respectively.

[0131] The foregoing has described in detail a sampling device according to an embodiment of this application. Below, a laser ranging device according to an embodiment of this application is provided. Thirdly, please refer to... Figure 12 As shown, the laser ranging device may include: a transmitter 60, a detector 10, a processor 910, a communication interface 920, a memory 930, and a communication bus 940. The transmitter 60 includes one or more light-emitting units 601 for emitting pulsed light signals. The detector 10 includes one or more detection units 101 for receiving light signals. Each light-emitting unit 601 corresponds to one or more detection units 101. The processor 910, communication interface 920, and memory 930 communicate with each other via the communication bus 940. The communication interface 920 is used to communicate with other devices, such as clients or other server network elements. The memory 930 stores computer programs or instructions 903 that implement the various units of the above method embodiments (i.e., sampling methods) or device embodiments (i.e., sampling devices). The processor 910 is connected to the transmitter 60 and detector 10 via the communication interface 920 and is used to call the computer program or instructions 903 to execute the operations of the above method embodiments, for example... Figure 2 S110 to S120 are shown. Figure 3 S111 to S112 are shown. Figure 5S110 to S150 are shown.

[0132] The laser ranging device provided in this application determines the flight time from the first sampling signal to the K*Nth sampling signal (e.g., from the first sampling signal to the fourth sampling signal) output by the above-described method or device embodiments. Then, it generates a point cloud map based on the flight time. By processing the point cloud map, it obtains parameters such as the distance, orientation, height, speed, attitude, and shape of obstacles, thereby realizing the laser detection function. It can then be applied to navigation and avoidance, obstacle recognition, ranging, speed measurement, and autonomous driving scenarios of products such as automobiles, robots, logistics vehicles, and inspection vehicles.

[0133] Specifically, in some embodiments, the emitter 60 includes a light-emitting unit 601. In this case, the emitter 60 can be a vertical-cavity surface-emitting laser (VCSEL), an edge-emitting laser (EEL), a light-emitting diode (LED), a micro light-emitting diode (Micro LED), a pulsed laser deposition (PLD), or a laser diode (LD), etc. This application does not limit the type of emitter 60.

[0134] In some other embodiments, the emitter 60 includes a plurality of light-emitting units 601; the plurality of light-emitting units 601 can be arranged in an array, that is, the emitter 60 can be a laser array. In this case, the emitter 60 can be a vertical-cavity surface-emitting laser (VCSEL) array, an edge-emitting laser (EEL) array, a light-emitting diode (LED) array, a micro-light-emitting diode (Micro LED) array, a pulsed laser deposition (PLD) array, or a laser diode (LD) array, etc. This application does not limit the type of emitter 60.

[0135] In some embodiments, detector 10 includes a detection unit 101. In this case, detector 10 can be a single-photon avalanche diode (SPAD) or a silicon photomultiplier (SIPM), and this application does not limit the type of detector 10. In other embodiments, detector 10 includes multiple detection units 101, which are arranged in an array, i.e., detector 10 can be a detector array. In this case, detector 10 can be a single-photon avalanche diode (SPAD) array or a silicon photomultiplier (SIPM) array, and this application does not limit the type of detector 10.

[0136] Furthermore, when the transmitter 60 includes multiple light-emitting units 601, the multiple light-emitting units 601 can emit light sequentially to scan and transmit pulsed light signals to the detection area to scan obstacles within the detection area. Correspondingly, the detection unit 101 in the detector 10 is used to detect the echo light signals reflected by obstacles located within the detection area.

[0137] Specifically, the processor 910 can be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor can be a microprocessor or any conventional processor.

[0138] The memory 930 can be an internal storage unit of the laser rangefinder, such as the hard drive or RAM of the laser rangefinder. The memory 930 can also be an external storage device of the laser rangefinder, such as a plug-in hard drive, Smart Media Card (SMC), Secure Digital (SD) card, or Flash Card equipped on the laser rangefinder. Furthermore, the memory 930 can include both internal and external storage units of the laser rangefinder. The memory 930 is used to store the computer program and other programs and data required by the terminal device. The memory 930 can also be used to temporarily store data that has been output or will be output.

[0139] This application also provides a computer-readable storage medium. The computer-readable storage medium stores at least one executable instruction, which, when executed by a processor, implements the above-described sampling method.

[0140] This application provides a computer program product that, when run on a laser ranging device, enables the laser ranging device to implement the above-mentioned sampling method.

[0141] Those skilled in the art will understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is merely an example. In practical applications, the functions described above can be assigned to different functional units and modules as needed, that is, the internal structure of the terminal device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiments can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit. Furthermore, the specific names of the functional units and modules are only for easy differentiation and are not intended to limit the scope of protection of this application. The specific working process of the units and modules in the above system can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here. In the above embodiments, the descriptions of each embodiment have different focuses; parts not described or recorded in detail in a certain embodiment can be referred to the relevant descriptions of other embodiments.

[0142] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0143] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A sampling method, characterized in that, include: With N f0 is the sampling rate used to sample the electrical signal output by the detection unit to generate an initial sampling signal; where f0 is the clock frequency of the first clock signal, and N is a positive integer greater than 1. Using f0 / K as the sampling rate, K adjacent clock cycles of the initial sampled signal N samples are sampled to generate the first sampled signal up to the Kth sampled signal. N is the sampled signal; where K is a positive integer greater than 1; Where N=2; the N The sampling rate f0 is used to sample the electrical signal output by the detection unit to generate an initial sampling signal. This includes: sampling the electrical signal output by the detection unit using the rising edge of the first clock signal to generate a first initial sampling signal; and sampling the electrical signal output by the detection unit using the falling edge of the first clock signal to generate a second initial sampling signal. The first initial sampling signal and the second initial sampling signal together constitute the initial sampling signal. K=2; the K adjacent K clock cycles of the initial sampled signal with a sampling rate of f0 / K N samples are sampled to generate the first sampled signal up to the Kth sampled signal. The N-sample signal includes: synchronizing the first initial sample signal with a first clock signal to generate a first synchronization signal; synchronizing the second initial sample signal with the first clock signal to generate a second synchronization signal; delaying the first synchronization signal by T0 to generate a third synchronization signal; delaying the second synchronization signal by T0 to generate a fourth synchronization signal; wherein T0 is the clock period of the first clock signal, and T0 = 1 / f0; sampling the first synchronization signal using the rising edge of the second clock signal and delaying by T2 to generate a first sample signal; sampling the second synchronization signal using the rising edge of the second clock signal and delaying by T2 to generate a second sample signal; sampling the third synchronization signal using the rising edge of the second clock signal to generate a third sample signal; sampling the fourth synchronization signal using the rising edge of the second clock signal to generate a fourth sample signal; wherein the clock frequency of the second clock signal is f0 / 2, and the clock period of the second clock signal is T2, T2 = 2 / f0.

2. The method according to claim 1, characterized in that, The K adjacent clock cycles of the initial sampled signal with a sampling rate of f0 / K N samples are sampled to generate the first sampled signal up to the Kth sampled signal. Following the N-sampled signal, it also includes: Determine the first sampled signal up to the Kth Whether a transition from 0 to 1 occurs between every two adjacent samples in the N-sampled signal, generate the first judgment result up to the Kth... N is the result of the judgment; Output the first judgment result up to the Kth... N is the result of the judgment; Obtain the first judgment result up to the Kth Based on the N-judgment result, the first sampling signal up to the Kth... Is the N-sampled signal a normal sampled signal? When the first sampled signal reaches the Kth... When the N-sampled signal is a normal sampled signal, output the first sampled signal up to the K-th sampled signal. N sampled signals.

3. A sampling device, characterized in that, include: The first sampling unit is used to sample N f0 is the sampling rate used to sample the electrical signal output by the detection unit to generate an initial sampling signal; where f0 is the clock frequency of the first clock signal, and N is a positive integer greater than 1. The second sampling unit is used to sample the K adjacent clock cycles of the initial sampled signal at a sampling rate of f0 / K. N samples are sampled to generate the first sampled signal up to the Kth sampled signal. N is the sampled signal; where K is a positive integer greater than 1; Wherein, N=2; the first sampling unit includes: a first sub-sampling unit, which samples the electrical signal output by the detection unit using the rising edge of the first clock signal to generate a first initial sampling signal; a second sub-sampling unit, which samples the electrical signal output by the detection unit using the falling edge of the first clock signal to generate a second initial sampling signal; wherein, the first initial sampling signal and the second initial sampling signal constitute the initial sampling signal; K=2; the second sampling unit includes: a first synchronization unit, used to synchronize the first initial sampling signal with the first clock signal to generate a first synchronization signal; a second synchronization unit, used to synchronize the second initial sampling signal with the first clock signal to generate a second synchronization signal; a first delay unit, used to delay the first synchronization signal by T0 to generate a third synchronization signal; a second delay unit, used to delay the second synchronization signal by T0 to generate a fourth synchronization signal; wherein, T0 is the clock period of the first clock signal, and T0=1 / f0; a first sampling and delay unit, used to use the rising edge of the second clock signal to sample the first initial sampling signal. A first sampling signal is generated by sampling a synchronization signal and delaying it for T2. A second sampling and delay unit is used to sample the second synchronization signal using the rising edge of the second clock signal and delay it for T2 to generate a second sampling signal. The clock frequency of the second clock signal is f0 / 2, and the clock period of the second clock signal is T2, where T2 = 2 / f0. A third sub-sampling unit is used to sample the third synchronization signal using the rising edge of the second clock signal to generate a third sampling signal. A fourth sub-sampling unit is used to sample the fourth synchronization signal using the rising edge of the second clock signal to generate a fourth sampling signal.

4. The sampling device according to claim 3, characterized in that, Also includes: The judgment unit is used to judge the first sampled signal up to the Kth digit. Whether a transition from 0 to 1 occurs between every two adjacent samples in the N-sampled signal, generate the first judgment result up to the Kth... N is the result of the judgment; Output unit, used to output the first judgment result up to the Kth... N is the result of the judgment; Determining unit, used to obtain the first judgment result up to the Kth... N is the judgment result, based on the first judgment result up to the Kth... The N-judgment result determines the first sampling signal up to the Kth... Is the N-sampled signal a normal sampled signal? The output unit is also used to process the first sampled signal to the Kth sampled signal. When the N-sampled signal is a normal sampled signal, output the first sampled signal up to the K-th sampled signal. N sampled signals.

5. A computer-readable storage medium storing at least one executable instruction that, when executed by a processor, implements the method as claimed in claim 1 or 2.

6. A laser ranging device, characterized in that, include: Transmitter, detector, processor, communication interface, memory, and communication bus; The processor communicates with the transmitter and the detector through the communication interface; The processor, communication interface, and memory communicate with each other through the communication bus; The transmitter includes one or more light-emitting units for emitting pulsed light signals; The detector includes one or more detection units for receiving optical signals; The memory is used to store computer programs or instructions; The processor is used to execute computer programs or instructions in the memory to implement the method as described in claim 1 or 2.

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