Stacked wafers

Abstract

This invention discloses a stacked wafer, relating to the field of semiconductor technology. A first wafer has a first surface including a first bonding region and a first edge region surrounding the first bonding region. The second surface of a second wafer, projected onto the first surface, lies within the first bonding region. The stacked wafer includes multiple chip regions arranged in an array, and dicing regions surrounding the chip regions. A first bonding structure on the first wafer and a second bonding structure on the second wafer are connected at the dicing region outside any one of the chip regions. A first test pad and a second test pad are both located in the first edge region. The first test pad is electrically connected to the first bonding structure, and the second test pad is electrically connected to the second bonding structure. The first and second test pads enable electrical interconnection testing during the process, thereby achieving real-time monitoring of the bonding process. Problems can be promptly rectified, improving production line reliability.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more specifically, to a stacked wafer. Background Technology

[0002] In semiconductor packaging technology, hybrid bonding interfaces, which combine dielectric and metallic materials, enable structural and electrical interconnections between wafers. However, testing the effectiveness of these electrical interconnections requires waiting until bonding is complete and multiple subsequent processes are finished. This process is time-consuming, hinders real-time monitoring, and makes it difficult to promptly address problems. Summary of the Invention

[0003] Therefore, this application provides a stacked wafer that facilitates electrical interconnect testing during the process.

[0004] The stacked wafer provided in this application includes a first wafer and a second wafer stacked together. The first wafer includes a first surface connected to the second wafer, and the second wafer includes a second surface connected to the first wafer. The first surface includes a first bonding region and a first edge region surrounding the first bonding region. The orthographic projection of the second surface onto the first surface lies within the first bonding region. Along a direction parallel to the first surface, the stacked wafer includes a plurality of chip regions arranged in an array, and dicing regions surrounding the chip regions. The first wafer also includes at least one first bonding structure, and the second wafer also includes at least one second bonding structure. The first bonding structure and the second bonding structure are connected to the dicing region outside any one of the chip regions. The first wafer also includes a first test pad and a second test pad, both disposed in the first edge region. The first test pad is electrically connected to the first bonding structure, and the second test pad is electrically connected to the second bonding structure.

[0005] In some embodiments, the stacked wafer further includes a first connection structure and a second connection structure disposed in the dicing area, wherein the first test pad is electrically connected to the first bonding structure through the first connection structure, and the second test pad is electrically connected to the second bonding structure through the second connection structure.

[0006] In some embodiments, the first connection structure includes a first conductive layer located within a first wafer, one end of which is electrically connected to a first test pad and the other end of which is electrically connected to a first bonding structure. The second connection structure includes a second conductive layer located within the first wafer, one end of which is electrically connected to a second bonding structure via the first bonding structure and the other end of which is electrically connected to a second test pad.

[0007] In some embodiments, the first connection structure includes a third conductive layer located within a first wafer, one end of which is electrically connected to a first test pad and the other end of which is electrically connected to a first bonding structure. The second connection structure includes a fourth conductive layer and a third bonding structure within the first wafer, and a fifth conductive layer and a fourth bonding structure located within a second wafer. One end of the fifth conductive layer is electrically connected to the second bonding structure and the other end of which is electrically connected to the fourth bonding structure. The third and fourth bonding structures are connected in a dicing region outside any chip region. One end of the fourth conductive layer is electrically connected to the third bonding structure and the other end of which is electrically connected to a second test pad.

[0008] In some embodiments, the first connection structure includes a sixth conductive layer and a fifth bonding structure located within a first wafer, and a seventh conductive layer and a sixth bonding structure located within a second wafer. One end of the sixth conductive layer is electrically connected to a first test pad, and the other end is electrically connected to the fifth bonding structure. The fifth bonding structure and the sixth bonding structure are connected in a dicing region outside any chip region. One end of the seventh conductive layer is electrically connected to the sixth bonding structure, and the other end is electrically connected to the first bonding structure via a second bonding structure. The second connection structure includes an eighth conductive layer and a seventh bonding structure located within the first wafer, and a ninth conductive layer and an eighth bonding structure located within the second wafer. One end of the ninth conductive layer is electrically connected to the second bonding structure, and the other end is electrically connected to the eighth bonding structure. The seventh bonding structure and the eighth bonding structure are connected in a dicing region outside any chip region. One end of the eighth conductive layer is electrically connected to the seventh bonding structure, and the other end is electrically connected to a second test pad.

[0009] In some embodiments, the stacked wafer further includes a third wafer located on the side of the second wafer away from the first wafer. The second wafer also includes a third surface connected to the third wafer and a fourth surface connected to the second wafer. The third surface includes a second bonding region and a second edge region surrounding the outer side of the second bonding region. The orthographic projection of the fourth surface onto the third surface lies within the second bonding region. The second wafer also includes at least one ninth bonding structure, and the third wafer also includes at least one tenth bonding structure. The ninth and tenth bonding structures are connected to a dicing region outside either chip region. The second wafer also includes a third test pad and a fourth test pad, both disposed in the second edge region. The third test pad is electrically connected to the ninth bonding structure, and the fourth test pad is electrically connected to the tenth bonding structure.

[0010] In some embodiments, the stacked wafer further includes a third connection structure and a fourth connection structure disposed in the dicing region, wherein the third test pad is electrically connected to the ninth bonding structure through the third connection structure, and the fourth test pad is electrically connected to the tenth bonding structure through the fourth connection structure.

[0011] In some embodiments, the third connection structure includes a tenth conductive layer located within the second wafer, one end of which is electrically connected to a third test pad, and the other end of which is electrically connected to a ninth bonding structure. The fourth connection structure includes an eleventh conductive layer located within the second wafer, one end of which is electrically connected to the tenth bonding structure via the ninth bonding structure, and the other end of which is electrically connected to a fourth test pad.

[0012] In some embodiments, the third connection structure includes a twelfth conductive layer located within the second wafer, one end of which is electrically connected to a third test pad, and the other end of which is electrically connected to a ninth bonding structure. The fourth connection structure includes a thirteenth conductive layer and an eleventh bonding structure within the second wafer, and a fourteenth conductive layer and a twelfth bonding structure located within the third wafer. One end of the fourteenth conductive layer is electrically connected to a tenth bonding structure, and the other end of which is electrically connected to a twelfth bonding structure. The eleventh and twelfth bonding structures are connected in a dicing region outside any chip region. One end of the thirteenth conductive layer is electrically connected to the eleventh bonding structure, and the other end of which is electrically connected to a fourth test pad.

[0013] In some embodiments, the third connection structure includes a fifteenth conductive layer and a thirteenth bonding structure located within the second wafer, and a sixteenth conductive layer and a fourteenth bonding structure located within the third wafer. One end of the fifteenth conductive layer is electrically connected to a third test pad, and the other end is electrically connected to the thirteenth bonding structure. The thirteenth and fourteenth bonding structures are connected in a dicing region outside any chip region. One end of the sixteenth conductive layer is electrically connected to the fourteenth bonding structure, and the other end is electrically connected to the ninth bonding structure via a tenth bonding structure. The fourth connection structure includes a seventeenth conductive layer and a fifteenth bonding structure located within the second wafer, and an eighteenth conductive layer and a sixteenth bonding structure located within the third wafer. One end of the eighteenth conductive layer is electrically connected to the tenth bonding structure, and the other end is electrically connected to the sixteenth bonding structure. The fifteenth and sixteenth bonding structures are connected in a dicing region outside any chip region. One end of the seventeenth conductive layer is electrically connected to the fifteenth bonding structure, and the other end is electrically connected to the fourth test pad.

[0014] In this embodiment, a first wafer and a second wafer are stacked, with the first surface of the first wafer connected to the second surface of the second wafer; this interface can be understood as a bonding interface. Along a direction parallel to the first surface, the stacked wafers include multiple chip regions arranged in an array, and dicing regions surrounding the chip regions. The first wafer also includes at least one first bonding structure, and the second wafer also includes at least one second bonding structure. The first bonding structure and the second bonding structure are connected in the dicing region outside any one of the chip regions. Testing the electrical interconnection effect between wafers is also testing the electrical interconnection effect between the first bonding structure and the second bonding structure. In this embodiment, the first surface includes a first bonding region and a first edge region surrounding the first bonding region. The orthographic projection of the second surface onto the first surface is located within the first bonding region. The first wafer also includes a first test pad and a second test pad, both disposed in the first edge region. The first test pad is electrically connected to the first bonding structure, and the second test pad is electrically connected to the second bonding structure. The first and second test pads are used for electrical testing. Since both pads are exposed in the first edge region, the test probes can directly connect to them during testing, allowing for direct electrical testing without damaging the stacked wafers. If the electrical test fails, remedial measures can be taken to repair the electrical interconnections between the wafers, such as continued annealing or debonding and rebonding until the electrical test passes, after which subsequent wafer thinning, via etching, and other processes can be performed. In other words, electrical interconnect testing can be performed during the process, enabling real-time monitoring of the bonding process and timely remediation of problems, thus improving production line reliability. Attached Figure Description

[0015] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which: Figure 1 This is a schematic diagram of a stacked wafer structure provided in an embodiment of this application; Figure 2 for Figure 1 The cross-sectional view of the stacked wafers shown along section line AA'; Figure 3 This is a schematic diagram of the stacked wafer structure in related technologies; Figure 4 This is a schematic diagram of the structure of a second type of stacked wafer provided in an embodiment of this application; Figure 5 This is a schematic diagram of the third type of stacked wafer structure provided in the embodiments of this application; Figure 6 This is a schematic diagram of the fourth type of stacked wafer structure provided in the embodiments of this application; Figure 7 This is a schematic diagram of the fifth type of stacked wafer structure provided in the embodiments of this application; Figure 8 This is a schematic diagram of the sixth type of stacked wafer provided in the embodiments of this application. Detailed Implementation

[0016] The technical solutions in some embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this application are within the scope of protection of this application.

[0017] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open and encompassing, that is, "including, but not limited to".

[0018] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this application, unless otherwise stated, "a plurality of" means two or more.

[0019] In describing some embodiments, the term "connection" and its derivative expressions may be used. The term "connection" should be interpreted broadly; for example, "connection" can be a fixed connection, a detachable connection, or an integral part; it can be a direct connection or an indirect connection through an intermediate medium. For example, in describing some embodiments, the term "connection" may be used to indicate that two or more components have direct physical or electrical contact with each other.

[0020] In addition, the use of “based on” implies openness and inclusivity, because processes, steps, calculations or other actions “based on” one or more of the stated conditions or values ​​may in practice be based on additional conditions or values ​​beyond those stated.

[0021] It should be understood that when a layer or element is referred to as being on another layer or substrate, it can mean that the layer or element is directly on the other layer or substrate, or that there is an intermediate layer between the layer or element and the other layer or substrate.

[0022] This document describes exemplary embodiments with reference to cross-sectional views, which are intended as idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include shape deviations caused, for example, by manufacturing processes. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of areas of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0023] Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.

[0024] As mentioned in the background section, in semiconductor packaging technology, hybrid bonding interfaces include dielectric and metal materials, enabling structural and electrical interconnections between wafers. However, testing the effectiveness of these electrical interconnections requires multiple steps after wafer stacking, including wafer thinning, via etching, and metal wire interconnection to bring out the electrical connections. This process is lengthy, hinders real-time monitoring, and makes timely remediation difficult when problems arise. Furthermore, stacked wafers typically comprise multiple chip regions, and current technologies only allow electrical testing on the diced portions corresponding to the outermost chip regions, making it difficult to test the central portion of the stacked wafer.

[0025] Based on this, embodiments of this application provide a stacked wafer, such as Figures 1-2 As shown, Figure 1 This is a schematic diagram of a stacked wafer structure provided in an embodiment of this application. Figure 2 for Figure 1 The image shows a cross-sectional view of the stacked wafers along section line AA'.

[0026] The stacked wafers include a first wafer 101 and a second wafer 102 stacked together. The first wafer 101 includes a first surface P1 connected to the second wafer 102, and the second wafer 102 includes a second surface P2 connected to the first wafer 101. The first surface P1 and the second surface P2 can be understood as the bonding interface of the stacked wafers.

[0027] The first surface P1 includes a first bonding region Q1 and a first edge region C1 surrounding the outer side of the first bonding region Q1. The orthographic projection of the second surface P2 onto the first surface P1 lies within the first bonding region Q1. Along a direction parallel to the first surface P1, the stacked wafer includes a plurality of chip regions M1 arranged in an array, and a dicing region N1 surrounding the outer side of the chip regions M1. The first wafer 101 also includes at least one first bonding structure 201, and the second wafer 102 also includes at least one second bonding structure 202. The first bonding structure 201 and the second bonding structure 202 are connected at the dicing region N1 outside any one of the chip regions M1. The test of the electrical interconnection effect between wafers 101 and 102 is also a test of the electrical interconnection effect between the first bonding structure 201 and the second bonding structure 202. The bonding positions of the first bonding structure 201 and the second bonding structure 202 in the dicing region N1 can be designed as needed. They can be close to the central chip region M1, close to the edge chip region M1, or near the outer side of each chip region M1.

[0028] The first wafer 101 also includes a first test pad 301 and a second test pad 302. The first test pad 301 and the second test pad 302 are both disposed in the first edge region C1. The first test pad 301 is electrically connected to the first bonding structure 201, and the second test pad 302 is electrically connected to the second bonding structure 202.

[0029] In this embodiment of the application, the first test pad 301 and the second test pad 302 are used for electrical testing. The first test pad 301 and the second test pad 302 are both disposed in the first edge region C1, that is, the first test pad 301 and the second test pad 302 are both exposed on the first surface P1.

[0030] For example, before bonding the stacked wafers, the second wafer 102 is trimmed. A trimming tool is used to smooth the edge region of the second surface P2 of the second wafer 102, ensuring that after bonding with the first wafer 101, the edge of the second wafer 102 will not break or peel due to lack of support. This improves the bonding effect of the stacked wafers and guarantees the bonding strength. Simultaneously, the trimming process makes the area of ​​the second surface P2 of the second wafer 102 smaller than the area of ​​the first surface P1 of the first wafer 101. After bonding, the second wafer 102 will expose a first edge region C1 on the first surface P1 of the first wafer 101.

[0031] This application makes full use of the first edge region C1, and sets a first test pad 301 and a second test pad 302 in the first edge region C1. During the electrical test, the test probe can be directly electrically connected to the first test pad 301 and the second test pad 302 respectively, without damaging the stacked wafer, which is beneficial to the electrical test process.

[0032] In related technologies, wafers are aligned and bonded together, followed by an annealing process to form electrical interconnects between them. The bonding effectiveness is then tested, including measuring bonding accuracy and detecting bonding bubbles. After passing the bonding effectiveness test, the wafers undergo multiple processes such as wafer thinning, via etching, and metal wire interconnection to expose the electrical components, followed by further electrical testing.

[0033] The stacked wafers provided in this application embodiment facilitate electrical testing during wafer bonding. For example, if the bonding accuracy test is passed, annealing is performed first, and electrical testing can be performed directly without damaging the structure of the stacked wafers. If the electrical test fails, remedial measures can be taken to repair the electrical interconnection between wafers, such as continuing annealing or debonding and rebonding until the electrical test is passed, and then subsequent wafer thinning, via etching, and other processes are performed.

[0034] In other words, the stacked wafers provided in this application embodiment facilitate the electrical testing process and enable electrical interconnection testing at any bonding position in the dicing area during the process, thereby achieving real-time monitoring of the bonding process. Problems can be rectified in a timely manner, which helps improve the reliability of the production line.

[0035] In some embodiments, such as Figure 1 and Figure 2 As shown, the stacked wafer also includes a first connection structure 11 and a second connection structure 12 disposed in the dicing region N1. The first test pad 301 is electrically connected to the first bonding structure 201 through the first connection structure 11, and the second test pad 302 is electrically connected to the second bonding structure 202 through the second connection structure 12.

[0036] In related technologies, such as Figure 3 As shown, Figure 3 This is a schematic diagram of a stacked wafer structure in the related technology. The stacked wafer includes multiple chip regions M1 and multiple dicing regions N0. Each dicing region N0 is located around the outside of a chip region M1. The first bonding structure 201 and the second bonding structure 202 are connected to each dicing region N0 respectively. The bonding structures of different dicing regions N0 are independent and not connected to each other. Each dicing region N0 can be regarded as an independent region.

[0037] In this embodiment, the first connecting structure 11 and the second connecting structure 12 can extend to different cutting channel regions N0, so that the bonding structures of different cutting channel regions N0 are interconnected. In other words, as Figure 1 As shown, from the perspective of electrical connectivity, the dicing area N1 surrounding the chip area M1 in this embodiment can be considered as a connected area. Furthermore, from the perspective of the dicing process, each chip area M1 is still surrounded by a corresponding dicing protection area. Each dicing protection area can be considered an independent area. During and after dicing, this dicing protection area can prevent each chip area M1 from being affected by moisture, and can also be used to set alignment marks to assist in the alignment process, or to implement other functions possessed by conventional dicing areas.

[0038] At least one pair of connected first bonding structures 201 and second bonding structures 202 are provided on the outer side of each chip region M1. For ease of explanation, a pair of connected first bonding structures 201 and second bonding structures 202 are regarded as a bonding point. The first connecting structure 11 and the second connecting structure 12 can realize the electrical connection between bonding points at different positions, and can also realize the electrical connection between any bonding point and the first test pad 301 and the second test pad 302. It can be understood that, for a certain bonding point, the conductive channel in the first connecting structure 11 and the second connecting structure 12 that realizes its electrical connection with the first test pad 301 and the second test pad 302 may include bonding points at other positions.

[0039] Based on this, the bonding points located in the central part of the stacked wafer can be electrically connected to the first test pad 301 and the second test pad 302 respectively through the first connection structure 11 and the second connection structure 12. Therefore, during electrical testing, the test probes can be directly electrically connected to the first test pad 301 and the second test pad 302 respectively, enabling electrical testing of the bonding effect in the central part of the stacked wafer without damaging the stacked wafer, which is beneficial for the electrical testing process. Furthermore, it facilitates real-time monitoring of the bonding process in the central part, allowing for timely remediation in case of problems, thus improving production line reliability.

[0040] Exemplary, in some embodiments, such as Figure 2 As shown, the first connection structure 11 includes a first conductive layer 401 located within the first wafer 101. One end of the first conductive layer 401 is electrically connected to the first test pad 301, and the other end is electrically connected to the first bonding structure 201. The second connection structure 12 includes a second conductive layer 402 located within the first wafer 101. One end of the second conductive layer 402 is electrically connected to the second bonding structure 202 via the first bonding structure 201, and the other end is electrically connected to the second test pad 302.

[0041] It is important to note that Figure 2 The first conductive layer 401 and the second conductive layer 402 shown are only for functional illustration, that is, they are used to realize the electrical connection between the first bonding structure 201 and the first test pad 301 and the second test pad 302 respectively, and are not used to limit their relative positions or shapes, and the same applies to the following text.

[0042] In this embodiment, both the first connection structure 11 and the second connection structure 12 are located within the first wafer 101, and the first conductive layer 401 and the second conductive layer 402 can be disposed on the same layer. For example, by designing the corresponding structure on the photomask in the early stage, the first bonding structures 201 at different positions within the first wafer 101 are fully connected, and any first bonding structure 201 is electrically connected to the first test pad 301 and the second test pad 302 respectively. During the electrical testing using the first test pad 301 and the second test pad 302, real-time monitoring of the bonding process between the first bonding structure 201 and the second bonding structure 202 at any position can be achieved. Problems can be remedied in a timely manner, which is beneficial to improving the reliability of the production line.

[0043] Alternatively, in some embodiments, such as Figure 4 As shown, Figure 4 This is a schematic diagram of a second type of stacked wafer structure provided in an embodiment of this application. The first connection structure 11 includes a third conductive layer 403 located within the first wafer 101. One end of the third conductive layer 403 is electrically connected to the first test pad 301, and the other end is electrically connected to the first bonding structure 201. The second connection structure 12 includes a fourth conductive layer 404 and the third bonding structure 203 within the first wafer 101, and a fifth conductive layer 405 and the fourth bonding structure 204 located within the second wafer 102. One end of the fifth conductive layer 405 is electrically connected to the second bonding structure 202, and the other end is electrically connected to the fourth bonding structure 204. The third bonding structure 203 and the fourth bonding structure 204 are connected in a dicing region N1 outside any chip region M1. One end of the fourth conductive layer 404 is electrically connected to the third bonding structure 203, and the other end is electrically connected to the second test pad 302.

[0044] In this embodiment, the third bonding structure 203 can be the first bonding structure 201 at another location, and the fourth bonding structure 204 can be the second bonding structure 202 at another location. A portion of the second connection structure 12 is located within the first wafer 101, and another portion is located within the second wafer 102. After the first wafer 101 and the second wafer 102 are bonded, it is ensured that any bonding point can be electrically connected to the first test pad 301 and the second test pad 302 through the first connection structure 11 and the second connection structure 12 respectively, so as to perform timely electrical testing on the bonding between the first bonding structure 201 and the second bonding structure 202 at any location.

[0045] Combination Figure 2 It is understood that the third conductive layer 403 and the fourth conductive layer 404 can be disposed in the same layer as the first conductive layer 401 and the second conductive layer 402 and interconnected with each other. For example, in some embodiments, the third conductive layer 403 is the first conductive layer 401, and the fourth conductive layer 404 is a part of the second conductive layer 402.

[0046] Alternatively, in some embodiments, such as Figure 5 As shown, Figure 5 This is a schematic diagram of the structure of a third type of stacked wafer provided in an embodiment of this application. The first connection structure 11 includes a sixth conductive layer 406 and a fifth bonding structure 205 located in the first wafer 101, and a seventh conductive layer 407 and a sixth bonding structure 206 located in the second wafer 102. One end of the sixth conductive layer 406 is electrically connected to the first test pad 301, and the other end is electrically connected to the fifth bonding structure 205. The fifth bonding structure 205 and the sixth bonding structure 206 are connected in the dicing area N1 outside any chip area M1. One end of the seventh conductive layer 407 is electrically connected to the sixth bonding structure 206, and the other end is electrically connected to the first bonding structure 201 through the second bonding structure 202. The second connection structure 12 includes an eighth conductive layer 408 and a seventh bonding structure 207 located in the first wafer 101, and a ninth conductive layer 409 and an eighth bonding structure 208 located in the second wafer 102. One end of the ninth conductive layer 409 is electrically connected to the second bonding structure 202, and the other end is electrically connected to the eighth bonding structure 208. The seventh bonding structure 207 and the eighth bonding structure 208 are connected in the dicing region N1 outside any chip region M1. One end of the eighth conductive layer 408 is electrically connected to the seventh bonding structure 207, and the other end is electrically connected to the second test pad 302.

[0047] In this embodiment, the fifth bonding structure 205 and the seventh bonding structure 207 can be the first bonding structure 201 at another location, and the sixth bonding structure 206 and the eighth bonding structure 208 can be the second bonding structure 202 at another location. A portion of the first connection structure 11 is located within the first wafer 101, and another portion is located within the second wafer 102. A portion of the second connection structure 12 is located within the first wafer 101, and another portion is located within the second wafer 102. After the first wafer 101 and the second wafer 102 are bonded, it is ensured that any bonding point can be electrically connected to the first test pad 301 and the second test pad 302 through the first connection structure 11 and the second connection structure 12 respectively, so as to perform timely electrical testing on the bonding between the first bonding structure 201 and the second bonding structure 202 at any location.

[0048] Combination Figure 4It is understandable that the sixth conductive layer 406 and the eighth conductive layer 408 can be disposed in the same layer as the third conductive layer 403 and the fourth conductive layer 404 and interconnected with each other, and the seventh conductive layer 407 and the ninth conductive layer 409 can be disposed in the same layer as the fifth conductive layer 405 and interconnected with each other. Combined with... Figure 2 , Figure 4 and Figure 5 It is understood that the conductive layers located within the first wafer 101 can be disposed in the same layer, and the conductive layers located within the second wafer 102 can be disposed in the same layer. Furthermore, the first connection structure 11 and the second connection structure 12 in different embodiments can be arranged and combined in various ways, for example, as shown in... Figure 5 As shown, the first wafer 101 also includes a first conductive layer 401 and a second conductive layer 402. The first conductive layer 401, the second conductive layer 402, the sixth conductive layer 406 and the eighth conductive layer 408 are disposed on the same layer and interconnected with each other. Any bonding point can be electrically connected to the first test pad 301 and the second test pad 302 through multiple conductive channels, so as to perform electrical testing on the bonding between the first bonding structure 201 and the second bonding structure 202 at any position in a timely manner.

[0049] In some embodiments, such as Figure 6 As shown, Figure 6 This is a schematic diagram of the structure of a fourth type of stacked wafer provided in an embodiment of this application. The stacked wafer also includes a third wafer 103, which is located on the side of the second wafer 102 away from the first wafer 101. The second wafer 102 also includes a third surface P3 connected to the third wafer 103. The third wafer 103 also includes a fourth surface P4 connected to the second wafer 102. The third surface P3 includes a second bonding region Q2 and a second edge region C2 surrounding the outside of the second bonding region Q2. The orthographic projection of the fourth surface P4 on the third surface P3 is located within the second bonding region Q2. The second wafer 102 further includes at least one ninth bonding structure 209, and the third wafer 103 further includes at least one tenth bonding structure 210. The ninth bonding structure 209 and the tenth bonding structure 210 are connected in the dicing region N1 outside any chip region M1. The second wafer 102 also includes a third test pad 303 and a fourth test pad 304, both of which are disposed in the second edge region C2. The third test pad 303 is electrically connected to the ninth bonding structure 209, and the fourth test pad 304 is electrically connected to the tenth bonding structure 210.

[0050] Similar to the bonding between the first wafer 101 and the second wafer 102, the third wafer 103 is trimmed before bonding the stacked wafers. A trimming tool is used to smooth the edge region of the fourth surface P4 of the third wafer 103, ensuring that after bonding with the second wafer 102, the edge of the third wafer 103 will not break or peel due to lack of support. This improves the bonding effect and ensures the bonding strength of the stacked wafers. Simultaneously, the trimming process makes the area of ​​the fourth surface P4 of the third wafer 103 smaller than the area of ​​the third surface P3 of the first wafer 101. After bonding with the second wafer 102, the third wafer 103 will expose a second edge region C2 on the third surface P3 of the second wafer 102.

[0051] For ease of explanation, in the following description, the pair of connected ninth bonding structures 209 and tenth bonding structures 210 can be regarded as a bonding point at the bonding interface between the second wafer 102 and the third wafer 103. By performing electrical tests on bonding points at different locations, it is possible to test whether the bonding process between the second wafer 102 and the third wafer 103 meets the design requirements.

[0052] Both the third test pad 303 and the fourth test pad 304 are exposed in the second edge region C2. During the electrical test, the test probe can be directly electrically connected to the third test pad 303 and the fourth test pad 304 respectively without damaging the stacked wafer, which is beneficial to the electrical test process.

[0053] Based on this, the stacked wafers provided in this application embodiment facilitate electrical testing of each bonding interface during the wafer bonding process. For example, if the bonding accuracy test passes, annealing is performed first, followed by electrical testing. This electrical testing targets both the bonding process between the first wafer 101 and the second wafer 102, and the bonding process between the second wafer 102 and the third wafer 103. If the electrical test fails, remedial measures such as continued annealing can be taken to repair the electrical interconnections between the wafers until the electrical test passes, after which subsequent wafer thinning, via etching, and other processes can be performed. In other words, the stacked wafers provided in this application embodiment facilitate electrical testing, enabling electrical interconnection testing during the process, thereby achieving real-time monitoring of the bonding process. Problems can be promptly rectified, improving production line reliability.

[0054] In some embodiments, such as Figure 6 As shown, the stacked wafer also includes a third connection structure 13 and a fourth connection structure 14 disposed in the dicing region N1. The third test pad 303 is electrically connected to the ninth bonding structure 209 through the third connection structure 13, and the fourth test pad 304 is electrically connected to the tenth bonding structure 210 through the fourth connection structure 14.

[0055] and Figure 2 Similarly, bonding points located at any position on the stacked wafer can be electrically connected to the third test pad 303 and the fourth test pad 304 respectively via the third connection structure 13 and the fourth connection structure 14. This allows the test probes to be directly electrically connected to the third test pad 303 and the fourth test pad 304 during electrical testing, enabling electrical testing of the bonding effect in the central portion of the stacked wafer without damaging the wafer, thus facilitating the electrical testing process. Furthermore, it allows for real-time monitoring of the bonding process in the central portion, enabling timely remediation of problems and improving production line reliability.

[0056] Exemplary, in some embodiments, such as Figure 6 As shown, the third connection structure 13 includes a tenth conductive layer 410 located within the second wafer 102. One end of the tenth conductive layer 410 is electrically connected to the third test pad 303, and the other end is electrically connected to the ninth bonding structure 209. The fourth connection structure 14 includes an eleventh conductive layer 411 located within the second wafer 102. One end of the eleventh conductive layer 411 is electrically connected to the tenth bonding structure 210 via the ninth bonding structure 209, and the other end is electrically connected to the fourth test pad 304.

[0057] In this embodiment, both the third connection structure 13 and the fourth connection structure 14 are located within the second wafer 102, and the tenth conductive layer 410 and the eleventh conductive layer 411 can be disposed on the same layer. For example, by designing the corresponding structure on the photomask in the early stage, the ninth bonding structure 209 at different positions within the second wafer 102 is fully connected and electrically connected to the third test pad 303 and the fourth test pad 304 respectively. During the electrical testing using the third test pad 303 and the fourth test pad 304, real-time monitoring of the bonding process between the ninth bonding structure 209 and the tenth bonding structure 210 at any position can be achieved. Problems can be remedied in a timely manner, which is beneficial to improving the reliability of the production line.

[0058] Alternatively, in some embodiments, such as Figure 7 As shown, Figure 7This is a schematic diagram of the fifth type of stacked wafer structure provided in this application embodiment. The third connection structure 13 includes a twelfth conductive layer 412 located within the second wafer 102. One end of the twelfth conductive layer 412 is electrically connected to the third test pad 303, and the other end is electrically connected to the ninth bonding structure 209. The fourth connection structure 14 includes a thirteenth conductive layer 413 and an eleventh bonding structure 211 within the second wafer 102, and a fourteenth conductive layer 414 and a twelfth bonding structure 212 located within the third wafer 103. One end of the fourteenth conductive layer 414 is electrically connected to the tenth bonding structure 210, and the other end is electrically connected to the twelfth bonding structure 212. The eleventh bonding structure 211 and the twelfth bonding structure 212 are connected in a dicing region N1 outside any chip region M1. One end of the thirteenth conductive layer 413 is electrically connected to the eleventh bonding structure 211, and the other end is electrically connected to the fourth test pad 304.

[0059] In this embodiment, the eleventh bonding structure 211 can be the ninth bonding structure 209 at another location, and the twelfth bonding structure 212 can be the tenth bonding structure 210 at another location. A portion of the fourth connection structure 14 is located within the second wafer 102, and another portion is located within the third wafer 103. After the second wafer 102 and the third wafer 103 are bonded, it is ensured that any bonding point can be electrically connected to the third test pad 303 and the fourth test pad 304 through the third connection structure 13 and the fourth connection structure 14, respectively, so as to promptly perform electrical testing on the bonding between the ninth bonding structure 209 and the tenth bonding structure 210 at any location.

[0060] Combination Figure 6 It is understood that the twelfth conductive layer 412 and the thirteenth conductive layer 413 can be disposed in the same layer as the tenth conductive layer 410 and the eleventh conductive layer 411 and interconnected with each other. For example, in some embodiments, the twelfth conductive layer 412 is the tenth conductive layer 410, and the thirteenth conductive layer 413 is a part of the eleventh conductive layer 411.

[0061] Alternatively, in some embodiments, such as Figure 8 As shown, Figure 8This is a schematic diagram of the sixth type of stacked wafer structure provided in the embodiments of this application. The third connection structure 13 includes a fifteenth conductive layer 415 and a thirteenth bonding structure 213 located in the second wafer 102, and a sixteenth conductive layer 416 and a fourteenth bonding structure 214 located in the third wafer 103. One end of the fifteenth conductive layer 415 is electrically connected to the third test pad 303, and the other end is electrically connected to the thirteenth bonding structure 213. The thirteenth bonding structure 213 and the fourteenth bonding structure 214 are connected in the dicing region N1 outside any chip region M1. One end of the sixteenth conductive layer 416 is electrically connected to the fourteenth bonding structure 214, and the other end is electrically connected to the ninth bonding structure 209 through the tenth bonding structure 210. The fourth connection structure 14 includes a seventeenth conductive layer 417 and a fifteenth bonding structure 215 located in the second wafer 102, and an eighteenth conductive layer 418 and a sixteenth bonding structure 216 located in the third wafer 103. One end of the eighteenth conductive layer 418 is electrically connected to the tenth bonding structure 210, and the other end is electrically connected to the sixteenth bonding structure 216. The fifteenth bonding structure 215 and the sixteenth bonding structure 216 are connected in the dicing region N1 outside any chip region M1. One end of the seventeenth conductive layer 417 is electrically connected to the fifteenth bonding structure 215, and the other end is electrically connected to the fourth test pad 304.

[0062] In this embodiment, the thirteenth bonding structure 213 and the fifteenth bonding structure 215 can be the ninth bonding structure 209 at another location, and the fourteenth bonding structure 214 and the sixteenth bonding structure 216 can be the tenth bonding structure 210 at another location. A portion of the third connection structure 13 is located within the second wafer 102, and another portion is located within the third wafer 103. A portion of the fourth connection structure 14 is located within the second wafer 102, and another portion is located within the third wafer 103. After the second wafer 102 and the third wafer 103 are bonded, it is ensured that any bonding point can be electrically connected to the third test pad 303 and the fourth test pad 304 through the third connection structure 13 and the fourth connection structure 14, respectively, so as to promptly perform electrical testing on the bonding between the ninth bonding structure 209 and the tenth bonding structure 210 at any location.

[0063] Combination Figure 7 It is understandable that the fifteenth conductive layer 415 and the seventeenth conductive layer 417 can be disposed on the same layer as the twelfth conductive layer 412 and the thirteenth conductive layer 413 and interconnected with each other, and the sixteenth conductive layer 416 and the eighteenth conductive layer 418 can be disposed on the same layer as the fourteenth conductive layer 414 and interconnected with each other. Figures 6-8It is understood that the conductive layers located within the second wafer 102 can be disposed in the same layer, and the conductive layers located within the third wafer 103 can be disposed in the same layer. Furthermore, the first connection structure 11 and the fourth connection structure 14 in different embodiments can be arranged and combined in various ways, for example, as shown in... Figure 5 As shown, the second wafer 102 also includes a tenth conductive layer 410 and an eleventh conductive layer 411. The tenth conductive layer 410, the eleventh conductive layer 411, the fifteenth conductive layer 415 and the seventeenth conductive layer 417 are disposed in the same layer and interconnected with each other. Any bonding point can be electrically connected to the third test pad 303 and the fourth test pad 304 through multiple conductive channels, so as to perform electrical testing on the bonding between the ninth bonding structure 209 and the tenth bonding structure 210 at any position in a timely manner.

[0064] In some embodiments, the third test pad 303 and the fourth test pad 304 may not be provided on the second wafer 102. Bonding points at any location can be electrically connected to the first test pad 301 and the second test pad 302. For example, the ninth bonding structure is connected to the second bonding structure 202. Under the conductive effect of the first bonding structure 201, the first conductive layer 401, and the second conductive layer 402, the first test pad 301 and the second test pad 302 can be used to perform electrical testing on the bond between any ninth bonding structure 209 and the tenth bonding structure 210. In other embodiments, the second bonding structure 202 and the ninth bonding structure 209 may or may not be connected within the second wafer 102, depending on the specific design requirements.

[0065] Similarly, the above scheme can also be used for the stacking structure of chips and wafers, as well as the stacking structure of chips and wafers, to enable timely electrical testing of the bonding process and facilitate electrical testing of the bonding process in the central part of the stacked structure. These will not be listed here.

[0066] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. In addition, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0067] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present invention.

Claims

1. A stacked wafer, characterized in that, The device includes a first wafer and a second wafer stacked together. The first wafer includes a first surface connected to the second wafer, and the second wafer includes a second surface connected to the first wafer. The first surface includes a first bonding region and a first edge region surrounding the outside of the first bonding region. The orthographic projection of the second surface onto the first surface is located within the first bonding region. Along a direction parallel to the first surface, the stacked wafer includes a plurality of chip regions arranged in an array, and dicing regions surrounding the outer side of the chip regions; the first wafer also includes at least one first bonding structure, and the second wafer also includes at least one second bonding structure, wherein the first bonding structure and the second bonding structure are connected to the dicing region outside any one of the chip regions. The first wafer further includes a first test pad and a second test pad, both disposed in the first edge region; the first test pad is electrically connected to the first bonding structure, and the second test pad is electrically connected to the second bonding structure.

2. The stacked wafer according to claim 1, characterized in that, The stacked wafer further includes a first connection structure and a second connection structure disposed in the dicing area. The first test pad is electrically connected to the first bonding structure through the first connection structure, and the second test pad is electrically connected to the second bonding structure through the second connection structure.

3. The stacked wafer according to claim 2, characterized in that, The first connection structure includes a first conductive layer located within the first wafer, one end of the first conductive layer being electrically connected to the first test pad, and the other end being electrically connected to the first bonding structure; The second connection structure includes a second conductive layer located within the first wafer. One end of the second conductive layer is electrically connected to the second bonding structure through the first bonding structure, and the other end is electrically connected to the second test pad.

4. The stacked wafer according to claim 2, characterized in that, The first connection structure includes a third conductive layer located within the first wafer, one end of which is electrically connected to the first test pad and the other end of which is electrically connected to the first bonding structure. The second connection structure includes a fourth conductive layer and a third bonding structure within the first wafer, and a fifth conductive layer and a fourth bonding structure within the second wafer; one end of the fifth conductive layer is electrically connected to the second bonding structure, and the other end is electrically connected to the fourth bonding structure; the third bonding structure and the fourth bonding structure are connected to a dicing area outside any chip region; one end of the fourth conductive layer is electrically connected to the third bonding structure, and the other end is electrically connected to the second test pad.

5. The stacked wafer according to claim 2, characterized in that, The first connection structure includes a sixth conductive layer and a fifth bonding structure located within the first wafer, and a seventh conductive layer and a sixth bonding structure located within the second wafer; one end of the sixth conductive layer is electrically connected to the first test pad, and the other end is electrically connected to the fifth bonding structure; the fifth bonding structure and the sixth bonding structure are connected in a dicing region outside any chip region; one end of the seventh conductive layer is electrically connected to the sixth bonding structure, and the other end is electrically connected to the first bonding structure through the second bonding structure; The second connection structure includes an eighth conductive layer and a seventh bonding structure located within the first wafer, and a ninth conductive layer and an eighth bonding structure located within the second wafer; one end of the ninth conductive layer is electrically connected to the second bonding structure, and the other end is electrically connected to the eighth bonding structure; the seventh bonding structure and the eighth bonding structure are connected to a dicing area outside any chip region; one end of the eighth conductive layer is electrically connected to the seventh bonding structure, and the other end is electrically connected to the second test pad.

6. The stacked wafer according to claim 1, characterized in that, It also includes a third wafer, which is located on the side of the second wafer that is away from the first wafer; The second wafer also includes a third surface connected to the third wafer, and the third wafer also includes a fourth surface connected to the second wafer. The third surface includes a second bonding region and a second edge region surrounding the outside of the second bonding region. The orthographic projection of the fourth surface onto the third surface is located within the second bonding region. The second wafer further includes at least one ninth bonding structure, and the third wafer further includes at least one tenth bonding structure, wherein the ninth bonding structure and the tenth bonding structure are connected in a dicing region outside any chip region. The second wafer also includes a third test pad and a fourth test pad, both disposed in the second edge region; the third test pad is electrically connected to the ninth bonding structure, and the fourth test pad is electrically connected to the tenth bonding structure.

7. The stacked wafer according to claim 6, characterized in that, The stacked wafer further includes a third connection structure and a fourth connection structure disposed in the dicing area. The third test pad is electrically connected to the ninth bonding structure through the third connection structure, and the fourth test pad is electrically connected to the tenth bonding structure through the fourth connection structure.

8. The stacked wafer according to claim 7, characterized in that, The third connection structure includes a tenth conductive layer located within the second wafer, one end of which is electrically connected to the third test pad and the other end of which is electrically connected to the ninth bonding structure. The fourth connection structure includes an eleventh conductive layer located within the second wafer. One end of the eleventh conductive layer is electrically connected to the tenth bonding structure through the ninth bonding structure, and the other end is electrically connected to the fourth test pad.

9. The stacked wafer according to claim 7, characterized in that, The third connection structure includes a twelfth conductive layer located within the second wafer, one end of which is electrically connected to the third test pad and the other end of which is electrically connected to the ninth bonding structure. The fourth connection structure includes a thirteenth conductive layer and an eleventh bonding structure within the second wafer, and a fourteenth conductive layer and a twelfth bonding structure within the third wafer; one end of the fourteenth conductive layer is electrically connected to the tenth bonding structure, and the other end is electrically connected to the twelfth bonding structure; the eleventh bonding structure and the twelfth bonding structure are connected in a dicing region outside any chip region; one end of the thirteenth conductive layer is electrically connected to the eleventh bonding structure, and the other end is electrically connected to the fourth test pad.

10. The stacked wafer according to claim 7, characterized in that, The third connection structure includes a fifteenth conductive layer and a thirteenth bonding structure located within the second wafer, and a sixteenth conductive layer and a fourteenth bonding structure located within the third wafer; one end of the fifteenth conductive layer is electrically connected to the third test pad, and the other end is electrically connected to the thirteenth bonding structure; the thirteenth bonding structure and the fourteenth bonding structure are connected in a dicing region outside any chip region; one end of the sixteenth conductive layer is electrically connected to the fourteenth bonding structure, and the other end is electrically connected to the ninth bonding structure through the tenth bonding structure; The fourth connection structure includes a seventeenth conductive layer and a fifteenth bonding structure located within the second wafer, and an eighteenth conductive layer and a sixteenth bonding structure located within the third wafer; one end of the eighteenth conductive layer is electrically connected to the tenth bonding structure, and the other end is electrically connected to the sixteenth bonding structure; the fifteenth bonding structure and the sixteenth bonding structure are connected in a dicing region outside any chip region; one end of the seventeenth conductive layer is electrically connected to the fifteenth bonding structure, and the other end is electrically connected to the fourth test pad.

Images