Method for manufacturing a semiconductor structure

Abstract

The present invention discloses a method for fabricating a semiconductor structure, belonging to the field of semiconductor technology. The method comprises: providing a substrate, sequentially forming a pad oxide layer and a pad nitride layer on the substrate; etching a portion of the pad oxide layer, the pad nitride layer, and the substrate to form a shallow trench; depositing an insulating dielectric in the shallow trench, performing a first planarization process on the insulating dielectric so that the insulating dielectric is flush with the pad nitride layers on both sides; micro-etching the pad nitride layer to form a microstructure layer, wherein the micro-etching adopts a weak physical sputtering method; oxidizing the pad nitride layer to form an intermediate oxide layer; removing an equal amount of the intermediate oxide layer and a portion of the insulating dielectric; repeating the micro-etching, oxidation, and equal amount removal steps until the pad nitride layer is removed; and removing the pad oxide layer and a portion of the insulating dielectric. The method for fabricating a semiconductor structure provided by the present invention can avoid the occurrence of concavities at the corner edges of a shallow trench isolation structure, thereby improving the performance of the semiconductor structure.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor technology, and in particular relates to a method for manufacturing a semiconductor structure. Background Art

[0002] Shallow trench isolation (STI) is a critical structure in integrated circuits. Installed between semiconductor devices, it prevents current leakage between adjacent semiconductor devices and reduces the area of the isolation region. During STI formation, after removing the pad nitride layer, the STI structure rises above the pad oxide layer. During this process, the raised STI structure is etched from multiple directions, which can easily cause excessive etching of the fill oxide layer at the corners of the STI-substrate interface, forming a divot. This divot phenomenon causes the polysilicon forming the gate to fill the divot area where the semiconductor device crosses the STI and active area, creating a parasitic device there. This can cause additional leakage during normal semiconductor device operation. It can also cause excessive electric field strength at the corners of the upper substrate layer, leading to leakage problems. Summary of the Invention

[0003] The object of the present invention is to provide a method for manufacturing a semiconductor structure. Through the method for manufacturing a semiconductor structure provided by the present invention, the corner edges of the shallow trench isolation structure are avoided from being recessed, leakage of the semiconductor structure can be avoided, the semiconductor structure has a good isolation effect, and the performance of the semiconductor structure is improved.

[0004] To solve the above technical problems, the present invention provides a method for manufacturing a semiconductor structure, which comprises at least the following steps:

[0005] providing a substrate, and sequentially forming a pad oxide layer and a pad nitride layer on the substrate;

[0006] etching a portion of the pad oxide layer, the pad nitride layer, and the substrate to form a shallow trench;

[0007] Depositing an insulating medium in the shallow trench and performing a first planarization process on the insulating medium so that the insulating medium is flush with the pad nitride layer on both sides;

[0008] Micro-etching the pad nitride layer to form a microstructure layer, wherein the micro-etching adopts a weak physical sputtering method;

[0009] Oxidizing the pad nitride layer to form an intermediate oxide layer;

[0010] Removing equal amounts of the intermediate oxide layer and a portion of the insulating medium;

[0011] Repeating the micro-etching process, the oxidation process, and the equal amount removal steps until the pad nitride layer is removed; and

[0012] The pad oxide layer and a portion of the insulating medium are removed.

[0013] In one embodiment of the present invention, the manufacturing method further includes:

[0014] placing the substrate after the first planarization process into a sputtering device; and

[0015] At the preset power and preset pressure, a mixed gas of hydrogen and inert gas is introduced for the preset time.

[0016] In one embodiment of the present invention, the preset power is 1000W-3000W, and the preset pressure is 0.1 Torr-10 Torr.

[0017] In one embodiment of the present invention, the total flow rate of the hydrogen gas and the inert gas is 300 sccm to 900 sccm, and the flow rate ratio of the hydrogen gas to the inert gas is 2:1 to 4:1.

[0018] In one embodiment of the present invention, the manufacturing method further includes:

[0019] placing the substrate on which the microstructure layer is formed into a plasma device; and

[0020] An oxygen-containing gas is introduced for oxidation treatment.

[0021] In one embodiment of the present invention, the operating power of the plasma equipment is 4000W-8000W, the pressure in the chamber is 0.1 Torr-10 Torr, and the processing time is 120s-150s.

[0022] In one embodiment of the present invention, the thickness of the intermediate oxide layer obtained by a single oxidation treatment is 90Å~110Å.

[0023] In one embodiment of the present invention, chemical mechanical polishing is used to remove equal amounts of the intermediate oxide layer and a portion of the insulating medium, and the polishing rate of the intermediate oxide layer is equal to the polishing rate of the insulating medium.

[0024] In one embodiment of the present invention, after the pad nitride layer is removed, the insulating medium is flush with the pad oxide layers on both sides.

[0025] In one embodiment of the present invention, after the pad oxide layer is removed, the insulating medium is flush with the substrates on both sides or the insulating medium is lower than the substrates on both sides, and the surface of the insulating medium is flush.

[0026] In summary, the present invention provides a method for manufacturing a semiconductor structure. By improving the method for manufacturing a semiconductor structure, the unexpected technical effect of the present application is that it can avoid the occurrence of depressions at the corner edges of the shallow trench isolation structure, can avoid leakage in the semiconductor structure, and the semiconductor structure has a good isolation effect, thereby improving the performance of the semiconductor structure. It can accelerate the oxidation rate of the pad nitride layer, accelerate the removal rate of the pad nitride layer, and improve the manufacturing efficiency. It can control the relative position between the shallow trench isolation structure and the substrate, and has high controllability. It can manufacture different shallow trench isolation structures according to the manufacturing requirements, meet the manufacturing requirements of different semiconductor devices, and improve the performance of semiconductor devices including semiconductor structures.

[0027] Of course, any product implementing the present invention does not necessarily need to achieve all of the advantages described above at the same time. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for describing the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0029] Figure 1 FIG. 1 is a schematic diagram of forming a pad oxide layer, a pad nitride layer, and a patterned photoresist layer on a substrate in one embodiment.

[0030] Figure 2 FIG. 4 is a schematic diagram of a shallow trench formed in one embodiment.

[0031] Figure 3 FIG. 1 is a schematic diagram of a deposited insulating medium in one embodiment.

[0032] Figure 4 Schematic diagram of the insulating medium after the first planarization process in one embodiment.

[0033] Figure 5 FIG. 1 is a schematic diagram of a microstructure layer formed in one embodiment.

[0034] Figure 6 FIG. 1 is a schematic diagram of an embodiment after forming an intermediate oxide layer.

[0035] Figure 7 Schematic diagram of planarization treatment of the intermediate oxide layer and the microstructure layer in one embodiment.

[0036] Figure 8 FIG. 1 is a schematic diagram of an embodiment after a microstructure layer is formed again.

[0037] Figure 9 FIG. 1 is a schematic diagram of an embodiment after the pad nitride layer is removed.

[0038] Figure 10 FIG. 1 is a schematic diagram of a semiconductor structure in one embodiment.

[0039] Description of labels:

[0040] 100, substrate; 110, pad oxide layer; 120, pad nitride layer; 130, patterned photoresist layer; 131, first opening; 140, shallow trench; 150, insulating medium; 160, microstructure layer; 170, intermediate oxide layer; 180, shallow trench isolation structure. DETAILED DESCRIPTION

[0041] The following describes the embodiments of the present invention through specific examples. Those skilled in the art will readily understand the other advantages and benefits of the present invention from the disclosure herein. The present invention may also be implemented or applied through various other specific embodiments, and the details in this specification may be modified or altered based on different viewpoints and applications without departing from the spirit of the present invention.

[0042] It should be noted that the illustrations provided in this embodiment are only used to schematically illustrate the basic concept of the present invention. Therefore, the illustrations only show components related to the present invention and are not drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component can be changed at will, and the component layout type may also be more complicated.

[0043] In the present invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer" and the like indicate positions or locations based on those shown in the accompanying drawings. These terms are intended solely to facilitate the description of the present application and simplify the description, and are not intended to indicate or imply that the devices or components referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limiting the present application. Furthermore, the terms "first" and "second" are used solely for descriptive and distinguishing purposes and should not be construed as indicating or implying relative importance.

[0044] See also Figure 1As shown, in one embodiment of the present invention, the substrate 100 provided by the present invention is any applicable semiconductor material, such as a substrate such as sapphire, silicon wafer, silicon carbide (SiC), gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), or silicon germanium (GeSi), and also includes a stacked structure composed of these semiconductor materials, or silicon-on-insulator, silicon-on-insulator, silicon-germanium-on-insulator, silicon-germanium-on-insulator, and germanium-on-insulator, etc. The specific material can be selected based on the manufacturing requirements of the semiconductor device. In this embodiment, substrate 100 is, for example, a silicon wafer semiconductor substrate, and substrate 100 can be an undoped substrate or a doped substrate, for example, an N-type substrate or a P-type substrate. The thickness of substrate 100 is not specifically limited and is selected based on the manufacturing requirements.

[0045] See also Figure 1 As shown, in one embodiment of the present invention, a pad oxide layer 110 is formed on a substrate 100. The pad oxide layer 110 is made of, for example, dense silicon oxide. The pad oxide layer 110 is prepared, for example, by thermal oxidation or in-situ steam generation (ISSG) to obtain dense silicon oxide. In this embodiment, the pad oxide layer 110 is prepared, for example, by the in-situ steam growth method. Specifically, the substrate 100 is placed in a furnace tube at a temperature of, for example, 900°C to 1150°C, and oxygen mixed with a small amount of hydrogen is introduced. The silicon on the surface of the substrate 100 reacts with the oxygen at high temperature to form a dense pad oxide layer 110. The quality of the generated pad oxide layer 110 is good. The thickness of the pad oxide layer 110 is, for example, 10nm to 40nm, specifically 10nm, 20nm, 30nm, or 40nm.

[0046] See also Figure 1As shown, in one embodiment of the present invention, after forming the pad oxide layer 110, a pad nitride layer 120 is formed on the pad oxide layer 110. The pad nitride layer 120 is, for example, silicon nitride or a stack of silicon nitride and silicon oxide. The pad oxide layer 110 acts as a buffer layer to improve the stress between the substrate 100 and the pad nitride layer 120. In this embodiment, the pad nitride layer 120 is, for example, silicon nitride. For example, the pad nitride layer 120 can be formed by a method such as low pressure chemical vapor deposition (LPCVD). Specifically, for example, the substrate 100 with the pad oxide layer 110 is placed in a furnace tube filled with dichlorosilane and ammonia, and the reaction is carried out at a pressure of, for example, 2 Torr to 10 Torr and a temperature of, for example, 700°C to 900°C to deposit the pad nitride layer 120. The thickness of the pad nitride layer 120 can be adjusted by controlling the heating time. In this embodiment, the thickness of the pad nitride layer 120 is, for example, 50 nm to 120 nm. By providing the pad nitride layer 120, the substrate 100 can be protected from the effects of planarization processes such as chemical mechanical polishing (CMP) involved in the fabrication of the shallow trench isolation structure. In addition, the pad nitride layer 120 can be used as a mask during the shallow trench formation process to protect other parts of the substrate 100 from damage when etching the substrate 100. Since the pad nitride layer 120 has high stress, the provided pad oxide layer 110 can be used to buffer the stress in the pad nitride layer 120 to prevent stress from causing defects in the substrate 100. At the same time, the pad oxide layer 110 also serves as a stop layer when etching and removing the pad nitride layer 120.

[0047] See also Figures 1 to 2 As shown, in one embodiment of the present invention, after forming the pad nitride layer 120, a photoresist layer is formed on the pad nitride layer 120. After exposure and development processes, a patterned photoresist layer 130 is formed. The patterned photoresist layer 130 includes a plurality of first openings 131. The first openings 131 expose portions of the pad nitride layer 120 to define the locations of shallow trenches. Using the patterned photoresist layer 130 as a mask, a dry etch process is performed toward the substrate 100 to form shallow trenches 140. The etching gas may include, for example, chlorine (Cl2), trifluoromethane (CHF3), difluoromethane (CH2F2), nitrogen trifluoride (NF3), sulfur hexafluoride (SF6), or hydrogen bromide (HBr), or a mixture thereof, or a mixture of these and oxygen (O2). In this embodiment, after forming the shallow trenches 140, the patterned photoresist layer 130 is removed by wet cleaning or ashing.

[0048] See also Figures 2 to 3As shown, in one embodiment of the present invention, after forming the shallow trench 140, an insulating dielectric 150 is deposited in the shallow trench 140 until the insulating dielectric 150 covers the surface of the pad nitride layer 120. Before depositing the insulating dielectric 150, the shallow trench 140 can be thermally oxidized to form an inner liner oxide layer (not shown in the figure) to round the bottom corners of the shallow trench 140, reduce tip leakage, and repair etching damage during the shallow trench formation process. The present invention does not limit the deposition method of the insulating dielectric 150. For example, the insulating dielectric 150 can be formed in the shallow trench 140 by deposition methods such as chemical vapor deposition (CVD) or high aspect ratio chemical vapor deposition (HARP-CVD). In this embodiment, the insulating dielectric 150 is obtained, for example, by depositing tetraethyl orthosilicate (TEOS). Specifically, tetraethyl orthosilicate and an oxygen-containing precursor, such as O2 or O3, are introduced at a temperature range of 300°C to 500°C and a pressure of 30 Torr to 700 Torr. The deposition time is controlled to obtain the insulating dielectric 150. Chemical vapor deposition allows for rapid deposition of the insulating dielectric 150 at low temperatures. The deposited silicon dioxide has excellent hole-filling capabilities and is less susceptible to voids, thereby improving the performance of subsequently formed shallow trench isolation structures.

[0049] See also Figures 3 and 4 As shown, in one embodiment of the present invention, after the insulating dielectric 150 is prepared, a first planarization process is performed on the insulating dielectric 150, for example, by using a process such as chemical mechanical polishing to planarize the insulating dielectric 150 until the insulating dielectric 150 on the pad nitride layer 120 is removed. During the first planarization process, the pad nitride layer 120 is used as a polishing stop layer. During the polishing process, when it is detected that the pad nitride layer 120 has been polished, the polishing is stopped. In this embodiment, after the first planarization process, the insulating dielectric 150 is, for example, flush with the pad nitride layer 120 on both sides.

[0050] See also Figures 4 and 5As shown, in one embodiment of the present invention, after planarizing the insulating dielectric 150, the pad nitride layer 120 is micro-etched, for example, to form a microstructure layer 160 to increase the specific surface area of the pad nitride layer 120. The thickness of the microstructure layer 160 is, for example, 5 Å to 20 Å. In this embodiment, the pad nitride layer 120 is micro-etched using, for example, weak physical sputtering. Specifically, the substrate 100, after the first planarization treatment of the insulating dielectric 150, is placed in a sputtering device, such as a magnetron sputtering device or an ion sputtering device. The sputtering device is controlled to have a preset power of, for example, 1000 W to 3000 W, a preset pressure in the chamber of, for example, 0.1 Torr to 10 Torr, and a mixture of hydrogen and inert gas is introduced. The treatment time is, for example, 5 s to 30 s. The inert gas is, for example, helium, and the total flow rate of the hydrogen and inert gas is, for example, 300 sccm to 900 sccm, with the flow ratio of hydrogen to inert gas being, for example, 2:1 to 4:1. By micro-etching the pad nitride layer 120, the surface of the pad nitride layer 120 can be roughened, and a plurality of fine recesses can be formed on the surface of the pad nitride layer 120, thereby increasing the specific surface area of the pad nitride layer 120. In the subsequent oxidation process, the oxidation amount of the pad nitride layer 120 can be increased, the removal rate of the pad nitride layer 120 can be accelerated, and the manufacturing efficiency can be improved.

[0051] See also Figures 5 and 6 As shown, in one embodiment of the present invention, after the microstructure layer 160 is formed, an oxidation treatment is performed to oxidize a portion of the pad nitride layer 120 to form an intermediate oxide layer 170. In this embodiment, the intermediate oxide layer 170 is formed, for example, by a high-density plasma oxidation method or the like. Specifically, the substrate 100 on which the microstructure layer 160 is formed is placed in a plasma device, such as a high-density plasma enhanced chemical vapor deposition device, the operating power of the plasma device being, for example, 4000W to 8000W, the pressure in the chamber being, for example, 0.1Torr to 10Torr, an oxygen-containing gas is introduced, and the processing time is, for example, 120s to 150s. The oxygen-containing gas, for example, includes at least one of oxygen or ozone, and the flow rate of the oxygen-containing gas is, for example, 5000sccm to 9000sccm. Due to the limitations of the oxidation process, the thickness of the intermediate oxide layer 170 obtained by a single oxidation is, for example, 90Å to 110Å. The intermediate oxide layer 170 is formed by oxidizing a portion of the pad nitride layer 120 , so that the polishing rate of the intermediate oxide layer 170 is close to the polishing rate of the insulating medium 150 , and can be removed synchronously.

[0052] See also Figures 6 and 7As shown, in one embodiment of the present invention, after the intermediate oxide layer 170 is formed, the intermediate oxide layer 170 and the insulating medium 150 are planarized, for example, by using a process such as chemical mechanical polishing to planarize the intermediate oxide layer 170 and the insulating medium 150 until the intermediate oxide layer 170 on the pad nitride layer 120 is removed. During the planarization process, for example, a cerium oxide-based polishing liquid is used for polishing, and the polishing rate of the intermediate oxide layer 170 is the same as the polishing rate of the insulating medium 150, for example, so that the intermediate oxide layer 170 and the insulating medium 150 can be removed synchronously in equal amounts. Therefore, during the polishing process, the pad nitride layer 120 is used as the polishing stop layer. During the polishing process, when it is detected that the pad nitride layer 120 is polished, the polishing is stopped. In this embodiment, after polishing, the insulating medium 150 is, for example, flush with the pad nitride layer 120 on both sides.

[0053] See also Figures 7 to 9 As shown, in one embodiment of the present invention, after removing the intermediate oxide layer 170 and part of the insulating medium 150, the micro-etching treatment, oxidation treatment and equal amount removal steps are repeated until the pad nitride layer 120 is completely removed. Among them, the methods and conditions for forming the microstructure layer, forming the intermediate oxide layer and removing the intermediate oxide layer and part of the insulating medium are consistent with the above, and the number of repetitions is set according to the thickness of the pad nitride layer 120 after the first planarization treatment of the insulating medium 150. In the present application, the insulating medium is made flush with the pad nitride layers on both sides through the first planarization treatment, and then the pad nitride layer and the insulating medium after treatment can be removed synchronously through multiple micro-etching, oxidation and planarization. After removing the pad nitride layer, the insulating medium is flush with the pad oxide layers on both sides, so that in the process of removing the pad oxide layer, the insulating medium 150 does not protrude from the pad oxide layer, thereby avoiding the occurrence of depressions at the edges of the substrate and the shallow trench isolation structure.

[0054] See also Figures 9 and 10As shown, in one embodiment of the present invention, after removing the pad nitride layer and a portion of the insulating dielectric 150, the pad oxide layer 110 is removed to form a shallow trench isolation structure 180. The pad oxide layer 110 is removed, for example, by wet etching, dry etching, or a combination of wet etching and dry etching. When dry etching is used, the etching gas includes, for example, one or a mixture of trifluoromethane, difluoromethane, or sulfur hexafluoride, or a mixture of these and oxygen. When wet etching is used, the wet etching solution is, for example, dilute hydrofluoric acid or buffered oxide etchant (BOE). Dilute hydrofluoric acid is, for example, a mixture of 49 wt% hydrofluoric acid solution and deionized water in a volume ratio of 1:20-50, to etch the pad oxide layer 110. At the same time, the etching rate of the insulating dielectric 150 is controlled to prevent problems such as over-etching of the insulating dielectric 150 due to excessive etching rate. In this embodiment, wet etching is used, for example, for etching. When etching the pad oxide layer 110, since the insulating dielectric 150 is made of the same material as the pad oxide layer 110, the pad oxide layer 110 and the insulating dielectric 150 are etched simultaneously. Before etching, the pad oxide layer 110 and the insulating dielectric 150 have flush surfaces, and no edges have a large contact angle with the etchant. Therefore, the pad oxide layer 110 and the insulating dielectric 150 have the same contact angle with the etchant, both 180°. Therefore, during the etching process, the insulating dielectric 150 is removed uniformly, and no recess is formed at the interface between the substrate 100 and the shallow trench isolation structure 180. The top of the shallow trench isolation structure 180 is flush. In this embodiment, the shallow trench isolation structure 180 is, for example, flush with the substrate 100. In other embodiments, by controlling the etching time, the shallow trench isolation structure 180 is, for example, lower than the surface of the substrate 100 and the surface of the shallow trench isolation structure 180 is flush. That is, in the present application, the height of the shallow trench isolation structure 180 can be controlled to be flush with or lower than the surface of the substrate 100 without forming a recess at the edge, thereby reducing leakage and meeting the manufacturing requirements of different semiconductor devices.

[0055] See also Figures 9 and 10As shown, in another embodiment of the present invention, for example, after removing the pad nitride layer, ions are implanted into the substrate 100 using the pad oxide layer 110 as an ion implantation buffer layer to form a well region or other structures, or after forming a gate structure on the pad oxide layer 110, the excess pad oxide layer 110 and a portion of the insulating dielectric 150 are removed. That is, in this application, the pad oxide layer 110 and a portion of the insulating dielectric 150 can be selectively removed in different steps based on the manufacturing requirements of the semiconductor device. When removing the pad oxide layer 110, the insulating dielectric 150 and the pad oxide layer 110 are flush. During the wet etching process, since the angle of contact between the insulating dielectric 150 and the etchant is equal to the angle of contact between the pad oxide layer 110 and the etchant, a shallow trench isolation structure 180 with a flat surface is formed. This can avoid the formation of concavities at the corner edges of the shallow trench isolation structure 180 due to differences in etching rates. When forming a gate on the substrate, the polysilicon constituting the gate can be prevented from filling the concavity, thus preventing leakage in the semiconductor structure and achieving good isolation effect. The morphology of the shallow trench isolation structure 180 can be ensured, and the performance of the semiconductor structure can be improved, thereby improving the performance of the semiconductor device including the semiconductor structure.

[0056] In summary, the present invention provides a method for manufacturing a semiconductor structure. By improving the method for manufacturing a semiconductor structure, the unexpected technical effect of the present application is that it can avoid the occurrence of depressions at the corner edges of the shallow trench isolation structure, can avoid leakage in the semiconductor structure, and the semiconductor structure has a good isolation effect, thereby improving the performance of the semiconductor structure. It can accelerate the oxidation rate of the pad nitride layer, accelerate the removal rate of the pad nitride layer, and improve the manufacturing efficiency. It can control the relative position between the shallow trench isolation structure and the substrate, and has high controllability. It can manufacture different shallow trench isolation structures according to the manufacturing requirements, meet the manufacturing requirements of different semiconductor devices, and improve the performance of semiconductor devices including semiconductor structures.

[0057] References throughout this specification to "one embodiment," "an embodiment," or "a specific embodiment" mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention, and not necessarily in all embodiments. Thus, various appearances of the phrases "in one embodiment," "in an embodiment," or "in a specific embodiment" in different places throughout this specification are not necessarily referring to the same embodiment. Furthermore, the particular features, structures, or characteristics of any specific embodiment of the invention may be combined with one or more other embodiments in any suitable manner. It should be understood that other variations and modifications of the embodiments of the invention described and illustrated herein are possible in light of the teachings herein and are considered part of the spirit and scope of the invention.

[0058] It should also be understood that the embodiments of the present invention disclosed above are intended only to illustrate the present invention. These embodiments do not exhaustively describe all details, nor do they limit the present invention to the specific embodiments described. Obviously, many modifications and variations are possible based on the content of this specification. These embodiments are selected and described in detail in this specification in order to better explain the principles and practical applications of the present invention, thereby enabling those skilled in the art to better understand and utilize the present invention. The present invention is limited only by the claims and their full scope and equivalents.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that: At least the following steps are included: providing a substrate, and sequentially forming a pad oxide layer and a pad nitride layer on the substrate; etching a portion of the pad oxide layer, the pad nitride layer, and the substrate to form a shallow trench; Depositing an insulating medium in the shallow trench and performing a first planarization process on the insulating medium so that the insulating medium is flush with the pad nitride layer on both sides; Micro-etching the pad nitride layer to form a microstructure layer, wherein the micro-etching adopts a weak physical sputtering method; Oxidizing the pad nitride layer to form an intermediate oxide layer; Removing equal amounts of the intermediate oxide layer and a portion of the insulating medium; Repeating the micro-etching process, the oxidation process, and the equal amount removal steps until the pad nitride layer is removed; as well as The pad oxide layer and a portion of the insulating medium are removed.

2. The method for manufacturing a semiconductor structure according to claim 1, wherein: The production method further comprises: placing the substrate after the first planarization process into a sputtering device; and At the preset power and preset pressure, a mixed gas of hydrogen and inert gas is introduced for the preset time.

3. The method for manufacturing a semiconductor structure according to claim 2, wherein: The preset power is 1000W~3000W, and the preset pressure is 0.1Torr~10Torr.

4. The method for manufacturing a semiconductor structure according to claim 2, wherein: The total flow rate of the hydrogen gas and the inert gas is 300 sccm to 900 sccm, and the flow rate ratio of the hydrogen gas to the inert gas is 2:1 to 4:

1.

5. The method for manufacturing a semiconductor structure according to claim 1, wherein: The production method further comprises: placing the substrate on which the microstructure layer is formed into a plasma device; and An oxygen-containing gas is introduced for oxidation treatment.

6. The method for manufacturing a semiconductor structure according to claim 5, wherein: The working power of the plasma equipment is 4000W~8000W, the pressure in the chamber is 0.1Torr~10Torr, and the processing time is 120s~150s.

7. The method for manufacturing a semiconductor structure according to claim 1, wherein: The thickness of the intermediate oxide layer obtained by a single oxidation treatment is 90Å~110Å.

8. The method for manufacturing a semiconductor structure according to claim 1, wherein: Chemical mechanical polishing is used to remove the intermediate oxide layer and part of the insulating medium in equal amounts, and the polishing rate of the intermediate oxide layer is equal to the polishing rate of the insulating medium.

9. The method for manufacturing a semiconductor structure according to claim 1, wherein: After the pad nitride layer is removed, the insulating medium is flush with the pad oxide layers on both sides.

10. The method for manufacturing a semiconductor structure according to claim 1, wherein: After the pad oxide layer is removed, the insulating medium is flush with the substrates on both sides or the insulating medium is lower than the substrates on both sides, and the surface of the insulating medium is flush.

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