Anti-interference semiconductor structure and its preparation method, electronic equipment

Abstract

This application relates to an anti-interference semiconductor structure and its fabrication method, as well as an electronic device. The anti-interference semiconductor structure includes a first electrode, a second electrode, and an electrode field plate structure extending along a first direction; the electrode field plate structure is located between the first electrode and the second electrode along a second direction; the first direction intersects the second direction; the electrode field plate structure includes a first field plate structure and a second field plate structure interconnected, the first field plate structure extending along a third direction, and the second field plate structure extending along a fourth direction; the third and fourth directions intersect at least the first direction; the first and second field plate structures jointly suppress the induced current generated by the anti-interference semiconductor structure under high-power microwave radiation. This application improves the stability of the semiconductor structure under HPM irradiation by canceling out the induced currents generated on the first and second field plate structures.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to an anti-interference semiconductor structure and its fabrication method, as well as electronic devices. Background Technology

[0002] Important power electronic systems in drones, such as power management modules and motor drive converters, are vulnerable to high-power microwave (HPM) pulse interference and damage, which can lead to power supply or power failure and crashes. Among these, power devices are the key core components of these power electronic systems.

[0003] The main form of HPM attacks is to transmit pulsed energy and couple it into the internal electronic system of the drone, such as the power electronic system, and then transfer the energy to the internal power semiconductor devices. Through electrical and thermal effects and their combination, these devices are subjected to instantaneous interference and power surges, which can lead to device degradation or even burnout. Summary of the Invention

[0004] Therefore, it is necessary to provide an anti-interference semiconductor structure, its fabrication method, and electronic devices that can resist current surges generated under HPM irradiation.

[0005] In a first aspect, this application provides an anti-interference semiconductor structure, comprising: a first electrode, a second electrode, and an electrode field plate structure extending along a first direction; wherein...

[0006] Along the second direction, the electrode field plate structure is located between the first electrode and the second electrode; the first direction intersects the second direction;

[0007] The electrode field plate structure includes a first field plate structure and a second field plate structure that are interconnected. The first field plate structure extends along a third direction, and the second field plate structure extends along a fourth direction. The third direction and the fourth direction intersect at least the first direction.

[0008] The first field plate structure and the second field plate structure are used together to suppress the induced current generated by the anti-interference semiconductor structure under high-power microwave radiation environment.

[0009] In one embodiment, the third direction and the fourth direction are different, and both the third direction and the fourth direction intersect the second direction; wherein, the end of the first field plate structure near the first target electrode is connected to the end of the second field plate structure near the first target electrode, and the first target electrode includes the first electrode or the second electrode.

[0010] In one embodiment, the electrode field plate structure includes a plurality of first field plate units arranged along the first direction, wherein the plurality of first field plate units respectively include the first field plate structure and the second field plate structure;

[0011] In any two adjacent first field plate units, the end of the second field plate structure of one first field plate unit near the second target electrode is connected to the end of the first field plate structure of the other first field plate unit near the second target electrode; wherein, one of the first target electrode and the second target electrode is the first electrode and the other is the second electrode.

[0012] In one embodiment, the third direction and the fourth direction are the same as or intersect with the second direction, respectively; wherein, the electrode field plate structure further includes a first connecting structure, wherein one end of the first field plate structure near the first target electrode and one end of the second field plate structure near the first target electrode are connected by the first connecting structure; the first target electrode includes the first electrode or the second electrode.

[0013] In one embodiment, the electrode field plate structure includes a second connection structure and a plurality of second field plate units arranged along the first direction, wherein the plurality of second field plate units include the first field plate structure and the second field plate structure;

[0014] Any two adjacent second field plate units are connected by the second connection structure, wherein in one second field plate unit, the end of the second field plate structure near the second target electrode is connected to one end of the second connection structure, and in another second field plate unit, the end of the first field plate structure near the second target electrode is connected to the other end of the second connection structure; wherein, one of the first target electrode and the second target electrode is the first electrode, and the other is the second electrode.

[0015] In one embodiment, the electrode field plate structure further includes a third field plate structure and a fourth field plate structure, both of which extend along the second direction. The end of the third field plate structure near the second electrode is connected to the end of the first field plate structure near the second electrode, and the end of the fourth field plate structure near the second electrode is connected to the end of the second field plate structure near the second electrode.

[0016] In one embodiment, the shape of the first field plate structure is either straight or curved, and the shape of the second field plate structure is either straight or curved.

[0017] In one embodiment, the anti-interference semiconductor structure further includes a third electrode;

[0018] In the second direction, the third electrode is located between the first electrode and the first field plate structure or the second field plate structure.

[0019] Secondly, this application also provides a method for fabricating a semiconductor structure, comprising:

[0020] Provide substrate;

[0021] A first electrode, a second electrode, and an electrode field plate structure extending along a first direction are formed on the substrate; wherein,

[0022] Along the second direction, the electrode field plate structure is located between the first electrode and the second electrode; the first direction intersects the second direction;

[0023] The electrode field plate structure includes a first field plate structure and a second field plate structure that are interconnected. The first field plate structure extends along a third direction, and the second field plate structure extends along a fourth direction. The third direction and the fourth direction intersect at least the first direction.

[0024] The first field plate structure and the second field plate structure are used together to suppress the induced current generated by the semiconductor structure under high-power microwave radiation.

[0025] Thirdly, this application also provides an electronic device, including the anti-interference semiconductor structure provided in any of the above embodiments, or prepared by the preparation method of the semiconductor structure provided in any of the above embodiments.

[0026] In the aforementioned anti-interference semiconductor structure, its fabrication method, and electronic device, the anti-interference semiconductor structure includes a first electrode, a second electrode, and an electrode field plate structure extending along a first direction; wherein, along a second direction, the electrode field plate structure is located between the first electrode and the second electrode; the first direction intersects the second direction; the electrode field plate structure includes a first field plate structure and a second field plate structure interconnected, the first field plate structure extending along a third direction, and the second field plate structure extending along a fourth direction; the third and fourth directions intersect at least the first direction; the first and second field plate structures jointly suppress the induced current generated by the semiconductor structure under high-power microwave radiation. The electrode field plate structure can improve the electric field distribution on the device surface and increase the device breakdown voltage. Furthermore, under high-power microwave radiation, the induced currents generated on the first and second field plate structures are in opposite directions and can cancel each other out, effectively suppressing the interference of HPM radiation on the device and improving the reliability of the semiconductor structure. Moreover, compared to a rectangular field plate structure covering the entire gate and source / drain surface, the field plate structure of this application has a smaller area, which can reduce the parasitic capacitance generated by introducing the field plate structure. Attached Figure Description

[0027] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0028] Figure 1 This is one of the top view schematic diagrams of the anti-interference semiconductor structure provided in one embodiment;

[0029] Figure 2 This is a second top view schematic diagram of the anti-interference semiconductor structure provided in one embodiment;

[0030] Figure 3 This is a third top view schematic diagram of the anti-interference semiconductor structure provided in one embodiment;

[0031] Figure 4 This is a top view of one embodiment of the anti-interference semiconductor structure.

[0032] Figure 5 This is a top view of the anti-interference semiconductor structure provided in one embodiment;

[0033] Figure 6 This is a top view of the anti-interference semiconductor structure provided in one embodiment, shown in diagram six.

[0034] Figure 7 This is a top view of the anti-interference semiconductor structure provided in one embodiment, shown as diagram seven.

[0035] Figure 8 This is the eighth top view schematic diagram of the anti-interference semiconductor structure provided in one embodiment;

[0036] Figure 9 This is a top view of the anti-interference semiconductor structure provided in one embodiment, shown as diagram nine.

[0037] Figure 10 This is a top view of one embodiment of the anti-interference semiconductor structure.

[0038] Figure 11 This is eleventh of the top view schematic diagrams of the anti-interference semiconductor structure provided in one embodiment;

[0039] Figure 12 This is a top view of the anti-interference semiconductor structure provided in one embodiment, shown as diagram 12.

[0040] Figure 13 This is a top view of the anti-interference semiconductor structure provided in one embodiment, shown as diagram number thirteen.

[0041] Figure 14 This is a top view of one embodiment of the anti-interference semiconductor structure, schematic diagram fourteen.

[0042] Figure 15 This is a top view of the anti-interference semiconductor structure provided in one embodiment, shown as diagram number fifteen.

[0043] Figure 16 This is a schematic flowchart of a method for fabricating a semiconductor structure provided in one embodiment;

[0044] Figure 17 This is a schematic diagram of the cross-sectional structure of a gallium nitride power device provided in one embodiment. Detailed Implementation

[0045] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0046] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0047] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various layers and electrodes, these layers and electrodes should not be limited by these terms. These terms are only used to distinguish one layer or electrode from another. Therefore, without departing from the teachings of this invention, the first layer or electrode discussed below may be referred to as the second layer or electrode; for example, the first electrode may be called the second electrode, and similarly, the second electrode may be called the first electrode; the first electrode and the second electrode are different electrodes, for example, the first electrode may be the source and the second electrode may be the drain, or the first electrode may be the drain and the second electrode may be the source.

[0048] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.

[0049] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, in this specification, the term “and / or” includes any and all combinations of the associated listed items.

[0050] In one embodiment, such as Figure 1As shown, this application provides an anti-interference semiconductor structure, including a first electrode 100, a second electrode 200, and an electrode field plate structure 300 extending along a first direction. Along a second direction, the electrode field plate structure 300 is located between the first electrode 100 and the second electrode 200. The first direction intersects the second direction. Exemplarily, the first direction can be... Figure 1 The vertical direction in the middle, the second direction can be Figure 1 In the horizontal direction, the first electrode 100 can be either the source or the drain, and the second electrode 200 can be either the source or the drain. The electrode field plate structure 300 can be either a source field plate or a drain field plate.

[0051] The electrode field plate structure 300 includes a first field plate structure 310 and a second field plate structure 320 that are interconnected. The first field plate structure 310 and the second field plate structure 320 can be directly connected or indirectly connected through other structures. The first field plate structure 310 extends along a third direction, and the second field plate structure 320 extends along a fourth direction. The third and fourth directions intersect at least with the first direction; that is, the third direction is parallel to or intersects with the fourth direction.

[0052] The first field plate structure 310 and the second field plate structure 320 work together to suppress the induced current generated in the anti-interference semiconductor structure under high-power microwave radiation. Under high-power microwave conditions, the induced current generated on the first field plate structure 310 flows from the first electrode 100 to the second electrode 200, or vice versa. Similarly, the induced current generated on the second field plate structure 320 flows from the first electrode 100 to the second electrode 200, or vice versa. Figure 1 As shown, the arrows indicate the direction of the induced current. The induced currents on the first field plate structure 310 and the second field plate structure 320 are out of phase and cancel each other out at the connection between the first field plate structure 310 and the second field plate structure 320.

[0053] In this embodiment, the anti-interference semiconductor structure includes a first electrode 100, a second electrode 200, and an electrode field plate structure 300 extending along a first direction. The electrode field plate structure 300 can improve the electric field distribution on the device surface and increase the device breakdown voltage. The electrode field plate structure 300 includes a first field plate structure 310 and a second field plate structure 320 connected to each other. The first field plate structure 310 extends along a third direction, and the second field plate structure 320 extends along a fourth direction. The first target electrode includes either the first electrode 100 or the second electrode 200. The third and fourth directions intersect at least with the first direction, that is, the third direction is parallel to or intersects with the fourth direction. Thus, under high-power microwave radiation, the induced currents generated on the first field plate structure 310 and the second field plate structure 320 are in opposite directions and can cancel each other out, effectively suppressing the interference of HPM radiation on the device and improving the reliability of the semiconductor structure. In addition, compared with a rectangular field plate structure covering the entire gate and source / drain surface, the field plate structure of this application has a smaller area, which can reduce the parasitic capacitance generated by introducing the field plate structure.

[0054] In one embodiment, the third direction and the fourth direction are different, and both the third direction and the fourth direction intersect with the second direction. The end of the first field plate structure 310 near the first target electrode is connected to the end of the second field plate structure 320 near the first target electrode. The first target electrode includes either a first electrode 100 or a second electrode 200.

[0055] Taking the first target electrode as the first electrode 100 as an example, such as Figure 1 or Figure 2 As shown, the first field plate structure 310 and the second field plate structure 320 are connected to each other at the ends near the first electrode 100. The electrode field plate structure formed by the first field plate structure 310 and the second field plate structure 320 can be triangular arc-shaped, such as... Figure 2 As shown, it can also be a triangle, such as... Figure 1 As shown.

[0056] In one embodiment, such as Figure 3 or Figure 4 As shown, the electrode field plate structure 300 includes a plurality of first field plate units arranged along a first direction. Figure 3 neutralization Figure 4 The area highlighted by the dashed line represents a first field plate unit. Multiple first field plate units each include a first field plate structure 310 and a second field plate structure 320. In any two adjacent first field plate units, the end of the second field plate structure 320 of one first field plate unit near the second target electrode is connected to the end of the first field plate structure 310 of the other first field plate unit near the second target electrode. The first target electrode and the second target electrode are, respectively, a first electrode 100 and a second electrode 200.

[0057] In one embodiment, the third direction and the fourth direction are the same as or intersect with the second direction, respectively; wherein, the electrode field plate structure 300 further includes a first connection structure 330, and the end of the first field plate structure 310 near the first target electrode is connected to the end of the second field plate structure 320 near the first target electrode through the first connection structure 330.

[0058] For example, such as Figure 5 and Figure 6 As shown, the third and fourth directions are the same as the second direction. The first connection structure 330 can be... Figure 5 The straight line structure shown can also be Figure 6 The triangular structure shown. The end of the first field plate structure 310 near the first target electrode is connected to the end of the second field plate structure 320 near the first target electrode via the first connection structure 330.

[0059] For example, such as Figure 7 As shown, the third and fourth directions intersect with the second direction respectively, and the end of the first field plate structure 310 near the first target electrode is connected to the end of the second field plate structure 320 near the first target electrode through the first connection structure 330.

[0060] In one embodiment, such as Figures 8-10 As shown, the electrode field plate structure 300 includes a second connection structure 340 and a plurality of second field plate units arranged along a first direction. The plurality of second field plate units include a first field plate structure 310 and a second field plate structure 320. Figures 8-10 In the diagram, the rectangular area represents a second field plate element, and the circular area represents a second connection structure 340. The shape of the second connection structure 340 can be linear or triangular.

[0061] Any two adjacent second field plate units are connected by a second connection structure 340. In one second field plate unit, the end of the second field plate structure 320 near the second target electrode is connected to one end of the second connection structure 340. In the other second field plate unit, the end of the first field plate structure 310 near the second target electrode is connected to the other end of the second connection structure. One of the first target electrode and the second target electrode is the first electrode 100, and the other is the second electrode 200.

[0062] In one embodiment, such as Figures 11-15As shown, the electrode field plate structure 300 also includes a third field plate structure 350 and a fourth field plate structure 360. Both the third and fourth field plate structures extend along a second direction. The end of the third field plate structure 350 near the second electrode 200 is connected to the end of a first field plate structure 310 near the second electrode 200, and the end of the fourth field plate structure 360 ​​near the second electrode 200 is connected to the end of a second field plate structure 320 near the second electrode 200. In this embodiment, under HPM irradiation, the induced currents generated on the third field plate structure 350 and the connected first field plate structure 310 are in opposite directions and can cancel each other out at the connection point; similarly, the induced currents generated on the fourth field plate structure 360 ​​and the connected second field plate structure 320 are in opposite directions and can also cancel each other out at the connection point. Furthermore, the third field plate structure 350 and the fourth field plate structure 360 ​​can be connected to the first target electrode or can be suspended in mid-air.

[0063] In one embodiment, the shape of the first field plate structure 310 is either a straight line or a curve, and the shape of the second field plate structure 320 is either a straight line or a curve.

[0064] In one embodiment, the semiconductor structure further includes an anti-interference third electrode. In a second direction, the third electrode is located between the first electrode 100 and either the first field plate structure 310 or the second field plate structure 320. The third electrode is a gate electrode.

[0065] In one embodiment, this application also provides a method for fabricating a semiconductor structure, such as... Figure 16 As shown, it includes steps S1602-S1604.

[0066] S1602 provides a substrate.

[0067] S1604, a first electrode, a second electrode, and an electrode field plate structure extending along a first direction are formed on the substrate.

[0068] Along the second direction, the electrode field plate structure is located between the first electrode and the second electrode; the first direction intersects the second direction. The electrode field plate structure includes a first field plate structure and a second field plate structure that are interconnected. The first field plate structure extends along a third direction, and the second field plate structure extends along a fourth direction. The third and fourth directions intersect at least the first direction. The first and second field plate structures work together to suppress the induced current generated by the semiconductor structure under high-power microwave radiation. A detailed description of this semiconductor structure can be found in the above embodiments regarding the limitations of the anti-interference semiconductor structure, and will not be repeated here.

[0069] The anti-interference semiconductor structure provided in this application can cover wide-bandgap semiconductor power devices such as gallium nitride and silicon carbide, as well as silicon-based power devices. For example, taking gallium nitride power devices as an example, such as... Figure 17As shown, the gallium nitride power device includes a substrate 400, a channel layer 500, a barrier layer 600, a first electrode 100, a second electrode 200, a third electrode 1000, a first passivation layer 700, a second passivation layer 800, a third passivation layer 900, and an electrode field plate structure 300. The first electrode 100 is the source electrode, the second electrode 200 is the drain electrode, and the third electrode 1000 is the gate electrode. The third electrode 1000 includes a P-GaN layer 1010 and a gate metal layer 1020. The electrode field plate structure 300 is the source field plate. In this configuration, a channel layer 500 is located between the substrate 400 and the barrier layer 600. A P-GaN layer 1010 is located on the side of the barrier layer 600 away from the channel layer 500. A gate metal layer 1020 is located on the side of the P-GaN layer 1010 away from the barrier layer 600. A first passivation layer 700 is located on the side of the barrier layer 600 away from the channel layer 500 and on the sidewall of the gate. The source and drain are located on the side of the first passivation layer 700 away from the barrier layer 600, respectively, and penetrate the first passivation layer 700, contacting the barrier layer 600. In the second direction, the gate is disposed between the source and the drain. A second passivation layer 800 is located on the side of the source, drain, and gate away from the first passivation layer 700, and on the exposed surface of the first passivation layer 700. A source field plate is located on the side of the second passivation layer 800 away from the first passivation layer 700, and one end of the source field plate is connected to the source. The third passivation layer is located on the side of the source electrode plate away from the second passivation layer.

[0070] The substrate material can be any suitable substrate material known in the art, such as silicon or silicon carbide. The channel layer is made of GaN, and the barrier layer is made of AlGaN. The channel layer and the barrier layer can form a heterojunction. The structure of the source field plate on the side of the second passivation layer 800 away from the first passivation layer 700 can be referred to the definition of the electrode field plate structure 300 in the above embodiments.

[0071] Since the induced currents generated by adjacent first field plate structures 310 and second field plate structures 320 in the source field plate are in opposite directions under HPM irradiation, they can cancel each other out, thereby improving the survivability and reliability of gallium nitride power devices in strong electromagnetic environments. Furthermore, the source field plate extends from near the drain terminal to the gate terminal and forms a spaced, non-closed structure near the drain terminal, which effectively modulates the electric field while further reducing parasitic capacitance, thereby effectively improving the device's breakdown voltage and fast turn-off speed, and enhancing the efficiency of the power electronic system.

[0072] Furthermore, the fabrication method of this gallium nitride power device may include the following steps:

[0073] S1 provides a substrate.

[0074] S2, a channel layer is grown on the substrate. The channel layer can be made of GaN.

[0075] S3, a barrier layer is grown on the side of the channel layer away from the substrate. The material of the barrier layer can be AlGaN.

[0076] S4, a p-GaN layer is grown on the side of the barrier layer away from the channel layer.

[0077] S5, a first passivation layer is grown on the side of the barrier layer away from the channel layer and on the side of the p-GaN layer away from the barrier layer.

[0078] S6, etch the first passivation layer to form the first opening, the second opening and the third opening.

[0079] S7, a source is formed in the first opening, a gate metal layer is formed in the second opening, and a drain is formed in the third opening.

[0080] S8, a second passivation layer is grown on the source, drain, and gate sides away from the barrier layer, as well as on the exposed surface of the first passivation layer.

[0081] S9, etching the second passivation layer to form the fourth and fifth openings.

[0082] S10, a source field plate is formed within the fourth opening and on the side of the second passivation layer away from the first passivation layer. The source field plate formed on the side of the second passivation layer away from the first passivation layer can refer to the electrode field plate structure provided in any of the above embodiments.

[0083] S11 forms a drain connection within the fifth opening.

[0084] S12, a third passivation layer is formed on the side of the source field plate away from the second passivation layer and on the exposed surface of the second passivation layer.

[0085] In one embodiment, this application also provides an electronic device, which can be prepared by the method for preparing the semiconductor structure provided in any of the above embodiments, or can include the anti-interference semiconductor structure provided in any of the above embodiments.

[0086] It should be understood that, unless otherwise expressly stated herein, there is no strict order in which the above steps are performed, and these steps may be performed in other orders. Moreover, at least some of the above steps may include multiple steps or multiple stages, which are not necessarily completed at the same time, but may be performed at different times, and the execution order of these steps or stages is not necessarily sequential, but may be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.

[0087] In the description of this specification, references to terms such as "some embodiments," "other embodiments," and "ideal embodiments" indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0088] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0089] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A semiconductor structure, characterized in that, include: A first electrode, a second electrode, and an electrode field plate structure extending along a first direction, respectively; wherein... Along the second direction, the electrode field plate structure is located between the first electrode and the second electrode; the first direction intersects the second direction; The electrode field plate structure includes a first field plate structure and a second field plate structure connected to each other. The first field plate structure extends along a third direction, and the second field plate structure extends along a fourth direction. The third direction and the fourth direction intersect at least the first direction. The electrode field plate structure also includes a third field plate structure and a fourth field plate structure. The third field plate structure and the fourth field plate structure both extend along the second direction. The end of the third field plate structure near the second electrode is connected to the end of the first field plate structure near the second electrode, and the end of the fourth field plate structure near the second electrode is connected to the end of the second field plate structure near the second electrode. The first field plate structure and the second field plate structure are used together to suppress the induced current generated by the semiconductor structure under high-power microwave radiation. In a high-power microwave radiation environment, the induced currents generated on the third field plate structure and the connected first field plate structure are in opposite directions and cancel each other out at the connection point. Similarly, the induced currents generated on the fourth field plate structure and the connected second field plate structure are in opposite directions and cancel each other out at the connection point.

2. The semiconductor structure according to claim 1, characterized in that, The third direction and the fourth direction are different, and both the third direction and the fourth direction intersect with the second direction; wherein, the end of the first field plate structure near the first target electrode is connected to the end of the second field plate structure near the first target electrode, and the first target electrode includes the first electrode or the second electrode.

3. The semiconductor structure according to claim 2, characterized in that, The electrode field plate structure includes a plurality of first field plate units arranged along the first direction, and the plurality of first field plate units respectively include the first field plate structure and the second field plate structure; In any two adjacent first field plate units, the end of the second field plate structure of one first field plate unit near the second target electrode is connected to the end of the first field plate structure of the other first field plate unit near the second target electrode; wherein, one of the first target electrode and the second target electrode is the first electrode and the other is the second electrode.

4. The semiconductor structure according to claim 1, characterized in that, The third direction and the fourth direction are the same as or intersect with the second direction, respectively; wherein, the electrode field plate structure further includes a first connecting structure, and the end of the first field plate structure near the first target electrode is connected to the end of the second field plate structure near the first target electrode through the first connecting structure; the first target electrode includes the first electrode or the second electrode.

5. The semiconductor structure according to claim 4, characterized in that, The electrode field plate structure includes a second connection structure and a plurality of second field plate units arranged along the first direction, wherein the plurality of second field plate units include the first field plate structure and the second field plate structure; Any two adjacent second field plate units are connected by the second connection structure, wherein in one second field plate unit, the end of the second field plate structure near the second target electrode is connected to one end of the second connection structure, and in another second field plate unit, the end of the first field plate structure near the second target electrode is connected to the other end of the second connection structure; wherein, one of the first target electrode and the second target electrode is the first electrode, and the other is the second electrode.

6. The semiconductor structure according to any one of claims 1-5, characterized in that, The shape of the first field plate structure is either straight or curved, and the shape of the second field plate structure is either straight or curved.

7. The semiconductor structure according to any one of claims 1-5, characterized in that, The semiconductor structure also includes a third electrode; In the second direction, the third electrode is located between the first electrode and the first field plate structure or the second field plate structure.

8. A method for fabricating a semiconductor structure, characterized in that, include: Provide substrate; A first electrode, a second electrode, and an electrode field plate structure extending along a first direction are formed on the substrate; wherein, Along the second direction, the electrode field plate structure is located between the first electrode and the second electrode; the first direction intersects the second direction; The electrode field plate structure includes a first field plate structure and a second field plate structure connected to each other. The first field plate structure extends along a third direction, and the second field plate structure extends along a fourth direction. The third direction and the fourth direction intersect at least the first direction. The electrode field plate structure also includes a third field plate structure and a fourth field plate structure. The third field plate structure and the fourth field plate structure both extend along the second direction. The end of the third field plate structure near the second electrode is connected to the end of the first field plate structure near the second electrode, and the end of the fourth field plate structure near the second electrode is connected to the end of the second field plate structure near the second electrode. The first field plate structure and the second field plate structure are used together to suppress the induced current generated by the semiconductor structure under high-power microwave radiation. In a high-power microwave radiation environment, the induced currents generated on the third field plate structure and the connected first field plate structure are in opposite directions and cancel each other out at the connection point. Similarly, the induced currents generated on the fourth field plate structure and the connected second field plate structure are in opposite directions and cancel each other out at the connection point.

9. An electronic device, characterized in that, It includes the semiconductor structure as described in any one of claims 1-7, or is prepared by the method for preparing the semiconductor structure as described in claim 8.

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