A homologous clock structure applied to an ultra-high-speed signal acquisition and processing system and a configuration method thereof

Abstract

The application belongs to the field of communication clock structure, and relates to a homologous clock structure and a configuration method applied to a super-high-speed signal acquisition and processing system, comprising: a clock source, a first-stage low-jitter clock distribution network, a second-stage multi-channel double-loop phase-locked loop, a third-stage high-frequency phase-locked loop and a clock expansion network connected in sequence; the clock source is composed of a differential crystal oscillator and an external clock; the first-stage low-jitter clock distribution network is composed of two double-path low-jitter clock buffers; the second-stage multi-channel double-loop phase-locked loop is composed of two ultra-low phase noise oscillators and two double-loop phase-locked circuits; the third-stage high-frequency phase-locked loop and the clock expansion network are composed of two high-frequency phase-locked loops and four 12-path clock buffers; through the priority setting of the clock source, the internal or external clock source can be flexibly selected.

Description

Technical Field

[0001] This invention pertains to clock structures in the field of communications, and in particular relates to a co-current clock structure and configuration method for use in ultra-high-speed signal acquisition and processing systems. Background Technology

[0002] The ultra-high-speed signal acquisition and processing system mainly includes ultra-high-speed signal acquisition, sampling data transmission, high-speed data buffering, signal processing, and high-speed bus transmission. To achieve ultra-high-speed signal acquisition and processing, a dedicated clock network needs to be designed to meet the clock requirements of each part of the system, ensuring clocks above GHz are from the same source. The clock network needs to comprehensively consider factors such as clock sources, the number of clock routes, drive capability, and clock frequency. In the case of multiple input clock sources, the priority of each clock source must first be set, then a PLL is used to multiply the input clock, followed by a frequency divider to generate the frequency required by each device, and finally, the clock is buffered and routed to each device.

[0003] Currently, ultra-high-speed signal acquisition and processing systems mainly adopt large-scale FPGA + ultra-high-speed ADC / DAC + single-level clock distribution chip. However, as the system scale expands, the single-level clock distribution network can no longer meet the requirements of ultra-high-speed ADC / DAC conversion for clock frequency and jitter, nor can it meet the requirements of the number and co-location of clock channels for the following components involved in the system: JESD204B / C reference clock, FPGA global clock, DDR4 working clock, and fiber optic communication. This has led to a bottleneck in the clock network design of ultra-high-speed signal acquisition and processing systems. Summary of the Invention

[0004] To address the problems existing in the prior art, this invention proposes a co-source clock structure for ultra-high-speed signal acquisition and processing systems. This structure includes a clock source, a first-stage low-jitter clock distribution network, a second-stage multi-channel dual-loop phase-locked loop, a third-stage high-frequency phase-locked loop, and a clock extension network connected in sequence.

[0005] The clock source consists of a differential crystal oscillator and an external clock. The selection of the internal or external clock can be achieved by setting the priority.

[0006] The first-level low-jitter clock distribution network consists of two dual-channel low-jitter clock buffers, which convert the signal output from the clock source.

[0007] The second-stage multi-channel dual-loop phase-locked loop consists of two ultra-low phase noise oscillators and two dual-loop phase-locked circuits, used to process the signal converted by the first-stage low-jitter clock distribution network;

[0008] The third-stage high-frequency phase-locked loop and clock extension network consists of two high-frequency phase-locked loops and four 12-channel clock buffers, used to process the signals output from the second-stage multi-channel dual-loop phase-locked loop;

[0009] A clock network configuration method for an ultra-high-speed signal acquisition and processing system, the method comprising:

[0010] S101. Power on the system, load the routing program on the FPGA, load the configuration code on the MCU, and set the maximum number of configuration attempts.

[0011] S102. Configure parameters for the dual-loop phase-locked circuit 1 and input the signal to the first dual-loop phase-locked circuit;

[0012] S103. Check whether the dual-loop phase-locked circuit 1 is locked. If yes, proceed to step S104. If no, determine whether the current configuration count exceeds the maximum configuration count. If yes, the configuration is incorrect. Otherwise, return to step S102.

[0013] S104. Configure the parameters of the dual-loop phase-locked circuit 2 and determine whether the dual-loop phase-locked circuit 2 is locked. If not, proceed to step S105; if yes, proceed to step S106.

[0014] S105. Determine whether the current configuration count is greater than the maximum configuration count. If not, return to step S104. If yes, the configuration is incorrect.

[0015] S106. Configure parameters for high-frequency phase-locked loop 1 and determine whether high-frequency phase-locked loop 1 is locked. If not, proceed to step S107; if yes, proceed to step S108.

[0016] S107. Determine whether the current configuration count is greater than the maximum configuration count. If not, return to step S106. If yes, the configuration is incorrect.

[0017] S108. Configure parameters for high-frequency phase-locked loop 2 and determine whether high-frequency phase-locked loop 2 is locked. If not, proceed to step S109; if yes, proceed to step S110.

[0018] S109. Determine whether the current configuration count is greater than the maximum configuration count. If not, return to step S108. If yes, the configuration is incorrect.

[0019] S110. Configure the parameters for the ultra-high-speed DAC1 and check whether the ultra-high-speed DAC1 has successfully established a link. If not, proceed to step S111; if yes, proceed to step S112.

[0020] S111. Determine if the current configuration count is greater than the maximum configuration count. If not, return to step S110. If yes, the configuration is incorrect.

[0021] S112. Configure the parameters of the ultra-high-speed DAC2 and check whether the ultra-high-speed DAC2 has successfully established a link. If not, proceed to step S113; if yes, proceed to step S114.

[0022] S113. Determine whether the current configuration count is greater than the maximum configuration count. If not, return to step S112. If yes, the configuration is incorrect.

[0023] S114. Configure the parameters of the ultra-high-speed ADC1 and check whether the ultra-high-speed ADC1 has successfully established a link. If not, proceed to step S115; if yes, proceed to step S116.

[0024] S115. Determine whether the current configuration count is greater than the maximum configuration count. If not, return to step S114. If yes, the configuration is incorrect.

[0025] S116. Configure the parameters for the ultra-high-speed ADC2 and check whether the ultra-high-speed ADC2 has successfully established a link. If not, proceed to step S117. If yes, the configuration is complete.

[0026] S117. Determine whether the current configuration count is greater than the maximum configuration count. If not, return to step S116. If yes, then there is a configuration error.

[0027] The beneficial effects of this invention are:

[0028] This invention achieves flexible selection of internal and external clocks through clock source priority settings; expands the clock source using two 1-to-2 low-jitter clock buffers; achieves jitter suppression, frequency multiplication, and frequency division using two ultra-low phase-noise oscillators and two 14-channel output dual-loop phase-locked loop circuits; generates four high-frequency clocks using two high-frequency phase-locked loops; expands the terminal clock using four 12-channel clock buffers; achieves stable and reliable configuration of multiple devices such as dual-loop phase-locked loops, high-speed phase-locked loops, ultra-high-speed ADCs, and ultra-high-speed DACs through a homogeneous clock structure configuration process; and routes eight control signals to 42 configuration signals through a multi-module configuration routing scheme using an MCU+FPGA. This solution addresses the requirements of ultra-high-speed signal acquisition and processing systems for complex clocks with multiple channels, high frequencies, and low jitter, enabling the homogeneous clock structure based on this invention to not only meet the needs of ultra-high-speed signal acquisition and processing systems but also the application requirements of similar large-scale communication and signal processing systems. Attached Figure Description

[0029] Figure 1 This is a schematic diagram of the same-source clock structure of the present invention;

[0030] Figure 2 This is a schematic diagram of the clock network configuration process of the present invention;

[0031] Figure 3 This is a schematic diagram of the multi-module configuration routing of the present invention. Detailed Implementation

[0032] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0033] A co-current clock structure for an ultra-high-speed signal acquisition and processing system is disclosed. This structure comprises a clock source, a first-stage low-jitter clock distribution network, a second-stage multi-channel dual-loop phase-locked loop (PLL), a third-stage high-frequency PLL, and a clock extension network connected sequentially. The clock source consists of a differential crystal oscillator and an external clock, with priority settings allowing selection between the internal and external clocks. The first-stage low-jitter clock distribution network consists of two dual-channel low-jitter clock buffers, which convert the signal output from the clock source. The second-stage multi-channel dual-loop PLL consists of two ultra-low phase-noise oscillators and two dual-loop PLL circuits, used to process the signal converted by the first-stage low-jitter clock distribution network. The third-stage high-frequency PLL and clock extension network consist of two high-frequency PLLs and four 12-channel clock buffers, used to process the signal output from the second-stage multi-channel dual-loop PLL, providing the required clock signals for devices such as two ultra-high-speed ADCs, two large-scale FPGAs, and two ultra-high-speed DACs in the ultra-high-speed signal acquisition and processing system.

[0034] In this embodiment, as Figure 1 As shown, a preferred embodiment of a co-source clock structure for an ultra-high-speed signal acquisition and processing system includes a clock source, a first-stage low-jitter clock distribution network, a second-stage multi-channel dual-loop phase-locked loop, a third-stage high-frequency phase-locked loop, and a clock extension network.

[0035] The clock source, serving as the input to the co-source clock network of the ultra-high-speed signal acquisition and processing system, consists of differential crystal oscillator 1 and external clock 1, with a clock frequency of 10MHz. Differential crystal oscillator 1 is integrated on the PCB, while external clock 1 is input via an SSMA connector. The differential crystal oscillator output uses LVDS level, while the external clock outputs LVCMOS level. Differential crystal oscillator 1 is used for the board-level clock network to operate independently, while external clock 1 is used to achieve system-level clock co-source.

[0036] The first-level low-jitter clock distribution network consists of dual-channel low-jitter clock buffer 1 and dual-channel low-jitter clock buffer 2. Dual-channel low-jitter clock buffer 1 converts one differential crystal oscillator input clock into two LVDS output clocks, and dual-channel low-jitter clock buffer 2 converts one external clock into two LVDS output clocks. The dual-channel low-jitter clock buffers have a maximum input frequency of 650MHz, jitter ≤50fs, support a wide frequency range, introduce low jitter, and effectively expand the clock source.

[0037] The second-stage multi-channel dual-loop phase-locked loop (PLL) consists of an ultra-low phase noise oscillator 1, an ultra-low phase noise oscillator 2, a dual-loop PLL circuit 1, and a dual-loop PLL circuit 2. Ultra-low phase noise oscillator 1 provides a stable de-jittering clock for the PLL in dual-loop PLL circuit 1. With CPOUT, the frequency of ultra-low phase noise oscillator 1 is fine-tuned to achieve synchronization with the clock source. Ultra-low phase noise oscillator 2 provides a stable de-jittering clock for the PLL in dual-loop PLL circuit 2. With CPOUT, the frequency of ultra-low phase noise oscillator 2 is fine-tuned to achieve synchronization with the clock source. The two input clocks in dual-loop PLL circuit 1 and dual-loop PLL circuit 2 are selected through internal register configuration. CLKIN0 is the internal differential crystal oscillator input, and CLKIN1 is the external clock source input; both clock frequencies are 10MHz.

[0038] The connections of the components in the second-stage multi-channel dual-loop phase-locked loop are as follows: the CLKIN0 terminal of the dual-loop phase-locked circuit 1 is connected to the first output terminal of the clock buffer 1 in the first-stage low-jitter clock distribution network; the CLKIN1 terminal of the dual-loop phase-locked circuit 1 is connected to the first output terminal of the first-stage clock buffer 2; the CPOUT signal of the dual-loop phase-locked circuit 1 is connected to the voltage control terminal of the low-phase-noise oscillator 1; the reference signal input terminal of the dual-loop phase-locked circuit 1 is connected to the output terminal of the low-phase-noise oscillator 1; and each output terminal of the dual-loop phase-locked circuit 1 is connected to the third-stage high-frequency phase-locked loop and the clock extension network, respectively.

[0039] The CLKIN0 terminal of the dual-loop phase-locked loop circuit 2 is connected to the second output terminal of the clock buffer 1 in the first-stage low-jitter clock distribution network, and the CLKIN1 terminal of the dual-loop phase-locked loop circuit 2 is connected to the second output terminal of the first-stage clock buffer 2. The CPOUT signal of the dual-loop phase-locked loop circuit 2 is connected to the voltage control terminal of the low-phase-noise oscillator 2, the reference signal input terminal of the dual-loop phase-locked loop circuit 2 is connected to the output terminal of the low-phase-noise oscillator 2, and each output terminal of the dual-loop phase-locked loop circuit 2 is connected to the third-stage high-frequency phase-locked loop and the clock extension network, respectively.

[0040] The dual-loop phase-locked loop circuits 1 and 2 internally contain two-stage phase-locked loops (PLL1 and PLL2) and a clock divider unit. PLL1 performs jitter removal on the input clock, while PLL2 generates the core clock. By configuring the R and N coefficients, any clock can be output. The clock divider unit routes and divides the core clock of PLL2. Each dual-loop phase-locked loop circuit supports LVDS, LVPECL, and CML level standards, with a maximum output clock speed of 3.2 GHz and a typical clock jitter of 44 fs, effectively achieving clock jitter removal.

[0041] The dual-loop phase-locked loop (PLL) circuit 1 outputs five clock channels: CLKOUT0, SCLKOUT1, CLKOUT2, SCLKOUT3, and SCLKOUT5. CLKOUT0 provides the reference clock for the ultra-high-speed ADC1 and ADC2 at a frequency of 10.23MHz; SCLKOUT1 and SCLKOUT3 provide the SYSREF clock for the JESD204B interface of the ultra-high-speed ADC1 and ADC2; CLKOUT2 provides the REFCLK clock for the GTY cell in the large-scale FPGA1; and SCLKOUT5 provides the SYSREF clock for the JESD204B interface of the large-scale FPGA1.

[0042] The dual-loop phase-locked loop circuit 2 outputs 11 clock channels: CLKOUT0, CLKOUT2, CLKOUT4, CLKOUT6, CLKOUT8, CLKOUT10, CLKOUT12, SCLKOUT1, SCLKOUT3, SCLKOUT5, and SCLKOUT7. CLKOUT0 provides the global clock for the large-scale FPGA1.

[0043] SCLKOUT1 provides the SYSREF clock for the large-scale FPGA1 JESD204B; CLKOUT2 provides the DDR4 clock for the large-scale FPGA1; CLKOUT4 ​​provides the REFCLK clock for the large-scale FPGA1 GTY cell; CLKOUT6 provides the REFCLK clock for the large-scale FPGA2 GTY cell; CLKOUT8 provides the global clock for the large-scale FPGA2; CLKOUT10 provides the DDR4 clock for the large-scale FPGA2; CLKOUT12 provides the REFCLK clock for the large-scale FPGA2 GTY cell; SCLKOUT3 provides the SYSREF clock for the ultra-high-speed DAC1 JESD204B interface; SCLKOUT5 provides the reference clock for the ultra-high-speed DAC1 and DAC2 at a frequency of 10MHz; SCLKOUT7 provides the SYSREF clock for the ultra-high-speed DAC2 JESD204B interface.

[0044] The third-stage high-frequency phase-locked loop (PLL) and clock expansion network consists of two PLLs and four 12-channel clock buffers: PLL 1, PLL 2, 12-channel clock buffer 1, 12-channel clock buffer 2, 12-channel clock buffer 3, and 12-channel clock buffer 4. The two PLLs generate the high-frequency clock, with a maximum output frequency of 15GHz and a clock jitter of 45fs, which is beneficial for improving the performance of ultra-high-speed ADC and DAC data conversion. The four 12-channel clock buffers are used for clock expansion. The maximum clock frequency of each 12-channel clock buffer is 1.2GHz, with a jitter of 54fs and a channel-to-channel difference of 70ps. This is beneficial for clock source expansion in ultra-high-speed signal acquisition and processing systems, especially for large-scale FPGA circuits requiring multiple pairs of clocks from the same source.

[0045] High-frequency phase-locked loop 1 converts the 10.23MHz reference clock output from the second-stage clock network into a sampling clock for ultra-high-speed ADC1 and ultra-high-speed ADC2, with an output frequency of 5.115GHz. The ultra-high-speed ADCs use the rising and falling edges of the clock for sampling; with a 5.115GHz sampling clock input, ultra-high-speed sampling of 10.23GSPS can be achieved. High-frequency phase-locked loop 2 converts the 10MHz reference clock output from the second-stage clock network into a conversion clock for ultra-high-speed DAC1 and ultra-high-speed DAC2, with an output frequency of 12GHz, achieving ultra-high-speed data conversion of 12GSPS.

[0046] The input clock of the 12-channel clock buffer 1 comes from the 165MHz clock output of the second-stage clock network. Through the clock buffer, eight 165MHz channels are output to the GTY cells of the large-scale FPGA1 as reference clocks for the GTY cells. The eight clock channels are: 5200A_GTYCLK0, 5200A_GTYCLK1, 5200A_GTYCLK2, 5200A_GTYCLK3, 5200B_GTYCLK0, 5200B_GTYCLK1, 5200B_GTYCLK2, and 5200B_GTYCLK3.

[0047] The 5200A_GTYCLK0 to 5200A_GTYCLK3 units are provided to the GTY222 to GTY225 units to realize data transmission between the ultra-high-speed ADC1 and the large-scale FPGA1, with a transmission line rate of 10.23Gbps.

[0048] Units 5200B_GTYCLK0 to 5200B_GTYCLK3 are provided to GTY226 to GTY229 units to realize data transmission between the ultra-high-speed ADC2 and the large-scale FPGA1, with a transmission line rate of 10.23Gbps.

[0049] The input clock of the 12-channel clock buffer 2 comes from the 125MHz output of the second-stage clock network. The clock buffer outputs 12 channels of 125MHz to the GTY cells of the large-scale FPGA1 as reference clocks for the GTY cells. The 12 clock channels are: 9081A_GTYCLK0, 9081A_GTYCLK1, 9081B_GTYCLK0, 9081B_GTYCLK1, A_ETH_GTYCLK, A_OPT_GTYCLK, FPGA1_GTYCLK0, FPGA1_GTYCLK1, FPGA1_GTYCLK2, FPGA1_GTYCLK3, FPGA1_GTYCLK4, and FPGA1_GTYCLK5. Specifically, 9081A_GTYCLK0 and 9081A_GTYCLK1 are provided to GTY130~GTY131 units to realize data transmission between FPGA1 and ultra-high-speed DAC1, with a transmission rate of 15Gbps; 9081B_GTYCLK0 and 9081B_GTYCLK1 are provided to GTY230~GTY231 units to realize data transmission between FPGA1 and ultra-high-speed DAC2, with a transmission rate of 15Gbps; A_ETH_GTYCLK is provided to GTY132 unit of FPGA1 to realize Gigabit Ethernet transmission of FPGA1, with a transmission line rate of 1Gbps; A_OPT_GTYCLK is provided to GTY129 module of FPGA1 to realize fiber optic communication of FPGA1, with a transmission line rate of 10Gbps.

[0050] FPGA1_GTYCLK0 to FPGA1_GTYCLK5 are provided to GTY125 to GTY128, GTY220 and GTY221 units of FPGA1 respectively, to realize large-scale bandwidth data transmission between large-scale FPGA1 and large-scale FPGA2, with a transmission rate of 15Gbps line rate.

[0051] The input clock of the 12-channel clock buffer 3 comes from the 125MHz output of the second-stage clock network. The clock buffer outputs 12 channels of 125MHz to large-scale FPGA1 and large-scale FPGA2 as reference clocks for the GTY cells. The 12 clock channels are: FPGA1_GTYCLK6, FPGA2_GTYCLK0, FPGA2_GTYCLK1, FPGA2_GTYCLK2, FPGA2_GTYCLK3, FPGA2_GTYCLK4, FPGA2_GTYCLK5, FPGA2_GTYCLK6, B_OPT_GTYCLK, and B_ETH_GTYCLK. FPGA1_GTYCLK6 is provided to the GTY124 unit of FPGA1 to realize high-bandwidth data transmission with FPGA1, with a transmission line rate of 15Gbps; FPGA2_GTYCLK0~FPGA2_GTYCLK6 are provided to the GTY225~GTY231 units of FPGA2 to realize high-bandwidth data transmission with FPGA2, with a transmission line rate of 15Gbps; B_OPT_GTYCLK is provided to the GTY131 unit of FPGA2 to realize fiber optic transmission of FPGA2, with a transmission line rate of 10Gbps; and B_ETH_GTYCLK is provided to the GTY130 unit of FPGA2 to realize gigabit Ethernet transmission of FPGA2, with a line rate of 1Gbps.

[0052] The input clock of the 12-channel clock buffer 4 comes from the output of the second-stage clock network and is used for communication between FPGA2 and the FMC1 and FMC2 daughter cards. This clock frequency can be adjusted according to the actual needs of the connected FMC daughter cards. The 10 clocks output through the clock buffer are: FMC1_GTYCLK0~FMC1_GTYCLK3, FMC2_GTYCLK0~FMC2_GTYCLK3, FMC1_EXTCLK, and FMC2_EXTCLK. FMC1_GTYCLK0 to FMC1_GTYCLK3 are connected to GTY119, GTY120, GTY125, and GTY126 units of FPGA2, providing a GTY reference clock to enable high-speed communication between FMC1 daughter card and FPGA2; FMC2_GTYCLK0 to FMC2_GTYCLK3 are connected to GTY121, GTY123, GTY122, and GTY124 units of large-scale FPGA2, providing a GTY reference clock to enable high-speed communication between FMC2 daughter card and FPGA2; FMC1_EXTCLK provides a source clock for FMC1 daughter card, and FMC2_EXTCLK provides a source clock for FMC2 daughter card.

[0053] In this embodiment, a clock network configuration method applied to an ultra-high-speed signal acquisition and processing system is described, such as... Figure 2As shown, the method includes:

[0054] S101. Power on the system, load the routing program on the FPGA, load the configuration code on the MCU, and set the maximum number of configuration attempts.

[0055] S102. Configure parameters for the dual-loop phase-locked circuit 1 and input the signal to the first dual-loop phase-locked circuit;

[0056] S103. Check whether the dual-loop phase-locked circuit 1 is locked. If yes, proceed to step S104. If no, determine whether the current configuration count exceeds the maximum configuration count. If yes, the configuration is incorrect. Otherwise, return to step S102.

[0057] S104. Configure the parameters of the dual-loop phase-locked circuit 2 and determine whether the dual-loop phase-locked circuit 2 is locked. If not, proceed to step S105; if yes, proceed to step S106.

[0058] S105. Determine whether the current configuration count is greater than the maximum configuration count. If not, return to step S104. If yes, the configuration is incorrect.

[0059] S106. Configure parameters for high-frequency phase-locked loop 1 and determine whether high-frequency phase-locked loop 1 is locked. If not, proceed to step S107; if yes, proceed to step S108.

[0060] S107. Determine whether the current configuration count is greater than the maximum configuration count. If not, return to step S106. If yes, the configuration is incorrect.

[0061] S108. Configure parameters for high-frequency phase-locked loop 2 and determine whether high-frequency phase-locked loop 2 is locked. If not, proceed to step S109; if yes, proceed to step S110.

[0062] S109. Determine whether the current configuration count is greater than the maximum configuration count. If not, return to step S108. If yes, the configuration is incorrect.

[0063] S110. Configure the parameters for the ultra-high-speed DAC1 and check whether the ultra-high-speed DAC1 has successfully established a link. If not, proceed to step S111; if yes, proceed to step S112.

[0064] S111. Determine if the current configuration count is greater than the maximum configuration count. If not, return to step S110. If yes, the configuration is incorrect.

[0065] S112. Configure the parameters of the ultra-high-speed DAC2 and check whether the ultra-high-speed DAC2 has successfully established a link. If not, proceed to step S113; if yes, proceed to step S114.

[0066] S113. Determine whether the current configuration count is greater than the maximum configuration count. If not, return to step S112. If yes, the configuration is incorrect.

[0067] S114. Configure the parameters of the ultra-high-speed ADC1 and check whether the ultra-high-speed ADC1 has successfully established a link. If not, proceed to step S115; if yes, proceed to step S116.

[0068] S115. Determine whether the current configuration count is greater than the maximum configuration count. If not, return to step S114. If yes, the configuration is incorrect.

[0069] S116. Configure the parameters for the ultra-high-speed ADC2 and check whether the ultra-high-speed ADC2 has successfully established a link. If not, proceed to step S117. If yes, the configuration is complete.

[0070] S117. Determine whether the current configuration count is greater than the maximum configuration count. If not, return to step S116. If yes, then there is a configuration error.

[0071] Specifically, after the ultra-high-speed signal acquisition and processing system is powered on, the FPGA loads the routing program from the configuration Flash, and the MCU loads the configuration code simultaneously. Then, it sends the configuration parameters for the dual-loop phase-locked circuit 1, completing the configuration of PLL1 and PLL2 within the phase-locked circuit 1, and sends the frequency division coefficients for the output paths of the phase-locked circuit 1, completing the configuration of channels SCLKOUT1, CLKOUT0, SCLKOUT3, CLKOUT2, and SCLKOUT5. The MCU detects the locking signal output by the phase-locked circuit 1 through the GPIO port. If locking is not completed, it checks whether the configuration count of the phase-locked circuit 1 has been exceeded. If the configuration count has not been exceeded, it performs the configuration again, incrementing the configuration counter by 1. If the configuration count has been exceeded, it stops the configuration and reports fault code 1. When the dual-loop phase-locked circuit 1 completes locking, the configuration counter is cleared, and the configuration of the dual-loop phase-locked circuit 2 continues. Configuration parameters for PLL1, PLL2, and the output channels within phase-locked circuit 2 are sent, completing the configuration of channels CLKOUT0, SCLKOUT1, CLKOUT2, CLKOUT4, CLKOUT6, CLKOUT8, CLKOUT10, CLKOUT12, SCLKOUT3, SCLKOUT5, and SCLKOUT7. The MCU detects the locking signal output by phase-locked circuit 2 via the GPIO port. If configuration is not completed and the number of configuration attempts has not exceeded, configuration is performed again, and the configuration counter is incremented by 1. If the number of configuration attempts exceeds the limit, configuration stops, and fault code 2 is reported.

[0072] In this embodiment, when the dual-loop phase-locked loop 2 completes locking, the configuration counter is reset to zero, and configuration of the high-frequency phase-locked loop 1 begins. The MCU determines whether locking is complete by reading the configuration register of the high-frequency phase-locked loop 1. If locking is not complete and the configuration count has not been exceeded, the high-frequency phase-locked loop 1 is configured again, and the configuration counter is incremented by 1. If the configuration count is exceeded, configuration stops and fault code 3 is reported. When the high-frequency phase-locked loop 1 completes locking, the configuration counter is reset to zero, and configuration of the high-frequency phase-locked loop 2 begins. The MCU determines whether locking is complete by reading the configuration register of the high-frequency phase-locked loop 2. If locking is not complete and the configuration count has not been exceeded, the high-frequency phase-locked loop 2 is configured again, and the configuration counter is incremented by 1. If the configuration count is exceeded, configuration stops and fault code 4 is reported.

[0073] In this embodiment, when the high-frequency phase-locked loop 2 completes locking, the configuration counter is reset to zero, and the MCU begins configuring the internal clock, JESD204B interface, and signal link parameters of the ultra-high-speed DAC1. The MCU determines whether the link between DAC1 and the FPGA has been successfully established by detecting the SYNCOUTB1 signal. If the link establishment fails and the configuration count has not been exceeded, the DAC1 configuration parameters are sent again, and the configuration counter is incremented by 1. If the configuration count is exceeded, the configuration stops and fault code 5 is reported. If the link between DAC1 and the FPGA is successfully established, the configuration counter is reset to zero, and the MCU executes the configuration of the internal clock, JESD204B interface, and signal link parameters of the ultra-high-speed DAC2. The MCU determines whether the link between DAC2 and the FPGA has been successfully established by detecting the SYNCOUTB2 signal. If the link establishment fails and the configuration count has not been exceeded, the DAC2 configuration parameters are sent again, and the configuration counter is incremented by 1. If the configuration count is exceeded, the configuration stops and fault code 6 is reported.

[0074] In this embodiment, when DAC2 successfully establishes a link, the MCU resets the configuration counter and begins configuring the high-speed ADC1, configuring the JESD204B interface clock and signal link parameters. The MCU determines whether the link between the high-speed ADC1 and the FPGA is successfully established by detecting the SYNCSE1 signal. If the link is not successfully established and the configuration count has not exceeded, the MCU resends the high-speed ADC1 configuration parameters, increments the configuration counter by 1, and if the configuration count is exceeded, the configuration stops and fault code 7 is reported. If the high-speed ADC1 successfully establishes a link, the MCU resets the configuration counter and begins configuring the high-speed ADC2, configuring the JESD204B interface clock and signal link parameters. The MCU determines whether the link between the high-speed ADC2 and the FPGA is successfully established by detecting the SYNCSE2 signal. If the link is not successfully established and the configuration count has not exceeded, the MCU resends the high-speed ADC2 configuration parameters, increments the configuration counter by 1, and if the configuration count is exceeded, the configuration stops and fault code 8 is reported. When ADC2 detects a successful link establishment, the configuration of the entire system is completed. The MCU sends a configuration completion signal to the FPGA, and the internal algorithm logic of the FPGA begins to run.

[0075] The following explains the operation of the multi-module configuration routing in the above clock structure: In this embodiment, a schematic diagram of multi-module configuration routing applied to an ultra-high-speed signal acquisition clock structure is shown below. Figure 3 As shown, the specific implementation method is as follows:

[0076] 1) The MCU acts as the master controller, transmitting configuration information for each module through eight GPIO ports. Specifically, GPIO0-GPIO3 are chip select signals used to select the module to be configured. GPIO4 is the clock signal, providing the serial clock for the module to be configured. GPIO5 is the data output, providing the serial data for the module to be configured. GPIO6 is the data input, used to receive feedback parameters from the module to be configured. GPIO7 is the control signal, used to provide additional control information to the module to be configured.

[0077] 2) The FPGA acts as a router for multi-module configuration, integrating routing logic internally to route GPIO signals from the MCU to the subsequent configuration modules. It uses time-division multiplexing of GPIO signals to convert 8 GPIO control signals into 42 configuration signals. Specifically, it includes 5 MUX units: CS_MUX, CLK_MUX, SDO_MUX, SDI_MUX, and CTL_MUX.

[0078] 3) CS_MUX implements the combination and routing of four GPIOs. GPIO0-GPIO3 are combined into a 4-bit chip select code, with the following chip select functions: Code 1 corresponds to the 7044A_SLEN signal, implementing chip select for dual-loop phase-locked circuit 1; Code 2 corresponds to the 7044B_SLEN signal, implementing chip select for dual-loop phase-locked circuit 2; Code 3 corresponds to the 2594A_CSB signal, implementing chip select for high-frequency phase-locked loop 1; Code 4 corresponds to the 2594B_CSB signal, implementing chip select for high-frequency phase-locked loop 2; Code 5 corresponds to the 9081A_CSB signal, implementing chip select for ultra-high-speed DAC1; Code 6 corresponds to the 9081B_CSB signal, implementing chip select for ultra-high-speed DAC2; Code 7 corresponds to the 5200A_SCSn signal, implementing chip select for ultra-high-speed ADC1; Code 8 corresponds to the 5200B_SCSn signal, implementing chip select for ultra-high-speed ADC2. Code 9 selects the link establishment signal for the ultra-high-speed ADC1, corresponding to the detection of SYNCSE1; code 10 selects the link establishment signal for the ultra-high-speed ADC2, corresponding to the detection of SYNCSE2; code 11 selects the link establishment signal for the ultra-high-speed DAC1, corresponding to the detection of SYNCOUTB1; code 12 selects the link establishment signal for the ultra-high-speed DAC2, corresponding to the detection of SYNCOUTB2; code 15 indicates that the configuration is complete.

[0079] 4) The CLK_MUX unit implements clock routing, routing the GPIO4 signal to the clock inputs of eight configuration modules: 7044A_CLK, 7044B_CLK, 2594A_SCK, 2594B_SCK, 9081A_SCLK, 9081B_SCLK, 5200A_SCLK, and 5200B_SCLK. The route selection is determined by the CS_MUX encoding. When CS_MUX selects a configuration module, GPIO4 is routed to the clock channel of that module.

[0080] 5) SDO_MUX implements the routing of output configuration data, corresponding to the data input of 8 configuration modules: 7044A_SDATA, 7044B_SDATA, 2594A_SDI, 2594B_SDI, 9081A_SDIO, 9081B_SDIO, 5200A_SDI, and 5200B_SDI. The route selection is determined by the CS_MUX encoding. When CS_MUX selects a configuration module, GPIO5 routes to the input data channel of that module.

[0081] 6) SDI_MUX implements the routing of input data and is used to receive status information. It corresponds to the configuration signals of 8 modules: 7044A_LOCK, 7044B_LOCK, 2594A_MUXout, 2594B_MUXout, 9081A_SDO, 9081B_SDO, 5200A_SDO, and 5200B_SDO, as well as 4 FPGA internal link establishment signals: SYNCSE1, SYNCSE2, SYNCOUTB1, and SYNCOUTB2. The route selection is determined by the CS_MUX encoding. When CS_MUX selects a certain configuration module, GPIO6 routes to the status information output channel of that module.

[0082] 7) The CTL_MUX unit implements the routing of control signals and is used to extend additional control signals: 7044A_RESET, 7044B_RESET, 9081A_RESETB, 9081B_RESETB, 5200A_PD, and 5200B_PD. These extended control signals enable the reset and restart of the configuration module. The route selection is determined by the CS_MUX encoding. When CS_MUX selects a configuration module, GPIO7 routes to the control signal channel of that module.

[0083] By adopting this synchronous clock network structure, not only can the clock management function of a multi-channel ultra-high-speed signal acquisition and processing system be realized, but the clock management needs of most communication systems and signal processing systems can also be covered.

[0084] This invention provides a unified clock structure for ultra-high-speed signal acquisition and processing systems, offering a complete clock solution. It employs a three-level clock network structure to achieve unified clocking for 54 channels. An MCU is used to configure multiple dual-loop phase-locked loops, high-speed phase-locked loops, ultra-high-speed ADCs, and ultra-high-speed DACs. An FPGA is used to route and bridge multiple configuration interfaces, enabling the routing and expansion of 8 control signals to 42 configuration signals.

[0085] The features of this invention are as follows: Internal or external clock sources can be flexibly selected by setting clock source priority; the dual-loop phase-locked loop + high-frequency phase-locked loop + multi-channel clock buffer structure solves the requirements of ultra-high-speed signal acquisition and processing systems for complex clocks with multiple channels, high frequency, and low jitter; closed-loop detection of configuration results adds a redundant configuration mechanism, enabling stable and reliable configuration of multiple devices and ensuring the reliability of the system clock network; and through routing bridging of the configuration interface, complexity is simplified, using a small number of control signals and logic to achieve unified configuration of the ultra-high-speed signal acquisition and processing system.

[0086] The above-described embodiments further illustrate the purpose, technical solution, and advantages of the present invention. It should be understood that the above-described embodiments are merely preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made to the present invention within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A co-current clock structure for use in ultra-high-speed signal acquisition and processing systems, characterized in that, It includes a clock source, a first-stage low-jitter clock distribution network, a second-stage multi-channel dual-loop phase-locked loop, a third-stage high-frequency phase-locked loop, and a clock extension network connected in sequence; The clock source consists of a differential crystal oscillator and an external clock. The selection of the internal or external clock can be achieved by setting the priority. The first-level low-jitter clock distribution network consists of two dual-channel low-jitter clock buffers, which convert the signal output from the clock source. The second-stage multi-channel dual-loop phase-locked loop consists of two ultra-low phase noise oscillators and two dual-loop phase-locked circuits, used to process the signal converted by the first-stage low-jitter clock distribution network; The connections of the components in the second-stage multi-channel dual-loop phase-locked loop are as follows: the two input terminals of dual-loop phase-locked circuit 1 and dual-loop phase-locked circuit 2 are respectively connected to the output terminals of the first-stage low-jitter clock distribution network; the CPOUT signal and reference signal input terminals of dual-loop phase-locked circuit 1 are connected to ultra-low phase noise oscillator 1; the CPOUT signal and reference signal input terminals of dual-loop phase-locked circuit 2 are connected to ultra-low phase noise oscillator 2; and the output terminals of dual-loop phase-locked circuit 1 and dual-loop phase-locked circuit 2 are respectively connected to the third-stage high-frequency phase-locked loop and the clock extension network. The third-stage high-frequency phase-locked loop and clock expansion network consists of two high-frequency phase-locked loops and four 12-channel clock buffers, which are used to multiply and expand the signal output from the second-stage multi-channel dual-loop phase-locked loop. The connections of the components in the third-stage high-frequency phase-locked loop and clock extension network are as follows: the input of high-frequency phase-locked loop 1 is connected to the output of the second-stage dual-loop phase-locked circuit 1; the two outputs of high-frequency phase-locked loop 1 are connected to the clock inputs of ultra-high-speed ADC1 and ultra-high-speed ADC2, respectively; the input of 12-channel clock buffer 1 is connected to the SCLKOUT1 output of the second-stage dual-loop phase-locked circuit 1; the output of 12-channel clock buffer 1 is connected to the GTY input of large-scale FPGA1; the inputs of 12-channel clock buffer 2, 12-channel clock buffer 3, 12-channel clock buffer 4, and high-frequency phase-locked loop 2 are all connected to the output of the second-stage dual-loop phase-locked circuit 2; all outputs of 12-channel clock buffer 2 are connected to the GTY input of large-scale FPGA1; and each terminal of 12-channel clock buffer 3 is sequentially connected to the GTY input of large-scale FPGA1 and the GTY input of large-scale FPGA2. The output of the 12-channel clock buffer 4 is connected in sequence to the input of the large-scale FPGA 2, FMC interface 1, and FMC interface 2; the two outputs of the high-frequency phase-locked loop 2 are connected to the clock inputs of the ultra-high-speed DAC 1 and ultra-high-speed DAC 2, respectively. The expanded clock network is used to drive two ultra-high-speed ADCs, two large-scale FPGAs, two ultra-high-speed DACs, and two FMC interfaces.

2. The co-current clock structure for an ultra-high-speed signal acquisition and processing system according to claim 1, characterized in that, The clock source has a clock frequency of 10MHz; the differential crystal oscillator is integrated on the PCB board and outputs LVDS level; the external clock is input through the SSMA connector and is LVCMOS level.

3. The co-current clock structure for an ultra-high-speed signal acquisition and processing system according to claim 1, characterized in that, The dual-channel low-jitter clock buffer can output a frequency of up to 650MHz with jitter ≤50fs.

4. The co-current clock structure for an ultra-high-speed signal acquisition and processing system according to claim 1, characterized in that, The dual-loop phase-locked circuit 1 includes two-stage phase-locked loops PLL1 and PLL2 and a clock divider unit; PLL1 performs jitter removal on the input clock, PLL2 generates the core clock, and the clock divider unit routes and divides the core clock of PLL2; the dual-loop phase-locked circuit 2 has a similar structure to the dual-loop phase-locked circuit 1.

5. The co-current clock structure for an ultra-high-speed signal acquisition and processing system according to claim 1, characterized in that, A 12-channel clock buffer is used for clock expansion, with a maximum clock frequency of 1.2GHz, jitter of 54fs, and channel-to-channel difference of 70ps.

6. A clock network configuration method for an ultra-high-speed signal acquisition and processing system, the method being used to configure the same-source clock structure as described in any one of claims 1 to 5, characterized in that, include: S101. Power on the system, load the routing program on the FPGA, load the configuration code on the MCU, and set the maximum number of configuration attempts. S102. Configure parameters for the dual-loop phase-locked circuit 1 and input the signal to the first dual-loop phase-locked circuit; S103. Check whether the dual-loop phase-locked circuit 1 is locked. If yes, proceed to step S104. If no, determine whether the current configuration count exceeds the maximum configuration count. If yes, the configuration is incorrect. Otherwise, return to step S102. S104. Configure the parameters of the dual-loop phase-locked circuit 2 and determine whether the dual-loop phase-locked circuit 2 is locked. If not, proceed to step S105; if yes, proceed to step S106. S105. Determine whether the current configuration count is greater than the maximum configuration count. If not, return to step S104. If yes, the configuration is incorrect. S106. Configure parameters for high-frequency phase-locked loop 1 and determine whether high-frequency phase-locked loop 1 is locked. If not, proceed to step S107; if yes, proceed to step S108. S107. Determine whether the current configuration count is greater than the maximum configuration count. If not, return to step S106. If yes, the configuration is incorrect. S108. Configure parameters for high-frequency phase-locked loop 2 and determine whether high-frequency phase-locked loop 2 is locked. If not, proceed to step S109; if yes, proceed to step S110. S109. Determine whether the current configuration count is greater than the maximum configuration count. If not, return to step S108. If yes, the configuration is incorrect. S110. Configure the parameters for the ultra-high-speed DAC1 and check whether the ultra-high-speed DAC1 has successfully established a link. If not, proceed to step S111; if yes, proceed to step S112. S111. Determine if the current configuration count is greater than the maximum configuration count. If not, return to step S110. If yes, the configuration is incorrect. S112. Configure the parameters of the ultra-high-speed DAC2 and check whether the ultra-high-speed DAC2 has successfully established a link. If not, proceed to step S113; if yes, proceed to step S114. S113. Determine whether the current configuration count is greater than the maximum configuration count. If not, return to step S112. If yes, the configuration is incorrect. S114. Configure the parameters of the ultra-high-speed ADC1 and check whether the ultra-high-speed ADC1 has successfully established a link. If not, proceed to step S115; if yes, proceed to step S116. S115. Determine whether the current configuration count is greater than the maximum configuration count. If not, return to step S114. If yes, the configuration is incorrect. S116. Configure the parameters for the ultra-high-speed ADC2 and check whether the ultra-high-speed ADC2 has successfully established a link. If not, proceed to step S117. If yes, the configuration is complete. S117. Determine whether the current configuration count is greater than the maximum configuration count. If not, return to step S116. If yes, then there is a configuration error.

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