A field programmable logic gate array and a method of stress testing

Abstract

The embodiment of the present specification provides a field programmable logic gate array and a pressure test method, the field programmable logic gate array comprises: an internal memory and a network card; a segment is arranged in the internal memory, and the segment is used for storing a data packet used in a pressure test process; the data packet is stored in the segment; and the network card interacts with a processor through the segment in the pressure test. The technical scheme provided in the present application is used to solve the problem of low precision of the existing pressure test.

Description

Technical Field

[0001] This document relates to the field of network performance testing technology, and in particular to a field-programmable gate array and stress testing method. Background Technology

[0002] Network and security devices, which handle and forward traffic, require network performance testers to simulate real traffic for performance and stability testing. Network performance testers can generate and receive various types of data packets, simulating diverse network communication traffic to perform functional and stress tests on network and network security devices.

[0003] To accurately test packet latency and throughput, traditional test instruments use FPGAs (Field Programmable Gate Arrays) to generate and transmit data packets. Data is generated and transmitted by the FPGA, while the CPU only plays a control role. The advantage of this approach is that the FPGA is self-contained; the generation, transmission, reception, and analysis of data packets are all handled by the FPGA, while the CPU only performs summarization and report analysis.

[0004] Ordinary network cards do not strictly limit the interval between data packets, which makes the data packets they send unevenly, making it difficult to accurately test throughput and microsecond-level latency. This will bring peaks and troughs to the device under test and the link, thus ultimately affecting the test results. Summary of the Invention

[0005] Based on the above analysis, this application aims to propose a field-programmable gate array and a stress testing method to improve testing accuracy.

[0006] In one aspect, one or more embodiments of this specification provide a field-programmable gate array, including internal memory and a network interface card; The internal memory is configured with a segment for storing data packets used in the stress test process; During stress testing, the network card interacts with the processor through the segment.

[0007] Furthermore, the segment includes: a first segment and a second segment; The processor sends a first data packet to the first segment through a preset first segment interface; The processor obtains the second data packet from the second segment through a preset second segment interface.

[0008] Furthermore, the network interface card (NIC) includes a first NIC and a second NIC; The first network interface card (NIC) obtains the first data packet through the first segment interface; The second network card sends the second data packet to the segment through the second segment interface.

[0009] Secondly, one or more embodiments of this specification provide a stress testing method based on network traffic simulation, characterized in that it is based on the field-programmable gate array (FPGA) described in any one of the first aspects, comprising: Obtained by presetting the first segment The first data packet from the processor; Set a first timestamp for the first data packet, and send the first data packet containing the first timestamp to the device under test; Receive the second data packet returned by the device under test; Set a second timestamp for the returned second data packet, and store the second data packet containing the second timestamp into the second segment; A request message for retrieving data is sent to the processor so that the application in the processor can retrieve the second data packet from the second segment.

[0010] Furthermore, the data packets obtained from the application through the first segment include: Detect whether the remaining space of the first segment is less than a first preset value; If the value is less than the first preset value, then a data packet is written to the first segment.

[0011] Furthermore, given the presence of multiple data packets, the method further includes: The transmission interval between the data packets can be set evenly or according to preset rules.

[0012] Further, the transmission to the processor via the second segment includes: Detect whether the remaining space in the second segment is greater than a second preset value; If the value is greater than the second preset value, a request message is sent to the processor.

[0013] Furthermore, the transmission interval of the data packet to be sent is determined based on the remaining space of the second segment, so that the remaining space is greater than a third preset value.

[0014] Thirdly, one or more embodiments of this specification provide a stress testing device based on network traffic simulation, including: an acquisition module, a first sending module, a receiving module, and a second sending module; The acquisition module is used to acquire a first data packet from the application through a preset first segment; The first sending module is used to set a first timestamp on the first data packet and send the first data packet containing the first timestamp to the device under test; The receiving module is used to receive the second data packet returned by the device under test; The second sending module is used to set a second timestamp for the returned second data packet and store the second data packet containing the second timestamp in the second segment; and send a request message to the internal memory to retrieve data so that the application in the internal memory can retrieve the second data packet from the second segment.

[0015] Furthermore, the acquisition module is used to detect whether the remaining space of the first segment is less than a preset value; if it is less than the preset value, a data packet is acquired from the first segment.

[0016] Furthermore, the device also includes a setting module; The setting module is used to uniformly set the transmission interval between each data packet.

[0017] Furthermore, the second sending module is used to detect whether the remaining space in the second segment is greater than a first preset value; if it is greater than the first preset value, the data packet in the second segment is sent to the processor.

[0018] Fourthly, one or more embodiments of this specification provide a storage medium, including: Used to store computer-executable instructions, which, when executed, implement the method described in any of the first aspects.

[0019] Compared with the prior art, this application can achieve at least the following technical effects: In existing technologies, stress testing involves the processor sending data packets. However, due to the instability of the processor's state at any given moment, the processor cannot send data packets at uniform intervals, leading to a decrease in test accuracy. This application addresses this by setting segments within the FPGA, which allows data packets during the test to be grouped together and then uniformly scheduled for transmission, thus ensuring test accuracy. Furthermore, the FPGA's built-in memory allows the packet retrieval interval to be set according to the application's load, facilitating the parsing of data packets returned by the device under test, thereby enriching the evaluation dimensions of the test results and improving evaluation accuracy. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in one or more embodiments of this specification or in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this specification. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1A schematic diagram of an FPGA structure provided for one or more embodiments of this specification; Figure 2 A flowchart illustrating a stress testing method based on network traffic simulation provided for one or more embodiments of this specification; Figure 3 This specification provides a structural schematic diagram of a stress testing device based on network traffic simulation, which is provided for one or more embodiments of this specification. Detailed Implementation

[0022] To enable those skilled in the art to better understand the technical solutions in one or more embodiments of this specification, the technical solutions in one or more embodiments of this specification will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this specification, and not all of the embodiments. Based on one or more embodiments of this specification, all other embodiments obtained by those skilled in the art without creative effort should fall within the protection scope of this document.

[0023] This application provides a field-programmable gate array, including: internal memory and network interface card; A segment is set up in the internal memory to store data packets used during the stress test process; During stress testing, the network card interacts with the processor via segments.

[0024] It should be noted that a segment interface refers to the interface used to receive or send segments. A segment is a unit of memory management used to organize and access data in memory. This memory is physical memory specifically designed for FPGAs.

[0025] Specific examples Figure 1 As shown, The paragraphs include: the first paragraph and the second paragraph; The processor sends the first data packet to the first segment through the preset first segment interface; The processor obtains the second data packet from the second segment through a preset second segment interface.

[0026] Network interface cards (NICs) include a first NIC and a second NIC; The first network interface card obtains the first data packet through the first interface segment; The second network card sends the second data packet through the second interface segment.

[0027] This application provides a stress testing method based on network traffic simulation, using the FPGA described in the foregoing embodiments, such as... Figure 2 As shown, it includes the following steps: Step 1: Obtain the first data packet from the application through the first segment.

[0028] In this embodiment, the FPGA network card communicates with the application program in the internal memory through a preset first segment. The application program is responsible for generating the data packets required for testing and sending these data packets to the FPGA network card through the first segment. The testing phase includes generating and sending data packets. By setting the first segment, the generated data packets are stored together, and a uniform sending interval is set to ensure that data packets are sent evenly.

[0029] Step 2: Set a first timestamp for the data packet and send the first data packet containing the first timestamp to the device under test.

[0030] In this embodiment, after receiving a data packet, the FPGA network card sets a unique first timestamp for each data packet. The timestamp can be the value of a timestamp counter, which is updated in real time within the FPGA. The purpose of setting the timestamp is to accurately record the transmission time of the data packets for performance analysis. After setting the timestamp, the FPGA network card sends the timestamped data packets to the device under test. The device under test can be a network device, security device, or other device requiring performance testing.

[0031] Step 3: Receive the second data packet returned by the device under test.

[0032] In this embodiment, after receiving the data packet, the device under test will perform corresponding processing. This processing may include parsing, forwarding, and storing the data packet. After processing, the device under test will send the processing result (i.e., the returned data packet) to the FPGA.

[0033] Step 4: Set a second timestamp for the returned second data packet, and store the second data packet containing the second timestamp into the second segment.

[0034] In this embodiment, the testing phase includes receiving and sending returned data packets. By setting a second segment, the returned data packets are stored together, and a uniform sending interval is set to ensure even data packet transmission. Furthermore, the timing of sending request information can be selected based on the application's running status. For example, if the application is currently running at near full capacity, request information can be temporarily withheld.

[0035] Step 5: Send a request message to the processor to obtain data, so that the application in the processor can obtain the second data packet from the second segment.

[0036] In this embodiment, after receiving the returned data packets, the FPGA network card also sets a unique second timestamp for each data packet. After setting the timestamp, the FPGA network card sends the second data packet containing the timestamp to the application in the internal memory via a second segment. After receiving the returned data packets, the application performs performance analysis based on the timestamps. Performance analysis may include the calculation and evaluation of metrics such as data packet latency, throughput, and packet loss rate. Because segments are set in the FPGA, data packets can be parsed when the application load is low, thereby improving testing efficiency.

[0037] It should be noted that, in the embodiments of this application, "first" and "second" are only used to distinguish between the sent data packets and the returned data packets.

[0038] In this embodiment, the FPGA performs a data packet acquisition operation once within a preset period. To further improve the efficiency of data packet acquisition, the remaining space of the first segment is first detected. When the remaining space of the first segment is less than a preset value, the FPGA directly acquires the data packet from the first segment, regardless of whether the current acquisition operation is within the preset period. This ensures that the FPGA does not cause overflow or waste of the first segment when acquiring data packets. In addition, the capacity of the first segment can be dynamically adjusted. For example, in small packet test scenarios (such as 64-byte data packets): the capacity of the first segment is 4KB, supporting fast writing. In large packet test scenarios (such as 1500-byte data packets), the capacity of the first segment is expanded to 16KB to reduce frequent switching overhead.

[0039] Specifically, it detects whether the remaining space of the first segment is less than a first preset value; When the value is less than the first preset value, the data packet is obtained from the first segment.

[0040] Preferably, if the first segment frequently triggers the first threshold, the FPGA automatically expands the capacity of the first segment by 50%, up to a maximum of the physical memory limit. When the utilization rate of the first segment is lower than a preset value, the capacity of the first segment is reduced.

[0041] In this embodiment, a mechanism for uniformly setting data packet transmission intervals is adopted to improve the accuracy of the test. When the processor generates data packets, it calculates the transmission interval between each data packet based on factors such as test requirements and the type and size of the data packets, and sends this interval information to the FPGA.

[0042] When sending data packets, the FPGA sets the transmission interval between each data packet evenly or according to certain rules based on the received transmission interval information or rules. This ensures a stable data packet transmission rate during testing, thereby improving the accuracy of the test.

[0043] For example, the Poisson distribution model can be chosen to calculate the data packet transmission interval, which is suitable for simulating the randomness of real network traffic. Alternatively, a uniform distribution model can be chosen, which is suitable for stability testing, where the interval is a fixed value.

[0044] In this embodiment, the FPGA performs a request to the processor once within a preset period, so that the processor can obtain data packets from the second segment of the FPGA. To further improve the efficiency of data packet transmission, the remaining space of the second segment is first detected. When the remaining space of the second segment is less than a preset value, the FPGA directly sends a request to the CPU, regardless of whether the current transmission operation is within the preset period. This ensures that the FPGA does not cause overflow or waste of the second segment when transmitting data packets. In addition, the capacity of the second segment can be dynamically adjusted. For example, in small packet test scenarios (such as 64-byte data packets): the capacity of the second segment is 4KB, supporting fast writing. In large packet test scenarios (such as 1500-byte data packets), the capacity of the second segment is expanded to 16KB to reduce frequent switching overhead.

[0045] The specific process of sending data packets to the processor is as follows: Detect whether the remaining space in the second segment is greater than a second preset value; If the value is greater than the second preset value, the data packet in the second segment will be sent to the processor.

[0046] Preferably, during the process of sending data packets to the processor, in order to prevent the second segment of data packets from reaching the upper limit, the transmission interval of the data packets to be sent is determined based on the remaining space of the second segment, so that the remaining space is greater than a third preset value. For example, based on the current remaining space and the third preset value, and based on the current transmission interval, it is calculated whether the second segment will be filled; if so, the transmission interval is reduced.

[0047] This application provides a stress testing device based on network traffic simulation, such as... Figure 3 As shown, it includes: an acquisition module 301, a first sending module 302, a receiving module 303, and a second sending module 304; The acquisition module 301 is used to acquire data packets from the application through a preset first segment; The first sending module 302 is used to set a first timestamp on the data packet and send the data packet containing the first timestamp to the device under test; The receiving module 303 is used to receive data packets returned by the device under test; The second sending module 304 is used to set a second timestamp on the returned data packet and store the data packet containing the second timestamp in the second segment; and send a request message to the internal memory to obtain data so that the application in the internal memory can obtain the second data packet from the second segment.

[0048] This application provides a storage medium, including: Used to store computer-executable instructions, which, when executed, implement the method described in any of the above embodiments.

[0049] The foregoing has described specific embodiments of this specification. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recited in the claims may be performed in a different order than that shown in the embodiments and may still achieve the desired result. Furthermore, the processes depicted in the drawings do not necessarily require the specific or sequential order shown to achieve the desired result. In some embodiments, multitasking and parallel processing are possible or may be advantageous.

[0050] In the 1930s, improvements to a technology could be clearly distinguished as either hardware improvements (e.g., improvements to the circuit structure of diodes, transistors, switches, etc.) or software improvements (improvements to the methodology). However, with technological advancements, many improvements to the methodology today can be considered direct improvements to the hardware circuit structure. Designers almost always obtain the corresponding hardware circuit structure by programming the improved methodology into the hardware circuit. Therefore, it cannot be said that an improvement to the methodology cannot be implemented using a hardware physical module. For example, a Programmable Logic Device (PLD) (such as a Field Programmable Gate Array (FPGA)) is such an integrated circuit whose logic function is determined by the user programming the device. Designers can program a digital methodology "integrated" onto a PLD themselves, without needing chip manufacturers to design and manufacture dedicated integrated circuit chips. Furthermore, nowadays, instead of manually manufacturing integrated circuit chips, this programming is mostly implemented using "logic compiler" software. Similar to the software compiler used in program development, the original code before compilation must also be written in a specific programming language, called a Hardware Description Language (HDL). There are many HDLs, such as ABEL (Advanced Boolean Expression Language), AHDL (Altera Hardware Description Language), Confluence, CUPL (Cornell University Programming Language), HDCal, JHDL (Java Hardware Description Language), Lava, Lola, MyHDL, PALASM, and RHDL (Ruby Hardware Description Language). Currently, the most commonly used are VHDL (Very-High-Speed ​​Integrated Circuit Hardware Description Language) and Verilog. Those skilled in the art should also understand that by simply performing some logic programming on the method flow using one of these hardware description languages ​​and programming it into an integrated circuit, the hardware circuit implementing the logical method flow can be easily obtained.

[0051] The controller can be implemented in any suitable manner. For example, it can take the form of a microprocessor or processor and a computer-readable medium storing computer-readable program code (e.g., software or firmware) executable by the (micro)processor, logic gates, switches, application-specific integrated circuits (ASICs), programmable logic controllers, and embedded microcontrollers. Examples of controllers include, but are not limited to, the following microcontrollers: ARC 625D, Atmel AT91SAM, Microchip PIC18F26K20, and Silicon Labs C8051F320. A memory controller can also be implemented as part of the control logic of the memory. Those skilled in the art will also recognize that, in addition to implementing the controller in purely computer-readable program code form, the same functionality can be achieved by logically programming the method steps to make the controller take the form of logic gates, switches, application-specific integrated circuits, programmable logic controllers, and embedded microcontrollers. Therefore, such a controller can be considered a hardware component, and the means included therein for implementing various functions can also be considered as structures within the hardware component. Alternatively, the means for implementing various functions can be considered as both software modules implementing the method and structures within the hardware component.

[0052] The methods, apparatus, modules, or units described in the above embodiments can be implemented by a computer chip or entity, or by a product with a certain function. A typical implementation device is a computer. Specifically, the computer can be, for example, a personal computer, laptop computer, cellular phone, camera phone, smartphone, personal digital assistant, media player, navigation device, email device, game console, tablet computer, wearable device, or any combination of these devices.

[0053] For ease of description, the above apparatus is described by dividing it into various functional units. Of course, when implementing the embodiments of this specification, the functions of each unit can be implemented in one or more software and / or hardware.

[0054] Those skilled in the art will understand that one or more embodiments of this specification can be provided as a method, method, or computer program product. Therefore, one or more embodiments of this specification may take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this specification may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0055] This specification is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (methods), and computer program products according to embodiments of this specification. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create a machine for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0056] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0057] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0058] In a typical configuration, a computing device includes one or more processors (CPU), input / output interfaces, network interfaces, and memory.

[0059] Memory may include non-persistent storage in computer-readable media, such as random access memory (RAM) and / or non-volatile memory, such as read-only memory (ROM) or flash RAM. Memory is an example of computer-readable media.

[0060] Computer-readable media includes both permanent and non-permanent, removable and non-removable media that can store information using any method or technology. Information can be computer-readable instructions, data structures, modules of programs, or other data. Examples of computer storage media include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, CD-ROM, digital versatile optical disc (DVD) or other optical storage, magnetic tape, magnetic magnetic disk storage or other magnetic storage devices, or any other non-transferable medium that can be used to store information accessible by a computing device. As defined herein, computer-readable media does not include transient computer-readable media, such as modulated data signals and carrier waves.

[0061] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0062] One or more embodiments of this specification can be described in the general context of computer-executable instructions, such as program modules, that are executed by a computer. Generally, program modules include routines, programs, objects, components, data structures, etc., that perform a particular task or implement a particular abstract data type. One or more embodiments of this specification can also be practiced in distributed computing environments where tasks are performed by remote processing devices connected via a communication network. In distributed computing environments, program modules can reside in local and remote computer storage media, including storage devices.

[0063] The various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to interchangeably. Each embodiment focuses on describing the differences from other embodiments. In particular, the method embodiments are basically similar to the method embodiments, so the description is relatively simple; relevant parts can be referred to the descriptions of the method embodiments.

[0064] The above description is merely an embodiment of this document and is not intended to limit the scope of this document. Various modifications and variations can be made to this document by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this document should be included within the scope of the claims of this document.

Claims

1. A field-programmable gate array, characterized in that, include: Internal memory and network card; The internal memory is configured with a segment for storing data packets used in the stress test process; During stress testing, the network card interacts with the processor through the segment; The segment includes: a first segment and a second segment; wherein, the first segment is used to enable the network card to obtain a first data packet from the processor when the remaining space is less than a first preset value, and the second segment is used to send a request message to the processor to obtain data when the remaining space is less than a second preset value, so that the application in the processor can obtain a second data packet from the second segment; the capacity of the first segment and the second segment can be dynamically adjusted according to the data packet size; The processor sends a first data packet to the first segment through a preset first segment interface; wherein, when there are multiple data packets, the sending interval of each data packet is set by selecting a Poisson distribution model or a uniform distribution model; The processor obtains the second data packet from the second segment through a preset second segment interface; wherein the second data packet is returned by the device under test and is set with a second timestamp; the second segment stores the second data packet containing the second timestamp; The network interface card includes a first network interface card and a second network interface card; The first network card obtains the first data packet through the first segment interface and sets a first timestamp on the first data packet to send the first data packet containing the first timestamp to the device under test; The second network card sends the second data packet to the second segment through the second segment interface; wherein, during the sending of the data packet, the sending interval of the data packet to be sent is determined according to the remaining space of the second segment, so that the remaining space is greater than a third preset value.

2. A stress testing method based on network traffic simulation, characterized in that, Based on the field-programmable gate array of claim 1, it includes: The remaining space of the first segment is checked to see if it is less than a first preset value. If it is less than the first preset value, a first data packet from the processor is obtained from the first segment. The capacity of the first segment can be dynamically adjusted according to the size of the data packet. Set a first timestamp for the first data packet, and send the first data packet containing the first timestamp to the device under test; When there are multiple data packets, either a Poisson distribution model or a uniform distribution model is selected to set the transmission interval between each data packet. Receive the second data packet returned by the device under test; A second timestamp is set on the returned second data packet, and the second data packet containing the second timestamp is stored in the second segment; wherein the capacity of the second segment can be dynamically adjusted according to the data packet size; The remaining space in the second segment is detected to be less than a second preset value. If it is less than the second preset value, a request for data acquisition is sent to the processor so that the application in the processor can acquire the second data packet from the second segment. During the process of sending data packets to the processor, the sending interval of the data packets to be sent is determined based on the remaining space of the second segment, so that the remaining space is greater than a third preset value.

3. A stress testing device based on network traffic simulation, characterized in that, include: Acquisition module, first sending module, receiving module, and second sending module; The acquisition module is used to acquire a first data packet from the processor from the first segment when it detects that the remaining space of the preset first segment is less than a first preset value; wherein, the capacity of the first segment can be dynamically adjusted according to the size of the data packet; The first sending module is used to set a first timestamp on the first data packet and send the first data packet containing the first timestamp to the device under test; When there are multiple data packets, either a Poisson distribution model or a uniform distribution model is selected to set the transmission interval between each data packet. The receiving module is used to receive the second data packet returned by the device under test; The second sending module is used to set a second timestamp for the returned second data packet and store the second data packet containing the second timestamp in a second segment; wherein, the capacity of the second segment can be dynamically adjusted according to the data packet size; when it is detected that the remaining space in the second segment is less than a second preset value, a request message for obtaining data is sent to the processor so that the application in the processor can obtain the second data packet from the second segment; during the process of sending data packets to the processor, the sending interval of the data packets to be sent is determined according to the remaining space in the second segment so that the remaining space is greater than a third preset value.

4. A storage medium, characterized in that, include: Used to store computer-executable instructions, which, when executed, implement the method of claim 2.

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