Packet receiving method and packet sending method

Abstract

The embodiment of the application provides a message receiving method and a message sending method, and relates to the fields of message transmission technology and the like. The method comprises the following steps: storing a first message by an FPGA and updating a current value of a head pointer of a first queue; when a current value of a tail pointer of the first queue is different from the current value of the head pointer, determining the first message by a CPU, processing the first message according to a length and an RSS value, and updating the current value of the tail pointer. According to the method, the current value of the tail pointer is different from the current value of the head pointer, the FPGA stores the first message, a write completion flag bit of the FPGA is not needed, PCIE bandwidth can be reduced, and the time delay of receiving the message is reduced.

Description

Technical Field

[0001] This application relates to fields such as message transmission technology, and in particular to a message receiving method and a message sending method. Background Technology

[0002] Currently, message receiving devices can perform message receiving and processing based on heterogeneous computing using a central processing unit (CPU) and a field-programmable gate array (FPGA).

[0003] In related technologies, a Field-Programmable Gate Array (FPGA) receives a message and stores it in the storage area corresponding to the message's physical address. Then, it stores a write-complete flag in the descriptor corresponding to the physical address of the descriptor. When the Central Processing Unit (CPU) detects the write-complete flag, it processes the message.

[0004] In the above technology, the FPGA stores the write completion flag in the descriptor corresponding to the physical address of the descriptor, which will occupy the bandwidth of the high-speed serial computer extended bus standard (Peripheral Component Interconnect Express, PCIE) and result in high latency in receiving messages. Summary of the Invention

[0005] This application provides a message receiving method and a message sending method to reduce the PCIe bandwidth usage and lower the latency of message reception.

[0006] In a first aspect, embodiments of this application provide a message receiving method applied to a first device, the first device including a central processing unit (CPU) and a field-programmable gate array (FPGA), the method comprising:

[0007] The FPGA receives a first message from the second device based on the physical address of the descriptor; the physical address of the descriptor is the physical address of the descriptor indicated by the current value of the head pointer of the first queue.

[0008] The FPGA stores the parsing information of the first message and the first message according to the physical address of the descriptor, and updates the current value of the head pointer of the first queue.

[0009] When the CPU determines that the current value of the tail pointer of the first queue is different from the current value of the head pointer, the CPU obtains the first message and the parsing information based on the physical address of the descriptor indicated by the current value of the tail pointer.

[0010] The CPU processes the first message according to the parsed information and updates the current value of the tail pointer; after the update, the current value of the tail pointer is the same as the current value of the head pointer.

[0011] In this scheme, after storing the first message via the FPGA, the FPGA updates the current value of the head pointer of the first queue. When the CPU determines that the current value of the tail pointer of the first queue is different from the current value of the head pointer, the CPU retrieves the first message. This achieves the goal of indicating that the FPGA has stored the first message by the difference between the current values ​​of the tail pointer and the head pointer. The FPGA does not need to store a write-complete flag in the descriptor corresponding to the physical address of the descriptor, which reduces the PCIe bandwidth usage and lowers the latency of receiving messages. In contrast, in related technologies, the FPGA needs to store a write-complete flag in the descriptor corresponding to the physical address of the descriptor, which leads to a larger PCIe bandwidth usage and higher latency of receiving messages.

[0012] In some embodiments, storing the parsing information of the first packet and the first packet via the FPGA according to the physical address of the descriptor includes:

[0013] The FPGA is used to determine the descriptor corresponding to the physical address of the descriptor.

[0014] The parsed information is stored in the descriptor corresponding to the physical address of the descriptor via the FPGA.

[0015] The packet physical address is obtained from the descriptor corresponding to the physical address of the descriptor through the FPGA;

[0016] The storage area corresponding to the physical address of the message is determined by the FPGA;

[0017] The first message is stored in the storage area corresponding to the physical address of the message using the FPGA.

[0018] In some embodiments, the method further includes:

[0019] The CPU allocates at least one descriptor physical address and at least one packet physical address in a continuous sequence, wherein the at least one descriptor physical address is associated with the at least one packet physical address, the at least one descriptor physical address includes the descriptor physical address, and the at least one packet physical address includes the packet physical address;

[0020] For one of the at least one descriptor physical addresses and the packet physical address associated with the descriptor physical address, the CPU stores the descriptor physical address and the packet physical address associated with the descriptor physical address into the descriptor corresponding to the descriptor physical address.

[0021] The CPU writes the physical address of at least one descriptor into the FPGA.

[0022] In some embodiments, after allocating the at least one descriptor physical address and at least one packet physical address consecutively via the CPU, the method further includes:

[0023] Initialize the first and second queues;

[0024] After initialization, the first queue and the second queue store the physical address of at least one descriptor. The current value of the head pointer and the tail pointer of the first queue is a first preset value, and the current value of the pointer of the second queue is the first preset value. The current value of the head pointer and the tail pointer of the first queue is used by the CPU to determine whether the first device has received the first message. The current value of the pointer of the second queue and the current value of the head pointer are used to indicate whether to release descriptors in batches.

[0025] In some embodiments, the method further includes:

[0026] When the CPU determines that the current value of the first pointer is equal to a multiple of the first number, if the current value of the pointer of the second queue is not the same as the current value of the first pointer, then the packet physical addresses in the descriptors corresponding to the first number of physical addresses of the target descriptor are released in batch; wherein, the target descriptor is the descriptor corresponding to the physical address of the descriptor currently pointed to by the first pointer;

[0027] The CPU rewrites the new packet physical address in each of the first number of descriptors, updating the current value of the pointer of the second queue to the current value of the first pointer; the current value of the pointer of the second queue is used to indicate whether to release the packet physical addresses in the first number of descriptors in batches.

[0028] In this scheme, if the CPU determines that the current value of the first pointer is equal to a multiple of the first number, and the current value of the pointer in the second queue is different from the current value of the first pointer, it releases the packet physical addresses in the descriptors corresponding to the first number of physical addresses before the target descriptor in batches. This helps to rewrite the new packet physical address in each of the first number of descriptors without releasing the descriptor physical addresses in the descriptors corresponding to the first number of physical addresses, thus improving the efficiency of release and rewriting, thereby reducing the PCIe bandwidth occupied and reducing the latency of receiving packets. In related technologies, before the FPGA stores the write completion flag in the descriptor corresponding to the descriptor physical address, the descriptor physical address and the packet physical address are already stored in the descriptor. Since the amount of data that a descriptor can carry is limited, the write-complete flag will occupy the physical address of the descriptor, causing the physical address of the descriptor to be incorrect. Therefore, during batch release, the physical address of the descriptor, the physical address of the message, etc., must be released in order to restore the physical address of the descriptor, the new physical address of the message, etc. This results in low efficiency of release and rewriting, which in turn leads to a large occupation of PCIe bandwidth and high latency in receiving messages.

[0029] Secondly, embodiments of this application provide a message transmission method applied to a first device, the first device including a CPU and an FPGA, the method including:

[0030] The FPGA obtains the packet physical address associated with the descriptor physical address and the length of the first packet based on the descriptor physical address; the descriptor physical address is the descriptor physical address indicated by the current value of the head pointer of the first queue.

[0031] The FPGA obtains the first message based on the message's physical address and length, and updates the current value of the first queue's head pointer.

[0032] When the CPU determines that the current value of the tail pointer of the first queue is different from the current value of the head pointer, the CPU controls the FPGA to send the acquired first message to the second device according to the physical address of the descriptor, and update the current value of the tail pointer; after the update, the current value of the tail pointer is the same as the current value of the head pointer.

[0033] In this scheme, after acquiring the first message via the FPGA, the FPGA updates the current value of the head pointer of the first queue. When the CPU determines that the current value of the tail pointer is different from the current value of the head pointer, the CPU controls the FPGA to send the acquired first message to the second device. This achieves the goal of indicating that the FPGA has acquired and stored the first message by showing that the current values ​​of the tail pointer and the head pointer are different. The FPGA does not need to store a read completion flag in the descriptor corresponding to the physical address of the descriptor, which reduces the PCIe bandwidth occupied and lowers the message transmission latency. In contrast, in related technologies, the FPGA needs to store a read completion flag in the descriptor corresponding to the physical address of the descriptor, which leads to a larger PCIe bandwidth occupation and higher message transmission latency.

[0034] In some embodiments, obtaining the packet physical address associated with the descriptor physical address and the length of the first packet through the FPGA based on the descriptor physical address includes:

[0035] The FPGA is used to determine the descriptor corresponding to the physical address of the descriptor.

[0036] The FPGA obtains the packet physical address associated with the physical address of the descriptor and the length of the first packet from the descriptor corresponding to the physical address of the descriptor.

[0037] In some embodiments, obtaining the first packet via the FPGA based on the packet's physical address and length includes:

[0038] The storage area corresponding to the physical address of the message is determined by the FPGA;

[0039] The FPGA retrieves the first message from the storage area corresponding to the message's physical address based on the length.

[0040] In some embodiments, the method further includes:

[0041] The CPU allocates at least one descriptor physical address and at least one packet physical address in a continuous sequence, wherein the at least one descriptor physical address is associated with the at least one packet physical address, the at least one descriptor physical address includes the descriptor physical address, and the at least one packet physical address includes the packet physical address;

[0042] For one of the at least one descriptor physical addresses and the packet physical address associated with the descriptor physical address, the CPU stores the descriptor physical address, the packet physical address associated with the descriptor physical address, and the length of the first packet into the descriptor corresponding to the descriptor physical address.

[0043] The CPU writes the physical address of at least one descriptor into the FPGA.

[0044] In some embodiments, after allocating the at least one descriptor physical address and at least one packet physical address consecutively via the CPU, the method further includes:

[0045] Initialize the first and second queues;

[0046] After initialization, the first queue and the second queue store the physical address of the at least one descriptor. The current value of the head pointer and the tail pointer of the first queue is a first preset value, and the current value of the pointer of the second queue is the first preset value. The current value of the head pointer and the tail pointer of the first queue is used by the CPU to determine whether the first device sends the first message, and the current value of the pointer of the second queue is used to indicate whether to release the descriptors corresponding to the physical addresses of the descriptors in batches.

[0047] In some embodiments, the method further includes: when the CPU determines that the current value of the first pointer is equal to a multiple of a first number, if the current value of the pointer of the second queue is not the same as the current value of the first pointer, then the packet physical address in the descriptor corresponding to the physical address of the first number of descriptors before the target descriptor, and the length of the first packet are released in batch; wherein, the target descriptor is the descriptor corresponding to the physical address of the descriptor currently pointed to by the first pointer;

[0048] The CPU rewrites the new packet physical address and the new packet length in each of the first number of descriptors, updating the current value of the pointer of the second queue to the current value of the first pointer; the current value of the pointer of the second queue is used to indicate whether to release the packet physical address and the length of the first packet in the first number of descriptors in batch.

[0049] In this scheme, if the CPU determines that the current value of the first pointer is equal to a multiple of the first number, and the current value of the pointer in the second queue is different from the current value of the first pointer, it releases the packet physical address and the length of the first packet in the descriptors corresponding to the first number of physical addresses before the target descriptor. This helps to rewrite the new packet physical address and the new packet length in each of the first number of descriptors without releasing the descriptor physical addresses in the descriptors corresponding to the first number of physical addresses, thus improving the efficiency of release and rewriting, thereby reducing the PCIe bandwidth occupied and reducing the latency of receiving packets. In related technologies, before the FPGA stores the write completion flag in the descriptor corresponding to the descriptor physical address, the descriptor physical address, the packet physical address, and the length of the first packet are already stored in the descriptor. Since the amount of data that a descriptor can carry is limited, the write-complete flag will occupy the physical address of the descriptor, causing the physical address of the descriptor to be incorrect. Therefore, during batch release, the physical address of the descriptor, the physical address of the message, etc., must be released in order to restore the physical address of the descriptor, the new physical address of the message, etc. This results in low efficiency of release and rewriting, which in turn leads to a large occupation of PCIe bandwidth and high latency in sending messages.

[0050] Thirdly, embodiments of this application provide a message transmission apparatus applied to a first device, the apparatus comprising:

[0051] The first processing module is configured to receive a first message from the second device based on the physical address of the descriptor; the physical address of the descriptor is the physical address of the descriptor indicated by the current value of the head pointer of the first queue.

[0052] The first processing module is further configured to store the parsing information of the first packet and the first packet according to the physical address of the descriptor, and update the current value of the head pointer of the first queue.

[0053] The second processing module is used to obtain the packet physical address and the parsing information based on the physical address of the descriptor indicated by the current value of the tail pointer of the first queue when it is determined that the current value of the tail pointer of the first queue is different from the current value of the head pointer.

[0054] The second processing module is further configured to obtain the first packet according to the packet physical address, process the first packet according to the parsing information, and update the current value of the tail pointer; after the update, the current value of the tail pointer is the same as the current value of the head pointer.

[0055] The message receiving device provided in this application embodiment can execute the technical solution shown in the above method embodiment. Its implementation principle and beneficial effects are similar, and will not be described again here.

[0056] In some embodiments, the first processing module is specifically used for:

[0057] The FPGA is used to determine the descriptor corresponding to the physical address of the descriptor.

[0058] The parsed information is stored in the descriptor corresponding to the physical address of the descriptor via the FPGA.

[0059] The packet physical address is obtained from the descriptor corresponding to the physical address of the descriptor through the FPGA;

[0060] The storage area corresponding to the physical address of the message is determined by the FPGA;

[0061] The first message is stored in the storage area corresponding to the physical address of the message using the FPGA.

[0062] In some embodiments, the second processing module is further configured to:

[0063] The CPU allocates at least one descriptor physical address and at least one packet physical address in a continuous sequence, wherein the at least one descriptor physical address is associated with the at least one packet physical address, the at least one descriptor physical address includes the descriptor physical address, and the at least one packet physical address includes the packet physical address;

[0064] For one of the at least one descriptor physical addresses and the packet physical address associated with the descriptor physical address, the CPU stores the descriptor physical address and the packet physical address associated with the descriptor physical address into the descriptor corresponding to the descriptor physical address.

[0065] The CPU writes the physical address of at least one descriptor into the FPGA.

[0066] In some embodiments, the second processing module is further configured to: initialize the first queue and the second queue;

[0067] After initialization, the first queue and the second queue store the physical address of at least one descriptor. The current value of the head pointer and the tail pointer of the first queue is a first preset value, and the current value of the pointer of the second queue is the first preset value. The current value of the head pointer and the tail pointer of the first queue is used by the CPU to determine whether the first device has received the first message. The current value of the pointer of the second queue and the current value of the head pointer are used to indicate whether to release descriptors in batches.

[0068] In some embodiments, the second processing module is further configured to:

[0069] When the CPU determines that the current value of the first pointer is equal to a multiple of the first number, if the current value of the pointer of the second queue is not the same as the current value of the first pointer, then the packet physical addresses in the descriptors corresponding to the first number of physical addresses of the target descriptor are released in batch; wherein, the target descriptor is the descriptor corresponding to the physical address of the descriptor currently pointed to by the first pointer;

[0070] The CPU rewrites the new packet physical address in each of the first number of descriptors, updating the current value of the pointer of the second queue to the current value of the first pointer; the current value of the pointer of the second queue is used to indicate whether to release the packet physical addresses in the first number of descriptors in batches.

[0071] The message receiving device provided in this application embodiment can execute the technical solution shown in the above method embodiment. Its implementation principle and beneficial effects are similar, and will not be described again here.

[0072] Fourthly, embodiments of this application provide a message sending apparatus applied to a first device, the apparatus comprising:

[0073] The first processing module is used to obtain the packet physical address associated with the descriptor physical address and the length of the first packet based on the descriptor physical address; the descriptor physical address is the descriptor physical address indicated by the current value of the head pointer of the first queue;

[0074] The first processing module is used to obtain the first packet according to the packet physical address and the length, and update the current value of the head pointer of the first queue;

[0075] The second processing module is configured to, when determining that the current value of the tail pointer of the first queue is different from the current value of the head pointer, control the first processing module to send the acquired first message to the second device according to the physical address of the descriptor, and update the current value of the tail pointer; after the update, the current value of the tail pointer is the same as the current value of the head pointer.

[0076] The message sending device provided in this application embodiment can execute the technical solution shown in the above method embodiment. Its implementation principle and beneficial effects are similar, and will not be described again here.

[0077] In some embodiments, the first processing module is specifically used to: determine the descriptor corresponding to the physical address of the descriptor; and obtain the packet physical address associated with the physical address of the descriptor and the length of the first packet from the descriptor corresponding to the physical address of the descriptor.

[0078] In some embodiments, the first processing module is specifically used to: determine the storage area corresponding to the physical address of the message; and obtain the first message from the storage area corresponding to the physical address of the message according to the length.

[0079] In some embodiments, the second processing module is further configured to:

[0080] Allocate at least one consecutive descriptor physical address and at least one packet physical address, wherein the at least one descriptor physical address is associated with the at least one packet physical address, the at least one descriptor physical address includes the descriptor physical address, and the at least one packet physical address includes the packet physical address;

[0081] For one of the at least one descriptor physical addresses and the packet physical address associated with the descriptor physical address, the descriptor physical address, the packet physical address associated with the descriptor physical address, and the length of the first packet are stored in the descriptor corresponding to the descriptor physical address.

[0082] Write the physical address of the at least one descriptor into the first processing module.

[0083] In some embodiments, after allocating the at least one descriptor physical address and the at least one packet physical address consecutively, the second processing module is further configured to: initialize the first queue and the second queue;

[0084] After initialization, the first queue and the second queue store the physical address of at least one descriptor. The current value of the head pointer and the tail pointer of the first queue is a first preset value, and the current value of the pointer of the second queue is the first preset value. The current value of the head pointer and the tail pointer of the first queue is used by the second processing module to determine whether the first device sends the first message, and the current value of the pointer of the second queue is used to indicate whether to release the descriptors corresponding to the physical addresses of the descriptors in batches.

[0085] In some embodiments, the second processing module is further configured to:

[0086] When the current value of the first pointer is determined to be equal to a multiple of the first number, if the current value of the pointer of the second queue is not the same as the current value of the first pointer, then the packet physical address in the descriptor corresponding to the physical address of the first number of descriptors before the target descriptor is released in batch, as well as the length of the first packet; wherein, the target descriptor is the descriptor corresponding to the physical address of the descriptor currently pointed to by the first pointer;

[0087] In each of the first number of descriptors, a new packet physical address and a new packet length are rewritten, and the current value of the pointer of the second queue is updated to the current value of the first pointer; the current value of the pointer of the second queue is used to indicate whether to release the packet physical address and the length of the first packet in the first number of descriptors in batch.

[0088] The message sending device provided in this application embodiment can execute the technical solution shown in the above method embodiment. Its implementation principle and beneficial effects are similar, and will not be described again here.

[0089] Fifthly, this application provides an electronic device, including: a processor, and a memory communicatively connected to the processor;

[0090] The memory stores the instructions that the computer executes;

[0091] The processor executes computer-executable instructions stored in memory to implement methods such as the first aspect and / or the second aspect.

[0092] The electronic device provided in this application embodiment can execute the technical solution shown in the above method embodiment. Its implementation principle and beneficial effects are similar, and will not be repeated here.

[0093] Sixthly, embodiments of this application provide a computer-readable storage medium storing computer-executable instructions, which, when executed by a processor, are used to implement the methods as described in the first and / or second aspects.

[0094] When the computer-executable instructions in the computer-readable storage medium provided in this application are executed by a processor, the technical solutions shown in the above method embodiments can be implemented. The implementation principle and beneficial effects are similar, and will not be repeated here.

[0095] In a seventh aspect, this application provides a computer program product, including a computer program that, when executed by a processor, implements the methods of the first and / or second aspects.

[0096] When the computer program in the computer program product provided in this application is executed by a processor, it can implement the technical solution shown in the above method embodiments. The implementation principle and beneficial effects are similar, and will not be repeated here. Attached Figure Description

[0097] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0098] Figure 1This application provides a mapping between physical addresses and descriptors in its embodiments.

[0099] Figure 2 This describes the CPU's processing flow when receiving messages in related technologies.

[0100] Figure 3 This describes the CPU processing flow when sending messages in related technologies.

[0101] Figure 4 A flowchart illustrating a message receiving method provided in this application embodiment. Figure 1 ;

[0102] Figure 5 A flowchart illustrating a message receiving method provided in this application embodiment. Figure 2 ;

[0103] Figure 6 A flowchart illustrating a message receiving method provided in this application embodiment. Figure 3 ;

[0104] Figure 7 A flowchart illustrating a message receiving method provided in this application embodiment. Figure 4 ;

[0105] Figure 8 A flowchart illustrating a message sending method provided in this application embodiment. Figure 1 ;

[0106] Figure 9 A flowchart illustrating a message sending method provided in this application embodiment. Figure 2 ;

[0107] Figure 10 A flowchart illustrating a message sending method provided in this application embodiment. Figure 3 ;

[0108] Figure 11 A flowchart illustrating a message sending method provided in this application embodiment. Figure 4 ;

[0109] Figure 12 This is a schematic diagram of the structure of a message transmission device provided in an embodiment of this application;

[0110] Figure 13 This is a structural diagram of an electronic device provided in an embodiment of this application.

[0111] The accompanying drawings illustrate specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concept of this application to those skilled in the art through reference to particular embodiments. Detailed Implementation

[0112] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0113] Definitions:

[0114] High-speed serial computer expansion bus standard (Peripheral Component Interconnect Express, PCIE) bandwidth: PCIE is a high-speed serial computer expansion bus standard used to connect various components inside a device. The CPU and FPGA will both occupy PCIE bandwidth when storing or retrieving data from the device.

[0115] Transaction Layer Packet (TLP): TLP is a data encapsulation format used in PCIe at the transaction layer. In PCIe, messages are not transmitted as a continuous data stream, but are segmented into individual TLPs for transmission.

[0116] TLP-based small packet transmission method: In this method, the maximum payload length of TLP is small, and the amount of data carried by each TLP is small. If the amount of data in the message to be transmitted is large, the message will be divided into multiple smaller data messages, and then multiple smaller data messages will be transmitted through multiple TLPs.

[0117] Large packet transmission method based on TLP: In this method, by increasing the maximum payload length of TLP, the amount of data carried by each TLP is larger. For large data packets, there is no need to split them, and they can be transmitted through a single TLP.

[0118] Direct Memory Access (DMA): Allows FPGAs to store or retrieve data directly in the memory of the first device without CPU intervention.

[0119] In the embodiments of the present application, terms such as "first" and "second" are used to distinguish identical or similar items that have substantially the same functions and effects. For example, a first numerical value and a second numerical value are only used to distinguish different numerical values, and do not limit their sequential order. Those skilled in the art can understand that terms such as "first" and "second" do not limit the quantity or execution sequence, and such terms do not necessarily mean that the items are different.

[0120] It should be noted that in the embodiments of the present application, words such as "exemplarily" or "for example" are used to denote examples, illustrations or descriptions. Any embodiment or design solution described as "exemplarily" or "for example" in the present application shall not be construed as being more preferred or advantageous than other embodiments or design solutions. Rather, the use of "exemplarily" or "for example" is intended to present related concepts in a specific manner.

[0121] In the embodiments of the present application, "at least one" refers to one or more, and "a plurality of" refers to two or more. "And / or" describes an association relationship between associated objects, indicating that three relationships may exist. For example, A and / or B may represent: the presence of A alone, the simultaneous presence of A and B, and the presence of B alone, where A and B may be singular or plural. The character " / " generally indicates that the associated objects before and after are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of a single item or a plurality of items. For example, at least one of a, b, or c may represent: a, b, c, a-b, a-c, b-c, or a-b-c, where a, b, and c may be individual or a plurality thereof.

[0122] With the development of the mobile Internet, innovative breakthroughs continue to emerge in applications such as autonomous driving and artificial intelligence, the scale of data to be processed is growing exponentially, and processors in devices need to have more powerful data processing capabilities to ensure that a large amount of data can be efficiently processed and transmitted in a short period of time.

[0123] Currently, a dual-processor configuration integrating a Central Processing Unit (CPU) and a Field-Programmable Gate Array (FPGA) can be integrated in a device, and packets can be processed efficiently through cooperative processing of the packets by the CPU and the FPGA.

[0124] In related technologies, Direct Memory Access (DMA) technology enables the CPU and FPGA to directly access the memory of the first device, thereby achieving collaborative processing of received messages by the CPU and FPGA. Specifically, the CPU and FPGA directly interact with the descriptors corresponding to the physical addresses of the descriptors in memory and the storage areas corresponding to the physical addresses of the messages.

[0125] The following section first explains the process of CPU and FPGA collaboratively processing messages in related technologies.

[0126] Figure 1 This application provides a mapping between physical addresses and descriptors in its embodiments. For example... Figure 1 As shown, it includes: multiple physical addresses of descriptors and multiple descriptors, wherein one physical address of a descriptor corresponds to one descriptor.

[0127] Multiple descriptors are stored in a circular descriptor queue.

[0128] Multiple physical descriptor addresses may include, for example, physical descriptor address 1, physical descriptor address 2, and physical descriptor address 3. Multiple descriptors may include, for example, descriptor 1, descriptor 2, and descriptor 3.

[0129] In this context, multiple physical descriptor addresses refer to the CPU allocating multiple consecutive physical descriptor addresses. After the CPU allocates these multiple physical descriptor addresses, they can be written into the FPGA.

[0130] The CPU can also assign multiple consecutive physical addresses for packets, such as packet physical address 1, packet physical address 2, and packet physical address 3.

[0131] During message reception, the CPU initializes a circular descriptor queue, writing multiple descriptor physical addresses and multiple message physical addresses into multiple descriptors. Specifically, each descriptor physical address and message physical address is written to (or stored in) a corresponding descriptor. For example, descriptor physical address 1 and message physical address 1 are written to (or stored in) descriptor 1. It should be noted that the descriptor physical address and message physical address written into the same descriptor can be considered as related.

[0132] During the message reception process, the FPGA obtains the message physical address from the descriptor based on the physical address of the descriptor, writes the received message into the storage area corresponding to the message physical address, and writes back the message length, the Receive Side Scaling-Receive Packet Steering (RSS) value, and the write completion flag to the descriptor.

[0133] During message transmission, the CPU initializes a circular descriptor queue, writing multiple descriptor physical addresses, multiple message physical addresses, and multiple message lengths into multiple descriptors. Specifically, a descriptor physical address, a message physical address, and a message length are written (or stored) into a corresponding descriptor, where one message corresponds to one message physical address. For example, descriptor physical address 1, message physical address 1, and message length 1 are written (or stored) into descriptor 1, where the physical address of message 1 is message physical address 1.

[0134] During the message transmission process, the FPGA obtains the message physical address and message length from the descriptor based on the descriptor physical address. Based on the message length, it retrieves the message from the storage area corresponding to the message physical address, writes the read completion flag back to the descriptor, and sends the retrieved message under the control of the CPU.

[0135] The following combination Figure 2 This indicates the operations performed by the CPU during the message reception process.

[0136] Figure 2 This describes the CPU's processing flow when receiving messages in related technologies. For example... Figure 2 As shown, it includes:

[0137] S201. After the FPGA writes back the message length, the message RSS value, and the write-complete flag to the descriptors in the ring descriptor queue, it retrieves the descriptor indicated by the current value of the pointer to the ring descriptor queue from the ring descriptor queue.

[0138] S202. Determine if the write completion flag exists in the descriptor.

[0139] If yes, execute S203; otherwise, execute S202.

[0140] S203. Obtain the message based on the message physical address in the descriptor, and process the message based on the message length and RSS value in the descriptor.

[0141] S204. Determine whether the current value of the pointer to the circular descriptor queue is equal to a multiple of the first number.

[0142] If yes, execute S205; otherwise, execute S206.

[0143] S205. Batch release descriptors and rewrite the descriptor physical address, packet physical address, etc. into the released descriptors.

[0144] S206. Update the current value of the pointer to the circular descriptor queue.

[0145] based on Figure 2 As shown in the related technology, the FPGA needs to write a write completion flag in the descriptor to instruct the CPU to retrieve the message. After the descriptor is released, the CPU needs to rewrite the physical address of the descriptor. Both the write completion flag of the FPGA and the write physical address of the descriptor of the CPU will occupy the PCIe bandwidth, increasing the latency of receiving messages.

[0146] Based on the above-mentioned technical problems, the technical concept of this application embodiment is as follows: The FPGA receives a first message from a second device according to the physical address of the descriptor, where the physical address of the descriptor is the physical address indicated by the current value of the head pointer of the first queue; the FPGA stores the parsing information of the first message according to the physical address of the descriptor; the FPGA stores the first message according to the message physical address associated with the physical address of the descriptor, and updates the current value of the head pointer of the first queue; when the CPU determines that the current value of the tail pointer of the first queue is different from the current value of the head pointer, the CPU obtains the message physical address and the parsing information of the first message according to the physical address of the descriptor indicated by the current value of the tail pointer; the CPU obtains the first message according to the message physical address, processes the first message according to its length and RSS value, and updates the current value of the tail pointer of the first queue. After the update, the current value of the tail pointer of the first queue is the same as the current value of the head pointer.

[0147] By using the above method, the FPGA can indicate that the first message has been stored without having to write the write completion flag into the descriptor corresponding to the physical address of the descriptor. This is achieved by indicating that the FPGA has stored the first message by the difference between the current value of the tail pointer and the current value of the head pointer, which can reduce the PCIe bandwidth occupied and reduce the latency of receiving messages.

[0148] The following combination Figure 3 This indicates the operations performed by the CPU during the message transmission process.

[0149] Figure 3 This describes the CPU processing flow when sending messages in related technologies. For example... Figure 3 As shown, it includes:

[0150] S301. After the FPGA writes the read completion flag back to the descriptor in the circular descriptor queue, it retrieves the descriptor currently pointed to by the pointer of the circular descriptor queue.

[0151] S302. Determine if the read completion flag exists in the descriptor.

[0152] If yes, execute S303; otherwise, execute S302.

[0153] S303, Control the FPGA to send the message corresponding to the descriptor.

[0154] S304. Determine whether the current value of the pointer to the circular descriptor queue is equal to a multiple of the first number.

[0155] If yes, execute S305; otherwise, execute S306.

[0156] S305. Batch release descriptors and rewrite the descriptor physical address, packet physical address, and packet length into the released descriptors.

[0157] S306. Update the current value of the pointer to the circular descriptor queue.

[0158] based on Figure 3 The related technologies shown require the FPGA to write a read completion flag into the descriptor to instruct the CPU to control the FPGA to send messages. When the descriptor is released, the CPU needs to rewrite the physical address of the descriptor. Both the FPGA's read completion flag and the CPU's write descriptor physical address will occupy PCIe bandwidth, increasing the latency of sending messages.

[0159] Based on the above-mentioned technical problems, the technical concept of this application embodiment is as follows: The FPGA obtains the packet physical address associated with the descriptor physical address and the length of the first packet according to the descriptor physical address; the descriptor physical address is the descriptor physical address indicated by the current value of the head pointer of the first queue; the FPGA obtains the first packet according to the packet physical address and length, and updates the current value of the head pointer of the first queue; when the CPU determines that the current value of the tail pointer of the first queue is different from the current value of the head pointer, the CPU controls the FPGA to send the obtained first packet to the second device according to the descriptor physical address, and updates the current value of the tail pointer. After the update, the current value of the tail pointer is the same as the current value of the head pointer.

[0160] By using the above method, the FPGA can be instructed to acquire and store the first message without having to write the read completion flag into the descriptor corresponding to the physical address of the descriptor. This is achieved by indicating that the current value of the tail pointer is different from the current value of the head pointer, which can reduce the PCIe bandwidth usage and reduce the latency of sending messages.

[0161] The technical solution of this application and how the technical solution of this application solves the above-mentioned technical problems are described in detail below with specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments. The embodiments of this application will now be described with reference to the accompanying drawings.

[0162] Figure 4 A flowchart illustrating a message receiving method provided in this application embodiment. Figure 1 ,like Figure 4 As shown, the method includes:

[0163] S401. The FPGA receives the first message from the second device according to the physical address of the descriptor, where the physical address of the descriptor is the physical address of the descriptor indicated by the current value of the head pointer of the first queue.

[0164] The FPGA refers to the FPGA of the first device. For the sake of simplicity, unless otherwise specified, all FPGAs mentioned in the embodiments herein are assumed to be the FPGAs in the first device.

[0165] The physical address of the descriptor is one of at least one physical address of the descriptor, and at least one physical address of the descriptor is pre-stored in the first queue.

[0166] The current value of the head pointer of the first queue is used to indicate one of the physical addresses of at least one descriptor stored in the first queue.

[0167] The first queue can be a circular queue, which can be called the used circular descriptor queue.

[0168] The first queue consists of N ordered data structure units, each of which pre-stores the physical address of a descriptor. N is an integer greater than or equal to 1.

[0169] N can be flexibly adjusted according to the message receiving requirements and / or performance requirements of the first device. The value of N can be between 1024 and 8112, and the common value of N is 4096.

[0170] For example, in a scenario where the first device is used in a scenario with extremely high real-time requirements and a large demand for message reception, N can be 8112 to ensure that enough physical addresses of descriptors can be stored.

[0171] For example, when the first device is used in a scenario where the message receiving demand is small, N can be 1024 to save memory resources in the first device.

[0172] The following describes the process of receiving the first message from the second device via the FPGA based on the physical address of the descriptor.

[0173] In one implementation, the FPGA obtains the physical address of the descriptor pointed to by the current head pointer of the first queue based on the current value of the head pointer; the FPGA obtains the message queue number based on the physical address of the descriptor; when the FPGA obtains the message queue number, it can receive the first message from the second device based on the message queue number; when the FPGA does not obtain the message queue number, it can also directly receive the first message from the second device.

[0174] Optionally, the first device can be a message receiving device and the second device can be a message sending device, or the first device can be a message sending device and the second device can be a message receiving device.

[0175] During the process of receiving messages, the first device can be a message receiving device, and the second device can be a message sending device.

[0176] During the process of sending a message, the first device can be a message sending device, and the second device can be a message receiving device.

[0177] In one implementation, the first message can be a message sent by the second device to the first device using a large packet transmission method based on TLP.

[0178] In related technologies, a second device sends a first message to a first device using a small packet transmission method based on TLP. In this method, if the first message has a large data volume, the second device will split it into multiple smaller second messages and send them to the first device. The first device receives the multiple second messages through an FPGA and reassembles them into a single first message. In this embodiment, the second device sends the first message to the first device using a large packet transmission method based on TLP. The first device does not need to reassemble the first message, thus reducing the latency of message reception.

[0179] S402. The FPGA stores the parsing information of the first message and stores the first message according to the physical address of the descriptor, and updates the current value of the head pointer of the first queue.

[0180] In one implementation, the FPGA can obtain the parsing information of the first message when it receives the first message.

[0181] The parsing information of the first message includes at least the length of the first message and the Receive Side Scaling (RSS) value when receiving the first message.

[0182] It is worth noting that when the FPGA receives the first message, it can obtain the parsing information of the first message. Please refer to relevant technologies for details, which will not be elaborated here.

[0183] In one implementation, the parsing information of the first message can be stored in the descriptor corresponding to the physical address of the descriptor.

[0184] In one implementation, the first packet is stored by the FPGA based on the packet physical address associated with the physical address of the descriptor.

[0185] The following describes the process of storing the first packet using the FPGA based on the packet physical address associated with the physical address of the descriptor.

[0186] In one implementation, the physical address of the message is obtained by the FPGA based on the physical address of the descriptor; the first message is then stored by the FPGA based on the physical address of the message.

[0187] In one implementation, the first message is stored in the storage area corresponding to the message's physical address.

[0188] In one implementation, updating the current value of the head pointer of the first queue can be understood as incrementing the current value of the head pointer by 1.

[0189] For example, the first pointer is set to 0, pointing to the physical address of the descriptor in the first data structure unit. The first pointer is then updated to 1, and the first pointer 1 points to the physical address of the descriptor in the second data structure unit.

[0190] S403. The CPU determines whether the current value of the tail pointer of the first queue is the same as the current value of the head pointer.

[0191] If yes, execute S403; otherwise, execute S404.

[0192] The CPU refers to the CPU of the first device. For the sake of simplicity, the CPU mentioned in all embodiments of this document is assumed to be the CPU of the first device unless otherwise specified.

[0193] The current values ​​of the tail pointer and the head pointer of the first queue are used by the CPU to determine whether the FPGA has stored the first message.

[0194] When the current value of the tail pointer in the first queue is different from the current value of the head pointer, the CPU determines that the FPGA has stored the first message.

[0195] When the current value of the tail pointer of the first queue is the same as the current value of the head pointer, the CPU determines that the FPGA has not stored the first message.

[0196] S404. The CPU obtains the first message and the first message parsing information by using the physical address of the descriptor indicated by the current value of the tail pointer.

[0197] In one implementation, the CPU obtains the physical address of the packet based on the physical address of the descriptor; and obtains the first packet based on the physical address of the packet.

[0198] In one implementation, the CPU retrieves the first message from the storage area corresponding to the message's physical address.

[0199] In one implementation, the CPU obtains the first message parsing information from the descriptor corresponding to the physical address of the descriptor.

[0200] S405. The CPU processes the first message according to the parsing information of the first message and updates the current value of the tail pointer of the first queue. After the update, the current value of the tail pointer of the first queue is the same as the current value of the head pointer.

[0201] In one implementation, the CPU processes the first message based on the length and RSS value of the first message included in the parsed information. For details on the specific processing steps, please refer to relevant technologies; they will not be elaborated here.

[0202] In one implementation, updating the current value of the tail pointer of the first queue can be understood as incrementing the current value of the tail pointer by 1.

[0203] The beneficial effects of this embodiment are as follows: In this embodiment, after storing the first message through the FPGA, the current value of the head pointer of the first queue is updated by the FPGA. When the CPU determines that the current value of the tail pointer of the first queue is different from the current value of the head pointer, the CPU retrieves the first message. This achieves the goal of indicating that the FPGA has stored the first message by the difference between the current values ​​of the tail pointer and the head pointer. The FPGA does not need to store a write-complete flag in the descriptor corresponding to the physical address of the descriptor, which can reduce the occupation of PCIe bandwidth and reduce the latency of receiving messages. In related technologies, the FPGA needs to store a write-complete flag in the descriptor corresponding to the physical address of the descriptor, which leads to a large occupation of PCIe bandwidth and a high latency of receiving messages.

[0204] Figure 5 A flowchart illustrating a message receiving method provided in this application embodiment. Figure 2 ,like Figure 5 As shown, the method includes:

[0205] S501. The FPGA receives the first message from the second device according to the physical address of the descriptor, where the physical address of the descriptor is the physical address of the descriptor indicated by the current value of the head pointer of the first queue.

[0206] The following describes the process of receiving the first message from the second device via the FPGA based on the physical address of the descriptor.

[0207] In one implementation, the FPGA obtains the physical address of the descriptor pointed to by the current head pointer of the first queue based on the current value of the head pointer; the FPGA determines the descriptor corresponding to the physical address of the descriptor based on the physical address of the descriptor; the FPGA obtains the message queue number from the descriptor; when the message queue number is obtained, the FPGA can receive the first message from the second device based on the message queue number; the FPGA can also receive the first message from the second device even when the message queue number is not obtained.

[0208] S502. Determine the descriptor corresponding to the physical address of the descriptor through the FPGA.

[0209] The physical address of a descriptor is one of at least one descriptor physical addresses, which are pre-stored in a first queue. There is a one-to-one correspondence between the at least one descriptor physical address and the at least one descriptor, where one descriptor physical address corresponds to one descriptor. The descriptor corresponding to the descriptor physical address can be stored in the storage area corresponding to the descriptor physical address. A descriptor may include a descriptor physical address and a message physical address. Within a descriptor, the descriptor physical address and the message physical address can be considered associated, that is, the descriptor physical address and the message physical address are associated, or one descriptor physical address corresponds to one message physical address.

[0210] In one implementation, the FPGA determines the descriptor corresponding to the physical address of the descriptor based on the correspondence between the physical address of at least one descriptor and at least one descriptor.

[0211] S503. The parsing information of the first message is stored in the descriptor corresponding to the physical address of the descriptor through the FPGA.

[0212] S504: Obtain the packet physical address from the descriptor corresponding to the physical address of the descriptor through the FPGA.

[0213] S505: Determine the storage area corresponding to the physical address of the message through the FPGA.

[0214] In one implementation, the memory region containing the physical address of the message is determined as the memory region corresponding to the physical address of the message.

[0215] S506. The first message is stored in the storage area corresponding to the physical address of the message through the FPGA, and the current value of the first queue's head pointer is updated.

[0216] The storage area corresponding to the physical address of the descriptor and the storage area corresponding to the physical address of the message are both located in the memory of the first device.

[0217] FPGAs can access memory via DMA technology. FPGA memory access includes, but is not limited to: FPGA storing the parsed information of the first message into the descriptor corresponding to the physical address of the descriptor; FPGA retrieving the physical address of the message from the descriptor corresponding to the physical address of the descriptor; and FPGA storing the first message into the storage area corresponding to the physical address of the message.

[0218] S507. The CPU determines whether the current value of the tail pointer of the first queue is the same as the current value of the head pointer.

[0219] If yes, execute S507; otherwise, execute S508.

[0220] S508: The CPU obtains the physical address of the packet and the parsing information of the first packet by using the physical address of the descriptor indicated by the current value of the tail pointer.

[0221] The following describes the process by which the CPU obtains the physical address of the packet and the parsing information of the first packet based on the physical address of the descriptor indicated by the current value of the tail pointer.

[0222] In one implementation, the CPU determines the descriptor corresponding to the physical address of the descriptor based on the physical address indicated by the current value of the tail pointer; the CPU then obtains the physical address of the message and the parsing information of the first message from the descriptor.

[0223] The CPU can access memory using DMA technology. CPU memory access includes, but is not limited to: the CPU retrieving the physical address of a packet and the parsing information of the first packet from the descriptor corresponding to the physical address of the descriptor.

[0224] S509. The CPU obtains the first message based on the message's physical address, processes the first message according to its parsing information, and updates the current value of the tail pointer of the first queue. After the update, the current value of the tail pointer of the first queue is the same as the current value of the head pointer.

[0225] The following section explains the process by which the CPU obtains the first packet based on its physical address.

[0226] In one implementation, the CPU determines the storage area corresponding to the physical address of the message based on the message's physical address; the CPU then retrieves the first message from the storage area corresponding to the message's physical address.

[0227] Before receiving a message, the first device can also perform initialization processing. The following is combined with... Figure 6The message receiving method involving initialization processing is explained.

[0228] Figure 6 A flowchart illustrating a message receiving method provided in this application embodiment. Figure 3 ,like Figure 6 As shown, the method includes:

[0229] S601. Allocate at least one descriptor physical address and at least one message physical address consecutively through the CPU, wherein at least one descriptor physical address is associated with at least one message physical address.

[0230] Specifically, the first device allocates at least one contiguous physical descriptor address and at least one physical packet address in its memory via the CPU. Each physical descriptor address corresponds to a descriptor in the first device's memory, and each physical packet address corresponds to a storage area in the first device's memory.

[0231] S602. Initialize the first and second queues.

[0232] After initialization, the first queue and the second queue store at least one physical address of a descriptor. The current values ​​of the head pointer and tail pointer of the first queue are the first preset values, and the current value of the pointer of the second queue is the first preset value.

[0233] The first preset value is, for example, 0.

[0234] The current values ​​of the head and tail pointers of the first queue are used by the CPU to determine whether the first device has received the first message. Alternatively, the current values ​​of the tail pointer and head pointer of the first queue are used by the CPU to determine whether the FPGA has stored the first message.

[0235] The second queue can be a circular queue, which can be called the available descriptor circular queue.

[0236] The current value of the pointer to the second queue is used to indicate whether to bulk release the descriptors corresponding to the physical addresses of the descriptors.

[0237] S603. For at least one descriptor physical address and the packet physical address associated with the descriptor physical address, the CPU stores the descriptor physical address and the packet physical address associated with the descriptor physical address into the descriptor corresponding to the descriptor physical address.

[0238] In one implementation, when the first device supports sending messages via multiple queues, the CPU can also store the message queue number into the descriptor corresponding to the physical address of the descriptor.

[0239] S604: Write at least one physical descriptor address into the FPGA via the CPU.

[0240] S605, execute S401 to S406, or S501 to S509.

[0241] In some embodiments, when the number of first messages received by the first device reaches a first quantity, a first quantity of descriptors are released in batches. The following is combined with... Figure 7 The method for receiving messages involving bulk release is explained.

[0242] Figure 7 A flowchart illustrating a message receiving method provided in this application embodiment. Figure 4 ,like Figure 7 As shown, the method includes:

[0243] S701, execute S401 to S406, S501 to S509, or S601 to S605.

[0244] S702: The CPU determines whether the current value of the first pointer of the first queue is equal to a multiple of the first quantity.

[0245] The first quantity is, for example, 32.

[0246] Optionally, the first quantity can be set according to the expected number of first messages to be received.

[0247] If yes, execute S703; otherwise, execute S701.

[0248] S703: The CPU determines whether the current value of the pointer to the second queue is the same as the current value of the head pointer.

[0249] If yes, execute S701; otherwise, execute S704.

[0250] S704. The CPU batch releases the packet physical addresses in the descriptors corresponding to the first number of physical addresses of the target descriptors, where the target descriptor is the descriptor corresponding to the physical address of the descriptor currently pointed to by the head pointer.

[0251] For example, the first preset value of the first pointer is 0, and the first quantity is 32. When the current value of the pointer in the second queue is 0 and the current value of the first pointer is 32, the target descriptor is the descriptor corresponding to the physical address of the descriptor pointed to by the first pointer when it is 32. The descriptors corresponding to the physical addresses of the first number of descriptors before the target descriptor are the descriptors corresponding to the physical addresses of the descriptors pointed to by the first pointer when it is 0, and the descriptors corresponding to the physical addresses of the descriptors pointed to by the first pointer when it is 31.

[0252] In one implementation, when the descriptor includes a packet queue number, the packet queue numbers in the descriptors corresponding to the first number of physical addresses of the target descriptor can also be released in batches.

[0253] S705: The CPU rewrites the new packet physical address in each of the first number of descriptors, updating the current value of the pointer of the second queue to the current value of the head pointer.

[0254] The current value of the pointer to the second queue indicates whether to release the packet physical addresses in the first number of descriptors in bulk.

[0255] In one implementation, when the first device supports sending messages via multiple queues, the message queue number can also be rewritten by the CPU in each of the first number of such descriptors.

[0256] The beneficial effects of this embodiment are as follows: In this embodiment, if the CPU determines that the current value of the first pointer is equal to a multiple of the first number, and the current value of the pointer of the second queue is different from the current value of the first pointer, it releases the packet physical addresses in the descriptors corresponding to the first number of physical addresses before the target descriptor in batches. This helps to rewrite the new packet physical address in each of the first number of descriptors without releasing the descriptor physical addresses in the descriptors corresponding to the first number of physical addresses, thereby improving the efficiency of release and rewriting, reducing the PCIe bandwidth occupied, and reducing the latency of receiving packets. In related technologies, before the FPGA stores the write completion flag in the descriptor corresponding to the physical address, the descriptor already stores the physical address of the descriptor and the packet physical address. Since the amount of data that a descriptor can carry is limited, the write-complete flag will occupy the physical address of the descriptor, causing the physical address of the descriptor to be incorrect. Therefore, during batch release, the physical address of the descriptor, the physical address of the message, etc., must be released in order to restore the physical address of the descriptor, the new physical address of the message, etc. This results in low efficiency of release and rewriting, which in turn leads to a large occupation of PCIe bandwidth and high latency in receiving messages.

[0257] Figure 8 A flowchart illustrating a message sending method provided in this application embodiment. Figure 1 ,like Figure 8 As shown, the method includes:

[0258] S801: Using the FPGA, obtain the physical address of the message associated with the physical address of the descriptor and the length of the first message. The physical address of the descriptor is the physical address of the descriptor indicated by the current value of the head pointer of the first queue.

[0259] The following describes the process of obtaining the physical address of the packet associated with the physical address of the descriptor and the length of the first packet through the FPGA based on the physical address of the descriptor.

[0260] In one implementation,

[0261] The FPGA obtains the physical address of the descriptor pointed to by the current head pointer based on the current value of the head pointer of the first queue;

[0262] The FPGA obtains the physical address of the packet associated with the physical address of the descriptor and the length of the first packet based on the physical address of the descriptor.

[0263] S802. The FPGA obtains the first message based on the message physical address associated with the physical address of the descriptor and the length of the first message, and updates the current value of the head pointer of the first queue.

[0264] In one implementation, the FPGA stores the first message it receives in the FPGA's buffer.

[0265] The FPGA's buffer can be a First In First Out (FIFO) buffer.

[0266] S803: The CPU determines whether the current value of the tail pointer of the first queue is the same as the current value of the head pointer.

[0267] If yes, execute S803; otherwise, execute S804.

[0268] S804: The CPU controls the FPGA to send the acquired first message to the second device according to the physical address of the descriptor, and updates the current value of the tail pointer. After the update, the current value of the tail pointer is the same as the current value of the head pointer.

[0269] The following describes the process by which the CPU controls the FPGA to send the acquired first message to the second device based on the physical address of the descriptor.

[0270] In one implementation, the CPU sends a control signal to the FPGA, which instructs the FPGA to send a first message to the second device. After receiving the control signal, the FPGA sends the acquired first message to the second device according to the physical address of the descriptor.

[0271] The following describes the process by which the FPGA sends the acquired first message to the second device based on the physical address of the descriptor.

[0272] In one implementation, the FPGA obtains the message queue number based on the physical address of the descriptor; when the FPGA obtains the message queue number, it can send the obtained first message to the second device according to the message queue number; when the FPGA does not obtain the message queue number, it can also send the obtained first message to the second device.

[0273] The first message can be a message sent by the first device to the second device using the TLP-based large packet transmission method.

[0274] In related technologies, a first device sends a first message to a second device using a small packet transmission method based on TLP. In this transmission method, if the data volume of the first message is large, the first device will split the first message into multiple second messages with smaller data volumes and send them to the second device. In this embodiment, the first device sends the first message to the second device using a large packet transmission method based on TLP, eliminating the need to split the first message and reducing the latency of the first device sending the message.

[0275] The beneficial effects of this embodiment are as follows: After acquiring the first message through the FPGA, the current value of the head pointer of the first queue is updated by the FPGA. When the CPU determines that the current value of the tail pointer is different from the current value of the head pointer, the CPU controls the FPGA to send the acquired first message to the second device. This achieves the goal of indicating that the FPGA has acquired and stored the first message by showing that the current value of the tail pointer is different from the current value of the head pointer. The FPGA does not need to store the read completion flag in the descriptor corresponding to the physical address of the descriptor, which can reduce the occupation of PCIe bandwidth and reduce the latency of sending messages. In related technologies, the FPGA needs to store the read completion flag in the descriptor corresponding to the physical address of the descriptor, which leads to a large occupation of PCIe bandwidth and a high latency of sending messages.

[0276] Figure 9 A flowchart illustrating a message sending method provided in this application embodiment. Figure 2 ,like Figure 9 As shown, the method includes:

[0277] S901. Determine the descriptor corresponding to the physical address of the descriptor through the FPGA.

[0278] It is worth noting that the execution method of S901 is similar to that of S502, and will not be described again here.

[0279] S902. Obtain the packet physical address associated with the physical address of the descriptor and the length of the first packet from the descriptor corresponding to the physical address of the descriptor through the FPGA.

[0280] S903. Determine the storage area corresponding to the physical address of the message through the FPGA.

[0281] S904. Based on the length of the first message, the FPGA retrieves the first message from the storage area corresponding to the physical address of the message and updates the current value of the head pointer of the first queue.

[0282] The following describes the process of retrieving the first message from the storage area corresponding to the physical address of the message using the FPGA, based on the length of the first message.

[0283] In one implementation, the physical address of the message is obtained from the descriptor corresponding to the physical address of the descriptor by the FPGA; the first message is obtained from the storage area corresponding to the physical address of the message by the FPGA according to the length of the first message.

[0284] S905. The CPU determines whether the current value of the tail pointer of the first queue is the same as the current value of the head pointer.

[0285] If yes, execute S905; otherwise, execute S906.

[0286] S906. The CPU controls the FPGA to send the acquired first message to the second device according to the physical address of the descriptor, and updates the current value of the tail pointer. After the update, the current value of the tail pointer is the same as the current value of the head pointer.

[0287] The following describes the process by which the FPGA sends the acquired first message to the second device based on the physical address of the descriptor.

[0288] In one implementation, the FPGA determines the descriptor corresponding to the physical address of the descriptor; the FPGA obtains the message queue number from the descriptor; when the FPGA obtains the message queue number, it can send the first message to the second device according to the message queue number; when the FPGA does not obtain the message queue number, it can also send the first message to the second device.

[0289] Before sending the message, the first device can also perform initialization processing. The following is combined with... Figure 10 The message sending method involving initialization processing is explained.

[0290] Figure 10 A flowchart illustrating a message sending method provided in this application embodiment. Figure 3 ,like Figure 10 As shown, the method includes:

[0291] S1001. Allocate at least one descriptor physical address and at least one packet physical address consecutively through the CPU, wherein at least one descriptor physical address is associated with at least one packet physical address.

[0292] S1002. Initialize the first and second queues.

[0293] After initialization, the first queue and the second queue store at least one physical address of a descriptor. The current values ​​of the head pointer and tail pointer of the first queue are the first preset values, and the current value of the pointer of the second queue is the first preset value.

[0294] The current values ​​of the head and tail pointers of the first queue are used by the CPU to determine whether the first device has sent the first message. Alternatively, the current values ​​of the tail pointer and head pointer of the first queue are used by the CPU to determine whether the FPGA has acquired and stored the first message.

[0295] The current value of the pointer to the second queue is used to indicate whether to bulk release the descriptors corresponding to the physical addresses of the descriptors.

[0296] S1003. For at least one descriptor physical address and the packet physical address associated with the descriptor physical address, the CPU stores the descriptor physical address, the packet physical address associated with the descriptor physical address, and the length of the first packet into the descriptor corresponding to the descriptor physical address.

[0297] In one implementation, when the first device supports receiving packets via multiple queues, the CPU can also store the packet queue number into the descriptor corresponding to the physical address of the descriptor.

[0298] S1004. Write at least one physical descriptor address into the FPGA via the CPU.

[0299] S1005, execute S801 to S804, or S901 to S906.

[0300] In some embodiments, when the number of first messages sent by the first device reaches a first quantity, a first quantity of descriptors are released in batches. The following is in conjunction with... Figure 11 The method for sending messages involving bulk release is explained.

[0301] Figure 11 A flowchart illustrating a message sending method provided in this application embodiment. Figure 4 ,like Figure 11 As shown, the method includes:

[0302] S1101, execute S801 to S804, S901 to S906, or S1001 to S1005.

[0303] S1102. The CPU determines whether the current value of the first pointer is equal to a multiple of the first quantity.

[0304] If yes, execute S1103; otherwise, execute S1101.

[0305] S1103. The CPU determines whether the current value of the pointer to the second queue is the same as the current value of the head pointer.

[0306] If yes, execute S1101; otherwise, execute S1104.

[0307] S1104. The CPU batch releases the physical addresses of the packets in the descriptors corresponding to the physical addresses of the first number of descriptors before the target descriptor, and the length of the first packet, where the target descriptor is the descriptor corresponding to the physical address of the descriptor currently pointed to by the first pointer.

[0308] In one implementation, when the descriptor includes a packet queue number, the packet queue numbers in the descriptors corresponding to the first number of physical addresses of the target descriptor can also be released in batches.

[0309] S1105. By having the CPU rewrite the new message physical address and the new message length in each of the first number of memory areas, the current value of the pointer of the second queue is updated to the current value of the first pointer.

[0310] The current value of the pointer to the second queue indicates the physical address of the packets in the first number of descriptors before bulk release of the target descriptor, as well as the length of the packets.

[0311] In one implementation, when the first device supports receiving packets via multiple queues, the packet queue number can also be rewritten by the CPU in each of the first number of descriptors.

[0312] The beneficial effects of this embodiment are as follows: If the CPU determines that the current value of the first pointer is equal to a multiple of the first number, and the current value of the pointer in the second queue is different from the current value of the first pointer, it releases in batches the packet physical addresses and the length of the first packet in the descriptors corresponding to the first number of physical addresses before the target descriptor. This helps to rewrite the new packet physical address and the new packet length in each of the first number of descriptors without releasing the descriptor physical addresses in the descriptors corresponding to the first number of physical addresses, thereby improving the efficiency of release and rewriting, reducing the PCIe bandwidth occupied, and reducing the latency of receiving packets. In related technologies, before the FPGA stores the write completion flag in the descriptor corresponding to the physical address, the descriptor physical address, the packet physical address, and the length of the first packet are already stored in the descriptor. Since the amount of data that a descriptor can carry is limited, the write-complete flag will occupy the physical address of the descriptor, causing the physical address of the descriptor to be incorrect. Therefore, during batch release, the physical address of the descriptor, the physical address of the message, etc., must be released in order to restore the physical address of the descriptor, the new physical address of the message, etc. This results in low efficiency of release and rewriting, which in turn leads to a large occupation of PCIe bandwidth and high latency in sending messages.

[0313] Figure 12 This is a schematic diagram of a message transmission device provided in an embodiment of this application. The message transmission device is applied to a first device, such as... Figure 12 As shown, the message transmission device 120 includes: a first processing module 1201 and a second processing module 1202.

[0314] In some embodiments, the first processing module 1201 is, for example, an FPGA, and the second processing module 1202 is, for example, a CPU.

[0315] In some embodiments, when the message transmission device 120 is used to receive the first message from the second device, the message transmission device 120 may also be referred to as a message receiving device.

[0316] In some embodiments, when the message transmission device 120 is used to send a first message to a second device, the message transmission device 120 may also be referred to as a message sending device.

[0317] When the message transmission device 120 receives the first message from the second device, the first processing module 1201 and the second processing module 1202 perform the following operations:

[0318] The first processing module 1201 is used to receive a first message from the second device according to the physical address of the descriptor; the physical address of the descriptor is the physical address of the descriptor indicated by the current value of the head pointer of the first queue;

[0319] The first processing module 1201 is further configured to store the parsing information of the first packet and the first packet according to the physical address of the descriptor, and update the current value of the head pointer of the first queue.

[0320] The second processing module 1202 is used to obtain the packet physical address and the parsing information based on the physical address of the descriptor indicated by the current value of the tail pointer of the first queue when it is determined that the current value of the tail pointer of the first queue is different from the current value of the head pointer.

[0321] The second processing module 1202 is further configured to obtain the first packet according to the packet physical address, process the first packet according to the parsing information, and update the current value of the tail pointer; after the update, the current value of the tail pointer is the same as the current value of the head pointer.

[0322] It should be noted that the message transmission device 120 provided in this application embodiment can implement the method steps in the method embodiment when the first device receives the first message from the second device, and can achieve the same technical effect. Here, the parts and beneficial effects that are the same as those in the method embodiment will not be described in detail.

[0323] In some embodiments, the first processing module 1201 is specifically used for:

[0324] The FPGA is used to determine the descriptor corresponding to the physical address of the descriptor.

[0325] The parsed information is stored in the descriptor corresponding to the physical address of the descriptor via the FPGA.

[0326] In some embodiments, the first processing module 1201 is specifically used for:

[0327] The packet physical address is obtained from the descriptor corresponding to the physical address of the descriptor through the FPGA;

[0328] The storage area corresponding to the physical address of the message is determined by the FPGA;

[0329] The first message is stored in the storage area corresponding to the physical address of the message using the FPGA.

[0330] In some embodiments, the second processing module 1202 is further configured to:

[0331] The CPU allocates at least one descriptor physical address and at least one packet physical address in a continuous sequence, wherein the at least one descriptor physical address is associated with the at least one packet physical address, the at least one descriptor physical address includes the descriptor physical address, and the at least one packet physical address includes the packet physical address;

[0332] For one of the at least one descriptor physical addresses and the packet physical address associated with the descriptor physical address, the CPU stores the descriptor physical address and the packet physical address associated with the descriptor physical address into the descriptor corresponding to the descriptor physical address.

[0333] The CPU writes the physical address of at least one descriptor into the FPGA.

[0334] In some embodiments, the second processing module 1202 is further configured to:

[0335] Initialize the first and second queues;

[0336] After initialization, the first queue and the second queue store the physical address of at least one descriptor. The current value of the head pointer and the tail pointer of the first queue is a first preset value, and the current value of the pointer of the second queue is the first preset value. The current value of the head pointer and the tail pointer of the first queue is used by the CPU to determine whether the first device has received the first message. The current value of the pointer of the second queue and the current value of the head pointer are used to indicate whether to release descriptors in batches.

[0337] In some embodiments, the second processing module 1202 is further configured to:

[0338] When the CPU determines that the current value of the first pointer is equal to a multiple of the first number, if the current value of the pointer of the second queue is not the same as the current value of the first pointer, then the packet physical addresses in the descriptors corresponding to the first number of physical addresses of the target descriptor are released in batch; wherein, the target descriptor is the descriptor corresponding to the physical address of the descriptor currently pointed to by the first pointer;

[0339] The CPU rewrites the new packet physical address in each of the first number of descriptors, updating the current value of the pointer of the second queue to the current value of the first pointer; the current value of the pointer of the second queue is used to indicate whether to release the packet physical addresses in the first number of descriptors in batches.

[0340] It should be noted that the message transmission device 120 provided in this application embodiment can implement the method steps in the method embodiment when the first device receives the first message from the second device, and can achieve the same technical effect. Here, the parts and beneficial effects that are the same as those in the method embodiment will not be described in detail.

[0341] During the process of the message transmission device 120 sending the first message to the second device, the first processing module 1201 and the second processing module 1202 are used to perform the following operations:

[0342] The first processing module 1201 is used to obtain the packet physical address associated with the descriptor physical address and the length of the first packet based on the descriptor physical address; the descriptor physical address is the descriptor physical address indicated by the current value of the head pointer of the first queue;

[0343] The first processing module 1201 is used to obtain the first packet according to the packet physical address and the length, and update the current value of the head pointer of the first queue;

[0344] The second processing module 1202 is configured to, when determining that the current value of the tail pointer of the first queue is different from the current value of the head pointer, control the first processing module 1201 to send the acquired first message to the second device according to the physical address of the descriptor, and update the current value of the tail pointer; after the update, the current value of the tail pointer is the same as the current value of the head pointer.

[0345] It should be noted that the message transmission device 120 provided in this application embodiment can implement the method steps in the method embodiment when the first device sends the first message to the second device, and can achieve the same technical effect. Here, the parts and beneficial effects that are the same as those in the method embodiment will not be described in detail.

[0346] In some embodiments, the first processing module 1201 is specifically used for:

[0347] Determine the descriptor corresponding to the physical address of the descriptor;

[0348] Obtain the packet physical address associated with the physical address of the descriptor and the length of the first packet from the descriptor corresponding to the physical address of the descriptor.

[0349] In some embodiments, the first processing module 1201 is specifically used for:

[0350] Determine the storage area corresponding to the physical address of the message;

[0351] Based on the length, the first message is retrieved from the storage area corresponding to the message's physical address.

[0352] In some embodiments, the second processing module 1202 is further configured to:

[0353] Allocate at least one consecutive descriptor physical address and at least one packet physical address, wherein the at least one descriptor physical address is associated with the at least one packet physical address, the at least one descriptor physical address includes the descriptor physical address, and the at least one packet physical address includes the packet physical address;

[0354] For one of the at least one descriptor physical addresses and the packet physical address associated with the descriptor physical address, the descriptor physical address, the packet physical address associated with the descriptor physical address, and the length of the first packet are stored in the descriptor corresponding to the descriptor physical address.

[0355] Write the physical address of the at least one descriptor into the first processing module 1201.

[0356] In some embodiments, after allocating the at least one descriptor physical address and the at least one packet physical address consecutively, the second processing module 1202 is further configured to:

[0357] Initialize the first and second queues;

[0358] After initialization, the first queue and the second queue store the physical address of at least one descriptor. The current value of the head pointer and the tail pointer of the first queue is a first preset value, and the current value of the pointer of the second queue is the first preset value. The current value of the head pointer and the tail pointer of the first queue is used by the second processing module 1202 to determine whether the first device sends the first message, and the current value of the pointer of the second queue is used to indicate whether to release the descriptors corresponding to the physical addresses of the descriptors in batches.

[0359] In some embodiments, the second processing module 1202 is further configured to:

[0360] When the current value of the first pointer is determined to be equal to a multiple of the first number, if the current value of the pointer of the second queue is not the same as the current value of the first pointer, then the packet physical address in the descriptor corresponding to the physical address of the first number of descriptors before the target descriptor is released in batch, as well as the length of the first packet; wherein, the target descriptor is the descriptor corresponding to the physical address of the descriptor currently pointed to by the first pointer;

[0361] In each of the first number of descriptors, a new packet physical address and a new packet length are rewritten, and the current value of the pointer of the second queue is updated to the current value of the first pointer; the current value of the pointer of the second queue is used to indicate whether to release the packet physical address and the length of the first packet in the first number of descriptors in batch.

[0362] It should be noted that the message transmission device 120 provided in this application embodiment can implement the method steps in the method embodiment when the first device sends the first message to the second device, and can achieve the same technical effect. Here, the parts and beneficial effects that are the same as those in the method embodiment will not be described in detail.

[0363] It should be understood that the aforementioned message transmission device 120 is embodied in the form of a functional module. The term "module" here may refer to an application-specific integrated circuit (ASIC), electronic circuitry, a processor (e.g., a shared processor, a proprietary processor, or a group processor, etc.) and memory for executing one or more software or firmware programs, combined logic circuitry, and / or other suitable components that support the described functions.

[0364] Figure 13 This is a structural diagram of an electronic device provided in an embodiment of this application. Figure 13 As shown, the electronic device 130 includes a processor 1301 and a memory 1302. The processor 1301 is communicatively connected to the memory 1302, and the memory 1302 is used to store computer execution instructions. The processor 1301 is configured to execute the technical solutions in any of the foregoing method embodiments by executing the computer execution instructions stored in the memory 1302.

[0365] Optionally, the memory 1302 can be either independent or integrated with the processor 1301. Optionally, when the memory 1302 is a device independent of the processor 1301, the electronic device 1300 may further include a bus 1303 for connecting the aforementioned devices.

[0366] The electronic device is used to execute the technical solutions in any of the foregoing method embodiments. Its implementation principle and technical effect are similar, and will not be described again here.

[0367] This application also provides a computer-readable storage medium storing computer-executable instructions, which, when executed by a processor, are used to implement the technical solutions provided in any of the foregoing method embodiments.

[0368] This application also provides a computer program product, including a computer program, which, when executed by a processor, is used to implement the technical solutions provided in the foregoing method embodiments.

[0369] It should be noted that, for the sake of simplicity, the foregoing method embodiments are all described as a series of actions. However, those skilled in the art should understand that this application is not limited to the described order of actions, as some steps may be performed in other orders or simultaneously according to this application. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are all optional embodiments, and the actions and modules involved are not necessarily essential to this application.

[0370] It should be further noted that although the steps in the flowchart are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowchart may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the sub-steps or stages of other steps.

[0371] It should be understood that the above-described device embodiments are merely illustrative, and the device of this application can also be implemented in other ways. For example, the division of units / modules in the above embodiments is only a logical functional division, and there may be other division methods in actual implementation. For example, multiple units, modules, or components may be combined, or integrated into another system, or some features may be ignored or not executed.

[0372] Furthermore, unless otherwise specified, the functional units / modules in the various embodiments of this application can be integrated into one unit / module, or each unit / module can exist physically separately, or two or more units / modules can be integrated together. The integrated units / modules described above can be implemented in hardware or as software program modules.

[0373] When integrated units / modules are implemented in hardware, the hardware can be digital circuits, analog circuits, etc. The physical implementation of the hardware structure includes, but is not limited to, transistors, memristors, etc. Unless otherwise specified, the processor can be any suitable hardware processor, such as a CPU, GPU, FPGA, DSP, and ASIC, etc. Unless otherwise specified, the storage unit can be any suitable magnetic or magneto-optical storage medium, such as Resistive Random Access Memory (RRAM), Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), Enhanced Dynamic Random Access Memory (EDRAM), High-Bandwidth Memory (HBM), Hybrid Memory Cube (HMC), etc.

[0374] If the integrated unit / module is implemented as a software program module and sold or used as an independent product, it can be stored in a computer-readable storage device (CMD). Based on this understanding, the technical solution of this application, in essence, or the part that contributes to related technologies, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a memory and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this application. The aforementioned memory includes various media capable of storing program code, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard drive, magnetic disk, or optical disk.

[0375] In the above embodiments, the descriptions of each embodiment have their own emphasis. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions of other embodiments. The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as these combinations of technical features do not contradict each other, they should be considered within the scope of this specification.

[0376] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this application are indicated by the following claims.

[0377] It should be understood that this application is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this application is limited only by the appended claims.

Claims

1. A message receiving method, characterized in that, Applied to a first device, the first device including a central processing unit (CPU) and a field-programmable gate array (FPGA), the method includes: The FPGA receives a first message from the second device based on the physical address of the descriptor; the physical address of the descriptor is the physical address of the descriptor indicated by the current value of the head pointer of the first queue. The FPGA stores the parsing information of the first message and the first message according to the physical address of the descriptor, and updates the current value of the head pointer of the first queue. When the CPU determines that the current value of the tail pointer of the first queue is different from the current value of the head pointer, the CPU obtains the first message and the parsing information based on the physical address of the descriptor indicated by the current value of the tail pointer. The CPU processes the first message according to the parsed information and updates the current value of the tail pointer; after the update, the current value of the tail pointer is the same as the current value of the head pointer.

2. The method according to claim 1, characterized in that, The step of storing the parsing information of the first message and the first message through the FPGA according to the physical address of the descriptor includes: The FPGA is used to determine the descriptor corresponding to the physical address of the descriptor. The parsed information is stored in the descriptor corresponding to the physical address of the descriptor via the FPGA. The packet physical address is obtained from the descriptor corresponding to the physical address of the descriptor through the FPGA; The storage area corresponding to the physical address of the message is determined by the FPGA; The first message is stored in the storage area corresponding to the physical address of the message using the FPGA.

3. The method according to claim 1 or 2, characterized in that, The method further includes: The CPU allocates at least one descriptor physical address and at least one packet physical address in a continuous sequence, wherein the at least one descriptor physical address is associated with the at least one packet physical address, the at least one descriptor physical address includes the descriptor physical address, and the at least one packet physical address includes the packet physical address; For one of the at least one descriptor physical addresses and the packet physical address associated with the descriptor physical address, the CPU stores the descriptor physical address and the packet physical address associated with the descriptor physical address into the descriptor corresponding to the descriptor physical address. The CPU writes the physical address of at least one descriptor into the FPGA.

4. The method according to claim 3, characterized in that, After allocating the at least one descriptor physical address and at least one packet physical address consecutively via the CPU, the method further includes: Initialize the first and second queues; After initialization, the first queue and the second queue store the physical address of at least one descriptor. The current value of the head pointer and the tail pointer of the first queue is a first preset value, and the current value of the pointer of the second queue is the first preset value. The current value of the head pointer and the tail pointer of the first queue is used by the CPU to determine whether the first device has received the first message. The current value of the pointer of the second queue and the current value of the head pointer are used to indicate whether to release descriptors in batches.

5. The method according to claim 4, characterized in that, The method further includes: When the CPU determines that the current value of the first pointer is equal to a multiple of the first number, if the current value of the pointer of the second queue is not the same as the current value of the first pointer, then the packet physical addresses in the descriptors corresponding to the first number of physical addresses of the target descriptor are released in batch; wherein, the target descriptor is the descriptor corresponding to the physical address of the descriptor currently pointed to by the first pointer; The CPU rewrites the new packet physical address in each of the first number of descriptors, updating the current value of the pointer of the second queue to the current value of the first pointer; the current value of the pointer of the second queue is used to indicate whether to release the packet physical addresses in the first number of descriptors in batches.

6. A message sending method, characterized in that, Applied to a first device, the first device including a CPU and an FPGA, the method includes: The FPGA obtains the packet physical address associated with the descriptor physical address and the length of the first packet based on the descriptor physical address; the descriptor physical address is the descriptor physical address indicated by the current value of the head pointer of the first queue. The FPGA obtains the first message based on the message's physical address and length, and updates the current value of the first queue's head pointer. When the CPU determines that the current value of the tail pointer of the first queue is different from the current value of the head pointer, the CPU controls the FPGA to send the acquired first message to the second device according to the physical address of the descriptor, and update the current value of the tail pointer; after the update, the current value of the tail pointer is the same as the current value of the head pointer.

7. The method according to claim 6, characterized in that, The step of obtaining the packet physical address associated with the descriptor physical address and the length of the first packet through the FPGA based on the descriptor physical address includes: The FPGA is used to determine the descriptor corresponding to the physical address of the descriptor. The FPGA obtains the packet physical address associated with the physical address of the descriptor and the length of the first packet from the descriptor corresponding to the physical address of the descriptor; The step of obtaining the first message through the FPGA based on the message's physical address and length includes: The storage area corresponding to the physical address of the message is determined by the FPGA; The FPGA retrieves the first message from the storage area corresponding to the message's physical address based on the length.

8. The method according to claim 6 or 7, characterized in that, The method further includes: The CPU allocates at least one descriptor physical address and at least one packet physical address in a continuous sequence, wherein the at least one descriptor physical address is associated with the at least one packet physical address, the at least one descriptor physical address includes the descriptor physical address, and the at least one packet physical address includes the packet physical address; For one of the at least one descriptor physical addresses and the packet physical address associated with the descriptor physical address, the CPU stores the descriptor physical address, the packet physical address associated with the descriptor physical address, and the length of the first packet into the descriptor corresponding to the descriptor physical address. The CPU writes the physical address of at least one descriptor into the FPGA.

9. The method according to claim 8, characterized in that, After allocating the at least one descriptor physical address and at least one packet physical address consecutively via the CPU, the method further includes: Initialize the first and second queues; After initialization, the first queue and the second queue store the physical address of the at least one descriptor. The current value of the head pointer and the tail pointer of the first queue is a first preset value, and the current value of the pointer of the second queue is the first preset value. The current value of the head pointer and the tail pointer of the first queue is used by the CPU to determine whether the first device sends the first message, and the current value of the pointer of the second queue is used to indicate whether to release the descriptors corresponding to the physical addresses of the descriptors in batches.

10. The method according to claim 9, characterized in that, The method further includes: When the CPU determines that the current value of the first pointer is equal to a multiple of the first number, if the current value of the pointer of the second queue is not the same as the current value of the first pointer, then the packet physical address in the descriptor corresponding to the physical address of the first number of descriptors before the target descriptor, and the length of the first packet are released in batch; wherein, the target descriptor is the descriptor corresponding to the physical address of the descriptor currently pointed to by the first pointer; The CPU rewrites the new packet physical address and the new packet length in each of the first number of descriptors, updating the current value of the pointer of the second queue to the current value of the first pointer; the current value of the pointer of the second queue is used to indicate whether to release the packet physical address and the length of the first packet in the first number of descriptors in batch.

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