Integrated circuit bus system, data processing method and programmable logic unit

Abstract

The invention discloses an integrated circuit bus system, a data processing method and a programmable logic unit, and relates to the technical field of storage equipment, and the system comprises a host, the programmable logic unit, a switch unit and a slave which are connected through a bus. If a processing module in the programmable logic unit detects that the slave receives the signal and does not respond within a preset time, an abnormal signal is sent to the host to enable the host to stop data access this time, and if the processing module in the programmable logic unit detects that the cumulative number of times of non-response of the slave reaches a first preset cumulative number of times, the processing module in the programmable logic unit sends an abnormal signal to the host to enable the host to stop data access this time; and the slave is disconnected and enabled again, so that the slave is recovered to a normal state. If the target slave does not respond, the programmable logic unit sends an abnormal signal to the host in time to promote the host to stop data access so as to prevent the host from falling into a deadlock state, and if the cumulative number of times of no response of the slave reaches a preset cumulative number of times, the programmable logic unit controls the switch unit to be switched off and enables the slave power supply after being switched off so as to prevent the host from falling into a deadlock state. And the slave computer can conveniently recover a normal state.

Description

Technical Field

[0001] This application relates to the technical field of centralized storage devices, and in particular, to an integrated circuit bus system, a data processing method applied to the integrated circuit bus system, and a programmable logic unit. Background Art

[0002] In a centralized storage device, generally, a BBU unit (Backup Battery Unit) is used to provide temporary power supply for the whole device during abnormal power-off data backup. The CPU (Central Processing Unit) uses the I2C bus (Inter-Integrated Circuit BUS) to implement version information, charge and discharge detection, and control of the BBU unit. Since the connection path between the motherboard where the CPU is located and the power board where the BBU is located is complex, and there are hot plug and unplug operation scenarios for the BBU unit or the power board, this I2C bus connecting the CPU and the BBU unit often has various abnormal scenarios that cause the bus to deadlock, resulting in data loss problems when the system performs data backup.

[0003] The deadlock fault includes the deadlock of slave devices such as the BBU unit, and also includes the deadlock of the control end of the CPU. There is no effective recovery method for the deadlock of the CPU, and only by restarting the CPU can it be recovered, but this has the risk of service interruption. Summary of the Invention

[0004] This application provides an integrated circuit bus system, a data processing method applied to the integrated circuit bus system, and a programmable logic unit, so as to at least solve the problem in the related art that there is a lack of an effective solution to cope with host deadlock and slave deadlock.

[0005] This application provides an integrated circuit bus system, including: a host, a programmable logic unit, a switch unit, and a slave. The programmable logic unit includes a processing module. The host and the programmable logic unit, the programmable logic unit and the switch unit, and the switch unit and the slave are all connected through an integrated circuit bus. If the processing module in the programmable logic unit detects that the slave receives a signal and does not respond within a predetermined time, it sends an abnormal signal to the host to make the host stop the current data access. If the processing module in the programmable logic unit detects that the cumulative number of times the slave does not respond reaches a first preset cumulative number of times, it disconnects and re-enables the slave so that the slave can return to the normal state.

[0006] Optionally, the programmable logic unit further includes a shaping module and a sampling module. The shaping module is configured to perform a hysteresis comparison on the received integrated circuit bus signal. If the integrated circuit bus signal is higher than the signal upper limit value, a high level is output. If the integrated circuit bus signal is lower than the signal lower limit value, a low level is output. The sampling module is configured to store the sampling value of the signal processed by the shaping module in a shift register, and update the shift register and determine it as a valid level when the sampling values are the same for multiple consecutive times. The sampling frequency of the sampling module is a preset multiple of the integrated circuit bus clock frequency.

[0007] Optionally, the processing module is further configured to: detect the signal status from the host. If the combination of the serial data signal and the serial clock signal meets the start condition, it jumps to the next state. If the combination meets the end condition, it enters the end state.

[0008] Optionally, the programmable logic unit further includes a latching module. The latching module is configured to store the serial data signal in a latch register.

[0009] Optionally, the processing module is further configured to: detect the signal received from the latch register. If the serial data signal received from the latch register is abnormal within one clock cycle, the programmable logic unit stops signal forwarding.

[0010] Optionally, the processing module is further configured to: in the data routing state, if the slave address is matched, establish a connection between the bus signal line of the corresponding slave and the output signal line of the latch register.

[0011] Optionally, the processing module is further configured to: if it is detected that the low level duration of the serial clock signal on the slave side exceeds a first preset time, forcibly pull up the serial clock signal by a preset number of pulses to generate an end condition and record an error log; in the ACK return stage, if the low level duration of the serial data signal on the slave side exceeds a second preset time, forcibly pull up the serial data signal to generate an end condition and record an error log, where the first preset time is greater than the second preset time.

[0012] Optionally, the processing module is further configured to: if the cumulative number of times the slave fails to respond reaches a second preset cumulative number, isolate the address of the slave and upload device failure information to the host.

[0013] Optionally, the processing module is further configured to: in the address matching stage, set a preset list of slave addresses, and the slave addresses in the preset list of slave addresses are allowed to be accessed.

[0014] Optionally, the programmable logic unit is further configured to: control the enabling of the slave power supply if the in-position signal of the slave is detected to be valid, and control the closing of the switch unit if the enabling of the slave power supply is successful.

[0015] Optionally, the switch unit includes a plurality of electrically connected MOS devices.

[0016] Optionally, the host is a controller, the slave is a backup battery unit, and the programmable logic unit is a complex programmable logic unit.

[0017] Optionally, there is one host and multiple slaves.

[0018] The present application also provides a data processing method applied to an integrated circuit bus system, including: receiving an integrated circuit bus signal sent by a host, performing a predetermined process on the integrated circuit bus signal, and then sending it to a slave; determining whether the slave responds to the received signal within a predetermined time; if the slave does not respond within the predetermined time, sending an abnormal signal to the host to cause the host to stop the current data access; if the cumulative number of times the slave does not respond reaches a first preset cumulative number, disconnecting the connection with the slave, and re-enabling the slave so that the slave returns to a normal state.

[0019] Optionally, performing a predetermined process on the integrated circuit bus signal includes: performing a shaping process on the integrated circuit bus signal, and the steps of the shaping process include performing a hysteresis comparison on the integrated circuit bus signal, outputting a high level if the integrated circuit bus signal is higher than the signal upper limit value, and outputting a low level if the integrated circuit bus signal is lower than the signal lower limit value; performing a sampling process on the signal after the shaping process, storing the sampling value in a shift register, and updating the shift register and determining it as a valid level when the sampling values are the same for multiple consecutive times.

[0020] Optionally, the integrated circuit bus signal includes a serial data signal and a serial clock signal. After performing a sampling process on the signal after the shaping process, storing the sampling value in a shift register, and updating the shift register and determining it as a valid level when the sampling values are the same for multiple consecutive times, the method further includes: storing the serial data signal in a latch register; matching the address in the serial data signal with the addresses in the preset list of slave addresses, and if the match is successful, connecting the bus signal line of the corresponding slave to the output signal line of the latch register.

[0021] Optionally, the method further includes: if the cumulative number of times the slave does not respond reaches a second preset cumulative number, isolating the address of the slave and uploading device failure information to the host.

[0022] Optionally, the method further includes: if the in-position signal of the slave is detected to be valid, enabling the power supply of the slave, where a preset level of the in-position signal line indicates that the in-position signal is valid.

[0023] Optionally, the method further includes: if the low-level duration of the serial clock signal on the slave side is detected to exceed a first preset time, forcibly pulling up the serial clock signal by a preset number of pulses to generate an end condition, and recording an error log; in the ACK return stage, if the low-level duration of the serial data signal on the slave side exceeds a second preset time, forcibly pulling up the serial data signal to generate an end condition, and recording an error log, where the first preset time is greater than the second preset time.

[0024] The present application further provides a programmable logic unit, including: a receiving module, configured to receive an integrated circuit bus signal sent by a host, and send the integrated circuit bus signal to a slave after performing a predetermined process on the integrated circuit bus signal; a judging module, configured to judge whether the slave responds to the received signal within a predetermined time; a sending module, configured to send an abnormal signal to the host to cause the host to stop the current data access if the slave does not respond within the predetermined time; and a disconnecting module, configured to disconnect the connection with the slave if the cumulative number of times the slave does not respond reaches a first preset cumulative number of times, and re-enable the slave so that the slave resumes to a normal state.

[0025] With the present application, since a programmable logic unit is added and a MOS circuit is added on the slave side, if the target slave does not respond, the programmable logic unit timely sends a NACK (Not Acknowledge) signal to the host, prompting the host to stop data access, avoiding the host from waiting for a long time and falling into a deadlock state, and if the cumulative number of times the slave does not respond reaches a preset cumulative number of times, the programmable logic unit controls the MOS circuit to disconnect, and enables the power supply of the slave after disconnection, facilitating the slave to resume to a normal state. Therefore, the technical problem that the I2C bus connecting the CPU (host) and the slave (including the BBU unit) often has multiple abnormal scenarios resulting in bus deadlock and data loss during system data backup can be solved, and the technical effect of effectively coping with host deadlock and slave deadlock can be achieved. Description of the Drawings

[0026] To more clearly illustrate the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0027] Figure 1Schematic diagram of the structure of an integrated circuit bus system provided by an embodiment of the present application;

[0028] Figure 2 Schematic diagram of the structure of another integrated circuit bus system provided by an embodiment of the present application;

[0029] Figure 3 Schematic diagram of the structure of a programmable logic unit provided by an embodiment of the present application;

[0030] Figure 4 Schematic flowchart of a data processing method applied to an integrated circuit bus system provided by an embodiment of the present application;

[0031] Figure 5 Flowchart of the slave address preset list mechanism provided by an embodiment of the present application;

[0032] Figure 6 Schematic diagram of the I2C bus control system provided by an embodiment of the present application;

[0033] Figure 7 Schematic diagram of the internal functional modules of a complex programmable logic unit provided by an embodiment of the present application;

[0034] Figure 8 Schematic diagram of the I2C bus control system and method provided by an embodiment of the present application;

[0035] Figure 9 Schematic flowchart of the I2C bus control system and method provided by an embodiment of the present application;

[0036] Figure 10 Flowchart of the SCL low-level detection provided by an embodiment of the present application;

[0037] Figure 11 Flowchart of the SDA low-level detection provided by an embodiment of the present application;

[0038] Figure 12 Block diagram of the structure of a programmable logic unit provided by an embodiment of the present application.

[0039] Among them, the above-mentioned drawings include the following reference numerals:

[0040] 01, integrated circuit bus system; 10, host; 20, programmable logic unit; 30, switch unit; 40, slave; 201, processing module; 202, shaping module; 203, sampling module; 204, latching module. Detailed implementation manners

[0041] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present application without creative efforts belong to the protection scope of the present application.

[0042] It should be noted that in the description of the present application, the terms "include", "comprise" or any other variation thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. The terms "first", "second", etc. in the present application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0043] In order to enable those skilled in the art of the present technology to better understand the solution of the present application, the present application will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0044] An embodiment of the present application provides an integrated circuit bus system, as Figure 1 shown. The integrated circuit bus system 01 includes a host 10, a programmable logic unit 20, a switch unit 30, and a slave 40. The programmable logic unit 20 includes a processing module 201. Between the host 10 and the programmable logic unit 20, between the programmable logic unit 20 and the switch unit 30, and between the switch unit 30 and the slave 40 are all connected by an integrated circuit bus. If the processing module in the programmable logic unit detects that the slave receives a signal and does not respond within a predetermined time, an abnormal signal is sent to the host to cause the host to stop the current data access. If the processing module in the programmable logic unit detects that the number of times the slave fails to respond accumulates to a first preset cumulative number of times, the slave is disconnected and re-enabled so that the slave can return to a normal state.

[0045] Specifically, the integrated circuit bus system includes a host, a Programmable Logic Device (PLD), a switching unit, and slaves. These components are interconnected via the I2C integrated circuit bus, constructing a multi-layer communication structure. The programmable logic unit serves as a transfer station for the integrated circuit bus system. It is not only responsible for signal processing and logic control but also has the ability to monitor the status of slaves. Specifically, the programmable logic unit includes a processing module that can detect the response of a slave after receiving a signal. When the processing module detects that the slave does not respond within a predetermined time after receiving the signal (i.e., NACK or no response), it sends an exception signal to the host, which causes the host to immediately terminate the current data access in progress to avoid unnecessary resource waste and possible system errors. If the cumulative number of times the slave fails to respond reaches a first preset cumulative number, it indicates that there may be deeper problems with the slave. At this time, the processing module of the programmable logic unit takes the measure of disconnecting the connection with the slave and attempts to restore its normal operating state by re-enabling the slave. In this embodiment, if the number of times the slave fails to respond exceeds 3 times, hardware repair is performed on the slave device, that is, the link between the slave and the programmable logic unit PLD is controlled to be disconnected, and the power supply of the slave device is re-enabled to attempt to restore the normal operating state of the slave. This process involves electrical isolation and restart, aiming to clear potential faults of the slave and restore its normal communication ability. Among them, the slave can be a backup battery (BBU), an extended I2C device, a device with extended General-Purpose Input / Output (GPIO) pins, a temperature sensor, etc., and can be many devices controlled by the host CPU.

[0046] Through the above mechanism, the integrated circuit bus system can actively react when faced with slave non-response or abnormal situations, protect the host from errors, and at the same time attempt to repair the slave to ensure the stable operation and data integrity of the entire I2C bus communication network. Compared with traditional I2C bus control systems, this design significantly enhances the robustness and fault recovery ability of the system by introducing a programmable logic unit and intelligent response monitoring and repair logic, and is particularly suitable for application environments that require high reliability and fault tolerance, such as servers, storage devices, etc.

[0047] Furthermore, as Figure 2As shown, the above programmable logic unit 20 further includes a shaping module 202 and a sampling module 203. The shaping module is used to perform a hysteresis comparison on the received integrated circuit bus signal. If the integrated circuit bus signal is higher than the signal upper limit value, a high level is output; if the integrated circuit bus signal is lower than the signal lower limit value, a low level is output. The sampling module is used to store the sampling value of the signal processed by the shaping module in a shift register, and when the above sampling values are the same for multiple consecutive times, the shift register is updated and determined as a valid level. The sampling frequency of the sampling module is a preset multiple of the integrated circuit bus clock frequency.

[0048] Specifically, the shaping module is a signal preprocessing component in the programmable logic unit, and its main task is to ensure that the signal received from the I2C bus conforms to specific logic level standards. The shaping module achieves this function through hysteresis comparison. When the received signal level is higher than the signal upper limit value, a high level is output; conversely, when the received signal level is lower than the signal lower limit value, a low level is output. Through this hysteresis comparison, the shaping module can eliminate noise interference in signal transmission and ensure the stability and reliability of the input signal.

[0049] The sampling module is used to convert the shaped signal into a digital signal and store it in a shift register. The sampling frequency of the sampling module is a preset multiple of the I2C bus clock frequency, which ensures that the sampling frequency can accurately capture each change point of the bus signal and avoids data loss or errors caused by mismatches between the sampling rate and the signal rate.

[0050] When the sampling module detects that the sampling values are the same for multiple consecutive times, it indicates that the signal is stable at a specific level (high or low). At this time, the shift register is updated to reflect the latest signal state, and this state is determined as a valid level. This process helps to ensure the accuracy and integrity of the data. Even when there are certain fluctuations or interferences in signal transmission, the true state of the signal can be confirmed through continuous sampling.

[0051] The combination of the shaping module and the sampling module provides two layers of guarantee for the processing of I2C bus signals inside the programmable logic unit. First, the shaping module ensures the stability of the signal and eliminates noise interference; second, the sampling module ensures the accurate conversion and storage of the signal through precise sampling and continuous level confirmation. This signal preprocessing and sampling mechanism is crucial for maintaining the reliability and accuracy of I2C bus communication, especially in an environment with poor signal transmission quality or potential interference. Through the shaping module and the sampling module, the programmable logic unit can more effectively process and manage I2C bus signals, providing a more stable data transmission environment for the entire integrated circuit bus system and enhancing the overall performance and user experience of the system.

[0052] Further, the above processing module is also used to: detect the signal status from the above host, and if the combination of the serial data signal and the serial clock signal meets the start condition, jump to the next state; if the above combination meets the end condition, enter the end state.

[0053] Specifically, the processing module is responsible for monitoring the I2C bus signals from the host, which mainly include the serial data signal SDA (Serial Data) and the serial clock signal SCL (Serial Clock). Monitoring the signal status ensures that both the sender and the receiver can perform data transmission and processing at the correct moment. Based on the detection of the signal status, the processing module determines whether the current communication should jump to the next state or enter the end state according to preset rules or conditions. I2C bus communication can be understood through a state machine model, where different signal combinations correspond to different states, such as the start state, data transmission state, acknowledgment state, and end state, etc.

[0054] When the combination of the serial data signal and the serial clock signal meets the start condition, it means that one party of the communication (usually the host) is ready to start or continue data transmission. After the processing module recognizes this condition, it will trigger the system to jump to the next state, allowing further processing of data transmission. On the contrary, if the signal combination indicates that the communication should end, that is, the end condition is met (for example, the host sends a stop signal), the processing module will recognize the signal combination that meets the end condition, thereby switching the system state to the end state and stopping the current data transmission process.

[0055] The processing module not only detects the signal status but also automatically adjusts the behavior of the system according to the status. This automated state transition control avoids manual intervention, improves the response speed and efficiency of the system, and at the same time reduces the possibility of errors. The state detection and control mechanism is the key to realizing efficient and reliable I2C bus communication. Through the intelligent judgment of the processing module, it can automatically respond to the start, continuation, and end of the communication, ensure the smooth progress of data transmission, and at the same time quickly react in case of anomalies, such as retrying the communication or entering the fault isolation state, thereby improving the robustness and fault tolerance of the system.

[0056] Further, referring to Figure 3 above, the programmable logic unit 20 further includes a latch module 204, and the latch module is used to store the serial data signal in the latch register.

[0057] Specifically, the latch module is responsible for acquiring and storing the serial data signal SDA on the I2C bus at specific time points. In I2C communication, data is transmitted bit by bit under the control of the serial clock signal SCL. The latch module triggers a latch operation at the falling edge of each clock cycle, acquires the level state of the data line at that time, and stores it in the latch register. This is because the validity of the data is determined at the falling edge of the serial clock signal, and the signal on the data line may change before and after the falling edge. Therefore, it is necessary to lock the serial data signal at the moment of the falling edge. The latch register is a storage unit used to temporarily store the serial data signal acquired by the latch module. As the clock cycle progresses, the content of the latch register is continuously updated until the data of an entire byte (or the required data length) is completely captured. These data can then be read and parsed by the processing module for subsequent communication processing or error checking.

[0058] In the specific implementation process, first, initialize the latch module and set its working parameters, including the address of the latch register and the timing signals for enabling and disabling the latch. This initialization process ensures that the latch module can correctly respond to subsequent signal changes and prepares for data latching. While receiving the serial data signal, the programmable logic unit synchronously detects the serial clock signal because in the I2C bus protocol, data sampling and latching usually occur at the rising edge of the clock signal. Therefore, it is necessary to accurately capture the change of the clock signal. Shape the received serial data signal to remove signal jitter and ensure the clarity and stability of the signal. At the rising edge of the serial clock signal, which is a stable point for data transmission, sample the shaped serial data signal. Sampling is the process of reading the current level of the signal to determine the actual value of the data (0 or 1). After the sampling process is completed, the latch module stores the sampled serial data signal in the latch register, that is, locks the sampled value of the serial data signal at the rising edge of the clock signal. The latch register can be regarded as a container for temporarily storing data, ensuring that the data will not change due to external interference during subsequent processing. The latch module will continuously latch the data at each sampling point according to the rhythm of the clock signal until the entire data byte is completely acquired and latched.

[0059] By adopting the latch module, the programmable logic unit can capture the serial data signal at the most critical moment of each clock cycle, thus avoiding data errors caused by signal instability or transmission delay. This ensures the stability and consistency of communication data in terms of time and space. Especially in high-speed communication scenarios, it can reduce data distortion or misreading. The introduction of the latch module significantly improves the data processing ability and transmission reliability of the integrated circuit bus system. It can ensure that in a complex communication environment, even if there is noise or interference, the data can still be accurately captured and processed. This has a direct positive impact on building a high-performance and highly reliable communication system.

[0060] Furthermore, the processing module is also used to detect the signal received from the latch register. If the serial data signal received from the latch register is abnormal within a clock cycle, the programmable logic unit stops forwarding the signal.

[0061] Specifically, the processing module is also responsible for detecting the data signal received from the latch register. The latch register captures and stores the state of the serial data signal SDA at the falling edge of each clock cycle, and these data are then read and analyzed by the processing module. In a complete clock cycle, the processing module checks the signal stored in the latch register to determine whether there is any irregular or unexpected behavior. Abnormalities of serial data signals include sudden changes in the signal level, remaining unchanged for a long time, or changes that are inconsistent with other signals, all of which represent data errors or communication failures. If the processing module detects that the state of the serial data signal is abnormal within a certain clock cycle, such as an unexpected flip or a continuous invalid level of the data bit, it will automatically take action to prevent the abnormal data from being forwarded to the slave. The above mechanism belongs to the system self-protection mechanism, which is designed to avoid abnormal slave response or system-level errors caused by erroneous data transmission.

[0062] By immediately stopping the forwarding of abnormal signals, the processing module can effectively contain potential data errors and prevent them from spreading in the system. This is crucial to the integrity of I2C bus communication, especially in data-sensitive application scenarios such as storage devices, data processing centers, etc., ensuring accurate data transmission is a basic requirement for system design. This mechanism not only improves the quality of data transmission, but also enhances the robustness and robustness of the entire integrated circuit bus system. Even in harsh electromagnetic environments or transient faults in the communication link, the system can quickly identify and respond, avoiding the risk of long-term data errors or system crashes.

[0063] Furthermore, the processing module is also used for: in the data routing state, if a slave address is matched, establishing a connection between the bus signal line of the corresponding slave and the output signal line of the latch register.

[0064] Specifically, the data routing state refers to the stage when the system is preparing to send data to a specific slave. The start of this state indicates that the host has sent the slave address and is waiting for the processing module of the programmable logic unit (PLD) to perform address matching to determine the target of data transmission. After receiving the slave address sent by the host, the processing module compares it with the preset list of slave addresses, which includes the address information of all slaves and is used to identify and verify the communication target. If the processing module identifies a successful address match, that is, it finds the slave corresponding to the address requested by the host, it proceeds to the next operation. Once the slave address match is successful, the processing module will establish a connection between the bus signal line and the output signal line of the latch register. That is to say, the I2C bus interface of the slave will be directly connected to the output of the latch register inside the programmable logic unit (PLD), thereby allowing data to flow from the latch register to the slave and completing the data transmission. This process ensures the correct and error-free data flow to the slave.

[0065] In the data routing state, the processing module realizes the data transmission from the host to the slave by controlling the connection of the signal lines. The latch register plays a role in data buffering and stabilization during this process, ensuring the integrity and accuracy of the data during transmission. Through precise address matching and dynamic connection of the signal lines, the processing module can ensure that the data is only sent to the correct slave, which not only improves the communication efficiency but also enhances the security of the system, preventing the data from being received by unauthorized slaves.

[0066] Furthermore, the above-mentioned processing module is also used for: if it detects that the low-level duration of the serial clock signal on the slave side exceeds the first preset time, forcibly pull up the serial clock signal by a preset number of pulses to generate an end condition and record an error log; in the ACK return stage, if the low-level duration of the serial data signal on the slave side exceeds the second preset time, forcibly pull up the serial data signal to generate an end condition and record an error log, where the first preset time is greater than the second preset time.

[0067] Specifically, the processing module continuously monitors the state of the serial clock signal SCL on the slave side. If it detects that the low-level state of the serial clock signal lasts for more than the first preset time (the first preset time is set according to the communication protocol and system requirements), it indicates that the slave controller fails to release the clock signal normally, resulting in a bus hang or communication anomaly. At this time, the processing module forcibly pulls up the serial clock signal by a preset number of pulses to simulate the normal end condition of the clock signal, thereby breaking the hang state and restoring the normal communication of the bus. This mechanism can prevent long-term communication stagnation and avoid the degradation of the overall system performance.

[0068] During the ACK return phase of the response, the processing module also monitors the status of the serial data signal SDA on the slave side. If the low-level state of the serial data signal lasts for more than a second preset time, it indicates that the slave fails to release the data line within the specified time, resulting in signal anomalies or communication blockages. Similarly, the processing module will forcibly pull up the serial data signal to simulate the normal end condition of the data signal, ensuring that the bus can continue subsequent communication operations. The first preset time is greater than the second preset time because the abnormal response to the clock signal usually needs to be faster to avoid long-term system stagnation, while the abnormal response to the data signal can be slightly looser on the premise of ensuring data integrity.

[0069] During the above process, the processing module also records the corresponding error logs. The error logs include detailed information about signal anomalies, such as the time point of occurrence, the type of abnormal signal (clock signal or data signal), the duration, and the response measures taken, etc. The error logs are crucial for later problem analysis, fault troubleshooting, and system optimization, providing a detailed record of the system operation status, helping to quickly locate the root cause of the problem, and taking effective measures for repair or optimization.

[0070] By introducing the above signal anomaly detection and response mechanism, as well as error log recording, the processing module can not only respond to communication anomalies in real time to ensure the stability and continuity of communication, but also enhance the robustness and maintainability of the system. Even in the face of hardware failures, software errors, or external interferences, the system can quickly resume normal operation through the self-recovery mechanism and provide a basis for later analysis of problems through the error logs.

[0071] Furthermore, the above-mentioned processing module is also used to: if the cumulative number of times the above-mentioned slave fails to respond reaches a second preset cumulative number, isolate the address of the above-mentioned slave and upload the device failure information to the host.

[0072] Specifically, the processing module continuously monitors the response of the slave. If the slave fails to give the expected response (ACK or data signal) in consecutive communication attempts, the processing module records the cumulative number of times of non-response, which helps to identify possible problems with the slave, such as software failures, hardware damage, or power supply problems, etc. When the cumulative number of times the slave fails to respond reaches the second preset cumulative number, it triggers a further system response. The second preset cumulative number is set based on system stability and fault tolerance, aiming to avoid overreacting system adjustments due to occasional communication failures. For example, if the second preset cumulative number is set to 5 times, it means that the slave needs to fail to respond 5 times consecutively to trigger the isolation mechanism.

[0073] When the cumulative number of times the slave fails to respond reaches the second preset cumulative number, the processing module will isolate the address of the slave from the current I2C communication network, that is, disconnect its physical or logical connection to the bus. Address isolation is an important means to prevent the further deterioration of system communication and protect other normally operating slaves. In addition to physical isolation, the processing module will also upload the device fault information of the slave to the host, usually in the form of an interrupt or a specific data packet. This enables the host to identify the abnormal status of a specific slave in the network, so as to adopt corresponding fault handling strategies, such as reconfiguring the communication network, starting a backup slave, or notifying the system administrator for maintenance.

[0074] Through the detection and response of the cumulative number of non-responses, the timely isolation of faulty slaves and the upload of fault information are achieved. This not only improves the overall stability of the system, reduces the risk of communication interruption caused by a single slave failure, but also enhances the maintainability and fault diagnosis ability of the system, enabling the system to more intelligently and efficiently handle device failures within the network.

[0075] Furthermore, the above-mentioned processing module is also used for: in the address matching stage, setting a preset list of slave addresses, and the slave addresses in the preset list of slave addresses are those allowed to be accessed.

[0076] Specifically, in I2C bus communication, before each communication starts, the host will send a slave address signal to specify the target slave for this communication. The processing module enters the address matching stage, that is, receives and parses the slave address sent by the host, and then compares it with the internal slave address list of the system. The preset list of slave addresses lists all the slave addresses allowed to be accessed. The preset list of slave addresses can be defined during system initialization or updated dynamically during operation to reflect the current system configuration and security policy. The existence of the preset list of slave addresses ensures that only compliant slave addresses can be recognized and responded to.

[0077] In the address matching stage, the processing module will check whether the slave address sent by the host exists in the preset list of slave addresses. If the address match is successful, that is, the slave address is within the preset list of slave addresses, the processing module will allow the communication to continue; otherwise, it will block the communication to prevent unauthorized access or malicious attacks. This security mechanism is particularly important for protecting the system from abnormal access, especially in a communication environment containing sensitive data or critical services.

[0078] By implementing the preset list of slave addresses, the processing module can effectively control which slaves can be accessed and which cannot. This not only enhances the security of the system, preventing unlisted devices from intervening in communication and posing threats, but also improves the controllability of the system. The preset list of slave addresses provides a flexible access control strategy for the system. The preset list of slave addresses can be adjusted according to actual needs, such as adding new slave addresses, deleting retired slave addresses, or even temporarily disabling certain slaves for maintenance or upgrade. This dynamic adjustment ability enables the system to adapt to the changing environment and maintain efficient communication and operation.

[0079] Furthermore, the above programmable logic unit is also used for: if the in-position signal of the above slave is detected to be valid, controlling the power enable of the above slave, and if the power enable of the above slave is successful, controlling the closing of the above switching unit.

[0080] Specifically, the programmable logic unit continuously monitors and evaluates the in-position signal of the slave, which is a signal indicating whether the slave is ready for communication. If the in-position signal is detected to be valid, that is, the slave is ready and able to respond to communication requests, the programmable logic unit will proceed to the next operation. Based on the validity of the in-position signal, the programmable logic unit sends a power enable signal to the slave through its GPIO pin. The purpose of this signal is to activate the power supply of the slave so that it can receive and process communication data at the physical level. If the power enable is successful, that is, the slave acknowledges and responds to the power enable signal, the programmable logic unit will continue the subsequent communication control process.

[0081] After confirming that the power enable of the slave is successful, the programmable logic unit further controls the closing state of the switching unit. The closing of the switching unit represents the establishment of a physical communication link between the host and the slave, thereby allowing data to be transmitted between the two parties through the I2C bus. If the power enable is not successful or the in-position signal is invalid, the programmable logic unit will not close the switching unit, thus protecting the system from sending data to unready slaves and avoiding possible electrical damage or communication errors.

[0082] Through the above mechanism, the programmable logic unit not only achieves fine-grained power management, ensuring that the slave receives power supply only when there is a communication need, saving energy and reducing unnecessary hardware losses, but also enhances the security of communication, avoiding opening communication links to unauthorized or unready slaves. This automated control process of power enable and switching unit closing simplifies the complexity of system integration, automatically adjusts the state of the slave according to communication needs without manual intervention, and can significantly improve communication efficiency and the overall automation level of the system.

[0083] Furthermore, the above switching unit includes a plurality of electrically connected MOS devices.

[0084] The MOS device here refers to a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET). MOS devices are an ideal choice for switching units due to their low on-resistance, high switching speed, and good current control characteristics. Especially in bus communication systems that require frequent state switching, MOS devices can quickly respond to the control signals of the programmable logic unit and efficiently turn on or off the communication channel.

[0085] Series and / or parallel configurations of MOS devices can be adopted. The series configuration can be used to increase the voltage withstand capacity. For example, in high-voltage applications, multiple MOS devices connected in series can share the high voltage, reduce the stress on a single device, and improve the reliability of the entire system. The parallel configuration, on the other hand, can increase the current-carrying capacity to ensure that the switching unit can operate stably in high-current applications. The specific connection method will be determined according to the design requirements and electrical specifications of the system.

[0086] By using MOS devices to form the switching unit, the integrated circuit bus system can achieve refined power management and communication control. The programmable logic unit can control the on and off states of the MOS device by changing the gate voltage of the MOS device, thereby realizing the dynamic management of the communication link. For example, when the slave is offline, its power supply can be disconnected to reduce unnecessary power consumption; or when there is a communication anomaly, the link can be quickly cut off to prevent electrical overload or data conflict. The use of MOS devices and their combination methods provide a high degree of flexibility for system design. Designers can flexibly select the number and connection method of MOS devices according to the current and voltage requirements of specific applications to achieve the optimal balance between performance and cost. In addition, this also facilitates the expansion and upgrade of the system. For example, when additional communication links are needed, the number of MOS devices and the corresponding control logic can be directly increased without significantly modifying the original circuit design. In short, the above settings of multiple electrically connected MOS devices not only meet the power management and signal isolation requirements during communication but also enhance the scalability and adaptability of the system, making it suitable for a variety of complex and changing application scenarios.

[0087] Furthermore, the above host is a controller, the above slave is a backup battery unit, and the above programmable logic unit is a Complex Programmable Logic Device (CPLD).

[0088] Specifically, the host is a controller, that is, the host is the device responsible for overall coordination and management, responsible for initiating communication requests, performing read and write operations, managing and maintaining communication protocols, etc. In the I2C bus system, the controller (i.e., the host) is the central processing unit CPU, responsible for controlling the interaction with multiple slaves to obtain data, send instructions, or perform status queries.

[0089] The slave is a backup battery unit BBU, which is a component commonly found in servers, network devices, and high-end computers, used to provide emergency power when the main power fails to maintain the operation of critical system functions. The communication between the programmable logic unit and the backup battery unit is crucial because it determines whether the system can quickly switch to the backup power supply in case of main power failure or other anomalies, ensuring data security and normal system operation.

[0090] The programmable logic unit is a complex programmable logic unit, which is a highly integrated and powerful programmable logic device that can implement complex digital circuit logic functions, such as signal processing, control algorithms, and communication protocols. The programmable logic unit not only serves as a relay station for the I2C bus but also is responsible for important logic control tasks, such as signal shaping, sampling, latching, protocol parsing and exception handling, as well as switch unit control and slave power enabling.

[0091] Defining the host as a controller, the slave as a backup battery unit, and specifying the programmable logic unit as a complex programmable logic unit, such a system design targets high-availability demand scenarios such as centralized storage devices or data centers. The high performance and flexibility of the programmable logic unit ensure efficient and reliable communication between the controller and the backup battery unit. Especially in emergency situations such as power failures, it can respond quickly to ensure data integrity and system stability. In addition, the use of the programmable logic unit also simplifies system design and maintenance. Hardware logic adjustment can be achieved through software programming, improving the maintainability and upgrade potential of the system.

[0092] Furthermore, there is one such host and multiple such slaves.

[0093] In a configuration with one host and multiple slaves, the host assumes the role of the control center of the system, responsible for initiating communication, coordinating data exchange, managing slave status, supervising the execution of communication protocols, etc. In this application, the host establishes a connection with the programmable logic unit through the I2C bus and then communicates indirectly with multiple slaves through the programmable logic unit, ensuring the unity and orderliness of system communication.

[0094] Slaves can be distributed at various positions in the system, and each slave has a specific function or task, such as data storage, sensor data acquisition, signal amplification, power management, etc. In this application, these slaves include different backup battery units, which are connected to the programmable logic unit through their respective I2C buses, and the programmable logic unit manages the communication with the host.

[0095] The programmable logic unit acts as a bridge between a host and multiple slaves. It not only processes the communication between the host and a specific slave but also is responsible for dynamically adjusting the communication link according to the status of the slave (such as the presence signal and power enable signal), thereby achieving effective management and communication control of multiple slaves.

[0096] The configuration of one host for multiple slaves provides good scalability and flexibility for the system. As the system requirements grow, the number of slaves can be increased, and only the number of GPIO pins and other resources of the programmable logic unit need to be expanded accordingly, without changing the structure or logic of the host. This flexibility enables the system to adapt to different scales and complexities.

[0097] Embodiments of this application also provide a data processing method applied to an integrated circuit bus system, as Figure 4 shown, the method includes the following steps:

[0098] Step S401: Receive the integrated circuit bus signal sent by the host, and after performing predetermined processing on the above integrated circuit bus signal, send it to the slave;

[0099] Specifically, receive the integrated circuit bus signals sent from the host. These signals can be data read requests, data write instructions, or other types of control signals. After receiving the signals, process the signals according to its internal logic and preset processing flow, including signal shaping to ensure the integrity of the signal; sampling to ensure accurate reading of the signal; and protocol parsing to ensure that the signal conforms to the I2C bus communication protocol and avoid communication errors. After processing, forward the signal to the target slave to start the response process of the slave.

[0100] Step S402: Determine whether the above slave responds to the received signal within a predetermined time;

[0101] Specifically, monitor the response of the slave within a predetermined time window (predetermined time). The predetermined time is set according to the I2C bus communication protocol and the response speed of the slave, and is used to determine whether the slave responds to the host's communication request within a reasonable time. If the response signal of the slave is detected within the predetermined time, it is considered that the slave has successfully responded to the host's communication request; otherwise, if no response signal is detected, enter the exception handling process.

[0102] Step S403, if the above slave does not respond within the above predetermined time, send an abnormal signal to the above host to cause the above host to stop the current data access;

[0103] Specifically, when the slave does not respond within the predetermined time, an abnormal signal is sent to the host. This abnormal signal notifies the host that the slave's non - response is due to communication link problems, slave failures, or other reasons. After receiving the abnormal signal, the host will stop the current data access, avoiding continuous data transmission to the non - responsive slave and preventing possible communication errors or resource waste.

[0104] Step S404, if the cumulative number of times the above slave does not respond reaches a first preset cumulative number of times, disconnect the connection with the above slave, and re - enable the above slave so that the above slave can return to the normal state.

[0105] Specifically, if the cumulative number of times the slave does not respond reaches a preset threshold (the first preset cumulative number of times), disconnect the communication connection with the slave, indicating that there is a problem with the slave and it needs to be diagnosed or repaired. After disconnecting the connection, re - enable the slave and try to restore its state. The process of re - enabling includes sending a specific power - on enable signal, executing an initialization sequence, or executing other fault recovery procedures to help the slave return to the normal working state. By re - enabling the slave, an opportunity for the slave to restore its communication ability is provided. If the slave can be successfully restored, the communication link will be re - established and the slave can continue to participate in the normal communication of the system.

[0106] The data - processing method of the embodiments of the present application significantly enhances the communication stability and fault - recovery ability of the integrated - circuit bus system, especially the I2C bus system. By receiving and processing the host's signals, the accuracy and integrity of the data are ensured, thus optimizing the communication efficiency. The slave - response monitoring mechanism can detect communication anomalies in a timely manner. By sending an abnormal signal to the host, invalid data access is immediately aborted, avoiding the waste of system resources and the accumulation of possible communication errors. When the cumulative number of times the slave does not respond exceeds the preset threshold, the connection with the slave is automatically disconnected and an attempt is made to re - enable it. This mechanism can not only effectively isolate the faulty slave and prevent its impact on the overall system communication, but also provide the possibility of automatic recovery of the slave state, greatly enhancing the self - repair ability and high availability of the system.

[0107] Further, perform predetermined processing on the above integrated circuit bus signal, including: performing shaping processing on the above integrated circuit bus signal, and the steps of the shaping processing include performing hysteresis comparison on the above integrated circuit bus signal. If the above integrated circuit bus signal is higher than the signal upper limit value, output a high level; if the above integrated circuit bus signal is lower than the signal lower limit value, output a low level; performing sampling processing on the signal after the above shaping processing, storing the sampling value in a shift register, and updating the above shift register and determining it as a valid level when the above sampling values are the same for multiple consecutive times.

[0108] Specifically, the purpose of signal shaping processing is to ensure the quality of the signal so that it is not easily affected by noise or interference during transmission. Hysteresis comparison makes the signal need to exceed a certain range to change the output state, which can avoid frequent signal jumps under the influence of noise and improve the stability of the signal. If the integrated circuit bus signal is higher than the signal upper limit value, the shaping processing will adjust it to a high level; on the contrary, if the integrated circuit bus signal is lower than the signal lower limit value, it will be adjusted to a low level. This mechanism ensures that even if the signal is slightly distorted during transmission, it can be corrected to the standard level range, thus ensuring the signal recognition and communication accuracy.

[0109] The signal after shaping processing will then be sampled, and the sampling values will be sequentially stored in the shift register. If the values of multiple consecutive samplings are the same, it means that the signal has remained at a relatively stable level for a period of time. At this time, the content of the shift register will be updated, and the corresponding level is regarded as a valid level. This mechanism can filter out short-term signal fluctuations or noise and only recognize those level changes that last for a long time and represent the true signal state, thus improving the signal processing accuracy and communication reliability.

[0110] Through shaping processing, signal distortion and noise interference can be effectively reduced, ensuring the transmission quality and integrity of the signal. Sampling processing combined with the determination of consecutive values can accurately identify the true state of the signal, and ensure the accurate reading of data even in a complex and dynamic communication environment. Through the above processing, the communication efficiency and stability of the integrated circuit bus system can be greatly improved.

[0111] Furthermore, the above integrated circuit bus signal includes a serial data signal and a serial clock signal. After performing sampling processing on the signal after the above shaping processing, storing the sampling value in a shift register, and updating the above shift register and determining it as a valid level when the above sampling values are the same for multiple consecutive times, the above method further includes: storing the above serial data signal in a latch register; matching the address in the above serial data signal with the addresses in the slave address preset list. If the match is successful, connect the bus signal line of the corresponding slave to the output signal line of the above latch register.

[0112] Specifically, after completing signal shaping and sampling processing, as well as determining the valid level of the sampled values, the serial data signal is stored in the latch register. The latch register can capture and hold the state of the signal in a certain clock cycle until the next clock cycle arrives. This is crucial for subsequent data processing because the latch register can ensure that the data does not change when it is read or processed, improving data consistency and predictability.

[0113] Communication in the I2C bus system is based on addresses, and each slave has its unique address. In the later stage of signal processing, the serial data signal stored in the latch register is parsed to extract the slave address information contained therein, and this address information is compared with the preset list of slave addresses to determine the identity of the target slave. The preset list of slave addresses is a database that stores all possible slave addresses. By matching the addresses in the signal, the target slave can be quickly located. If the address match is successful, that is, the specified slave address in the serial data signal is found to be the same as an address in the preset list of slave addresses, then the corresponding slave will be selected for communication. Specifically, the bus signal line of the selected slave is connected to the output signal line of the latch register to prepare for data reading and writing operations.

[0114] By using the latch register, the integrity and consistency of the data can be further ensured on the basis of the results of signal shaping and sampling processing, avoiding the impact on communication caused by transient changes during data transmission. The address matching mechanism ensures that the host can accurately identify and select the correct slave for communication, reducing communication latency and errors and improving communication efficiency. Combined with signal shaping and sampling processing, the address matching further enhances the communication reliability of the I2C bus system, and can effectively filter out noise and avoid communication failures caused by incorrect address parsing.

[0115] Furthermore, the above method further includes: if the cumulative number of times the above slave fails to respond reaches the second preset cumulative number of times, isolating the address of the above slave and uploading the device fault information to the host.

[0116] Specifically, if the cumulative number of times the slave fails to respond reaches a higher warning threshold, i.e., the second preset cumulative number of times, it means that there may be serious communication failures or hardware problems with the slave, and further measures need to be taken to prevent its impact on the entire system. At this time, communication with it will not continue to be attempted, but its address will be isolated instead. That is to say, in subsequent communication polls, the address of this slave will be ignored by the system and will not be selected by the host for data access or sending control instructions. This measure can avoid continuous attempts on faulty or abnormal slaves, reduce unnecessary communication overhead, and prevent potential communication conflicts or incorrect instructions from affecting the system. In addition to address isolation, the fault information of the slave will also be uploaded to the host. This information includes the ID of the slave, the type of fault (such as communication failure), the specific number of abnormal responses, etc. After receiving this information, the host can perform higher-level error handling based on the fault information, such as recording the fault log, starting a standby slave, or executing a fault recovery program. This process ensures timely response and management of faults, improving the overall stability and fault recovery ability of the system.

[0117] By setting the second preset cumulative number of times, a more conservative but effective strategy can be adopted after the initial attempt to recover fails, avoiding the normal operation of the entire system being affected by a single slave failure. The slave address isolation mechanism reduces ineffective communication attempts on faulty slaves, optimizes the allocation of communication resources, and improves the efficiency and overall performance of system communication. The upload of fault information enables the host to analyze and record the faults of the slave in more detail, which helps with subsequent fault diagnosis, equipment maintenance, and the execution of fault recovery programs, improving the self-repair ability and maintenance efficiency of the system.

[0118] Furthermore, the above method further includes: if the in-position signal of the above slave is detected to be valid, then control the power enable of the above slave, where the in-position signal line level being the preset level indicates that the in-position signal is valid.

[0119] Specifically, the presence signal is a signal used to indicate whether the slave is in a communicable state, which is transmitted through a dedicated signal line (presence signal line). Continuously monitor the level state of the presence signal line to determine whether the slave is online and ready to receive or respond to communication requests. When the level of the presence signal line reaches a preset level, it indicates that the signal is valid, that is, the slave is in a communicable state. The preset level is set according to the hardware characteristics of the slave and the requirements of the communication protocol, and serves as a reference for logical judgment to distinguish whether the slave is online. When the presence signal of the slave is detected to be valid, control the power enable signal of the slave to allow the slave to receive data or perform other communication operations. The power enable signal usually controls the power supply of the slave, ensuring that its power is only activated when the slave is online and ready to communicate, thus avoiding unnecessary energy consumption. The above mechanism ensures the logical relationship between the presence signal of the slave and the power enable signal. Only when the slave is in a communicable state, its power will be activated, otherwise it will be turned off. This not only enhances the accuracy of slave state management, but also improves the energy efficiency and security of the system.

[0120] By detecting the presence signal and controlling the power of the slave accordingly, the state of the slave can be precisely managed, ensuring that only the online slave can participate in communication and avoiding ineffective communication attempts for non-online slaves. The control mechanism of power enable can avoid powering the slave when it is not necessary, reducing energy waste. Ensuring the consistency between the presence state and the power state of the slave can avoid communication problems caused by unstable or abnormal power states, improving the overall stability and security of the system.

[0121] Furthermore, the above method further includes: if it is detected that the low-level duration of the serial clock signal on the slave side exceeds a first preset time, forcibly pull up the serial clock signal by a preset number of pulses to generate an end condition, and record an error log; in the ACK return stage, if the low-level duration of the serial data signal on the slave side exceeds a second preset time, forcibly pull up the serial data signal to generate an end condition, and record an error log, where the first preset time is greater than the second preset time.

[0122] Specifically, I2C bus communication relies on the serial clock signal to synchronize data transmission. If it is detected that the low-level duration of the serial clock signal on the slave side exceeds the first preset time, it indicates that the slave controller fails to release the clock signal normally, resulting in a bus hang or communication anomaly. At this time, forcibly pull up the serial clock signal by a preset number of pulses to simulate the normal end condition of the clock signal, thereby breaking the hang state and restoring normal communication of the bus. This mechanism can prevent long-term communication stagnation and avoid a decline in the overall performance of the system.

[0123] The ACK (Acknowledgement) signal is a feedback signal used to confirm data reception in I2C communication and is usually sent by the slave after the data transfer is completed. If the low-level duration of the serial data signal exceeds the second preset time during the slave response phase, it indicates that the slave fails to release the data line within the specified time, resulting in signal anomalies or communication blockages. At this time, the serial data signal is forcibly pulled high to simulate the normal end condition of the data signal and ensure that the bus can continue subsequent communication operations. The first preset time is greater than the second preset time because an abnormal response to the clock signal usually requires a faster speed to avoid long-term system stagnation, while the abnormal response to the data signal can be slightly looser on the premise of ensuring data integrity.

[0124] In both of the above cases, whether intervention measures are taken due to abnormalities in the serial clock signal or the serial data signal, detailed error logs will be recorded. The error logs include detailed information about the signal anomalies, such as the time point of occurrence, the type of abnormal signal (clock signal or data signal), the duration, and the response measures taken, etc. The error logs are crucial for later problem analysis, fault troubleshooting, and system optimization, providing a detailed record of the system operation status, helping to quickly locate the root cause of the problem, and taking effective measures for repair or optimization.

[0125] Generating an end condition by forcibly pulling high the signal can actively intervene and restore communication, shorten the fault time, and reduce the negative impacts caused by data loss or communication failures. The recording of the error logs provides clues for fault troubleshooting, helps to quickly locate the problem, perform targeted repairs on the system, and improve the system availability and maintenance efficiency. It can ensure that measures can be taken in a timely manner when the signal is abnormal, avoid the communication link being in an unstable state for a long time, and enhance the robustness and anti-interference ability of I2C bus communication.

[0126] Through the description of the above implementation manners, those skilled in the art can clearly understand that the method according to the above embodiments can be implemented by means of software plus a necessary general hardware platform. Of course, it can also be implemented by hardware, but in many cases, the former is a better implementation manner.

[0127] In I2C communication, the clock signal is usually generated by the master, but the slave is allowed to extend the current clock cycle by pulling down the serial clock signal SCL during data reception or processing. This process is called clock stretching. The CPLD can be designed to have a dynamic clock stretching control function and can automatically adjust the duration of clock stretching according to the actual response ability of the slave. For example, when the CPLD detects that the slave responds slowly, it allows a longer clock stretching to ensure that the slave has enough time to process the data and avoid data transmission errors.

[0128] CPLD can monitor the communication status of I2C bus and dynamically adjust the communication rate according to the real-time communication conditions (such as signal quality, slave response speed, etc.). When it detects that the communication quality is poor or the slave processing capacity is limited, CPLD will automatically reduce the transmission rate to reduce communication errors; on the contrary, when the communication conditions are good, CPLD can increase the rate to speed up data transmission and improve system efficiency. This adaptive adjustment mechanism can ensure the stability and efficiency of I2C bus communication under different working environments.

[0129] The integrated circuit bus system of the present application and the data processing method applied to the integrated circuit bus system are described below through a specific embodiment.

[0130] The present application adds a programmable logic unit between the CPU host and the slave, thereby realizing the recovery of the slave deadlock and avoiding the CPU-side host deadlock, significantly improving the reliability of the I2C bus and ensuring the stable operation of the electronic equipment.

[0131] This application includes the following key components and corresponding functions:

[0132] Host: As the controller of the I2C bus control system, its I2C signal is connected to the GPIO pin of the CPLD. It has a retry mechanism when accessing slave data. When a NACK signal is received, it automatically initiates data access again. If a NACK signal is still received after 3 retries, the address is isolated and the device error is reported to prevent continuous problems caused by a single communication anomaly.

[0133] Switch unit: includes multiple electrically connected MOS devices, which form a MOS circuit. The MOS circuit serves as a switch link between the CPLD and the slave, and is controlled by the GPIO of the CPLD. When the CPLD detects that the slave device is in place and the power is enabled, the link is connected; when the repair mechanism is triggered, the link is disconnected and reconnected, ensuring the timely connection and disconnection of the communication link, and providing the necessary electrical isolation conditions for the repair operation of the slave.

[0134] Slave: As a slave device of the I2C bus control system, its power enable signal and presence signal are connected to the GPIO pin of the CPLD. Based on the detected slave device presence signal, the CPLD controls the opening of the power enable signal to achieve precise control of the slave power supply, ensuring that the slave will not be powered by mistake when it is not in the presence state.

[0135] CPLD: As the transfer station of the I2C bus control system, it undertakes the core signal processing and logic control functions. Two of its GPIOs are connected to the host I2C bus, and the other two GPIOs are connected to the slave I2C bus. Verilog hardware description language is used to implement many important functions:

[0136] Shaping Module: Implement a Schmitt trigger using Verilog language to perform hysteresis comparison on the input I2C signal to eliminate signal noise. Set the signal upper limit parameter HYSTERESIS_HIGH and the signal lower limit parameter HYSTERESIS_LOW. When the input signal is higher than the upper limit, output a high level; when it is lower than the lower limit, output a low level to ensure the stability and reliability of the input signal.

[0137] Sampling Module: Sample the signal at a frequency 4 times that of the I2C clock, and store the sampled values in a shift register. Only when the sampled values are the same for 3 consecutive times will the register be updated and determined as a valid level, ensuring the accuracy and stability of the sampling results and providing a reliable basis for subsequent signal processing.

[0138] Latching Module: At the rising edge of the SCL of I2C, put the SDA signal at this time into the latch register to achieve buffered storage of the I2C signal and provide a stable signal source for the protocol parsing and exception handling links.

[0139] Processing Module: Includes a protocol parsing sub-module and an exception handling sub-module, which comprehensively parse the latched I2C signal, covering multiple important states such as START / STOP state detection, protocol filtering, address matching, data routing, signal forwarding, and error detection. Specifically:

[0140] In terms of START / STOP state detection, strictly detect the signal state from the host. When the combination of SCL and SDA meets the START condition, immediately jump to the next state; when the combination meets the STOP condition, quickly enter the STOP state to ensure accurate state transitions during the communication process.

[0141] In the abnormal signal analysis section, carefully detect the signal from the latch. If, within one clock cycle, the SDA signal shows unexpected situations such as a continuous low level or a continuous high level, it is determined as an abnormal signal. At this time, the CPLD returns an ACK signal and does not forward the signal, effectively preventing abnormal signals from spreading on the bus and avoiding interference with other devices.

[0142] In the address matching stage, set a preset list of slave addresses. When the address sent by the host is a legal address, the address signal is forwarded to the slave; conversely, if the address is illegal, the CPLD sends a NACK signal to the host and records a detailed error log to provide key information for subsequent fault troubleshooting. The flow chart of the preset list mechanism for slave addresses can be seen in Figure 5 .

[0143] In the data routing state, once the slave address is matched, the connection between the I2C signal line of the corresponding slave and the output signal line of the latch is immediately established to ensure the precise establishment of the data transmission path and guarantee the correct transmission of data.

[0144] In the signal forwarding state, the address bits and data bits in the latch register are accurately sent to the corresponding slave device. If the target slave does not respond, the CPLD promptly sends a NACK signal to the host to prompt the host to stop data access and avoid the host being in a deadlock state due to long-term waiting.

[0145] In the error detection section, low-level timeout detection is performed on the SDA and SCL signals:

[0146] Once it is detected that the low-level duration of the SCL at the slave end exceeds 35 ms, the CPLD resolutely and forcibly pulls up the SCL signal by 9 pulses to generate a STOP condition and record the corresponding error log; if the low-level of SCL does not time out, the communication continues normally to ensure the normal periodic change of the SCL signal and maintain the smoothness of the communication.

[0147] For the SDA signal, if it remains low during the data bit stage, it is regarded as normal communication; but in the ACK return stage, if the low-level duration of SDA exceeds 4 ms, the CPLD immediately forcibly pulls up the SDA signal to generate a STOP condition and record the error record to prevent the abnormal continuous low-level state of the SDA signal from affecting the entire communication system.

[0148] When an error first occurs in a certain slave, the system records the alarm status; if the number of errors exceeds 3 times, hardware repair is performed on the slave device, that is, the link between the slave and the CPLD is controlled to be disconnected, and the power of the slave device is re-enabled to attempt to restore the normal working state of the slave; if the number of errors of the slave device exceeds 5 times, the address of the device is isolated to prevent the faulty slave from further affecting the entire I2C bus system and ensure the reliability and stability of the system.

[0149] Specifically, as Figure 6 shown, the integrated circuit bus system of the present application consists of a host, a complex programmable logic unit CPLD, a switch unit, and slaves. Among them, the switch unit includes multiple electrically connected MOS devices, and a MOS circuit is formed by multiple electrically connected MOS devices. The I2C signal of the host is connected to the GPIO pin of the CPLD, and the MOS circuit serves as the switch link between the CPLD and the slaves and is controlled by the GPIO of the CPLD. The power enable signal and the presence signal of the slaves are connected to the GPIO pins of the CPLD, and the CPLD controls the turning on of the power enable signal according to the detection result.

[0150] The CPLD serves as the core transfer station of the system, and its internal functional modules are as Figure 7As shown in the figure. The shaping module performs hysteresis comparison on the input I2C signal through a Schmitt trigger to eliminate noise. The sampling module samples the signal at a frequency four times that of the I2C clock to ensure sampling accuracy. The latching module latches the SDA signal into the register at the rising edge of SCL. The processing module includes a protocol parsing sub-module and an exception handling sub-module, and the protocol parsing and exception handling module is responsible for performing a series of protocol parsing and exception handling operations on the latched signal.

[0151] When the host sends data to the slave, the signal enters the protocol parsing sub-module and the exception handling sub-module after being processed by the shaping, sampling, latching, etc. of the CPLD. First, the START state is detected to confirm the start of communication; then operations such as protocol filtering and address matching are performed on the signal. If the address matching is successful, it enters the data routing state to establish the connection of the slave signal line; then in the signal forwarding state, the data is sent to the corresponding slave. If an exception occurs during the process, such as the slave not responding or the signal low level timing out, etc., the CPLD processes it according to the corresponding rules, such as sending a NACK signal, recording an error log, forcibly pulling up the signal to generate a STOP condition, etc., and triggering the hardware repair mechanism when necessary to control the MOS circuit to disconnect the link and re-enable the slave power supply, or isolate the faulty slave address. The schematic diagram of the I2C bus control system and method can be seen in Figure 8 .

[0152] In practical applications, taking an I2C bus system with multiple slaves as an example, the operation process of this application is elaborated in detail. The schematic diagram of the I2C bus control system and method flow can be seen in Figure 9 .

[0153] Suppose the system has 3 slaves with addresses 0x50, 0x51, and 0x52 respectively. The preset list of slave addresses is preset inside the CPLD as 0x50, 0x51, and 0x52.

[0154] When the host needs to read the data of slave 0x50, the host sends a data frame containing the slave address 0x50 and the read command through the I2C bus. The I2C signal of the host is transmitted to the CPLD via its GPIO pin. The shaping module of the CPLD first processes the input I2C signal and eliminates the signal noise through a Schmitt trigger. For example, if during the transmission process, due to factors such as line interference, the I2C signal has small fluctuations, the shaping module can smooth out these fluctuations to ensure that the subsequent processing module receives a stable signal.

[0155] Next, the sampling module samples the signal at a frequency four times that of the I2C clock. Assuming the I2C clock frequency is 100 kHz, the sampling frequency of the sampling module is 400 kHz. The sampled values are stored in the shift register. Only when the sampled values are the same for three consecutive times will the register be updated and the valid level be determined, which can effectively avoid misjudgment caused by occasional signal glitches.

[0156] At the rising edge of the SCL signal of I2C, the latching module latches the SDA signal at this time into the latch register. Subsequently, the protocol parsing sub-module and the exception handling sub-module start to work. First, the START state is detected to confirm that the host has initiated a new communication request. Then, the signal is protocol-filtered to check whether the data frame conforms to the I2C protocol specification. In the address matching stage, the address 0x50 sent by the host is compared with the addresses in the preset list of slave addresses. It is found that the match is successful, so it enters the data routing state, and connects the I2C signal line of slave 0x50 to the output signal line of the latch.

[0157] In the signal forwarding state, the CPLD sends the address bits and read command data bits in the latch register to slave 0x50. After receiving the address and command, slave 0x50 returns the corresponding data. If slave 0x50 responds normally, the data is forwarded back to the host through the CPLD to complete a successful read operation.

[0158] If slave 0x50 fails to respond due to a fault and does not send an acknowledgment signal to the CPLD within the specified time, after the CPLD detects this situation, it sends a NACK signal to the host, and the host stops the current data access after receiving it. At this time, the CPLD records the error count of this slave. If the error count of slave 0x50 accumulates to 3 times, the CPLD triggers the hardware repair mechanism, controls the MOS circuit to disconnect the link with slave 0x50, and re-enables the power supply of slave 0x50. After the power is re-powered on, slave 0x50 performs a reset initialization operation and attempts to restore the normal working state. The CPLD attempts to establish a connection with slave 0x50 again after a period of time. If the connection is successful and the communication is normal, it will continue to include it in the normal communication scope; if the error count of slave 0x50 further increases and exceeds 5 times, the CPLD isolates the device address 0x50, no longer sends data access requests to it, and reports the fault information of this device to the host for subsequent maintenance processing.

[0159] For the in - place detection of the slave device, the CPLD monitors it in real - time through the in - place signal line connected to the slave device. For example, when the level of the in - place signal line of slave device 0x51 is high, the CPLD determines that the slave device is in place, and then turns on the power enable signal of the slave device to supply power to slave device 0x51, enabling it to work properly and participate in the I2C bus communication. If the level of the in - place signal line is low, the CPLD does not turn on the power enable signal to avoid invalid power supply to the absent slave device.

[0160] During the communication process, the CPLD continuously performs error detection. Figure 10 It is the flowchart of SCL low - level detection. Taking the SCL signal detection as an example, if the low - level duration of the SCL at the slave device end exceeds 35 ms, the CPLD immediately forces the SCL signal to be pulled high for 9 pulses, generates a STOP condition, terminates the current abnormal communication process, and records an error log. This can prevent the entire I2C bus communication from being blocked due to the continuous low - level of the slave device's SCL signal, affecting the communication of other normal slave devices.

[0161] See Figure 11 , for the SDA signal, during the data - bit transmission stage, if the SDA is continuously low, it belongs to normal communication situations, such as when the slave device is sending data; but during the ACK return stage, if the low - level duration of the SDA exceeds 4 ms, the CPLD forces the SDA signal to be pulled high, generates a STOP condition, and records an error record. This helps to timely handle the abnormal continuous low - level problem of the SDA signal during the ACK stage, ensuring the correctness and timeliness of communication.

[0162] The CPLD can integrate intelligent fault - detection functions. It can not only detect abnormalities in I2C bus signals (such as continuous high - level or low - level states), but also identify more complex problems, such as abnormal slave - device response modes, sudden changes in communication traffic, etc. Once a fault is detected, the CPLD immediately records the fault information and takes corresponding actions according to the preset fault - handling strategies.

[0163] After detecting a fault, the CPLD can perform a series of preset automatic recovery operations, such as resetting the I2C bus, re - initiating communication attempts, switching to a standby slave device, etc., to minimize the impact of the fault on the system. For recoverable faults, such as momentary signal interference, the automatic recovery mechanism can quickly restore communication, avoiding manual intervention and improving the self - healing ability of the system.

[0164] The embodiments of this application also provide a programmable logic unit, such as Figure 12As shown, the programmable logic unit includes a receiving module 100, a judging module 200, a sending module 300, and a disconnecting module 400. The receiving module is used to receive the integrated circuit bus signal sent by the host, and after performing predetermined processing on the above integrated circuit bus signal, send it to the slave; the judging module is used to judge whether the above slave responds to the received signal within a predetermined time; the sending module is used to send an abnormal signal to the above host to cause the above host to stop the current data access if the above slave does not respond within the above predetermined time; the disconnecting module is used to disconnect the connection with the above slave if the cumulative number of times the above slave does not respond reaches a first preset cumulative number of times, and re-enable the above slave so that the above slave returns to a normal state.

[0165] The above embodiments significantly enhance the communication stability and fault recovery ability of the integrated circuit bus system, especially the I2C bus system. By receiving and processing the signals of the host, the accuracy and integrity of the data are ensured, thus optimizing the communication efficiency. The slave response monitoring mechanism can detect communication anomalies in a timely manner. By sending an abnormal signal to the host, invalid data access is immediately aborted, avoiding waste of system resources and possible accumulation of communication errors. When the cumulative number of times the slave does not respond exceeds the preset threshold, the connection with the faulty slave is automatically disconnected and an attempt is made to re-enable it. This mechanism can not only effectively isolate the faulty slave and prevent its impact on the overall system communication, but also provide the possibility of automatic recovery of the slave state, greatly enhancing the self-repair ability and high availability of the system.

[0166] Further, the above receiving module includes a shaping sub-module and a sampling sub-module. The shaping sub-module is used to perform shaping processing on the above integrated circuit bus signal. The steps of the above shaping processing include performing a hysteresis comparison on the above integrated circuit bus signal. If the above integrated circuit bus signal is higher than the signal upper limit value, a high level is output. If the above integrated circuit bus signal is lower than the signal lower limit value, a low level is output; the sampling sub-module is used to perform sampling processing on the signal after the above shaping processing, store the sampling value in a shift register, and update the shift register and determine it as a valid level when the above sampling values are the same for multiple consecutive times.

[0167] Through the shaping processing, signal distortion and noise interference can be effectively reduced, ensuring the transmission quality and integrity of the signal. The sampling processing combined with the determination of consecutive values can accurately identify the true state of the signal, ensuring accurate data reading even in a complex and dynamic communication environment. Through the above processing, the communication efficiency and stability of the integrated circuit bus system can be greatly improved.

[0168] Furthermore, the above integrated circuit bus signals include a serial data signal and a serial clock signal, and the above programmable logic unit further includes a storage module and a matching module. The storage module is used to sample the signal after the above shaping process, store the sampled value in a shift register, and update the shift register and determine it as a valid level after the above sampled values are the same for multiple consecutive times, and then store the above serial data signal in a latch register; the matching module is used to match the address in the above serial data signal with the addresses in the slave address preset list. If the match is successful, the bus signal line of the corresponding slave is connected to the output signal line of the above latch register.

[0169] By using a latch register, the integrity and consistency of data can be further ensured on the basis of the results of signal shaping and sampling processing, avoiding the impact on communication caused by transient changes during data transmission. The address matching mechanism ensures that the host can accurately identify and select the correct slave for communication, reducing communication latency and errors, and improving communication efficiency. Combined with signal shaping and sampling processing, address matching further enhances the communication reliability of the I2C bus system, can effectively filter out noise, and avoid communication failures caused by address parsing errors.

[0170] Furthermore, the above programmable logic unit further includes an isolation module, which is used to isolate the address of the above slave and upload device failure information to the host if the cumulative number of times the above slave does not respond reaches a second preset cumulative number of times.

[0171] By setting the second preset cumulative number of times, a more conservative but effective strategy can be adopted after the initial attempt to recover fails, avoiding the impact of a single slave failure on the normal operation of the entire system. The slave address isolation mechanism reduces the ineffective communication attempts for the faulty slave, optimizes the allocation of communication resources, and improves the communication efficiency and overall performance of the system. The upload of failure information enables the host to perform more detailed analysis and recording of the slave's failure, which helps with subsequent fault diagnosis, device maintenance, and the execution of the fault recovery program, improving the system's self-repair ability and maintenance efficiency.

[0172] Furthermore, the above programmable logic unit further includes a control module, which is used to control the power enable of the above slave if the presence signal of the above slave is detected to be valid, where the level of the presence signal line being the preset level indicates that the presence signal is valid.

[0173] By detecting the in-place signal and controlling the slave power supply accordingly, the status of the slave can be precisely managed, ensuring that only the online slaves can participate in communication, and avoiding ineffective communication attempts for non-online slaves. The power enable control mechanism can avoid powering the slave when it is not necessary, reducing energy waste. Ensuring the consistency between the in-place status and the power status of the slave can avoid communication problems caused by unstable or abnormal power supply, improving the overall stability and security of the system.

[0174] Further, the programmable logic unit further includes a first pull-up module and a second pull-up module. The first pull-up module is configured to, if it detects that the low-level duration of the serial clock signal on the slave side exceeds a first preset time, forcibly pull up the serial clock signal by a preset number of pulses to generate an end condition, and record an error log; the second pull-up module is configured to, in the ACK return phase, if the low-level duration of the serial data signal on the slave side exceeds a second preset time, forcibly pull up the serial data signal to generate an end condition, and record an error log, where the first preset time is greater than the second preset time.

[0175] By forcibly pulling up the signal to generate an end condition, it is possible to actively intervene and restore communication, shorten the fault time, and reduce the negative impacts brought by data loss or communication failure. The recording of the error log provides clues for fault troubleshooting, helps to quickly locate problems, perform targeted repairs on the system, and improve the availability and maintenance efficiency of the system. It can ensure that timely measures can be taken when the signal is abnormal, avoid the communication link being in an unstable state for a long time, and enhance the robustness and anti-interference ability of the I2C bus communication.

[0176] For the description of the features in the embodiments corresponding to the programmable logic unit, reference can be made to the relevant descriptions in the embodiments corresponding to the data processing method applied to the integrated circuit bus system, which will not be elaborated here.

[0177] An embodiment of the present application further provides an electronic device, including a memory and a processor. A computer program is stored in the memory, and the processor is configured to run the computer program to execute the steps in any of the above embodiments of the data processing method applied to the integrated circuit bus system.

[0178] An embodiment of the present application further provides a computer-readable storage medium, in which a computer program is stored. The computer program is configured to execute the steps in any of the above embodiments of the data processing method applied to the integrated circuit bus system when running.

[0179] In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as USB flash drives, read-only memory (ROM), random access memory (RAM), mobile hard disks, magnetic disks, or optical discs.

[0180] The embodiments of the present application also provide a computer program product. The computer program product includes a computer program, and when the computer program is executed by a processor, it implements the steps in any of the above-described embodiments of the data processing method applied to the integrated circuit bus system.

[0181] The embodiments of the present application also provide another computer program product, including a non-volatile computer-readable storage medium. The non-volatile computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, it implements the steps in any of the above-described embodiments of the data processing method applied to the integrated circuit bus system.

[0182] Those skilled in the art can further realize that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be implemented by electronic hardware, computer software, or a combination of the two. To clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described according to functions in the above description. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Skilled professionals can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of the present application.

[0183] The above has introduced in detail an integrated circuit bus system, a data processing method applied to the integrated circuit bus system, and a programmable logic unit provided by the present application. Specific examples are used herein to elaborate on the principles and implementation manners of the present application. The description of the above embodiments is only used to help understand the method and its core idea of the present application. It should be noted that for those of ordinary skill in the art in the technical field, without departing from the principle of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the protection scope of the claims of the present application.

Claims

1. An integrated circuit bus system, characterized in that, Including: A host, a programmable logic unit, a switching unit, and a slave. The programmable logic unit includes a processing module. The host and the programmable logic unit, the programmable logic unit and the switching unit, and the switching unit and the slave are all connected through an integrated circuit bus. If the processing module in the programmable logic unit detects that the slave has received a signal and has not responded within a predetermined time, it sends an abnormal signal to the host to cause the host to stop the current data access. If the cumulative number of times the processing module in the programmable logic unit detects that the slave does not respond reaches a first preset cumulative number of times, it disconnects and re-enables the slave so that the slave can resume to the normal state.

2. The integrated circuit bus system according to claim 1, wherein The programmable logic unit further includes a shaping module and a sampling module. The shaping module is used to perform a hysteresis comparison on the received integrated circuit bus signal. If the integrated circuit bus signal is higher than the signal upper limit value, it outputs a high level. If the integrated circuit bus signal is lower than the signal lower limit value, it outputs a low level. The sampling module is used to store the sampling value of the signal processed by the shaping module in a shift register, and updates the shift register and determines it as a valid level when the sampling values are the same for multiple consecutive times. The sampling frequency of the sampling module is a preset multiple of the integrated circuit bus clock frequency.

3. The integrated circuit bus system according to claim 1, characterized in that, The processing module is further used for: detecting the signal state from the host. If the combination of the serial data signal and the serial clock signal meets the opening condition, it jumps to the next state. If the combination meets the ending condition, it enters the ending state.

4. The integrated circuit bus system according to claim 1, wherein The programmable logic unit further includes a latching module, and the latching module is used to store the serial data signal in a latch register.

5. The integrated circuit bus system according to claim 4, characterized in that, The processing module is further used for: detecting the signal received from the latch register. If the serial data signal received from the latch register is abnormal within one clock cycle, the programmable logic unit stops signal forwarding.

6. The integrated circuit bus system according to claim 4, characterized in that, The processing module is further used for: in the data routing state, if the slave address is matched, establishing a connection between the bus signal line of the corresponding slave and the output signal line of the latch register.

7. The integrated circuit bus system according to claim 1, wherein The processing module is further used for: If it detects that the low-level duration of the serial clock signal on the slave side exceeds a first preset time, it forcibly raises the serial clock signal by a preset number of pulses to generate an ending condition and records an error log; In the ACK return stage, if the low-level duration of the serial data signal on the slave side exceeds a second preset time, it forcibly raises the serial data signal to generate an ending condition and records an error log. The first preset time is greater than the second preset time.

8. The integrated circuit bus system according to claim 1, wherein, The processing module is further used for: if the cumulative number of times the slave does not respond reaches a second preset cumulative number of times, isolating the address of the slave and uploading device failure information to the host.

9. The integrated circuit bus system according to claim 1, wherein The processing module is further used for: in the address matching stage, setting a preset list of slave addresses, and the slave addresses in the preset list of slave addresses are allowed to be accessed.

10. The integrated circuit bus system according to claim 1, wherein The programmable logic unit is further configured to: control the enabling of the slave power supply if the in-position signal of the slave is detected to be valid, and control the closing of the switch unit if the enabling of the slave power supply is successful.

11. The integrated circuit bus system according to any one of claims 1 to 10, characterized in that, The switch unit includes a plurality of electrically connected MOS devices.

12. The integrated circuit bus system according to any one of claims 1 to 10, characterized in that, The host is a controller, the slave is a backup battery unit, and the programmable logic unit is a complex programmable logic unit.

13. The integrated circuit bus system according to any one of claims 1 to 10, characterized in that, There is one host and multiple slaves.

14. A data processing method applied to an integrated circuit bus system, characterized in that, It includes: Receiving an Inter-Integrated Circuit (I2C) bus signal sent by the host, and performing predetermined processing on the I2C bus signal and then sending it to the slave; Judging whether the slave responds to the received signal within a predetermined time; If the slave does not respond within the predetermined time, sending an abnormal signal to the host to cause the host to stop the current data access; If the cumulative number of times the slave does not respond reaches a first preset cumulative number of times, disconnecting the connection with the slave and re-enabling the slave so that the slave resumes to the normal state.

15. The data processing method according to claim 14, wherein Performing predetermined processing on the I2C bus signal includes: Performing shaping processing on the I2C bus signal, and the steps of the shaping processing include performing hysteresis comparison on the I2C bus signal, outputting a high level if the I2C bus signal is higher than the signal upper limit value, and outputting a low level if the I2C bus signal is lower than the signal lower limit value; Performing sampling processing on the signal after the shaping processing, storing the sampling value in a shift register, and updating the shift register and determining it as a valid level when the sampling values are the same for multiple consecutive times.

16. The data processing method according to claim 15, wherein The I2C bus signal includes a serial data signal and a serial clock signal. After performing sampling processing on the signal after the shaping processing, storing the sampling value in a shift register, and updating the shift register and determining it as a valid level when the sampling values are the same for multiple consecutive times, the method further includes: Storing the serial data signal in a latch register; Matching the address in the serial data signal with the addresses in the preset list of slave addresses. If the match is successful, connecting the bus signal line of the corresponding slave to the output signal line of the latch register.

17. The data processing method according to claim 14, wherein The method further includes: If the cumulative number of times the slave does not respond reaches a second preset cumulative number of times, isolating the address of the slave and uploading the device fault information to the host.

18. The data processing method according to claim 14, wherein The method further includes: Controlling the enabling of the slave power supply if the in-position signal of the slave is detected to be valid, where the in-position signal line level being a preset level indicates that the in-position signal is valid.

19. The data processing method according to claim 14, wherein The method further includes: If it is detected that the low-level duration of the serial clock signal on the slave side exceeds a first preset time, forcibly pulling up the serial clock signal by a preset number of pulses to generate an end condition and recording an error log; In the ACK return stage, if the low-level duration of the serial data signal on the slave side exceeds a second preset time, forcibly pulling up the serial data signal to generate an end condition and recording an error log, where the first preset time is greater than the second preset time.

20. A programmable logic unit, characterized in that, It includes: A receiving module, configured to receive an Inter-Integrated Circuit (I2C) bus signal sent by a host, and after performing predetermined processing on the I2C bus signal, send it to a slave device; A judging module, configured to judge whether the slave device responds to the received signal within a predetermined time; A sending module, configured to, if the slave device does not respond within the predetermined time, send an abnormal signal to the host to cause the host to stop the current data access; A disconnecting module, configured to, if the cumulative number of times the slave device does not respond reaches a first preset cumulative number of times, disconnect the connection with the slave device, and re-enable the slave device so that the slave device returns to a normal state.

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