A single event effect sensitivity evaluation method based on cross-scale coupling mechanism

Abstract

The application provides a single event effect sensitivity evaluation method based on a cross-scale coupling mechanism, belongs to the technical field of electric digital processing, and solves the problems that a traditional single event effect evaluation method cannot evaluate functional failure risks at the algorithm level, cannot locate key weight bits and key network layers, and thus cannot reveal the cross-scale coupling mechanism of single event effects and neural network error propagation under an in-memory computing architecture, and comprises the following steps: acquiring key parameter information of semiconductor devices of an in-memory computing array, constructing a three-dimensional semiconductor device model and performing parameter calibration and checking, and establishing a three-dimensional in-memory computing unit model; establishing a single event fault injection model and performing single event effect fault injection transient simulation; according to a mapping relationship between the in-memory computing array and the neural network, mapping a single event multi-bit flip error pattern to the neural network to track an error propagation path in the neural network, and identifying key layers and key weight bits in the neural network.

Description

Technical Field

[0001] This invention relates to a single-event effect sensitivity assessment method based on a cross-scale coupling mechanism, belonging to the field of electrical digital processing technology. Background Technology

[0002] Deploying advanced artificial intelligence applications in space and integrating edge computing into tasks such as on-orbit distributed decision-making, spaceborne data analysis, and autonomous operation is of great significance for the disruptive development of defense technology and space exploration. In-memory computing architectures, due to their high energy efficiency and in-memory computing capabilities, are used to handle space AI tasks. However, high-energy particles in the space radiation environment can induce single-event effects (SEE), leading to single-event upsets (SEUs) in in-memory computing arrays. In nanoscale processes, the charge-sharing effect of SEEs can cause SEUs in multiple adjacent cells within the in-memory computing array, resulting in multiple bit upsets (MBUs), posing a severe challenge to in-memory computing systems that rely on fixed-weighted storage. Assessing the SEE sensitivity of in-memory computing circuits can help guide radiation-hardened design. The SEE sensitivity of in-memory computing circuits is not only related to their physical implementation but also influenced by the characteristics of neural network models. Traditional single-event effect (SEE) assessment methods rely solely on circuit-level simulations to statistically analyze MBU (Multi-Event Flip) occurrence rates. They fail to establish the correlation between weight errors and neural network output deviations, thus failing to assess algorithm-level functional failure risks and locate critical weight bits and layers. Furthermore, the isolated analysis of hardware and algorithms lacks a systematic analysis of SEE and charge-sharing effects in in-memory computing circuits under space radiation environments, failing to reveal the cross-scale coupling mechanism of SEE and neural network error propagation within in-memory computing architectures. Therefore, a cross-scale assessment method integrating device physical simulation and neural network error propagation analysis is urgently needed to reveal the cascading failure mechanism of SEE in in-memory computing architectures and provide precise guidance for the radiation-hardened design of space-based AI chips. Summary of the Invention

[0003] This invention addresses the problem that traditional single-event effect assessment methods cannot assess the risk of functional failure at the algorithm level, nor can they locate key weights and key network layers, thus failing to reveal the cross-scale coupling mechanism of single-event effects and neural network error propagation in in-memory computing architectures. Therefore, this invention proposes a single-event effect sensitivity assessment method based on the cross-scale coupling mechanism.

[0004] The technical solution adopted by the present invention to solve the above problems is as follows: The present invention includes the following steps:

[0005] Step 1: Obtain the specific structure, layout, and process information of the in-memory computing circuit to be evaluated, and determine the key parameter information of the semiconductor devices constituting the in-memory computing array;

[0006] Step 2: Based on the key parameter information of the semiconductor device, use computer-aided design tools or other professional software to create a three-dimensional semiconductor device model;

[0007] Step 3: Based on the actual manufacturing process documents of the in-memory computing circuit to be evaluated, calibrate the doping concentration parameters of the established three-dimensional semiconductor device model;

[0008] Step 4: Simulate the electrical characteristics of the 3D semiconductor device based on the calibrated 3D semiconductor device model, and check the consistency between the simulation results and the electrical parameters of the SPICE model under the same size. If the electrical characteristics match, proceed to Step 5; if they do not match, repeat Step 3 until the electrical characteristics match.

[0009] Step 5: Using the inspected 3D semiconductor device model and combining it with the actual in-memory computing layout, establish a 3D in-memory computing unit model;

[0010] Step 6: Establish a single-event fault injection model and define the parameters of the single-event fault injection model;

[0011] Step 7: Perform a single-event fault injection transient simulation to simulate the impact of single-event effects on the in-memory computing array;

[0012] Step 8: Determine whether all single-particle incident scenarios have been executed. If all have been executed, proceed to step 9. If not all have been executed, change the incident state of the particles and re-execute steps 6 and 7 until all single-particle incident scenarios have been executed.

[0013] Step 9: Under the condition that all single-particle incident scenarios have been executed, analyze the sensitive area of ​​single-particle charge sharing effect in the in-memory computing array, and summarize the distribution of single-particle multi-bit flip error patterns.

[0014] Step 10: Based on the mapping relationship between the in-memory computing array and the neural network, map the single-particle multi-bit flip error pattern to the corresponding weight parameters of one layer in the neural network, thus completing the mapping from hardware-level errors to software-level errors.

[0015] Step 11: Based on the mapped single-particle multi-position flip error pattern, the weight parameters in the neural network are injected with faults by modifying the weight parameter values, and the weight parameter matrix is ​​regenerated.

[0016] Step 12: Using the mapping layer as the initial injection layer, starting from the initial injection layer, trace the propagation path of the injected error in the neural network, record the impact of the error on the output of each neuron and the final output result, and identify the key layers and key weights in the neural network to complete the single-event sensitivity assessment of the circuit.

[0017] Furthermore, the key parameter information of the semiconductor device in step 1 includes the type, shape, region, material, contact position, process constraints, and impurity doping type and concentration of each region.

[0018] Furthermore, in step 3, the actual manufacturing process document for the in-memory computing circuit to be evaluated is a process design kit document using a specific process node, which contains documents describing the details of the semiconductor process.

[0019] Furthermore, in step 4, the electrical parameters are the IV characteristic curves under electrical characteristic simulation, and the IV characteristic curves include the output characteristic curve and the transfer characteristic curve.

[0020] Furthermore, in step 5, a three-dimensional in-memory computing unit model is modeled based on the actual in-memory computing layout, and the parameters of the three-dimensional in-memory computing unit model are set using the checked three-dimensional semiconductor device model.

[0021] Furthermore, in step 6, the single-event fault injection model is a heavy-ion model provided by CAD tools or other professional software, used to simulate the impact of single-event effects on semiconductor devices.

[0022] The parameters of the single-event fault injection model include the incident time, incident position, incident direction, incident depth, incident radius, and LET value of the heavy particles. Different single-event radiation environments are simulated by inputting these parameters.

[0023] Furthermore, in step 9, the sensitive area is the region in the in-memory computing array that is affected by the single-event effect and causes a single-event flip, resulting in the destruction of stored data. The single-event multi-bit flip error pattern distribution is used for the single-event multi-bit flip error pattern distribution, where MBU refers to the simultaneous flipping of multiple physically adjacent bit cells caused by the single-event effect.

[0024] Furthermore, in step 10, the mapping relationship between the in-memory computing array and the neural network is the correspondence between the weights of the neural network stored in the in-memory computing array and the in-memory computing units.

[0025] The beneficial effects of this invention are:

[0026] (1) This invention breaks through the limitations of traditional single-event effect evaluation, which only focuses on the hardware circuit level, and establishes a full-link analysis framework from device charge collection, multi-bit flipping of memory arrays to neural network error propagation. Through the synergy of physical simulation and algorithm-level fault injection, the cascading failure mechanism of single-event effects in in-memory computing architecture is revealed, providing theoretical support for system-level reliability design.

[0027] (2) By identifying critical layers and key weight bits, this invention provides important guidance for the radiation hardening design of in-memory computing circuits. Designers can selectively harden based on this information, avoiding resource waste caused by blind redundancy, and facilitating the synergistic optimization of the radiation hardness and computing energy efficiency of in-memory computing circuits.

[0028] (3) This invention studies the transmission characteristics of radiation errors between neural network layers, which helps to optimize the structure and parameter configuration of neural networks. By understanding the error propagation mechanism, more robust neural network architectures can be designed, providing a key theoretical basis for designing fault-tolerant algorithms.

[0029] (4) This invention provides a method for evaluating the radiation resistance of in-memory computing circuits during the design phase, which helps reduce the cost of later testing and modifications, and improves design efficiency and reliability. By considering single-event effects during the design phase, expensive rework and redesign problems that may occur in the later stages of product development can be effectively avoided, reducing product development time and costs. Attached Figure Description

[0030] Figure 1 A flowchart of a single-event effect sensitivity assessment method based on a cross-scale coupling mechanism provided by the present invention;

[0031] Figure 2 This is a schematic diagram of the structure of the three-dimensional semiconductor device model established in this invention;

[0032] Figure 3 This is a schematic diagram of single-particle fault injection provided by the present invention;

[0033] Figure 4 This is a schematic diagram of an MBU error pattern provided by the present invention;

[0034] Figure 5 A schematic diagram illustrating the mapping relationship between neural network weights and in-memory computing units provided by this invention;

[0035] Figure 6 This is a schematic diagram of error propagation across layers in a neural network provided by the present invention. Detailed Implementation

[0036] Combination Figure 1-6 This implementation method is described as follows: Figure 1As shown, the steps of the single-event effect sensitivity assessment method based on a cross-scale coupling mechanism described in this embodiment include:

[0037] S1: Based on the specific structure and layout information of the actual in-memory computing circuit, as well as the process information used, determine the key parameter information such as the type, geometric dimensions (such as channel width W, gate length L), physical arrangement, and process constraints of the semiconductor devices constituting the in-memory computing array.

[0038] S2: Based on the type and geometric dimensions of the semiconductor device, use semiconductor process files and device simulation software TCAD or other specialized software to create a 3D semiconductor device model. The geometric information and metal contact information of each part of the semiconductor model, as well as the material properties, must be consistent with those provided in the PDK file. Figure 2 As shown.

[0039] Semiconductor process documentation is a process design kit (PDK) file that uses a specific process node. This file contains device model cards and design rule files (DRCs) that describe the details of the semiconductor process.

[0040] S3: Based on the process used, set the doping information for each part of the 3D device, including substrate doping, well doping, source / drain doping, light source / drain doping, channel doping, Halo doping, etc. Simulate the electrical characteristics of the 3D device to obtain the output characteristics (IL). ds -V ds ) and transfer characteristics (I ds -V gs )curve.

[0041] S4: Compare the IV curves of the TCAD simulation and the SPICE model, including the IV curves of output characteristics and transfer characteristics. If the electrical characteristics match, proceed to S5; if they do not match, adjust the doping concentration and re-execute S3 until the electrical characteristics match.

[0042] S5: Using the established three-dimensional device model, a three-dimensional in-memory computing unit model is established based on the physical implementation of the actual in-memory computing array.

[0043] S6: Single-event fault injection is achieved using the heavy ion model provided in the TCAD tool, such as... Figure 3 As shown, the effect of single-event effects on in-memory computing arrays is simulated.

[0044] Parameters such as particle incident time, incident position, incident depth, incident radius, incident angle, and particle LET value are set to simulate different single-particle radiation environments. The spatiotemporal distribution of charge around the ion orbit is modeled using a Gaussian radial profile.

[0045] S7: Perform transient simulation of single-event effect fault injection to analyze the charge collection process. When radiated particles are incident on a semiconductor device, the reaction between the particles and the material generates a large number of charge carriers. These charge carriers are collected by nodes in the in-memory computing unit under the influence of concentration gradients and electric fields, affecting the storage state of the in-memory computing unit.

[0046] S8: Determine if all expected scenarios have been executed. If all preset scenarios have been executed, then execute S9; if there are unexecuted preset scenarios (such as particles with a specific LET value being incident on the internal computing unit at a specific angle), then if it is necessary to modify the incident state of the particles and update the relevant parameters of the heavy ion model, execute S6-S7 until all expected scenarios have been executed.

[0047] S9: Summarize the single-particle multi-bit flip error pattern distribution under all preset particle incidence conditions. Mark the bit cells that have flipped, such as... Figure 4 As shown. Statistical analysis of MBU error patterns and their distribution across all cases.

[0048] S10: Based on the mapping relationship between neural network weights and in-memory computing units, the statistical MBU error patterns are mapped to the weight parameters corresponding to a certain layer of the neural network.

[0049] The mapping relationship between neural network weights and in-memory computing units is as follows: Figure 5 As shown, the mapping relationship refers to the correspondence between the weights of the neural network stored in the in-memory computing array and the in-memory computing units. This involves how to store the weight parameters of the neural network in the in-memory computing array according to certain rules.

[0050] This invention, through the aforementioned steps, completes the mapping from hardware-level errors to the software-level, overcoming the limitations of traditional single-event effect (SEE) assessments that rely solely on circuit-level simulation to statistically analyze MBU occurrence rates. These SEE assessments fail to establish the correlation between weight errors and neural network output deviations, thus hindering the assessment of algorithm-level functional failure risks. This invention establishes a comprehensive analytical framework encompassing device charge collection, multi-bit flips in the memory array, and neural network error propagation. Through the synergy of physical simulation and algorithm-level fault injection, it reveals the cascading failure mechanism of SEE in in-memory computing architectures, providing theoretical support for system-level reliability design.

[0051] S11: Based on the information of the flipped cells marked in the MBU error pattern, fault injection is performed on the weight parameters in the neural network by modifying the weight parameter values, and the weight parameter matrix is ​​regenerated.

[0052] S12: Starting from the injected layer, trace as follows Figure 6The diagram illustrates the propagation path of injected errors, records the changes in the output of each neuron layer, and the final output result, and identifies key layers and key weights in the neural network. Errors at these locations can lead to significant performance degradation. By identifying key layers and key weights, this invention provides important guidance for the radiation-hardened design of in-memory computing circuits. Designers can use this information to selectively harden, avoiding resource waste caused by blind redundancy, and facilitating the synergistic optimization of radiation resistance and computing energy efficiency in in-memory computing circuits.

[0053] In summary, this invention studies the propagation characteristics of radiated errors between neural network layers, which helps optimize the structure and parameter configuration of neural networks. Understanding the error propagation mechanism allows for the design of more robust neural network architectures, providing a key theoretical basis for designing fault-tolerant algorithms. Furthermore, this invention enables the assessment of the radiation resistance of in-memory computing circuits during the design phase, helping to reduce the cost of later testing and modifications, and improving design efficiency and reliability. By considering single-event effects during the design phase, costly rework and redesign problems that may occur later in product development can be effectively avoided, reducing product development time and costs.

[0054] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the present invention. Any simple modifications, equivalent substitutions, and improvements made to the above embodiments without departing from the scope of the present invention, based on the technical essence of the present invention and within the spirit and principles of the present invention, shall still fall within the protection scope of the present invention.

Claims

1. A method for assessing the sensitivity of single-event effects based on a cross-scale coupling mechanism, characterized in that, The steps of the single-event effect sensitivity assessment method based on cross-scale coupling mechanism include: Step 1: Obtain the specific structure, layout, and process information of the in-memory computing circuit to be evaluated, and determine the key parameter information of the semiconductor devices constituting the in-memory computing array; Step 2: Based on the key parameter information of the semiconductor device, use computer-aided design tools or other professional software to create a three-dimensional semiconductor device model; Step 3: Based on the actual manufacturing process documents of the in-memory computing circuit to be evaluated, calibrate the doping concentration parameters of the established three-dimensional semiconductor device model; Step 4: Simulate the electrical characteristics of the 3D semiconductor device based on the calibrated 3D semiconductor device model, and check the consistency between the simulation results and the electrical parameters of the SPICE model under the same size. If the electrical characteristics match, proceed to Step 5; if they do not match, repeat Step 3 until the electrical characteristics match. Step 5: Using the inspected 3D semiconductor device model and combining it with the actual in-memory computing layout, establish a 3D in-memory computing unit model; Step 6: Establish a single-event fault injection model and define the parameters of the single-event fault injection model; Step 7: Perform a single-event fault injection transient simulation to simulate the impact of single-event effects on the in-memory computing array; Step 8: Determine whether all single-particle incident scenarios have been executed. If all have been executed, proceed to step 9. If not all have been executed, change the incident state of the particles and re-execute steps 6 and 7 until all single-particle incident scenarios have been executed. Step 9: Under the condition that all single-particle incident scenarios have been executed, analyze the sensitive area of ​​single-particle charge sharing effect in the in-memory computing array, and summarize the distribution of single-particle multi-bit flip error patterns. Step 10: Based on the mapping relationship between the in-memory computing array and the neural network, map the single-particle multi-bit flip error pattern to the corresponding weight parameters of one layer in the neural network, thus completing the mapping from hardware-level errors to software-level errors. Step 11: Based on the mapped single-particle multi-position flip error pattern, the weight parameters in the neural network are injected with faults by modifying the weight parameter values, and the weight parameter matrix is ​​regenerated. Step 12: Using the mapping layer as the initial injection layer, starting from the initial injection layer, trace the propagation path of the error in the neural network, record the impact of the error on the output of each neuron and the final output result, and identify the key layers and key weights in the neural network to complete the single-event sensitivity assessment of the circuit.

2. The single-event effect sensitivity assessment method based on a cross-scale coupling mechanism according to claim 1, characterized in that, The key parameter information of the semiconductor device in step 1 includes the type, shape, area, material, contact position, process constraints, and impurity doping type and concentration of each area.

3. The single-event effect sensitivity assessment method based on a cross-scale coupling mechanism according to claim 1, characterized in that, In step 3, the actual manufacturing process document for the in-memory computing circuit to be evaluated is a process design kit file using a specific process node. The process design kit file contains documents describing the details of the semiconductor process.

4. The single-event effect sensitivity assessment method based on a cross-scale coupling mechanism according to claim 1, characterized in that, In step 4, the electrical parameters are the IV characteristic curves under electrical characteristic simulation. The IV characteristic curves include the output characteristic curve and the transfer characteristic curve.

5. The single-event effect sensitivity assessment method based on a cross-scale coupling mechanism according to claim 1, characterized in that, In step 5, a three-dimensional in-memory computing unit model is created based on the actual in-memory computing layout, and the parameters of the three-dimensional in-memory computing unit model are set using the checked three-dimensional semiconductor device model.

6. The single-event effect sensitivity assessment method based on a cross-scale coupling mechanism according to claim 1, characterized in that, In step 6, the single-event fault injection model is a heavy ion model provided by CAD tools or other professional software, used to simulate the impact of single-event effects on semiconductor devices; The parameters of the single-event fault injection model include the incident time, incident position, incident direction, incident depth, incident radius, and LET value of the heavy particles. Different single-event radiation environments are simulated by inputting these parameters.

7. The single-event effect sensitivity assessment method based on a cross-scale coupling mechanism according to claim 1, characterized in that, In step 9, the sensitive area is the region in the in-memory computing array that is affected by the single-event effect and causes a single-event flip, resulting in the destruction of stored data. The single-event multi-bit flip error pattern distribution is used to mark the bit cells that have been flipped.

8. The single-event effect sensitivity assessment method based on a cross-scale coupling mechanism according to claim 1, characterized in that, In step 10, the mapping relationship between the in-memory computing array and the neural network is the correspondence between the weights of the neural network stored in the in-memory computing array and the in-memory computing units.

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