A modeling method and device of a structure simulation model of a chip advanced package

Abstract

The application discloses a modeling method and device of a chip advanced packaging structure simulation model. The modeling method of the chip advanced packaging structure simulation model comprises the following steps: obtaining packaging structure description data; determining component space layout parameters according to component placement parameters in the packaging structure description data, and performing assembly block template specification processing based on component description parameters in the packaging structure description data to obtain an assembly block specification template; performing mesh layout on the assembly block specification template according to the assembly block specification template to obtain a to-be-divided assembly block template, and performing mesh division on the to-be-divided assembly block template to obtain a to-be-spliced assembly block; and performing layout on the to-be-spliced assembly block according to the component space layout parameters to obtain a discretized packaging structure simulation model. The technical scheme of the embodiment of the application can reduce the artificial cost of advanced packaging structure simulation and improve the processing effect of large-scale packaging structures.

Description

Technical Field

[0001] This invention relates to the field of advanced chip packaging design technology, and in particular to a modeling method and apparatus for a structural simulation model of advanced chip packaging. Background Technology

[0002] In the technological evolution of silicon-based semiconductors, the number of transistors doubles every 18-24 months, resulting in a doubling of chip performance or a halving of cost—a pattern known as "Moore's Law." However, maintaining Moore's Law requires raising the bar for new technology development, lengthening development cycles, and taking longer to iterate manufacturing processes, significantly increasing costs. To further improve chip performance and reduce costs, using advanced packaging technologies to achieve heterogeneous system integration has become a key technology for manufacturers in the industry. But at the same time, advanced packaging also brings complexity to the packaging structure, posing more challenges in understanding the potential failure mechanisms and modes of chip packaging. Structural simulation analysis of chip packaging, as an important part of advanced packaging design, has received increasing attention from researchers.

[0003] The structural simulation analysis process is divided into four stages: geometric modeling, preprocessing, simulation solving, and postprocessing. The geometric modeling stage establishes the geometric model to be analyzed. The preprocessing stage discretizes the geometric model and sets relevant structural simulation data to generate a simulation model. The solving stage sets simulation parameters and performs simulation calculations to obtain simulation results. The postprocessing stage performs visualization analysis of the simulation results and feeds the analysis results back to the packaging design.

[0004] Currently, major EDA (Electronic Design Automation) providers offer general-purpose tools to support the structural analysis of advanced chip packages. Engineers first use CAD (Computer-Aided Design) software for geometric modeling of the package, and then import the modeling results into CAE (Computer-Aided Engineering) preprocessing software for mesh generation. While these separate, general-purpose processing tools are comprehensive in function, they lack close interoperability and do not provide customized support and optimization for advanced package structure analysis. This results in a significant amount of manual work required for the geometric modeling and preprocessing stages of current advanced package structure simulation analysis, and frequent crashes when handling large-scale package structures. Summary of the Invention

[0005] This invention provides a modeling method and apparatus for the structural simulation model of advanced chip packaging, in order to solve the problems of high labor costs and poor processing effect of large-scale packaging structures in existing advanced packaging structural simulation.

[0006] According to one aspect of the present invention, a modeling method for a structural simulation model of advanced chip packaging is provided, comprising:

[0007] Obtain the encapsulation structure description data;

[0008] Based on the component placement parameters in the encapsulation structure description data, the component spatial layout parameters are determined, and based on the component description parameters in the encapsulation structure description data, the assembly block template is reduced to obtain the assembly block reduction template.

[0009] Based on the assembly block specification template, the assembly block specification template is meshed to obtain the assembly block template to be divided, and the assembly block template to be divided is meshed to obtain the assembly block to be assembled.

[0010] Based on the spatial layout parameters of the components, the assembly blocks to be assembled are laid out to obtain a discrete encapsulation structure simulation model.

[0011] According to another aspect of the present invention, a simulation modeling apparatus for chip packaging structures is provided, comprising:

[0012] The data acquisition module is used to acquire the encapsulation structure description data;

[0013] The assembly block specification template determination module is used to determine the component spatial layout parameters based on the component placement parameters in the encapsulation structure description data, and to perform assembly block template specification processing based on the component description parameters in the encapsulation structure description data to obtain the assembly block specification template.

[0014] The grid layout and division module is used to perform grid layout on the assembly block specification template according to the assembly block specification template to obtain the assembly block template to be divided, and to perform grid division on the assembly block template to be divided to obtain the assembly block to be assembled.

[0015] The assembly block layout module is used to lay out the assembly blocks to be assembled according to the component spatial layout parameters, so as to obtain a discrete encapsulation structure simulation model.

[0016] According to another aspect of the present invention, an electronic device is provided, the electronic device comprising:

[0017] At least one processor; and

[0018] A memory communicatively connected to the at least one processor; wherein,

[0019] The memory stores a computer program that can be executed by the at least one processor, which enables the at least one processor to execute the modeling method for the structural simulation model of the advanced chip packaging according to any embodiment of the present invention.

[0020] According to another aspect of the present invention, a computer-readable storage medium is provided, the computer-readable storage medium storing computer instructions, the computer instructions being used to cause a processor to execute and implement the modeling method of the structure simulation model of the advanced chip packaging according to any embodiment of the present invention.

[0021] The technical solution of this invention acquires encapsulation structure description data, determines component spatial layout parameters based on component placement parameters in the encapsulation structure description data, and performs assembly block template reduction processing based on component description parameters in the encapsulation structure description data to obtain assembly block reduction templates. Then, the assembly block reduction templates are meshed to obtain assembly block templates to be divided, and the assembly block templates to be divided are meshed to obtain assembly blocks to be assembled. Finally, the assembly blocks to be assembled are laid out according to the component spatial layout parameters to obtain a discretized encapsulation structure simulation model. In this solution, the spatial layout of components can be automatically determined based on the encapsulation structure description data, and the corresponding assembly block templates can be reduced to decrease the number of templates and improve subsequent processing efficiency. This effectively avoids system crashes during large-scale encapsulation structure processing. Furthermore, the meshing of templates, meshing, and the final assembly of assembly blocks based on the component spatial layout all require no manual intervention. This solves the problems of high labor costs and poor processing effects of large-scale encapsulation structures in existing advanced encapsulation structure simulations, reducing the labor costs of advanced encapsulation structure simulation and improving the processing effect of large-scale encapsulation structures.

[0022] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0023] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0024] Figure 1 A flowchart illustrating a modeling method for a structural simulation model of an advanced chip packaging according to Embodiment 1 of the present invention;

[0025] Figure 2 A flowchart illustrating a modeling method for a structural simulation model of an advanced chip packaging according to Embodiment 2 of the present invention;

[0026] Figure 3This is a functional block diagram of a modeling tool for a structural simulation model of an advanced chip packaging provided in Embodiment 3 of the present invention;

[0027] Figure 4 This is a schematic diagram of a singular template and a trivial template in a convex dot array component provided in Embodiment 3 of the present invention;

[0028] Figure 5 This is a schematic diagram of the position to be added to the buffer to be adjusted, provided in Embodiment 3 of the present invention;

[0029] Figure 6 This is a schematic diagram of the position of a cross-section in the vertical direction provided in Embodiment 3 of the present invention;

[0030] Figure 7 This is a logical schematic diagram of a homotopy mapping provided in Embodiment 3 of the present invention;

[0031] Figure 8 This is a schematic diagram of the modeling device for a structural simulation model of an advanced chip packaging according to Embodiment 4 of the present invention;

[0032] Figure 9 A schematic diagram of an electronic device that can be used to implement embodiments of the present invention is shown. Detailed Implementation

[0033] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0034] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0035] Example 1

[0036] Figure 1This is a flowchart illustrating a modeling method for a structural simulation model of an advanced chip package according to Embodiment 1 of the present invention. This embodiment is applicable to automatic modeling during structural simulation of advanced packages. Advanced packages specifically refer to 2.5D, 3D, and 3.5D packages. Structural simulation is used to analyze the reliability of the package structure. Specific structural simulations include warpage and bump array breakage simulations. This method can be executed by a modeling device for the structural simulation model of the advanced chip package. This modeling device can be implemented in hardware and / or software and can be configured in an electronic device. This electronic device may include, but is not limited to, a computer or server. Figure 1 As shown, the method includes:

[0037] Step 110: Obtain the encapsulation structure description data.

[0038] The package structure description data can be used to describe the package structure of advanced chip packaging. The language type of the package structure description data can include, but is not limited to, DSL (Domain-Specific Language). The package structure description data can include component description parameters (such as component type, number of components, etc.), component placement parameters, component combination relationships, and component material description data. A component can be understood as the various parts or components that make up the package. Components can include, but are not limited to, die components, bump array components, silicon interposer components, substrate components, filler material components, epoxy molding compound components, and through-silicon via components. Component combination relationships can include, but are not limited to, a group of components combined into a logical group, a group of components combined into a physical group, a group of components stacked vertically into a logical group, and a group of components stacked vertically into a physical group.

[0039] In this embodiment of the invention, the encapsulation structure description data written by the user through the user data input interface can be obtained.

[0040] Optionally, users can query component material information in a pre-configured material database, and can also define and store component material information within the database. The material database provides users with different types of engineering data templates. Based on the material properties and parameter definitions in the templates, users can flexibly edit and create various component material description data. Users can also organize and save frequently used material databases for future project use. The material database's data organization based on specific keywords, along with a fuzzy naming method similar to natural language abbreviation rules, allows users to input data in a simple tabular format.

[0041] Step 120: Determine the component spatial layout parameters based on the component placement parameters in the encapsulation structure description data, and perform assembly block template specification processing based on the component description parameters in the encapsulation structure description data to obtain the assembly block specification template.

[0042] The component placement parameters can be parameters describing the relative positions of components. These parameters can include: the offset of the component's center relative to the center of another component (front, back, left, right, up, down); the offset of the component's center relative to the center of another component when the component is placed on top of it; the offset of the component's center relative to the center of another component when the component is placed below it; placing the component while maintaining its left, right, front, and back positions so that its top surface is at the same height as the bottom surface of another component; placing the component while maintaining its left, right, front, and back positions so that its bottom surface is at the same height as the top surface of another component; placing the component while maintaining its front, back, up, and down positions so that its right side is at the same position as the left side of another component; placing the component while maintaining its front, back, up, and down positions so that its left side is at the same position as the right side of another component; and placing the component while maintaining its top, bottom, left, and right positions. Place this component so that its rear is aligned with the front of another component; keep its top, bottom, left, and right positions unchanged, and place it so that its front is aligned with the rear of another component; keep its left, bottom, left, right, and front-back positions unchanged, and place it so that its bottom surface is aligned with the bottom surface of another component; keep its top, bottom, left, right, and front-back positions unchanged, and place it so that its top surface is aligned with the top surface of another component; keep its top, bottom, left, and front-back positions unchanged, and place it so that its left side is aligned with the left side of another component; keep its top, bottom, left, and front-back positions unchanged, and place it so that its right side is aligned with the right side of another component; keep its top, bottom, left, and right positions unchanged, and place it so that its front is aligned with the front of another component; keep its top, bottom, left, and right positions unchanged, and place it so that its rear is aligned with the rear of another component. Component spatial layout parameters can be used to describe the position and contact relationships of components in three-dimensional space. Component description parameters can be used to describe the basic information of components in the encapsulation structure.

[0043] The assembly block template reduction process can be used to reduce the number of assembly block templates. This process can include, but is not limited to, the reduction of non-singular templates and the reduction of singular templates. The reduction of non-singular templates involves directly merging adjacent non-singular templates, which can be understood as converting small templates into larger ones to reduce the number of templates. The reduction of singular templates involves aligning the discrete sections of the outer boundaries of singular templates using added buffers to reduce the number of template types for the same component type. Singular templates are regions in the simulation model of the encapsulated structure where certain physical quantities (such as stress, strain, temperature gradient, etc.) are infinitely large or discontinuous. The assembly block reduction template can be the assembly block template after the assembly block template reduction process. The assembly block template can also be a template describing the assembly relationships and configurations of components in the encapsulated structure during simulation.

[0044] In this embodiment of the invention, component placement parameters can be parsed from the encapsulation structure description data, and a spatial positioning system for each component can be established based on the component placement parameters. Boolean operations are performed on each component and other components to obtain component spatial layout parameters. Then, based on the component description parameters parsed from the encapsulation structure description data, the assembly block template corresponding to the component description parameters is determined, and the determined assembly block template is reduced to obtain an assembly block reduction template. By reducing the assembly block template, the types (or quantities) of assembly block templates can be reduced.

[0045] Step 130: Grid layout is performed on the assembly block specification template to obtain the assembly block template to be divided, and the assembly block template to be divided is gridded to obtain the assembly block to be assembled.

[0046] The assembly block template to be divided can be an assembly block template with a completed mesh layout. The assembly blocks to be assembled can be instantiated objects of the assembly block template to be divided with a completed mesh.

[0047] In this embodiment of the invention, each assembly block specification template can be divided into multiple topological polyhedra. Based on the discretized section position set by the user and the topological polyhedra divided by each assembly block specification template, a mesh layout of each assembly block specification template is constructed to obtain the assembly block template to be divided. Then, according to the discretized section position and the mesh layout of the assembly block to be divided, the assembly block template to be divided is meshed to obtain the assembly block to be assembled.

[0048] In general, in package structure simulation, the discretized section position is the specific section or position selected when discretizing the package structure.

[0049] Step 140: Lay out the assembly blocks to be spliced ​​according to the component spatial layout parameters to obtain a discrete encapsulation structure simulation model.

[0050] Among them, the discrete packaging structure simulation model can be a structural simulation model of advanced chip packaging created based on the packaging structure description data.

[0051] In this embodiment of the invention, the assembly blocks corresponding to the components can be assembled according to the spatial layout parameters of the components to obtain a discrete packaging structure simulation model. The final discrete packaging structure simulation model can be used for structural simulation of advanced chip packaging.

[0052] The technical solution of this invention acquires encapsulation structure description data, determines component spatial layout parameters based on component placement parameters in the encapsulation structure description data, and performs assembly block template reduction processing based on component description parameters in the encapsulation structure description data to obtain assembly block reduction templates. Then, the assembly block reduction templates are meshed to obtain assembly block templates to be divided, and the assembly block templates to be divided are meshed to obtain assembly blocks to be assembled. Finally, the assembly blocks to be assembled are laid out according to the component spatial layout parameters to obtain a discretized encapsulation structure simulation model. In this solution, the spatial layout of components can be automatically determined based on the encapsulation structure description data, and the corresponding assembly block templates can be reduced to decrease the number of templates and improve subsequent processing efficiency. This effectively avoids system crashes during large-scale encapsulation structure processing. Furthermore, the meshing of templates, meshing, and the final assembly of assembly blocks based on the component spatial layout all require no manual intervention. This solves the problems of high labor costs and poor processing effects of large-scale encapsulation structures in existing advanced encapsulation structure simulations, reducing the labor costs of advanced encapsulation structure simulation and improving the processing effect of large-scale encapsulation structures.

[0053] Example 2

[0054] Figure 2 This is a flowchart illustrating a modeling method for a structural simulation model of an advanced chip package according to Embodiment 2 of the present invention. This embodiment is a specific embodiment based on the above embodiment, providing a detailed and optional implementation method for obtaining an assembly block specification template by performing assembly block template reduction processing based on component description parameters in the package structure description data. For example... Figure 2 As shown, the method includes:

[0055] Step 210: Obtain the encapsulation structure description data.

[0056] Step 220: Determine the component spatial layout parameters based on the component placement parameters in the encapsulation structure description data.

[0057] Step 230: Based on the component description parameters in the encapsulation structure description data, divide the space occupied by all components to obtain the space division result, and find the intersection between the space division result and each component to obtain the first type template and the second type template of each component.

[0058] The first type of template is the non-singular template (or trivial template) of the component. The spatial partitioning result can be obtained by partitioning the component boundary in three-dimensional space. The second type of template is the singular template of the component.

[0059] Specifically, after determining the component spatial layout parameters based on the component placement parameters in the encapsulation structure description data, the components required for this advanced encapsulation structure simulation can be determined first based on the component description parameters. Then, the boundaries of these components are determined, and spatial partitioning is performed in three-dimensional space based on the boundaries of each component. The intersection of this spatial partitioning result and the space occupied by each component is calculated to clear any empty spaces in the components that do not require assembly block template filling. This yields the first type template and the second type template for each component. During spatial partitioning, each geometric boundary of the component becomes a boundary surface for spatial partitioning, and all components collectively determine the spatial partitioning of the encapsulation structure. If no singular template exists after spatial partitioning of the current component, the second type template is empty.

[0060] Step 240: Based on the first type template and the second type template of each component, perform assembly block template specification processing to obtain the assembly block specification template.

[0061] In this embodiment of the invention, for each specific template type corresponding to a component, a suitable assembly block template specification processing is determined. For the first type of template of the component, it is directly merged according to the adjacent relationship. For the second type of template, the assembly block template specification processing is performed by aligning the discrete cross sections of the outer boundary to obtain the assembly block specification template.

[0062] In an optional embodiment of the present invention, the assembly block template reduction process is performed based on the first type template and the second type template of each component to obtain the assembly block reduction template. This may include: determining the buffer to be adjusted for the current component when the discrete cross-sectional positions of the second type template and the first type template of the current component are different; and performing the assembly block template reduction process based on the density of the inner border cross-sectional position points, the density of the outer border cross-sectional position points, and the buffer adjustment threshold of the buffer to be adjusted for the current component to obtain the assembly block reduction template corresponding to the current component.

[0063] The buffer to be adjusted can be an extended region of the second type template when the discrete cross-sectional positions of the second type template and the first type template in the current component are different, occupying the region of the first type template adjacent to the second type template in the current component. The inner border cross-sectional point density can be the point density of discrete points selected on the adjacent edge of the buffer to be adjusted and the second type template in the current component. The outer border cross-sectional point density can be the point density of discrete points selected on the adjacent edge of the buffer to be adjusted and the first type template in the current component. The buffer adjustment threshold can be a preset buffer size threshold.

[0064] In this embodiment of the invention, if it is determined that the discrete cross-sectional positions of the second type template and the first type template of the current component are different, it indicates that the range of the second type template of the current component needs to be expanded for subsequent assembly block template reduction processing. That is, according to the preset second type template range expansion rule, the buffer to be adjusted of the current component is determined. Then, based on the discrete cross-sectional point positions of the second type template and the first type template of the current component, the inner border cross-sectional point density and the outer border cross-sectional point density of the buffer to be adjusted of the current component are determined. Under the premise of ensuring that the size of the buffer to be adjusted is less than the buffer adjustment threshold, the point density of the discrete cross-sectional points of the outer border and inner border of the buffer to be adjusted is adjusted to align the discrete cross-sectional positions of the current component with those of other components. The first type template of the current component is adjusted according to the buffer to be adjusted, and then the first type template is reduced to minimize the template types of the current component, thereby realizing the assembly block template reduction processing and obtaining the assembly block reduction template corresponding to the current component.

[0065] In an optional embodiment of the present invention, the assembly block template reduction process is performed based on the density of the inner border section location points, the density of the outer border section location points, and the buffer adjustment threshold of the current component to be adjusted, to obtain the assembly block reduction template corresponding to the current component. This process may include: calculating the density difference between the density of the outer border section location points and the density of the inner border section location points when the density of the outer border section location points of the buffer to be adjusted is less than the density of the inner border section location points; expanding the buffer to be adjusted based on the density difference and the buffer size threshold to obtain the template to be reduced for the current component; performing spatial division based on the expanded buffer to be adjusted and updating the first type of template; and performing assembly block template reduction processing on the first type of template to obtain the assembly block reduction template corresponding to the current component.

[0066] Among them, the template to be standardized can be a template that needs to be standardized after the buffer to be adjusted is divided.

[0067] In this embodiment of the invention, the density of the outer frame cross-section position points of the buffer to be adjusted can be compared with the density of the inner frame cross-section position points. If the density of the outer frame cross-section position points of the buffer to be adjusted is less than that of the inner frame cross-section position points, the density difference between the outer frame cross-section position points and the inner frame cross-section position points is further calculated. Based on the calculated density difference, the buffer to be adjusted is expanded. That is, new discrete cross-section positions are set at certain intervals in the expanded buffer to align the discrete cross-section positions of the current component with those of other components. It is also necessary to ensure that the size of the expanded buffer to be adjusted is not greater than the buffer size threshold. Then, the expanded buffer to be adjusted is spatially divided to update the first type template. The updated first type model is further subjected to assembly block template reduction processing to obtain the assembly block reduction template corresponding to the current component.

[0068] In an optional embodiment of the present invention, when the discrete cross-sectional positions of the second type template and the first type template of the current component are different, determining the buffer to be adjusted for the current component may include: determining the template size of the second type template of the current component and obtaining the buffer size ratio coefficient; determining the size of the buffer to be adjusted based on the template size of the second type template and the buffer size ratio coefficient; and dividing the buffer to be adjusted adjacent to the second type template of the current component in the first type template adjacent to the second type template of the current component according to the size of the buffer to be adjusted.

[0069] The buffer size ratio coefficient can be a pre-set description of the proportion of the buffer area to be adjusted to the second type of template area.

[0070] In this embodiment of the invention, the template size of the current second-type template of the current component can be determined, and the buffer size ratio coefficient set by the user can be obtained. Then, the product of the current second-type template size and the buffer size ratio coefficient is used as the buffer size to be adjusted (i.e., the size of the buffer to be adjusted). Further, in the first-type templates adjacent to the current second-type template, according to the buffer size to be adjusted, the buffers adjacent to the current second-type template and capable of uniformly surrounding the second-type template are determined. It should be noted that the logic for determining the buffers to be adjusted for different second-type templates under the current component is the same, and will not be repeated here.

[0071] Step 250: Grid layout is performed on the assembly block specification template to obtain the assembly block template to be divided, and the assembly block template to be divided is gridded to obtain the assembly block to be assembled.

[0072] In an optional embodiment of the present invention, performing a grid layout on the assembly block specification template to obtain the assembly block template to be divided may include: obtaining the cross-sectional position points corresponding to the assembly block specification template; dividing the assembly block specification template into multiple topological solid units according to the cross-sectional position points and at least one grid layout, and calculating the root mean square error of the edge length of the topological solid unit under each grid layout; and determining the assembly block template to be divided based on the root mean square error of the edge length of the topological solid unit under each grid layout.

[0073] The topological solid unit can be a topological hexahedron. The mean square error of the edge length can be used to describe the dispersion of the edge length distribution of the polyhedron.

[0074] In this embodiment of the invention, the cross-sectional position point corresponding to the assembly block specification template can be determined first. Then, according to the cross-sectional position point and at least one grid layout configured by the user, the assembly block specification template is divided into multiple topological solid units. The mean square error of the edge length of the multiple topological solid units divided by the assembly block specification template under each grid layout is calculated. The grid layout with the smallest mean square error of the edge length of the topological solid units is taken as the final grid layout, and the assembly block template under this grid layout is taken as the assembly block template to be divided.

[0075] For example, the intersection lines of each cross-sectional location point and the outer shell of the assembly block specification template are used as the intersection lines of the topological solid unit and the outer shell of the assembly block specification template under the internal grid layout of the assembly block specification template, thereby realizing the grid layout of the assembly block specification template.

[0076] Step 260: Lay out the assembly blocks to be spliced ​​according to the component spatial layout parameters to obtain a discrete encapsulation structure simulation model.

[0077] In an optional embodiment of the present invention, the process of meshing the template of the assembly block to be divided to obtain the assembly block to be assembled may include: meshing the template of the assembly block to be divided based on the homotopy mapping method and the equidistant interpolation method to obtain the assembly block to be assembled; after laying out the assembly block to be assembled according to the component spatial layout parameters to obtain the discretized encapsulation structure simulation model, the process may further include: obtaining boundary condition setting parameters, and outputting a simulation model description file according to the boundary condition setting parameters and the discretized encapsulation structure simulation model.

[0078] The boundary condition setting parameters can be parameters representing the physical behavior or constraints of the structural simulation model on the boundaries, as defined by the user. These parameters can include, but are not limited to, surface boundary conditions and point boundary conditions. The simulation model description file can be the simulation file required for advanced chip packaging simulation.

[0079] In this embodiment of the invention, the sampling points of the topological solid unit can be determined based on the mesh layout of the assembly block template to be divided and the discretized cross-section position set by the user. Based on the homotopy mapping of each edge of the topological solid unit to the unit line segment, the mapping between the topological solid unit and the standard cube is established. Then, the sampling points of the topological solid unit are interpolated at equal intervals in the standard cube on its mapping according to the equidistant interpolation method. Through the inverse mapping of the homotopy mapping, that is, the parameterized inverse mapping based on the edges and faces, the position values ​​of the interpolation points are mapped back to the three-dimensional space to obtain the three-dimensional values ​​of the mesh points on the assembly block template to be divided, as well as the one-dimensional, two-dimensional and three-dimensional template element units, thereby completing the final mesh division and obtaining the assembly block to be assembled.

[0080] After laying out the assembly blocks to be assembled according to the component spatial layout parameters to obtain the discrete packaging structure simulation model, the boundary condition setting parameters written by the user can be further obtained. Then, based on the boundary condition setting parameters and the discrete packaging structure simulation model, a simulation model description file for advanced chip packaging structure simulation can be generated.

[0081] The technical solution of this invention involves acquiring encapsulation structure description data, determining component spatial layout parameters based on component placement parameters in the encapsulation structure description data, dividing the space occupied by all components based on the component description parameters, obtaining spatial division results, and intersecting the spatial division results with each component to obtain a first type template and a second type template for each component. Then, based on the first type template and the second type template of each component, assembly block template reduction processing is performed to obtain an assembly block reduction template. The assembly block reduction template is then meshed to obtain an assembly block template to be divided. This meshing of the assembly block template to be divided yields assembly blocks to be assembled. The assembly blocks to be assembled are then laid out according to the component spatial layout parameters to obtain a discretized encapsulation structure simulation model. In this solution, the spatial layout of components can be automatically determined based on the encapsulation structure description data, and the assembly block templates corresponding to the components can be standardized to reduce the number of templates and improve subsequent processing efficiency. This effectively avoids system crashes when processing large-scale encapsulation structures. Furthermore, the process of meshing the templates, meshing, and finally assembling the assembly blocks based on the spatial layout of the components does not require manual intervention. This solves the problems of high labor costs and poor processing effect of large-scale encapsulation structures in existing advanced encapsulation structure simulations. It can reduce the labor costs of advanced encapsulation structure simulation and improve the processing effect of large-scale encapsulation structures.

[0082] Example 3

[0083] Embodiment 3 of the present invention provides an optional embodiment for modeling a structural simulation model of advanced chip packaging, the specific implementation of which can be found in the following embodiments. Technical terms that are the same as or corresponding to those in the above embodiments will not be repeated here.

[0084] Figure 3 This is a functional block diagram of a modeling tool for a structural simulation model of an advanced chip packaging provided in Embodiment 3 of the present invention. (See diagram below.) Figure 3 As shown, the tool includes a domain-specific language module, a spatial management module, a template extraction module, an assembly block module, a template module, an output module, and a material library module. The domain-specific language module includes a material description module (equivalent to a configuration module for component material description data), a basic component description module (equivalent to a configuration module for component description parameters), a coordinate system module (equivalent to a configuration module for component placement parameters), and a component combination management module (equivalent to a management module for component combination relationships). The spatial management module includes a component positioning module and a component Boolean operation module. The template extraction module includes a template recognition module and a template reduction module. The assembly block module includes an assembly block management module, an assembly block generation module, and an assembly block splicing module. The template module includes a template management module, a template generation module, and a mesh generation module. The material library module includes a material management module, a material property module, and a database user interface module. The output module includes a cdb file export module, a k file export module, and other solver file type export modules. Figure 3 The arrows in the diagram indicate the dependencies between modules.

[0085] Domain-specific language modules provide user programming interfaces, allowing users to describe encapsulated structures using natural language.

[0086] The spatial management module is used to identify the connection and contact relationships of components. Specifically, it obtains the spatial position of each component through the component positioning module, establishes a spatial positioning system for each component, and establishes a mapping relationship between spatial positions and components through the spatial positioning system. Based on the spatial positioning system, it can also establish a lookup table of spatial positions of each component and assembly blocks, establish the mapping between components and assembly blocks, obtain the assembly blocks belonging to the components, and establish the point, edge, and face mapping relationship between components and their assembly blocks. Thus, through the spatial positioning system and the component-assembly block lookup table, it establishes the layout of assembly blocks for each component. The component Boolean operation module performs Boolean operations on each component with other components to obtain the connection and contact relationships with each component.

[0087] The number of templates determines the overall problem scale of modeling. The goal of the template extraction module is to reduce the number of templates, thereby reducing the problem scale and supporting the discretization of large-scale models. Adjacent trivial templates can be combined to form new trivial templates, i.e., reducing the number of templates through template reduction. For example, in practical applications, there may be a large number of convex point arrays of different sizes. Singular templates exist in the convex point array. To maintain mesh consistency, the same singular template needs to have discrete cross-section points added to each other because of the different singular templates next to it, so as to keep the cross-section position consistent with the neighboring singular templates. However, adding cross-section points will generate a large number of different singular templates. To reduce the problem of generating new templates due to different cross-section positions of the same template, assembly block template reduction processing can be performed.

[0088] The assembly block template specification processing flow is as follows: 1) Space division: The space occupied by all components is divided according to the geometric boundaries of the components. The division result intersects with each component, and the components are divided into assembly block occupants. According to the component type in the geometric model, the occupant attribute can be a trivial template or a singular template. For example... Figure 4 As shown, Figure 4 The dark blue areas in the lower left and lower right corners are the singular template areas of the convex dot array components, while the light blue areas are the ordinary template areas of the convex dot array components.

[0089] 2) Calculate the discretization section position: Based on the discretization size set by the user, the discretization section positions of the singular template and the trivial template are determined by the principle of equal division.

[0090] 3) Determine the buffer zone to be adjusted: Compare the discrete cross-sectional positions of the singular template with those of adjacent trivial templates. If the cross-sectional positions are the same, no buffer zone to be adjusted is set. If the cross-sectional positions are different, a certain proportion of trivial templates are placed around the singular template, based on its size, to serve as the buffer zone to be adjusted. For example... Figure 5 As shown, Figure 5 The orange area represents the added buffer to be adjusted, and the buffer contains a trivial template. Figure 5The orange area represents the outer border of the buffer to be adjusted, while the green dashed line represents its inner border. The size of the buffer to be adjusted needs to be dynamically adjusted based on the difference in the density of cross-sectional points between the inner and outer borders. If the required increase in cross-sectional point density for the inner border is too large, the discretized mesh size will be too small. This can be addressed by increasing the size of the buffer to be adjusted, but it must be kept within a certain range and not expanded indefinitely. An excessively large buffer to be adjusted will limit subsequent simulations. Therefore, when the calculated buffer layer size exceeds the buffer adjustment threshold, the increase in buffer layer size stops, and a new singular template is added. This new singular template increases the number of discrete cross-sectional points by changing the mesh size, thereby increasing the density of discrete cross-sectional points within the inner border of the buffer to be adjusted.

[0091] 4) Determine the surrounding trivial template region adjacent to the buffer to be adjusted: Because the buffer to be adjusted occupies part of the trivial template, space needs to be divided according to the buffer to obtain a new trivial template. For trivial templates, adjacent trivial templates can be grouped into one template, for example... Figure 6 Regions A and B in the template can be merged into one template.

[0092] 5) Determine the latest discretization section position for each template: For subsequent discretization, it is necessary to determine the section position of each template. First, determine the discretization section position of the final buffer, and then determine the discretization section position of each trivial template based on the final buffer. Figure 6 An example of vertical cross-sectional position partitioning is given. To ensure that the number of singular templates does not increase and the discretized cross-sectional positions of the singular templates do not change, it is necessary to adjust the cross-sectional point positions of the outer and inner borders of the buffer to be adjusted to make the point density consistent. Figure 6 The outer border of the buffer to be adjusted is an orange area, and the corresponding inner border is a green dashed line. Based on the discretized cross-section obtained in step 2), compare the point density of the outer border and inner border cross-sections of the buffer to be adjusted, ensuring that the point density of the outer border is greater than or equal to that of the inner border. If the point density of the outer border cross-section is less than that of the inner border cross-section, adjust the mesh size of the outer border so that the point density of the outer border cross-section is greater than or equal to that of the inner border cross-section.

[0093] Once the cross-sectional position of the buffer to be adjusted is determined, the position can be passed to the adjacent trivial templates. In this way, the collected templates will only contain a few trivial templates, some singular templates, and a few templates with adjusted and enlarged buffers, which greatly reduces the number of templates and makes it possible to process large-scale convex arrays.

[0094] The template module is designed with configurable, adaptive matching assembly block templates based on the geometry of advanced encapsulation, providing configuration methods for assembly blocks, as well as adaptive mesh layout and partitioning methods.

[0095] The template management module manages various assembly block templates (cube assembly block template, cube embedded sphere template, cube embedded ellipsoid template, cube embedded lantern template, etc.) based on geometric shape and grid layout.

[0096] The template generation module divides the assembly block into multiple topological hexahedrons through mesh layout. A reasonable mesh layout is the key to ensuring mesh quality.

[0097] Under the current discretization conditions, the optimal mesh layout is selected: the intersection lines of each cross-sectional location point and the outer shell of the assembly block specification template are used as the intersection lines between the topological solid elements and the outer shell of the assembly block specification template under the internal mesh layout, thus realizing the mesh layout of the assembly block specification template. The root mean square error of the edge lengths of each topological hexahedron under the current layout is calculated, and the layout with the smallest root mean square error is selected as the acceptable mesh layout from multiple layouts. The parametric representation of each edge of each topological hexahedron is calculated (optional but not limited to equal arc length and equal central angle parametric methods). The parametric representation of each face of each topological hexahedron is calculated, further establishing the topological relationships of the solid, face, and edge to obtain the assembly block template to be divided.

[0098] The mesh generation module is used to generate a mesh after the internal geometry and mesh layout of the assembly block template are determined. The module performs the mesh generation through the following steps: Based on the mesh layout and the user-defined discretized cross-section, it calculates the sampling point parameters on each edge of the topological hexahedron. It then calculates the homotopy mapping from each edge of the topological hexahedron to the unit line segment (see...). Figure 7 The process involves establishing a mapping between topological hexahedrons and standard cubes. For each topological hexahedron, isometric interpolation is performed within its standard cube. Through the inverse mapping of homotopy and the parametric inverse mapping of composite edges and faces, the positional values ​​of the interpolated points are mapped back to the original 3D space, yielding the 3D values ​​of the mesh points. Furthermore, one-dimensional, two-dimensional, and three-dimensional template element units are constructed to obtain the final mesh generation, and a mapping relationship is established between the template geometry and the one-dimensional, two-dimensional, and three-dimensional template element units.

[0099] Assembly blocks are instances of templates and are the basic units used to build geometric models. The assembly block management module generates assembly block instances (generated by the assembly block generation module) based on different templates according to user requirements and manages them in groups as needed. The assembly block splicing module provides the function of placing assembly blocks and automatically merging the mesh units (points, lines, and surfaces) within a group. The assembly block generation module generates assembly block instances and determines their actual positions in 3D space. Assembly blocks are added to user-specified assembly block groups. The assembly block groups automatically identify the positional relationships of each vertex according to user-specified tolerances and perform point merging operations. A global mesh index is established, converting the geometric mesh mapping relationship of the template into the geometric mesh mapping relationship of the assembly blocks.

[0100] The ability to output specific solver file formats makes it possible to unify and integrate modeling tools, material database modules, and solvers.

[0101] The output module outputs solver files that meet the requirements of different solvers. The input to the solver is a simulation model description file, which is the output file of the aforementioned modeling tools. The simulation model description file can specifically include finite elements (i.e., the meshed data), component materials, and boundary conditions, etc.

[0102] This solution addresses the issue of large-scale mesh generation prone to crashes in structural simulation of advanced packaging, simplifies the modeling process of structural simulation in advanced packaging, and improves the automation level of structural simulation modeling in advanced packaging.

[0103] Example 4

[0104] Figure 8 This is a schematic diagram of the modeling device for a structural simulation model of an advanced chip packaging provided in Embodiment 4 of the present invention. Figure 8 As shown, the device includes:

[0105] Data acquisition module 310 is used to acquire encapsulation structure description data;

[0106] The assembly block specification template determination module 320 is used to determine the component spatial layout parameters based on the component placement parameters in the encapsulation structure description data, and perform assembly block template specification processing based on the component description parameters in the encapsulation structure description data to obtain the assembly block specification template.

[0107] The grid layout and division module 330 is used to perform grid layout on the assembly block specification template according to the assembly block specification template to obtain the assembly block template to be divided, and to perform grid division on the assembly block template to be divided to obtain the assembly block to be assembled.

[0108] The assembly block layout module 340 is used to lay out the assembly blocks to be assembled according to the component spatial layout parameters to obtain a discrete encapsulation structure simulation model.

[0109] The technical solution of this invention acquires encapsulation structure description data, determines component spatial layout parameters based on component placement parameters in the encapsulation structure description data, and performs assembly block template reduction processing based on component description parameters in the encapsulation structure description data to obtain assembly block reduction templates. Then, the assembly block reduction templates are meshed to obtain assembly block templates to be divided, and the assembly block templates to be divided are meshed to obtain assembly blocks to be assembled. Finally, the assembly blocks to be assembled are laid out according to the component spatial layout parameters to obtain a discretized encapsulation structure simulation model. In this solution, the spatial layout of components can be automatically determined based on the encapsulation structure description data, and the corresponding assembly block templates can be reduced to decrease the number of templates and improve subsequent processing efficiency. This effectively avoids system crashes during large-scale encapsulation structure processing. Furthermore, the meshing of templates, meshing, and the final assembly of assembly blocks based on the component spatial layout all require no manual intervention. This solves the problems of high labor costs and poor processing effects of large-scale encapsulation structures in existing advanced encapsulation structure simulations, reducing the labor costs of advanced encapsulation structure simulation and improving the processing effect of large-scale encapsulation structures.

[0110] Optionally, the assembly block specification template determination module 320 is specifically used to divide the space occupied by all components based on the component description parameters in the encapsulation structure description data, obtain the space division result, and intersect the space division result with each component to obtain the first type template and the second type template of each component; and perform assembly block template reduction processing according to the first type template and the second type template of each component to obtain the assembly block specification template.

[0111] Optionally, the assembly block specification template determination module 320 is specifically used to determine the buffer to be adjusted of the current component when the discrete cross-sectional positions of the second type template and the first type template of the current component are different; and to perform assembly block template reduction processing based on the density of the inner border cross-sectional position points, the density of the outer border cross-sectional position points, and the buffer adjustment threshold of the buffer to be adjusted of the current component, so as to obtain the assembly block specification template corresponding to the current component.

[0112] Optionally, the assembly block specification template determination module 320 is specifically used to calculate the density difference between the density of the outer frame cross-section position points and the density of the inner frame cross-section position points when the density of the outer frame cross-section position points of the buffer to be adjusted is less than the density of the inner frame cross-section position points; expand the buffer to be adjusted according to the density difference and the buffer size threshold to obtain the specification template of the current component; perform spatial division based on the expanded buffer to be adjusted to update the first type of template; and perform assembly block template specification processing on the first type of template to obtain the assembly block specification template corresponding to the current component.

[0113] Optionally, the grid layout and division module 330 is specifically used to determine the template size of the second type template of the current component and obtain the buffer size ratio coefficient; determine the size of the buffer to be adjusted according to the template size of the second type template and the buffer size ratio coefficient; and divide the buffer to be adjusted adjacent to the second type template of the current component in the first type template adjacent to the second type template of the current component according to the size of the buffer to be adjusted.

[0114] Optionally, the mesh layout and partitioning module 330 is specifically used to obtain the cross-sectional position points corresponding to the assembly block specification template; divide the assembly block specification template into multiple topological solid units according to the cross-sectional position points and at least one mesh layout, and calculate the root mean square error of the edge length of the topological solid unit under each mesh layout; and determine the assembly block template to be partitioned based on the root mean square error of the edge length of the topological solid unit under each mesh layout.

[0115] Optionally, the grid layout and partitioning module 330 is specifically used to perform grid partitioning on the assembly block template to be partitioned based on the homotopy mapping method and the equidistant interpolation method to obtain the assembly block to be spliced.

[0116] Optionally, the modeling device for the structural simulation model of advanced chip packaging further includes acquiring boundary condition setting parameters and outputting a simulation model description file based on the boundary condition setting parameters and the discretized packaging structure simulation model.

[0117] The modeling apparatus for the advanced chip packaging structure simulation model provided in this embodiment of the invention can execute the modeling method for the advanced chip packaging structure simulation model provided in any embodiment of the invention, and has the corresponding functional modules and beneficial effects of the execution method.

[0118] Example 5

[0119] Figure 9 A schematic diagram of an electronic device that can be used to implement embodiments of the present invention is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital assistants, cellular phones, smartphones, wearable devices (e.g., helmets, glasses, watches, etc.), and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the invention described and / or claimed herein.

[0120] like Figure 9As shown, the electronic device 10 includes at least one processor 11 and a memory, such as ROM 12, RAM 13, etc., communicatively connected to the at least one processor 11. The memory stores computer programs executable by the at least one processor. The processor 11 can perform various appropriate actions and processes based on the computer program stored in the ROM 12 or loaded into the RAM 13 from the storage unit 18. The RAM 13 can also store various programs and data required for the operation of the electronic device 10. The processor 11, ROM 12, and RAM 13 are interconnected via a bus 14. An I / O interface 15 is also connected to the bus 14. The ROM 12 is a read-only memory, the RAM 13 is a random access memory, and the I / O interface 15 is an input / output interface.

[0121] Multiple components in electronic device 10 are connected to I / O interface 15, including: input unit 16, such as keyboard, mouse, etc.; output unit 17, such as various types of displays, speakers, etc.; storage unit 18, such as disk, optical disk, etc.; and communication unit 19, such as network card, modem, wireless transceiver, etc. Communication unit 19 allows electronic device 10 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0122] Processor 11 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of processor 11 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. Processor 11 performs the various methods and processes described above, such as modeling methods for structural simulation models of advanced chip packages.

[0123] In some embodiments, the modeling method for the structural simulation model of an advanced chip package can be implemented as a computer program tangibly contained in a computer-readable storage medium, such as storage unit 18. In some embodiments, part or all of the computer program can be loaded and / or installed on the electronic device 10 via ROM 12 and / or communication unit 19. When the computer program is loaded into RAM 13 and executed by processor 11, one or more steps of the modeling method for the structural simulation model of an advanced chip package described above can be performed. Alternatively, in other embodiments, processor 11 can be configured to execute the modeling method for the structural simulation model of an advanced chip package by any other suitable means (e.g., by means of firmware).

[0124] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems-on-a-chip (SoCs), payload-programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.

[0125] Computer programs used to implement the methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, such that when executed by the processor, the computer programs cause the functions / operations specified in the flowcharts and / or block diagrams to be performed. The computer programs may be executed entirely on a machine, partially on a machine, or as a standalone software package, partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0126] In the context of this invention, a computer-readable storage medium can be a tangible medium that may contain or store a computer program for use by or in conjunction with an instruction execution system, apparatus, or device. A computer-readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. Alternatively, a computer-readable storage medium may be a machine-readable signal medium. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, RAM, ROM, erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0127] To provide interaction with a user, the systems and techniques described herein can be implemented on an electronic device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the electronic device. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).

[0128] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as data servers), or computing systems that include middleware components (e.g., application servers), or computing systems that include frontend components (e.g., user computers with graphical user interfaces or web browsers through which users can interact with implementations of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., communication networks). Examples of communication networks include local area networks (LANs), wide area networks (WANs), blockchain networks, and the Internet.

[0129] A computing system can include clients and servers. Clients and servers are generally located far apart and typically interact through communication networks. The client-server relationship is created by computer programs running on the respective computers and having a client-server relationship with each other. The server can be a cloud server, also known as a cloud computing server or cloud host, which is a hosting product within the cloud computing service system to address the shortcomings of traditional physical hosts and VPS servers, such as high management difficulty and weak business scalability.

[0130] This application also discloses a computer program product, which includes a computer program that, when executed by a processor, implements the modeling method for the structural simulation model of advanced chip packaging provided in any embodiment of this application. This program product and the modeling method for the structural simulation model of advanced chip packaging disclosed in the embodiments of this application belong to the same inventive concept, and therefore will not be described in detail here.

[0131] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0132] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A modeling method of a structure emulation model of a chip advanced package, characterized by, include: Obtain the encapsulation structure description data; Based on the component placement parameters in the encapsulation structure description data, the component spatial layout parameters are determined, and based on the component description parameters in the encapsulation structure description data, the assembly block template is reduced to obtain the assembly block reduction template. The assembly block specification template is meshed to obtain the assembly block template to be divided, and the assembly block template to be divided is meshed to obtain the assembly block to be assembled. The assembly blocks to be assembled are laid out according to the component spatial layout parameters to obtain a discrete packaging structure simulation model. Based on the component description parameters in the encapsulation structure description data, an assembly block template reduction process is performed to obtain an assembly block reduction template. This includes: dividing the space occupied by all components based on the component description parameters in the encapsulation structure description data to obtain a space division result; intersecting the space division result with each component to obtain a first type template and a second type template for each component; and performing assembly block template reduction processing based on the first type template and the second type template for each component to obtain the assembly block reduction template. The step of performing assembly block template reduction processing based on the first type template and the second type template of each component to obtain the assembly block reduction template includes: determining the buffer to be adjusted for the current component when the discrete cross-sectional positions of the second type template and the first type template of the current component are different; calculating the density difference between the density of the outer border cross-sectional position points and the density of the inner border cross-sectional position points when the density density of the outer border cross-sectional position points of the buffer to be adjusted is less than the density of the inner border cross-sectional position points; expanding the buffer to be adjusted based on the density difference and the buffer size threshold to obtain the template to be reduced for the current component; performing spatial partitioning based on the expanded buffer to be adjusted and updating the first type template; and performing assembly block template reduction processing on the first type template to obtain the assembly block reduction template corresponding to the current component.

2. The method according to claim 1, characterized in that, The step of determining the adjustment buffer zone of the current component when the discrete section positions of the second type template and the first type template of the current component are different includes: Determine the template size of the second type template of the current component, and obtain the buffer size ratio coefficient; The size of the buffer to be adjusted is determined based on the template size of the second type of template and the buffer size ratio coefficient. In the first type template adjacent to the second type template of the current component, the buffer to be adjusted is divided according to the size of the buffer to be adjusted.

3. The method according to claim 1, characterized in that, The step of performing a grid layout on the assembly block specification template to obtain the assembly block template to be divided includes: Obtain the cross-sectional position point corresponding to the assembly block specification template; According to the cross-sectional location points and at least one grid layout, the assembly block specification template is divided into multiple topological solid units, and the mean square error of the edge length of the topological solid unit under each grid layout is calculated. The template for the assembly block to be divided is determined based on the mean square error of the edge length of each topological unit under the grid layout.

4. The method according to claim 1, characterized in that, The step of dividing the template of the assembly block to be divided into a mesh to obtain the assembly block to be assembled includes: Based on the homotopy mapping method and the equidistant interpolation method, the template of the assembly block to be divided is meshed to obtain the assembly block to be spliced. After laying out the assembly blocks to be assembled according to the component spatial layout parameters to obtain a discrete packaging structure simulation model, the method further includes: Obtain the boundary condition setting parameters, and output the simulation model description file based on the boundary condition setting parameters and the discretized packaging structure simulation model.

5. A modeling device for a structural simulation model of advanced chip packaging, characterized in that, include: The data acquisition module is used to acquire the encapsulation structure description data; The assembly block specification template determination module is used to determine the component spatial layout parameters based on the component placement parameters in the encapsulation structure description data, and perform assembly block template specification processing based on the component description parameters in the encapsulation structure description data to obtain the assembly block specification template. The grid layout and division module is used to perform grid layout on the assembly block specification template according to the assembly block specification template to obtain the assembly block template to be divided, and to perform grid division on the assembly block template to be divided to obtain the assembly block to be assembled. The assembly block layout module is used to lay out the assembly blocks to be assembled according to the component spatial layout parameters to obtain a discrete packaging structure simulation model. The assembly block specification template determination module is specifically used to divide the space occupied by all components based on the component description parameters in the encapsulation structure description data, obtain the space division result, and intersect the space division result with each component to obtain the first type template and the second type template of each component. Based on the first type template and the second type template of each component, the assembly block template specification process is performed to obtain the assembly block specification template; The assembly block specification template determination module is specifically used to determine the buffer to be adjusted for the current component when the discrete cross-sectional positions of the second type template and the first type template of the current component are different; when the density of the outer frame cross-sectional position points of the buffer to be adjusted is less than the density of the inner frame cross-sectional position points, calculate the density difference between the density of the outer frame cross-sectional position points and the density of the inner frame cross-sectional position points; expand the buffer to be adjusted according to the density difference and the buffer size threshold to obtain the specification template to be adjusted for the current component; perform spatial division based on the expanded buffer to be adjusted; and update the first type template. The first type of template is subjected to assembly block template specification processing to obtain the assembly block specification template corresponding to the current component.

6. An electronic device, characterized in that, The electronic device includes: At least one processor; and A memory communicatively connected to the at least one processor; wherein, The memory stores a computer program that can be executed by the at least one processor, the computer program being executed by the at least one processor to enable the at least one processor to execute the modeling method for the structural simulation model of the advanced chip package according to any one of claims 1-4.

7. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions that are used to cause a processor to execute the modeling method of the structure simulation model of the chip advanced package as described in any one of claims 1-4.

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