Closed-loop control device for switching power supply and multipath analog quantity

Abstract

The invention belongs to the technical field of power supplies, and particularly relates to a closed-loop control device for a switching power supply and multi-channel analog quantity, the closed-loop control device for the multi-channel analog quantity comprises a signal input module, a multi-channel voltage conversion module and a logic conversion module, the signal input module comprises a first signal connection end and a multi-channel variable input sub-module, each path of voltage conversion module is connected with each path of variable input sub-module; the logic conversion module comprises a first logic sub-module, a second logic sub-module and four paths of third logic sub-modules. According to the closed-loop control device for the multi-channel analog quantity, closed-loop conversion, comparison conversion, phase conversion, logic conversion and pulse edge conversion processing are carried out on clock signals, reference signals and multi-channel sampling variable level signals input by a signal input module through a multi-channel voltage conversion module and a logic conversion module; and finally, a phase multi-path adjustable full-bridge-driven PWM signal is output, and the stability of synchronously controlling the output of a plurality of variables is realized.

Description

Technical Field

[0001] This application belongs to the technical field of power supplies, and particularly relates to a switching power supply and a closed-loop control device for multiple analog quantities. Background Art

[0002] The power output system has high requirements for the stability of output current, voltage, power supply temperature, ambient air pressure, etc. At present, the multi-analog quantity closed-loop control technology of the power output system adopts a constant output method by collecting a single output variable. For example, if the output current is collected, it is a constant current power supply, and if the output voltage is collected, it is a constant voltage power supply; this control method of a single variable constant cannot ensure the stability of other variables, has certain limitations, and brings great inconvenience to the project in terms of the output stability of power supply design and development. Summary of the Invention

[0003] An embodiment of this application provides a switching power supply and a closed-loop control device for multiple analog quantities to solve the problem that the existing power output adopts a control method of a single variable constant, which cannot ensure the stability of other variables and has certain limitations in power output.

[0004] In a first aspect, an embodiment of this application provides a closed-loop control device for multiple analog quantities, including: A signal input module for connecting to an input signal. The signal input module includes a first signal connection end for inputting a clock signal and a multi-channel variable input sub-module. Each variable input sub-module includes a second signal connection end for inputting a reference signal and a third signal connection end for inputting a sampled variable level signal; A voltage conversion module. The number of voltage conversion modules is set corresponding to the number of variable input sub-modules. Each voltage conversion module is connected to each variable input sub-module. Each voltage conversion module is used to perform closed-loop conversion and comparison conversion processing on the reference signal and the sampled variable level signal input to each variable input sub-module to obtain a level signal after voltage conversion corresponding to each variable input sub-module; A logic conversion module, including a first logic sub-module, a second logic sub-module, and four third logic sub-modules. The input end of the first logic sub-module is connected to the first signal connection end, the output end of the first logic sub-module is connected to the second logic sub-module, the second logic sub-module is also connected to the output end of each voltage conversion module, the output end of the second logic sub-module is connected to the input end of each third logic sub-module, and each third logic sub-module is used to output a PWM signal; Wherein, the first logic sub-module is configured to perform exclusive-OR processing on the clock signal to obtain a first processed signal; the second logic sub-module is configured to perform exclusive-OR and logic level conversion processing on each path of the level signal and the first processed signal to obtain four paths of logic transformation signals; each path of the third logic sub-module is configured to perform pulse edge transformation processing on the input logic transformation signal to obtain a PWM signal.

[0005] Optionally, the multi-channel analog quantity closed-loop control device includes a voltage supply module for providing a comparison voltage signal to each path of the voltage conversion module. The voltage supply module includes a first diode, a second diode, a constant current diode, a first capacitor, and a second capacitor. The first end of the constant current diode is connected to a DC bias power supply. The second end of the constant current diode is respectively connected to the first end of the first capacitor, the first end of the second capacitor, the first end of the second diode, and each path of the voltage conversion module. The second end of the second diode is connected to the first end of the first diode. The second end of the first diode is connected to the first logic sub-module. The second ends of the first capacitor and the second capacitor are both grounded.

[0006] Optionally, each path of the voltage conversion module includes a first operational amplifier, a second operational amplifier, and a comparator with an open collector. The second end of the first operational amplifier is connected to the third signal connection end of one path of the variable input sub-module through a fifth resistor. The third end of the first operational amplifier is connected to the second signal connection end of one path of the variable input sub-module through a sixth resistor. The sixth end of the first operational amplifier is connected to the third end of the second operational amplifier through a ninth resistor and an eleventh resistor. The second end of the second operational amplifier is connected to the first end of the second operational amplifier. The first end of the second operational amplifier is further connected to the third end of the comparator through a twelfth resistor. The second end of the comparator is connected to the second end of the constant current diode. The seventh end of the comparator is connected to the input end of the second logic sub-module. The first end and the fourth end of the comparator are grounded. The fifth end, the sixth end, the eighth end of the comparator, the eighth end of the second operational amplifier, and the seventh end of the first operational amplifier are all connected to the positive DC bias power supply. The fourth end of the first operational amplifier and the fourth end of the second operational amplifier are both connected to the negative DC bias power supply.

[0007] Optionally, the positive DC bias power supply is connected to the seventh end of the comparator through a thirteenth resistor. An eighth resistor and a third capacitor are connected in parallel between the second end and the sixth end of the first operational amplifier. The third end of the first operational amplifier is further grounded through a seventh resistor. The third end of the first operational amplifier is further grounded through a fourth capacitor.

[0008] Optionally, the first logic sub-module includes a first OR gate element and a first exclusive-OR gate element. A first end of the first OR gate element is connected to the first signal connection end through a first resistor. A second end of the first OR gate element is respectively connected to the first end of the first OR gate element and a first end of a second resistor. A second end of the second resistor is grounded. A third end of the first OR gate element is respectively connected to a second end of the first diode and a first end of a third resistor. A second end of the third resistor is connected to a second end of the first exclusive-OR gate element. A first end of the first exclusive-OR gate element is grounded through a fourth resistor. A third end of the first exclusive-OR gate element is connected to the second logic sub-module.

[0009] Optionally, the second logic sub-module includes a second OR gate element, a switching transistor, a first D flip-flop, a second D flip-flop, a second exclusive-OR gate element, a third exclusive-OR gate element, and a fourth exclusive-OR gate element. Input ends of the second OR gate element are connected to output ends of four voltage conversion modules. An output end of the second OR gate element is respectively connected to a second end of the switching transistor and a sixth end of the second D flip-flop through a forty-first resistor. A control end of the switching transistor is connected to an output end of the first logic sub-module through a forty-second resistor. The output end of the first logic sub-module is also respectively connected to a fifth end of the first D flip-flop and a fourth end of the second D flip-flop. A third end of the switching transistor, a fourth end of the first D flip-flop, a sixth end of the first D flip-flop, a third end of the second D flip-flop, and a fifth end of the second D flip-flop are all grounded. A first end of the first D flip-flop is respectively connected to an input end of a first path of the third logic sub-module and a first end of the third exclusive-OR gate element. A second end of the first D flip-flop is respectively connected to a third end of the first D flip-flop, a first end of the fourth exclusive-OR gate element, and an input end of a second path of the third logic sub-module. A second end of the second D flip-flop is connected to a second end of the second exclusive-OR gate element through a forty-third resistor. A first end of the second exclusive-OR gate element is connected to the positive DC bias power supply through a forty-fourth resistor. A third end of the second exclusive-OR gate element is respectively connected to a second end of the third exclusive-OR gate element and a second end of the fourth exclusive-OR gate element. A third end of the third exclusive-OR gate element is connected to an input end of a third path of the third logic sub-module. A third end of the fourth exclusive-OR gate element is connected to an input end of a fourth path of the third logic sub-module.

[0010] Optionally, the third logic sub-module includes a Schmitt trigger and a NOR gate element. The input end of the Schmitt trigger is connected to the output end of the second logic sub-module. The output end of the Schmitt trigger is connected to the first input end of the NOR gate element. The second input end of the NOR gate element is grounded through a fifty-third resistor. The output end of the NOR gate element serves as the output end for the third logic sub-module to output a PWM signal.

[0011] Optionally, a resistor and a capacitor are connected between the output end of the Schmitt trigger and the first input end of the NOR gate element. The first end of the resistor is connected to the output end of the Schmitt trigger. The second end of the resistor is respectively connected to the first end of the capacitor and the first input end of the NOR gate element. The capacitor is grounded.

[0012] Optionally, the switching transistor is a MOS transistor. The gate of the MOS transistor serves as the control end of the switching transistor. The source of the MOS transistor serves as the third end of the switching transistor. The drain of the MOS transistor serves as the second end of the switching transistor.

[0013] In a second aspect, an embodiment of the present application provides a switching power supply, including the above-mentioned closed-loop control device for multiple analog quantities.

[0014] A switching power supply and a closed-loop control device for multiple analog quantities provided by an embodiment of the present application. The closed-loop control device for multiple analog quantities includes a signal input module for connecting to an input signal. The signal input module includes a first signal connection end for clock signal input and a multiple-channel variable input sub-module. Each channel of the variable input sub-module includes a second signal connection end for reference signal input and a third signal connection end for sampling variable level signal input; a voltage conversion module, the number of voltage conversion modules is set corresponding to the number of variable input sub-modules. Each channel of the voltage conversion module is connected to each channel of the variable input sub-module. Each channel of the voltage conversion module is used to perform closed-loop conversion and comparison conversion processing on the reference signal and the sampled variable level signal input to each channel of the variable input sub-module to obtain a level signal after voltage conversion corresponding to each channel of the variable input sub-module; a logic conversion module, including a first logic sub-module, a second logic sub-module, and four channels of third logic sub-modules. The input end of the first logic sub-module is connected to the first signal connection end. The output end of the first logic sub-module is connected to the second logic sub-module. The second logic sub-module is also connected to the output end of each channel of the voltage conversion module. The output end of the second logic sub-module is connected to the input end of each channel of the third logic sub-module. Each channel of the third logic sub-module is used to output a PWM signal; wherein, the first logic sub-module is used to perform exclusive OR processing on the clock signal to obtain a first processed signal; the second logic sub-module is used to perform exclusive OR and logic level conversion processing according to each channel of the level signal and the first processed signal to obtain four channels of logic conversion signals; each channel of the third logic sub-module is used to perform pulse edge conversion processing on the input logic conversion signal to obtain a PWM signal. The closed-loop control device for multiple analog quantities realizes closed-loop conversion, comparison conversion, phase conversion, logic conversion, and pulse edge conversion processing on the clock signal, reference signal, and multiple-channel sampled variable level signals input by the signal input module through multiple-channel voltage conversion modules and logic conversion modules, and finally outputs a PWM signal with phase-adjustable full-bridge drive to realize the stability of synchronous control of multiple variable outputs, and solves the problem that the existing power supply output adopts a control method with a single variable constant, which cannot ensure the stability of other variables and there are certain limitations in the power supply output.

[0015] The switching power supply adopts a closed-loop control device for multiple analog quantities. During the working process, the switching power supply can synchronously control the stability of multiple variable outputs and ensure the stability of the switching power supply operation. Brief Description of the Drawings

[0016] In order to more clearly illustrate the technical solutions in an embodiment of the present application, the following will briefly introduce the drawings required for the description of the embodiment. Obviously, the following described drawings are only some embodiments of the present application. For those skilled in the art, without creative efforts, other drawings can also be obtained according to these drawings.

[0017] To more fully understand the present application and its beneficial effects, the following will be described in conjunction with the accompanying drawings. Among them, the same reference numerals in the following description represent the same parts.

[0018] Figure 1 Schematic diagram of the framework of a multi-channel analog closed-loop control device provided by an embodiment of the present application.

[0019] Figure 2 Schematic diagram of the circuit of a multi-channel analog closed-loop control device provided by an embodiment of the present application.

[0020] Figure 3 For the present application Figure 2 Enlarged view at position A in the figure.

[0021] Figure 4 For the present application Figure 2 Enlarged view at position B in the figure.

[0022] Figure 5 Schematic diagram of the signals input and output by the comparator in a multi-channel analog closed-loop control device provided by an embodiment of the present application.

[0023] Figure 6 Schematic diagram of the signals input and output by the first logic sub-module in a multi-channel analog closed-loop control device provided by an embodiment of the present application.

[0024] Figure 7 For the present application Figure 2 Enlarged view at position C in the figure.

[0025] Figure 8 Schematic diagram of the signals of the second logic sub-module in a multi-channel analog closed-loop control device provided by an embodiment of the present application.

[0026] Figure 9 For the present application Figure 2 Enlarged view at position D in the figure.

[0027] Figure 10 Schematic diagram of the signals of the third logic sub-module in a multi-channel analog closed-loop control device provided by an embodiment of the present application. Detailed implementation manners

[0028] Next, the technical solutions in an embodiment of the present application will be clearly and completely described in conjunction with the accompanying drawings in an embodiment of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative efforts belong to the scope protected by the present application.

[0029] An embodiment of the present application provides a switching power supply and a closed-loop control device for multiple analog quantities to solve the problem that the existing power supply output adopts a control method with a single variable constant, which cannot ensure the stability of other variables and there are certain limitations in the power supply output. The switching power supply and the closed-loop control device for multiple analog quantities are applicable to switching power supplies such as high-frequency pulse switching power supplies, high-power DC switching power supplies, and DC bias power supplies.

[0030] Embodiment 1: A closed-loop control device for multiple analog quantities provided by an embodiment of the present application. Exemplarily, please refer to Figure 1 , Figure 1 which is a schematic framework diagram of the closed-loop control device for multiple analog quantities provided by an embodiment of the present application, Figure 2 and

[0031] is Figure 1 and Figure 2 shown, the present invention provides a closed-loop control device for multiple analog quantities, including a signal input module 10, a multiple-channel voltage conversion module 20, and a logic conversion module 30.

[0032] Further explanation is that the closed-loop control device for multiple analog quantities realizes closed-loop transformation, comparison transformation, phase transformation, logic transformation, and pulse edge transformation processing on the clock signal, reference signal REF, and multiple-channel sampled variable level signals input by the signal input module 10 through the multiple-channel voltage conversion module 20 and the logic conversion module 30, and finally outputs a PWM signal with 4-way adjustable phase full-bridge drive. In this embodiment, the closed-loop control device for multiple analog quantities adopts a multiple-channel analog quantity closed-loop method, and during its operation, it can synchronously control the stability of multiple variable outputs and ensure the stability of the power supply system operation.

[0033] In the embodiment of the invention of the application, the signal input module 10 is used to connect with the input signal. The signal input module includes a first signal connection end SYN for clock signal input and a multiple-channel variable input sub-module. Each variable input sub-module includes a second signal connection end REF for reference signal input and a third signal connection end for sampled variable level signal input.

[0034] Further explanation is that there are four variable input sub-modules, and correspondingly, there are also four multiple-channel voltage conversion modules 20. In Figure 2 , the third signal connection ends of the four variable input sub-modules are respectively denoted as |FB-1|, |FB-2|, |FB-3|, and |FB-4|. In this embodiment, the reference signal is set according to requirements.

[0035] In the embodiment of the invention claimed, the number of voltage conversion modules 20 is set corresponding to the number of variable input sub-modules. Each voltage conversion module 20 is connected to each variable input sub-module. Each voltage conversion module 20 is used to perform closed-loop conversion and comparison conversion processing on the reference signal and the sampled variable level signal input to each variable input sub-module, and obtain the level signal after voltage conversion corresponding to each variable input sub-module.

[0036] Furthermore, each voltage conversion module 20 performs voltage conversion according to the input reference signal and sampled variable level signal to obtain the level signal input to the logic conversion module 30.

[0037] In the embodiment of the invention claimed, the logic conversion module 30 includes a first logic sub-module 31, a second logic sub-module 32, and four third logic sub-modules 33. The input end of the first logic sub-module 31 is connected to the first signal connection end SYN. The output end of the first logic sub-module 31 is connected to the second logic sub-module 32. The second logic sub-module 32 is also connected to the output end of each voltage conversion module 20. The output end of the second logic sub-module 32 is connected to the input end of each third logic sub-module 33. Each third logic sub-module 33 is used to output a PWM signal. Among them, the first logic sub-module 31 is used to perform exclusive OR processing on the clock signal to obtain a first processing signal; the second logic sub-module 32 is used to perform exclusive OR and logic level conversion processing according to each level signal and the first processing signal to obtain four logic conversion signals; each third logic sub-module 33 is used to perform pulse edge conversion processing on the input logic conversion signal to obtain a PWM signal.

[0038] Furthermore, the logic conversion module 30 performs logic conversion on the level signal input by the voltage conversion module 20 and the clock signal input by the first signal connection end SNY through the first logic sub-module 31, the second logic sub-module 32, and the four third logic sub-modules 33 to output four PWM signals. As Figure 2 shown, the four output PWM signals are respectively denoted as DR4D, DR3C, DR1B, and DR2A. The output ends of the four third logic sub-modules 33 are connected to a full-bridge circuit of a power electronic conversion topology structure composed of four bridge arms. For example: the first PWM signal DR4D is used as the driving signal of the upper tube of the rear bridge arm of the full-bridge circuit, the second PWM signal DR3C is used as the driving signal of the lower tube of the rear bridge arm of the full-bridge circuit, the third PWM signal DR1B is used as the driving signal of the upper tube of the front bridge arm of the full-bridge circuit, and the fourth PWM signal DR2A is used as the driving signal of the lower tube of the front bridge arm of the full-bridge circuit.

[0039] In the embodiment of the invention claimed, the multi-channel analog closed-loop control device can synchronously control the stability of multiple variable outputs, and further better ensure the stability and reliability of the power supply system.

[0040] A closed-loop control device for multiple analog quantities provided by an embodiment of the present application includes a signal input module for connecting to an input signal. The signal input module includes a first signal connection end for clock signal input and a multiple-channel variable input sub-module. Each channel of the variable input sub-module includes a second signal connection end for reference signal input and a third signal connection end for sampling variable level signal input; a voltage conversion module, the number of voltage conversion modules is set corresponding to the number of variable input sub-modules. Each channel of the voltage conversion module is connected to each channel of the variable input sub-module. Each channel of the voltage conversion module is used to perform closed-loop conversion and comparison conversion processing on the reference signal and the sampled variable level signal input to each channel of the variable input sub-module to obtain a level signal after voltage conversion corresponding to each channel of the variable input sub-module; a logic conversion module, including a first logic sub-module, a second logic sub-module, and four channels of third logic sub-modules. The input end of the first logic sub-module is connected to the first signal connection end. The output end of the first logic sub-module is connected to the second logic sub-module. The second logic sub-module is also connected to the output end of each channel of the voltage conversion module. The output end of the second logic sub-module is connected to the input end of each channel of the third logic sub-module. Each channel of the third logic sub-module is used to output a PWM signal; wherein, the first logic sub-module is used to perform exclusive OR processing on the clock signal to obtain a first processing signal; the second logic sub-module is used to perform exclusive OR and logic level conversion processing according to each channel of the level signal and the first processing signal to obtain four channels of logic conversion signals; each channel of the third logic sub-module is used to perform pulse edge conversion processing on the input logic conversion signal to obtain a PWM signal. The closed-loop control device for multiple analog quantities realizes closed-loop conversion, comparison conversion, phase conversion, logic conversion, and pulse edge conversion processing on the clock signal, reference signal, and multiple-channel sampled variable level signals input by the signal input module through the multiple-channel voltage conversion module and the logic conversion module, and finally outputs a PWM signal for a phase multi-channel adjustable full-bridge drive, realizing the stability of synchronous control of multiple variable outputs, improving the power supply safety and reliability of the closed-loop control device for multiple analog quantities, and solving the problem that the existing power supply output adopts a control method with a single variable constant, which cannot guarantee the stability of other variables and there are certain limitations in the power supply output.

[0041] Figure 3 For the present application Figure 2 The enlarged view at position A in

[0042] Such as Figure 2 and Figure 3As shown, in the embodiment of the invention under application, the closed-loop control device for multiple analog quantities further includes a voltage supply module M1 for providing a comparison voltage signal to each voltage conversion module 20. The voltage supply module M1 includes a first diode D1, a second diode D2, a constant current diode D3, a first capacitor C1, and a second capacitor C2. The first end of the constant current diode D3 is connected to a DC bias power supply. The second end of the constant current diode D3 is respectively connected to the first end of the first capacitor C1, the first end of the second capacitor C2, the first end of the second diode D2, and each voltage conversion module 30. The second end of the second diode D2 is connected to the first end of the first diode D1. The second end of the first diode D1 is connected to the first logic sub-module 31. The second ends of the first capacitor C1 and the second capacitor C2 are both grounded.

[0043] Further explanation is that the DC bias power supply can be selected as 15V DC power. The first end of the constant current diode D3 is connected to the positive DC bias power supply. In this embodiment, the voltage supply module M1 is used to perform voltage conversion on the voltage provided by the DC bias power supply through the constant current diode D3 to provide a comparison voltage signal to each voltage conversion module 30. In this embodiment, the anode of the diode is used as the first end of the diode, and the cathode of the diode is used as the second end of the diode.

[0044] Figure 4 For this application Figure 2 the enlarged view at B, Figure 5 is a signal schematic diagram of the input and output of the comparator in the closed-loop control device for multiple analog quantities provided by an embodiment of this application. In Figure 5 , U5-2 represents the comparison voltage signal output by the voltage supply module M1 to the input end of the comparator U5 (such as Figure 5 the horizontal line in), U5-3 represents the voltage signal output by the second operational amplifier to the input end of the comparator U5 (such as Figure 5 the wavy line in), U5-7 represents the level signal at the output end of the comparator U5; U8-2 represents the comparison voltage signal output by the voltage supply module M1 to the input end of the comparator U8 (such as Figure 5 the horizontal line in), U8-3 represents the voltage signal output by the second operational amplifier to the input end of the comparator U8 (such as Figure 5 the wavy line in), U8-7 represents the level signal at the output end of the comparator U8; U11-2 represents the comparison voltage signal output by the voltage supply module M1 to the input end of the comparator U11 (such as Figure 5 the horizontal line in), U11-3 represents the voltage signal output by the second operational amplifier to the input end of the comparator U11 (such as Figure 5 the wavy line in), U11-7 represents the level signal at the output end of the comparator U11; U14-2 represents the comparison voltage signal output by the voltage supply module M1 to the input end of the comparator U14 (such asFigure 5 the horizontal line in [reference numeral]; U14-3 represents the voltage signal output from the second operational amplifier to the input terminal of comparator U14 (such as Figure 5 the wavy line in [reference numeral]); U14-7 represents the level signal at the output terminal of comparator U14.

[0045] In the embodiment of the invention claimed, the variable input sub-module is provided with four paths, and correspondingly, the voltage conversion module 20 is also provided with four paths. The four voltage conversion modules 20 are respectively denoted as the first voltage conversion module, the second voltage conversion module, the third voltage conversion module, and the fourth voltage conversion module. As shown in Figure 2 and Figure 4 , the first voltage conversion module 20 includes a first operational amplifier U3 (model OP07), a second operational amplifier U4 (model TL084CDR), and a comparator U5 with open collector (model LM211). The second terminal of the first operational amplifier U3 is connected to the third signal connection terminal of a path of variable input sub-module through a fifth resistor R5. The third terminal of the first operational amplifier U3 is connected to the second signal connection terminal of a path of variable input sub-module through a sixth resistor R6. The sixth terminal of the first operational amplifier U3 is connected to the third terminal of the second operational amplifier U4 through a ninth resistor R9 and an eleventh resistor R11. The second terminal of the second operational amplifier U4 is connected to the first terminal of the second operational amplifier U4. The first terminal of the second operational amplifier U4 is further connected to the third terminal of the comparator U5 through a twelfth resistor R12. The second terminal of the comparator U5 is connected to the second terminal of the constant current diode D3. The seventh terminal of the comparator U5 is connected to the input terminal of the second logic sub-module 32. The first terminal and the fourth terminal of the comparator U5 are grounded. The fifth terminal, the sixth terminal, the eighth terminal of the comparator U5, the eighth terminal of the second operational amplifier U4, and the seventh terminal of the first operational amplifier U3 are all connected to a positive DC bias power supply. The fourth terminal of the first operational amplifier U3 and the fourth terminal of the second operational amplifier U4 are both connected to a negative DC bias power supply. The positive DC bias power supply is connected to the seventh terminal of the comparator U5 through a thirteenth resistor R13. An eighth resistor R8 and a third capacitor C3 are connected in parallel between the second terminal and the sixth terminal of the first operational amplifier U3. The third terminal of the first operational amplifier U3 is further grounded through a seventh resistor R7 and also grounded through a fourth capacitor C4.

[0046] Furthermore, as shown in Figure 5As shown, the voltage conversion module 20 performs a closed-loop conversion on the input reference signal and the sampled variable level signal through the first operational amplifier U3 and the second operational amplifier U4 to obtain a first conversion signal; the voltage conversion module 20 performs a comparison conversion on the input first conversion voltage signal and the comparison voltage signal provided by the voltage supply module M1 through the comparator U5 to obtain a level signal. In this embodiment, the first operational amplifier of the second voltage conversion module 20 is denoted as U6, the second operational amplifier is denoted as U7, and the comparator is denoted as U8. The first operational amplifier of the third voltage conversion module 20 is denoted as U9, the second operational amplifier is denoted as U10, and the comparator is denoted as U11; the first operational amplifier of the fourth voltage conversion module 20 is denoted as U12, the second operational amplifier is denoted as U13, and the comparator is denoted as U14.

[0047] Figure 6 It is a signal schematic diagram of the input and output of the first logic sub-module in the multi-channel analog closed-loop control device provided by an embodiment of the present application. In Figure 6 SYN and U1-1 represent clock signals; U2-3 represents the voltage signal at the output end of the first exclusive-OR gate element U2.

[0048] As Figure 2 , Figure 3 and Figure 6 shown, in the embodiment of the invention of the present application, the first logic sub-module 31 includes a first OR gate element U1 and a first exclusive-OR gate element U2. The first end of the first OR gate element U1 is connected to the first signal connection end SYN through a first resistor. The second end of the first OR gate element U1 is respectively connected to the first end of the first OR gate element U1 and the first end of the second resistor R2. The second end of the second resistor R2 is grounded. The third end of the first OR gate element U1 is respectively connected to the second end of the first diode D1 and the first end of the third resistor R3. The second end of the third resistor R3 is connected to the second end of the first exclusive-OR gate element U2. The first end of the first exclusive-OR gate element U2 is grounded through a fourth resistor R4. The third end of the first exclusive-OR gate element U2 is connected to the second logic sub-module 32.

[0049] Further, as Figure 6 shown, the first logic sub-module 31 is used to perform OR gate and exclusive-OR gate processing on the input clock signal to obtain a first processed signal.

[0050] Figure 7 For the present application Figure 2 the enlarged view at C, Figure 8 It is a signal schematic diagram of the second logic sub-module in the multi-channel analog closed-loop control device provided by an embodiment of the present application. In Figure 8 U16- The signal output from the second terminal of the first D flip-flop U16, U16-Q represents the signal output from the first terminal of the first D flip-flop U16, and U15-1 represents the signal output from the output terminal of the second OR gate element U15; U17-S represents the signal at the sixth terminal of the second D flip-flop U17; U17-R represents the signal at the fourth terminal of the second D flip-flop U17, U17- represents the signal at the second terminal of the second D flip-flop U17; U18-3 is the signal output from the output terminal of the second exclusive-OR gate element U18; U19-3 is the signal output from the output terminal of the third exclusive-OR gate element U19, and U20-3 is the signal output from the output terminal of the fourth exclusive-OR gate element U20.

[0051] Such as Figure 2 , Figure 7 and Figure 8 As shown in, in the embodiment of the invention claimed, the second logic sub-module 32 includes a second OR gate element U15 (model CD4072), a switching transistor Q1, a first D flip-flop U16 (model CD4013), a second D flip-flop U17 (model CD4013), a second exclusive-OR gate element U18 (model CD4070), a third exclusive-OR gate element U19 (model CD4070), and a fourth exclusive-OR gate element U20 (model CD4070). The input terminals of the second OR gate element U18 are connected to the output terminals of the four-way voltage conversion module 20. The output terminal of the second OR gate element U15 is connected to the second terminal of the switching transistor Q1 and the sixth terminal of the second D flip-flop U17 respectively through the forty-first resistor R41. The control terminal of the switching transistor Q1 is connected to the output terminal of the first logic sub-module 31 through the forty-second resistor R42. The output terminal of the first logic sub-module 31 is also connected to the fifth terminal of the first D flip-flop U16 and the fourth terminal of the second D flip-flop U17 respectively; the third terminal of the switching transistor Q1, the fourth terminal of the first D flip-flop U16, the sixth terminal of the first D flip-flop U16, the third terminal of the second D flip-flop U17, and the fifth terminal of the second D flip-flop U17 are all grounded; the first terminal of the first D flip-flop U16 is connected to the input terminal of the first path of the third logic sub-module 33 and the first terminal of the third exclusive-OR gate element U19 respectively. The second terminal of the first D flip-flop U16 is connected to the third terminal of the first D flip-flop U16, the first terminal of the fourth exclusive-OR gate element U20, and the input terminal of the second path of the third logic sub-module 33 respectively; the second terminal of the second D flip-flop U17 is connected to the second terminal of the second exclusive-OR gate element U18 through the forty-third resistor R43. The first terminal of the second exclusive-OR gate element U18 is connected to the positive DC bias power supply through the forty-fourth resistor R44. The third terminal of the second exclusive-OR gate element U18 is connected to the second terminal of the third exclusive-OR gate element U19 and the second terminal of the fourth exclusive-OR gate element U20 respectively; the third terminal of the third exclusive-OR gate element U19 is connected to the input terminal of the third path of the third logic sub-module 33, and the third terminal of the fourth exclusive-OR gate element U20 is connected to the input terminal of the fourth path of the third logic sub-module 33.

[0052] Further, the switching transistor Q1 can be selected as a MOS transistor. The gate of the MOS transistor serves as the control terminal of the switching transistor Q1, the source of the MOS transistor serves as the third terminal of the switching transistor Q1, and the drain of the MOS transistor serves as the second terminal of the switching transistor Q1. In this embodiment, the second OR gate element U15 performs an OR operation on the levels output by the four-way voltage conversion module 20 and then inputs the result together with the signal output by the switching transistor Q1 into the sixth terminal of the second D flip-flop U17. Then, it performs a logic transformation process with the first processing signal input to the fourth terminal of the second D flip-flop U17 to obtain the first transformation signal U17- ; the first transformation signal is processed by the second XOR gate element U18 to obtain the third transformation signal U18-3; the first processing signal is subjected to a logic transformation process by the first D flip-flop U16 to obtain the second transformation signal U16-Q and the third transformation signal U16- , the third transformation signal U18-3 and the second transformation signal U16-Q are input to the third XOR gate element U19 for an XOR operation to obtain the third logic transformation signal U19-3 input to the third logic sub-module 33 of the third path; the third transformation signal U18-3 and the third transformation signal U16- are input to the fourth XOR gate element U20 for an XOR operation to obtain the fourth logic transformation signal U20-3 input to the third logic sub-module 33 of the fourth path. The second transformation signal U16-Q serves as the first logic transformation signal of the first logic sub-module 33 of the first path, and the third transformation signal U16- serves as the second logic transformation signal of the second logic sub-module 33 of the second path.

[0053] Figure 9 This is for Figure 2 the enlarged view at D in this application Figure 10 and is the signal schematic diagram of the third logic sub-module in the multi-channel analog closed-loop control device provided by an embodiment of this application. In Figure 10 , U21-3 serves as the signal at the output terminal of the Schmitt trigger U21, U22-3 serves as the signal at the output terminal of the Schmitt trigger U22, U23-3 serves as the signal at the output terminal of the Schmitt trigger U23, and U24-3 serves as the signal at the output terminal of the Schmitt trigger U24; DR4D, DR3C, DR1B, and DR2A are respectively the PWM signals output by the corresponding four-way third logic sub-modules 33.

[0054] As shown in Figure 2 , Figure 9 and Figure 10As shown, in the embodiment of the invention being applied, taking the third logic sub-module of the first path as an example, the third logic sub-module 33 of the first path includes a Schmitt trigger U21 (model CD4093) and a NOR gate element U25 (model CD4001). The input end of the Schmitt trigger U21 is connected to the output end of the second logic sub-module 32 (such as the first end of the first D flip-flop U16). The output end of the Schmitt trigger U21 is connected to the first input end of the NOR gate element U25. The second input end of the NOR gate element U25 is grounded through the fifty-third resistor 53. The output end of the NOR gate element U25 serves as the output end for the third logic sub-module 33 to output a PWM signal. A resistor R49 and a capacitor C15 are connected between the output end of the Schmitt trigger U21 and the first input end of the NOR gate element U25. The first end of the resistor R49 is connected to the output end of the Schmitt trigger U21. The second end of the resistor R49 is respectively connected to the first end of the capacitor C15 and the first input end of the NOR gate element U25. The capacitor C15 is grounded.

[0055] Further illustration is as follows Figure 2 and Figure 9As shown, the first input terminal of the Schmitt trigger U21 is connected to the first terminal of the first D flip-flop U16 through the forty-fifth resistor R45. The connection between the forty-fifth resistor R45 and the Schmitt trigger U21 is grounded through the eleventh capacitor C11. The second input terminal of the Schmitt trigger U21 is directly connected to the first terminal of the first D flip-flop U16. In the second third logic sub-module 33, the second terminal of the first D flip-flop U16 is directly connected to the first terminal of the Schmitt trigger U22. The second terminal of the first D flip-flop U16 is connected to the second terminal of the Schmitt trigger U22 through the forty-sixth resistor R46. The connection between the forty-sixth resistor R46 and the Schmitt trigger U22 is grounded through the twelfth capacitor C12. The third terminal of the Schmitt trigger U22 is connected to the first terminal of the NOR gate element U26 through the fiftieth resistor R50. The second terminal of the NOR gate element U26 is grounded through the fifty-third resistor R53. The connection between the NOR gate element U26 and the fiftieth resistor R50 is also grounded through the sixteenth capacitor C16. The third terminal of the NOR gate element U26 serves as the output terminal of the second third logic sub-module 33. In the third third logic sub-module 33, the third terminal (output terminal) of the third exclusive-OR gate element U19 is directly connected to the second terminal of the Schmitt trigger U23. The third terminal (output terminal) of the third exclusive-OR gate element U19 is connected to the first terminal of the Schmitt trigger U23 through the forty-seventh resistor R47. The connection between the forty-seventh resistor R47 and the Schmitt trigger U23 is grounded through the thirteenth capacitor C13. The third terminal of the Schmitt trigger U23 is connected to the first terminal of the NOR gate element U27 through the fifty-first resistor R51. The second terminal of the NOR gate element U27 is grounded through the fifty-third resistor R53. The connection between the NOR gate element U27 and the fifty-first resistor R51 is also grounded through the seventeenth capacitor C17. The third terminal of the NOR gate element U27 serves as the output terminal of the third third logic sub-module 33. In the fourth third logic sub-module 33, the third terminal (output terminal) of the fourth exclusive-OR gate element U20 is directly connected to the first terminal of the Schmitt trigger U24. The third terminal (output terminal) of the fourth exclusive-OR gate element U20 is connected to the second terminal of the Schmitt trigger U24 through the forty-eighth resistor R48. The connection between the forty-eighth resistor R48 and the Schmitt trigger U24 is grounded through the fourteenth capacitor C14. The third terminal of the Schmitt trigger U24 is connected to the first terminal of the NOR gate element U28 through the fifty-second resistor R52. The second terminal of the NOR gate element U28 is grounded through the fifty-third resistor R53. The connection between the NOR gate element U28 and the fifty-second resistor R52 is also grounded through the eighteenth capacitor C18. The third terminal of the NOR gate element U28 serves as the output terminal of the fourth third logic sub-module 33. As Figure 10As shown, the first third logic sub-module 33 is used to perform logic transformation and NOR gate processing on the input second transformation signal U16-Q through the Schmidt trigger U21 and the NOR gate element U25 to obtain the first PWM signal DR4D; the second third logic sub-module 33 is used to perform logic transformation and NOR gate processing on the input third transformation signal U16- through the Schmidt trigger U22 and the NOR gate element U26 to obtain the second PWM signal DR3C; the third third logic sub-module 33 is used to perform logic transformation and NOR gate processing on the input third logic transformation signal U19-3 through the Schmidt trigger U23 and the NOR gate element U27 to obtain the third PWM signal DR1B; the fourth third logic sub-module 33 is used to perform logic transformation and NOR gate processing on the input fourth logic transformation signal U20-3 through the Schmidt trigger U24 and the NOR gate element U28 to obtain the fourth PWM signal DR2A.

[0056] In the embodiment of the invention claimed, as Figure 5 , Figure 6 , Figure 8 and Figure 10 shown, the multi-channel analog closed-loop control device performs OR gate processing on the input clock signal SYN through the first OR gate element U1 and the first XOR gate element U2 to obtain the first processing signal corresponding to the negation of the clock signal SYN, as Figure 6 shown. The input reference signal and the sampled variable level signal are logically processed through the first operational amplifiers U3 / U6 / U9 / U12 (model OP07) and the second operational amplifiers U4 / U7 / U10 / U13 (model TL084CDR) to obtain the input to the comparators U5 / U8 / U11 / U14 (model LM211), the third-terminal first transformation voltage signal (such as Figure 5 the wavy lines shown in U5-3, U8-3, U11-3, and U14-3 in), and in the comparators U5 / U8 / U11 / U14, the first transformation voltage signal of the wavy line is compared with the comparison voltage signal with a fixed value provided by the voltage supply module M1 (such as Figure 5 the horizontal lines shown in U5-2, U8-2, U11-2, and U14-2 in) to obtain the level signal (such as Figure 5 the level signal composed of high and low levels shown in U5-7, U8-7, U11-7, and U14-7 in). The level signal is subjected to negation processing through the OR gate of the second OR gate element U15 (model CD4072) to obtain the second level signal such as Figure 8 U15-1 in; the second level signal passes through the clock CLK port of the D-type flip-flop U16 (model: CD4013) to obtain the third transformation signal such as Figure 8 U16- shown and the third transformation signal and such as Figure 8The second transformation signal shown in U16-Q; the second level signal passes through the set S port of the D-type flip-flop U17 (model: CD4013) and the first processing signal corresponding to the inverted SYN passes through the reset R port of the D-type flip-flop U17 (model: CD4013) to obtain as Figure 8 shown in U17- the fourth transformation signal; U17- the fourth transformation signal of is subjected to an exclusive-OR process by the second exclusive-OR gate element U18 (model: CD4070) to obtain as Figure 8 the fifth transformation signal shown in U18-3; the fifth transformation signal and the second transformation signal of U16-Q are subjected to an exclusive-OR process using the third exclusive-OR gate element U19 (model: CD4070) to obtain as Figure 8 the third logic transformation signal shown in U19-3; the fifth transformation signal and U16- the third transformation signal of are subjected to an exclusive-OR process using the fourth exclusive-OR gate element U20 (model: CD4070) to obtain as Figure 8 the fourth logic transformation signal shown in U20-3. Finally, the second transformation signal U16-Q undergoes a NAND logic process with 2 inputs of the Schmitt trigger U21 (model: CD4093) to obtain as Figure 10 the first NAND signal of U21-3 shown; the first NAND signal of U21-3 undergoes a NOR logic process with 2 inputs of the NOR gate element U25 (model: CD4001) to obtain as Figure 10 the first PWM signal shown in DR4D; the third transformation signal U16- undergoes a NAND logic process with 2 inputs of the Schmitt trigger U22 (model: CD4093) to obtain as Figure 10 the second NAND signal of U22-3 shown; the second NAND signal of U22-3 undergoes a NOR logic process with 2 inputs of the NOR gate element U26 (model: CD4001) to obtain as Figure 10 the second PWM signal shown in DR3C; the third logic transformation signal U19-3 undergoes a NAND logic process with 2 inputs of the Schmitt trigger U23 (model: CD4093) to obtain as Figure 10 the third NAND signal of U23-3 shown; the third NAND signal of U23-3 undergoes a NOR logic process with 2 inputs of the NOR gate element U27 (model: CD4001) to obtain as Figure 10 the third PWM signal shown in DR1B; the fourth logic transformation signal U20-3 undergoes a NAND logic process with 2 inputs of the Schmitt trigger U24 (model: CD4093) to obtain as Figure 10 the fourth NAND signal of U24-3 shown; the fourth NAND signal of U24-3 undergoes a NOR logic process with 2 inputs of the NOR gate element U28 (model: CD4001) to obtain asFigure 10 The fourth PWM signal shown in DR2A.

[0057] Embodiment 2: The present invention further provides a switching power supply, including the above-mentioned closed-loop control device for multiple analog quantities.

[0058] The content of the closed-loop control device for multiple analog quantities has been described in Embodiment 1, and the description of the content of the closed-loop control device for multiple analog quantities will not be repeated in this embodiment. The switching power supply adopts the closed-loop control device for multiple analog quantities. During the working process, the switching power supply can synchronously control the stability of multiple variable outputs, ensuring the stability of the switching power supply during operation.

[0059] In the above embodiments, the descriptions of the respective embodiments have their own focuses. For the parts not detailed in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0060] In the description of the present application, the terms "first" and "second" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more features.

[0061] The above has introduced in detail the closed-loop control device for multiple analog quantities provided in an embodiment of the present application. Specific examples are used herein to illustrate the principle and implementation manner of the present application. The description of the above embodiments is only used to help understand the method and its core idea of the present application; at the same time, for those skilled in the art, according to the idea of the present application, there will be changes in the specific implementation manner and application scope. In summary, the content of this specification should not be construed as a limitation to the present application.

Claims

1. A closed-loop control device for multiple analog quantities, characterized in that Comprising: A signal input module for connecting to an input signal. The signal input module includes a first signal connection terminal for clock signal input and a multi-channel variable input sub-module. Each variable input sub-module includes a second signal connection terminal for reference signal input and a third signal connection terminal for sampling variable level signal input; A voltage conversion module. The number of voltage conversion modules is set corresponding to the number of variable input sub-modules. Each voltage conversion module is connected to each variable input sub-module. Each voltage conversion module is used to perform closed-loop conversion and comparison conversion processing on the reference signal and the sampled variable level signal input to each variable input sub-module to obtain a level signal after voltage conversion corresponding to each variable input sub-module; A logic conversion module, including a first logic sub-module, a second logic sub-module, and four third logic sub-modules. The input end of the first logic sub-module is connected to the first signal connection terminal. The output end of the first logic sub-module is connected to the second logic sub-module. The second logic sub-module is also connected to the output end of each voltage conversion module. The output end of the second logic sub-module is connected to the input end of each third logic sub-module. Each third logic sub-module is used to output a PWM signal; Wherein, the first logic sub-module is used to perform exclusive OR processing on the clock signal to obtain a first processed signal; the second logic sub-module is used to perform exclusive OR and logic level conversion processing according to each level signal and the first processed signal to obtain four logic conversion signals; each third logic sub-module is used to perform pulse edge conversion processing on the input logic conversion signal to obtain a PWM signal.

2. The closed-loop control device for multiple analog quantities according to claim 1, wherein It further includes a voltage supply module for providing a comparison voltage signal to each voltage conversion module. The voltage supply module includes a first diode, a second diode, a constant current diode, a first capacitor, and a second capacitor. The first end of the constant current diode is connected to a DC bias power supply. The second end of the constant current diode is respectively connected to the first end of the first capacitor, the first end of the second capacitor, the first end of the second diode, and each voltage conversion module. The second end of the second diode is connected to the first end of the first diode. The second end of the first diode is connected to the first logic sub-module. The second ends of the first capacitor and the second capacitor are both grounded.

3. The closed-loop control device for multiple analog quantities according to claim 2, characterized in that, Each of the voltage conversion modules includes a first operational amplifier, a second operational amplifier, and a comparator with an open collector. The second terminal of the first operational amplifier is connected to the third signal connection terminal of one of the variable input sub-modules through a fifth resistor. The third terminal of the first operational amplifier is connected to the second signal connection terminal of one of the variable input sub-modules through a sixth resistor. The sixth terminal of the first operational amplifier is connected to the third terminal of the second operational amplifier through a ninth resistor and an eleventh resistor. The second terminal of the second operational amplifier is connected to the first terminal of the second operational amplifier. The first terminal of the second operational amplifier is further connected to the third terminal of the comparator through a twelfth resistor. The second terminal of the comparator is connected to the second terminal of the constant current diode. The seventh terminal of the comparator is connected to the input terminal of the second logic sub-module. The first terminal and the fourth terminal of the comparator are grounded. The fifth terminal, the sixth terminal, the eighth terminal of the comparator, the eighth terminal of the second operational amplifier, and the seventh terminal of the first operational amplifier are all connected to the positive DC bias power supply. The fourth terminal of the first operational amplifier and the fourth terminal of the second operational amplifier are both connected to the negative DC bias power supply.

4. The closed-loop control device for multiple analog quantities according to claim 3, wherein The positive DC bias power supply is connected to the seventh terminal of the comparator through a thirteenth resistor. An eighth resistor and a third capacitor are connected in parallel between the second terminal and the sixth terminal of the first operational amplifier. The third terminal of the first operational amplifier is further grounded through a seventh resistor. The third terminal of the first operational amplifier is further grounded through a fourth capacitor.

5. The closed-loop control device for multiple analog quantities according to claim 2, wherein The first logic sub-module includes a first OR gate element and a first XOR gate element. The first terminal of the first OR gate element is connected to the first signal connection terminal through a first resistor. The second terminal of the first OR gate element is connected to the first terminal of the first OR gate element and the first terminal of a second resistor respectively. The second terminal of the second resistor is grounded. The third terminal of the first OR gate element is connected to the second terminal of the first diode and the first terminal of a third resistor respectively. The second terminal of the third resistor is connected to the second terminal of the first XOR gate element. The first terminal of the first XOR gate element is grounded through a fourth resistor. The third terminal of the first XOR gate element is connected to the second logic sub-module.

6. The closed-loop control device for multiple analog quantities according to claim 1, characterized in that, The second logic sub-module includes a second OR gate element, a switching transistor, a first D flip-flop, a second D flip-flop, a second XOR gate element, a third XOR gate element, and a fourth XOR gate element. The input ends of the second OR gate element are connected to the output ends of four-way voltage conversion modules. The output end of the second OR gate element is connected to the second end of the switching transistor and the sixth end of the second D flip-flop respectively through a forty-first resistor. The control end of the switching transistor is connected to the output end of the first logic sub-module through a forty-second resistor. The output end of the first logic sub-module is also connected to the fifth end of the first D flip-flop and the fourth end of the second D flip-flop respectively. The third end of the switching transistor, the fourth end of the first D flip-flop, the sixth end of the first D flip-flop, the third end of the second D flip-flop, and the fifth end of the second D flip-flop are all grounded. The first end of the first D flip-flop is connected to the input end of the first-way third logic sub-module and the first end of the third XOR gate element respectively. The second end of the first D flip-flop is connected to the third end of the first D flip-flop, the first end of the fourth XOR gate element, and the input end of the second-way third logic sub-module respectively. The second end of the second D flip-flop is connected to the second end of the second XOR gate element through a forty-third resistor. The first end of the second XOR gate element is connected to a positive DC bias power supply through a forty-fourth resistor. The third end of the second XOR gate element is connected to the second end of the third XOR gate element and the second end of the fourth XOR gate element respectively. The third end of the third XOR gate element is connected to the input end of the third-way third logic sub-module. The third end of the fourth XOR gate element is connected to the input end of the fourth-way third logic sub-module.

7. The closed-loop control device for multiple analog quantities according to claim 6, wherein, The third logic sub-module includes a Schmitt trigger and a NOR gate element. The input end of the Schmitt trigger is connected to the output end of the second logic sub-module. The output end of the Schmitt trigger is connected to the first input end of the NOR gate element. The second input end of the NOR gate element is grounded through a fifty-third resistor. The output end of the NOR gate element serves as the output end for outputting the PWM signal of the third logic sub-module.

8. The closed-loop control device for multiple analog quantities according to claim 7, wherein A resistor and a capacitor are connected between the output end of the Schmitt trigger and the first input end of the NOR gate element. The first end of the resistor is connected to the output end of the Schmitt trigger. The second end of the resistor is connected to the first end of the capacitor and the first input end of the NOR gate element respectively. The capacitor is grounded.

9. The closed-loop control device for multiple analog quantities according to claim 6, characterized in that, The switching transistor is a MOS transistor. The gate of the MOS transistor serves as the control end of the switching transistor. The source of the MOS transistor serves as the third end of the switching transistor. The drain of the MOS transistor serves as the second end of the switching transistor.

10. A switching power supply, characterized in that, It includes a closed-loop control device for multi-channel analog quantities as described in any one of claims 1-9.

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