Data processing methods, caching subsystem, and multiprocessor system
By introducing sniffing request queues, conflict checking circuits, and data forwarding circuits into multiprocessor systems, the problems of cache consistency and performance optimization in cross-cluster environments are solved, achieving efficient cross-processor communication and improved system performance.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SOPHGO TECH LTD
- Filing Date
- 2025-03-14
- Publication Date
- 2026-07-17
AI Technical Summary
In multiprocessor systems, how can performance be optimized while ensuring cache consistency, especially in cross-cluster environments to reduce communication latency and improve system performance?
By introducing a sniffing request queue, a conflict checking circuit, and a data forwarding circuit into a multiprocessor system, address conflict checking and data forwarding are performed to ensure that when there is an address conflict between a write request and a sniffing request, the request data is immediately transmitted when the data forwarding condition is met, avoiding waiting for the write request to complete.
It effectively reduces the latency of cross-processor communication, enables efficient interconnection between processors in a multiprocessor system, and improves system performance.
Smart Images
Figure CN120371729B_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of computer technology, and in particular to a data processing method, a cache subsystem, and a multiprocessor system. Background Technology
[0002] Multiprocessor systems are widely used due to their high performance and scalability. A multiprocessor system can include multiple processors and memory, with the processors sharing the memory space. Each processor can include at least one core. Each processor has its own cache, which caches data in memory for fast access by the processor.
[0003] However, different processors reading from and writing to their respective caches may cause the same data to be inconsistent in the caches of different processors. How to optimize the performance of multiprocessor systems while ensuring cache consistency across multiple processors remains an important direction for current technological development. Summary of the Invention
[0004] To overcome the problems existing in related technologies, this disclosure proposes a data processing method, a caching subsystem, and a multiprocessor system. The data processing method proposed in this disclosure can effectively shorten the communication latency across processors in a multiprocessor system and improve the performance of the multiprocessor system.
[0005] According to a first aspect of the present disclosure, a data processing method is provided, the method comprising:
[0006] In response to a first sniffing request in the sniffing request queue, an address conflict check is performed on the first sniffing request based on at least one write request from within the first processor; wherein the first sniffing request is a sniffing request from the interconnect bus, and the second processor is connected to the first processor via the interconnect bus; the first processor is any processor in the multiprocessor system, and the second processor is any processor in the multiprocessor system other than the first processor;
[0007] If at least one write request contains an address conflict between the target write request and the first sniffing request, determine whether the target write request satisfies the data forwarding condition.
[0008] If the target write request meets the data forwarding condition, the request data of the target write request is passed to the first sniffing request in the sniffing request queue.
[0009] According to a second aspect of the present disclosure, a caching subsystem is provided for use in a multiprocessor system, the caching subsystem comprising:
[0010] A sniffing request queue is used to store the first sniffing request from the interconnect bus; the first processor is any processor in the multiprocessor system, and the second processor is any processor in the multiprocessor system other than the first processor; the second processor is connected to the first processor via the interconnect bus.
[0011] A conflict checking circuit, connected to a sniffing request queue, is used to perform address conflict checking on a first sniffing request based on at least one write request from a first processor.
[0012] The data forwarding circuit, connected to the conflict checking circuit and the sniffing request queue, is used to determine whether the target write request meets the data forwarding condition if there is an address conflict between the target write request and the first sniffing request in at least one write request; if the target write request meets the data forwarding condition, the request data of the target write request is passed to the first sniffing request.
[0013] According to a third aspect of the present disclosure, a multiprocessor system is provided, comprising:
[0014] Multiple processors are connected via an interconnect bus, and each processor includes a cache subsystem according to the second aspect of the present disclosure.
[0015] The technical solutions provided by the embodiments of this disclosure may include the following beneficial effects:
[0016] In the data processing method proposed in this embodiment, address conflict checks are performed on at least one write request in the first processor and a first sniffing request from the interconnect bus in the sniffing request queue. If at least one write request has a target write request that conflicts with the address of the first sniffing request, it is determined whether the target write request meets the data forwarding condition. If the target write request meets the data forwarding condition, the request data of the target write request is passed to the first sniffing request using the data forwarding circuit, without waiting for the target write request to be completed before executing the first sniffing request. In this way, data consistency between multiple processors is guaranteed, and the first processor can respond quickly to the first sniffing request, effectively shortening the communication latency of cross-processor communication, realizing efficient interconnection between multiple processors in a multiprocessor system, and improving the performance of the multiprocessor system.
[0017] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description
[0018] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure.
[0019] Figure 1 This is a partial structural diagram of a caching subsystem according to an exemplary embodiment;
[0020] Figure 2 This is a flowchart illustrating a data processing method according to an exemplary embodiment. Figure 1 ;
[0021] Figure 3 This is a schematic diagram of the overall architecture of a caching subsystem according to an exemplary embodiment;
[0022] Figure 4 This is a schematic diagram illustrating the architecture of a sniffing buffer according to an exemplary embodiment;
[0023] Figure 5 This is a flowchart illustrating a data processing method according to an exemplary embodiment. Figure 2 ;
[0024] Figure 6 This is a schematic diagram illustrating a data forwarding process according to an exemplary embodiment. Detailed Implementation
[0025] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numerals in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this disclosure. Rather, they are merely examples of apparatuses consistent with some aspects of this disclosure as detailed in the appended claims.
[0026] With the rapid development of multi-core processor technology, the number of processor cores in modern computer systems is constantly increasing, making cache coherence a particularly important issue. Cache coherence refers to maintaining consistency in the cache across multiple processor cores (i.e., kernels), ensuring that modifications made to data by one processor core are promptly known to other processor cores, thereby avoiding inconsistencies in the data seen by different processor cores, which can lead to data loss, calculation errors, and other problems. To achieve cache coherence, the industry has proposed and widely adopted various protocols and methods. Among them, common cache coherence protocols include Modified Exclusive Shared Invalid (MESI), Modified Owned Exclusive Shared Invalid (MOESI), and Modified Shared Invalid (MSI). The MESI protocol is one of the fundamental protocols for maintaining cache coherence. It ensures consistency by maintaining four states for each cache block. The MOESI protocol adds an ownership state to MESI to indicate that a cache block has been modified but is shared across multiple caches.
[0027] In practical applications, the AMBA (Advanced Microcontroller Bus Architecture) protocol also plays a crucial role in multi-core system design. Proposed by ARM, the AMBA protocol aims to improve communication efficiency between various components in a system. It includes several sub-protocols, such as ACE (Advanced Microcontroller Bus Architecture Coherency Extension), which support high-bandwidth and low-latency data transmission and can work in conjunction with cache coherency protocols. The ACE protocol provides support for burst transmissions and cache coherency operations, enabling effective maintenance of data sharing and consistency in multi-core processor environments. Its AR, AW, and AC channels can also effectively couple read / write and sniffing paths within the cluster. The CHI (Coherent Hub Interface) protocol, the fifth generation of AMBA and an evolution of the ACE protocol, uses packets to transmit all information, addressing data consistency issues between multiple processors. The CHI protocol aims for scalability, enabling the construction of small, medium, or large systems. These systems utilize multiple components, ranging from processor clusters, graphics processors, and memory controllers to I / O bridges, PCIExpress (PCIe) subsystems, and the interconnect itself.
[0028] With the ever-increasing demands for computing power, especially in massively parallel computing and distributed systems, cache consistency technology faces new challenges. How to optimize performance while ensuring data consistency remains an important direction for current technological development.
[0029] In current processor architectures, the ACE protocol is typically used within a cluster (i.e., between multiple cores of a processor) to achieve cache coherency and data sharing. The ACE protocol provides efficient cache coherency support for multi-core processors and is particularly suitable for communication within a single cluster. However, the application of the ACE protocol in multi-cluster environments (i.e., multi-processor systems) faces several challenges. First, the large number of signal ports in the ACE protocol makes it inadequate for directly supporting efficient interconnection between multiple clusters. Specifically, the complexity and high overhead of the ACE protocol lead to a significant increase in communication latency during cross-cluster data transmission, thus affecting the overall system performance. In this situation, relying solely on the ACE protocol is insufficient to meet the high-performance and low-latency data communication requirements of multi-cluster systems. The CHI protocol is specifically designed to support efficient communication between multiple clusters, providing better bandwidth and latency performance between different clusters, making it suitable for complex multi-processor system architectures. Its flexible architecture allows CHI to effectively manage cross-cluster data sharing and consistency maintenance, ensuring smooth collaboration between clusters. Therefore, implementing the conversion between ACE and CHI is particularly important in modern processor design. By implementing this conversion, processors can seamlessly switch between different workloads and application scenarios, fully leveraging the advantages of the ACE protocol within the cluster, while seamlessly switching to the CHI protocol when cross-cluster communication is required to ensure data consistency and efficient transmission. However, current processor cache subsystem designs have not yet adequately implemented the conversion from the ACE protocol to the CHI protocol. This gap limits the performance improvement of multi-cluster systems and hinders the realization of efficient multi-cluster interconnection.
[0030] Based on this, embodiments of this disclosure provide a caching subsystem, see [link to relevant documentation]. Figure 1 , Figure 1 This is a partial structural diagram of a caching subsystem according to an exemplary embodiment. The caching subsystem 100 may include:
[0031] Sniffing request queue 110 is used to store first sniffing requests from the interconnect bus; the first processor is any processor in the multiprocessor system, and the second processor is any processor in the multiprocessor system other than the first processor; the second processor is connected to the first processor via the interconnect bus.
[0032] The conflict checking circuit 120, connected to the sniffing request queue 110, is used to perform address conflict checking on the first sniffing request based on at least one write request from the first processor.
[0033] The data forwarding circuit 130 is connected to the conflict checking circuit 120 and the sniffing request queue 110. It is used to determine whether the target write request meets the data forwarding condition if there is an address conflict between the target write request and the first sniffing request in at least one write request. If the target write request meets the data forwarding condition, the request data of the target write request is passed to the first sniffing request.
[0034] It should be noted that the cache subsystem shown in this embodiment can be applied to a multiprocessor system, which may include multiple processors, and each processor includes a cache subsystem. Here, the first processor can be any processor in the multiprocessor system, and the second processor can be any processor in the multiple processor system other than the first processor. The second processor is connected to the first processor via an interconnect bus.
[0035] The caching subsystem may include a sniffing request queue, a conflict checking circuit, and a data forwarding circuit.
[0036] A sniffing request queue is used to receive at least one first sniffing request from the interconnect bus and to store at least one first sniffing request.
[0037] Here, the first sniffing request is a sniffing request from the interconnect bus, and the first sniffing request can be used to request the first data in the cache of the first processor.
[0038] The first sniffing request is sent by the interconnect bus to the first processor after receiving a data processing request from the second processor. It can be understood that the second processor can send a data processing request to the interconnect bus, and the interconnect bus, based on this request, can discover that the data requested by the data processing request is stored in the cache of the first processor. In this case, the interconnect bus can send the first sniffing request to the first processor to request the first data in the cache of the first processor in the multiprocessor system.
[0039] It should be noted that each processor can include a cache, which stores data accessible to the processor. A processor's cache can include multiple cache lines, which can be used to store data copied from memory and record the state of that data. In a multiprocessor system, the caches of the first and second processors can contain the same cache lines, but the data stored in the same cache lines in both processors must be identical. Furthermore, to maintain data consistency across the caches of multiple processors in a multiprocessor system, when any processor performs a write operation on a cache line, it must ensure that the cache line exists only in its own cache at the time of the write operation, and is not present in the caches of other processors; or, it must ensure that the state of the cache line in other processors is invalidated before the write operation.
[0040] If the data requested by the second processor is stored in the cache of the first processor, the interconnect bus can send a first sniffing request to the first processor to request the first data in the cache of the first processor, and then send the first data to the second processor so that the second processor can perform the corresponding processing.
[0041] The conflict checking circuit can be connected to the sniffing request queue to read the first sniffing request in the sniffing request queue and perform address conflict checking on the first sniffing request based on at least one write request from the first processor.
[0042] Here, the write request from the first processor can be a write request that the first processor is prepared to issue via the interconnect bus. In some embodiments, the write request can be a write request from the second-level cache of the first processor.
[0043] It should be noted that the cache of the first processor may include a level 1 cache and a level 2 cache. Write requests from the first processor may include write requests from the level 1 cache and write requests from the level 2 cache. Write requests from the level 1 cache are used to request that requested data be written back to the level 2 cache; the requested data will not be retained in the level 1 cache. Write requests from the level 2 cache are used to request that requested data be written back to memory via the interconnect bus; the requested data will not be retained in the level 2 cache.
[0044] The sniffing request queue of the first processor can store multiple first sniffing requests. The conflict checking circuit can read the first sniffing requests in the sniffing request queue in sequence, and perform address conflict checking on the first sniffing requests based on at least one write request from the first processor, so as to determine whether there is an address conflict between the first sniffing request and the write request of the first processor.
[0045] It should be noted that if the address of the first data requested by the first sniffing request is the same as the address of the data requested by the write request, it can be determined that there is an address conflict between the first sniffing request and the first processor's write request. If the address of the first data requested by the first sniffing request is different from the address of the data requested by the write request, it can be determined that there is no address conflict between the first sniffing request and the first processor's write request.
[0046] In some embodiments, the conflict checking circuitry can perform address conflict checks on all requests that the first processor needs to process. In one example, the conflict checking circuitry can perform address conflict checks on read requests from the first processor's kernel, write requests from the first processor's kernel, second sniffing requests from the first processor's L2 cache, write requests being processed in the first processor's bus interaction unit, and first sniffing requests from the second processor.
[0047] The data forwarding circuit can be connected to the conflict checking circuit and the sniffing request queue. When the conflict checking circuit determines that there is a target write request in at least one write request that conflicts with the address of the first sniffing request, it determines whether the target write request meets the data forwarding condition based on the storage location of the target write request. If it is determined that the target write request meets the data forwarding condition, the request data of the write request is directly passed to the first sniffing request, so that the first sniffing request does not need to wait for the target write request to be executed before it is executed.
[0048] In this embodiment, the processor's cache subsystem may include a sniffing request queue, a conflict checking circuit, and a data forwarding circuit. The conflict checking circuit performs address conflict checks on at least one write request within the first processor and a first sniffing request from the interconnect bus in the sniffing request queue. If at least one write request has a target write request that conflicts with the address of the first sniffing request, the data forwarding circuit determines whether the target write request meets the data forwarding condition. If the target write request meets the data forwarding condition, its request data is forwarded to the first sniffing request without waiting for the target write request to complete before executing the first sniffing request. This maintains data consistency among multiple processors, enables the first processor to respond quickly to the first sniffing request, effectively reduces communication latency across processors, achieves efficient interconnection between multiple processors in a multiprocessor system, and improves the performance of the multiprocessor system.
[0049] In some embodiments, such as Figure 1 As shown, the caching subsystem also includes:
[0050] Write request queue 140 is used to store at least one write request and the request data of the write request; the write requests stored in write request queue 140 are write requests to be executed or are being executed.
[0051] Write request buffer 150 is used to store at least one write request and the request data of the write request; the write requests stored in write request buffer 150 are write requests to be transmitted to the write request queue.
[0052] The sniff buffer 160 is also used to store at least one write request and the request data of the write request; the write request stored in the sniff buffer 160 is a write request to be transmitted to the write request buffer.
[0053] The data forwarding circuit 130 is connected to the write request queue 140, the write request buffer 150, and the sniffing buffer 160, and is used to forward the request data of the target write request that meets the data forwarding conditions in the write request queue 140, the write request buffer 150, or the sniffing buffer 160 to the first sniffing request.
[0054] In this embodiment of the disclosure, the caching subsystem may include a write request queue, a write request buffer, and a sniffing buffer.
[0055] A write request queue can be used to store at least one write request and the request data for that write request. The write requests stored in the write request queue can be write requests that are pending or currently being executed.
[0056] In some embodiments, a write request to be executed can be understood as a write request that is about to be sent through the interconnect bus. In some embodiments, a write request being executed can be understood as a write request that has been sent through the interconnect bus but for which no response has yet been received.
[0057] A write request buffer can be used to store at least one write request and the request data for that write request. The write requests stored in the write request buffer can be write requests that are to be transferred to the write request queue.
[0058] It should be noted that, since the write request queue can only store a limited number of write requests and the data of those requests, when the write request queue is full, write requests can be temporarily stored in the write request buffer. This allows the write requests in the write request buffer to be transferred to the write request queue to await issuance when there is free space in the write request queue.
[0059] The sniff buffer can be used to store at least one write request and the request data for the write request. The write request stored in the sniff buffer is the write request to be transferred to the write request buffer.
[0060] A target write request that meets the data forwarding condition can be a target write request whose requested data is stored in a write request queue, write request buffer, or sniff buffer.
[0061] It should be noted that during the data forwarding process using the data forwarding circuit, the data sources for forwarding mainly include three sources: write request data in the write request queue, write request data in the write request buffer, and write request data in the sniffing buffer. Therefore, the data forwarding circuit can be connected to the write request queue, write request buffer, and sniffing buffer to pass the target write request request data that meets the data forwarding conditions in the write request queue, write request buffer, or sniffing buffer to the first sniffing request.
[0062] In some embodiments, if it is determined that the target write request meets the data forwarding condition and the target write request is stored in the sniffing buffer, the data forwarding circuit can obtain the request data of the target write request from the sniffing buffer and pass it to the first sniffing request.
[0063] In some embodiments, if it is determined that the target write request meets the data forwarding condition and the target write request is stored in the write request buffer, the data forwarding circuit can obtain the request data of the target write request from the write request buffer and pass it to the first sniffing request.
[0064] In some embodiments, if it is determined that the target write request meets the data forwarding condition and the target write request is stored in the write request queue, the data forwarding circuit can obtain the request data of the target write request from the write request queue and pass it to the first sniffing request.
[0065] In this embodiment of the disclosure, by connecting the data forwarding circuit to the write request queue, the write request buffer, and the sniffing buffer, the request data of the target write request that meets the data forwarding condition in the write request queue, the write request buffer, or the sniffing buffer is passed to the first sniffing request when the target write request meets the data forwarding condition. This enables data forwarding of the request data of the target write request that meets the data forwarding condition inside the first processor, thereby enabling the first processor to respond quickly to the first sniffing request initiated by the second processor and effectively shortening the communication latency of cross-processor communication.
[0066] This disclosure provides an embodiment of a data processing method, see [link to relevant documentation]. Figure 2 , Figure 2 This is a flowchart illustrating a data processing method according to an exemplary embodiment. Figure 1 The data processing method may include the following steps:
[0067] Step S201: In response to the first sniffing request in the sniffing request queue, perform an address conflict check on the first sniffing request based on at least one write request from the first processor; wherein, the first sniffing request is a sniffing request from the interconnect bus, and the second processor is connected to the first processor through the interconnect bus; the first processor is any processor in the multiprocessor system, and the second processor is any processor in the multiprocessor system other than the first processor.
[0068] Step S202: If at least one write request has an address conflict with the first sniffing request, determine whether the target write request meets the data forwarding condition.
[0069] Step S203: If the target write request meets the data forwarding condition, the request data of the target write request is passed to the first sniffing request in the sniffing request queue.
[0070] It should be noted that the data processing method shown in the embodiments of this disclosure can be applied to the cache subsystem of a multiprocessor system. The multiprocessor system may include multiple processors, and each processor includes a cache subsystem. In the embodiments of this disclosure, the first processor may be any processor in the multiprocessor system, and the second processor may be any processor in the multiprocessor system other than the first processor. The second processor is connected to the first processor via an interconnect bus.
[0071] In step S201, within the first processor, in response to a first sniffing request in the sniffing request queue, the first processor can perform an address conflict check on the first sniffing request based on at least one write request within the first processor.
[0072] Here, the first sniffing request originates from the interconnect bus and can be used to request the acquisition of first data from the cache of the first processor. The sniffing request queue can store at least one first sniffing request issued by the interconnect bus.
[0073] Here, the first sniffing request is sent by the interconnect bus to the first processor after receiving a data processing request from the second processor. It can be understood that the second processor can send a data processing request to the interconnect bus, and the interconnect bus, based on this request, can detect that the first processor's cache contains the data requested by the data processing request. In this case, the interconnect bus can send the first sniffing request to the first processor to request access to the first data in the cache of the first processor in the multiprocessor system. It should be noted that each processor can include a cache, which stores data accessible to the processor. Typically, the first processor can copy the data it needs to access from the shared memory of multiple processors to its own cache for processing.
[0074] A processor's cache can include multiple cache lines, which can be used to store data copied by the processor from memory and record the status of that data.
[0075] In a multiprocessor system, the caches of the first and second processors can contain the same cache lines, but the data stored in the same cache lines in both processors must be identical. Furthermore, to maintain data consistency across the caches of multiple processors in a multiprocessor system, when any processor performs a write operation on a cache line, it must ensure that the cache line exists only in its own cache at the time of the write operation, and is not present in the caches of other processors; or, it must ensure that the cache line in other processors is invalidated before the write operation is performed.
[0076] At least one write request within the first processor can be a write request that the first processor is prepared to issue via the interconnect bus, and the write request can be a write request from the second-level cache of the first processor.
[0077] It should be noted that the cache of the first processor may include a level 1 cache and a level 2 cache. Write requests from the first processor may include write requests from the level 1 cache and write requests from the level 2 cache. Write requests from the level 1 cache are used to request that requested data be written back to the level 2 cache; the requested data will not be retained in the level 1 cache. Write requests from the level 2 cache are used to request that requested data be written back to memory via the interconnect bus; the requested data will not be retained in the level 2 cache.
[0078] In some embodiments, the first processor may perform address conflict checks on all requests that need to be processed by the first processor. The requests that need to be processed by the first processor may include, but are not limited to, read requests from the kernel of the first processor, write requests from the kernel of the first processor, second sniffing requests from the second-level cache of the first processor, write requests being processed in the bus interaction unit of the first processor, and first sniffing requests from the interconnect bus.
[0079] In some embodiments, address conflict checking of the first sniffing request can be implemented by the conflict checking circuit of the first processor.
[0080] In step S202, if at least one write request contains a target write request that conflicts with the address of the first sniffing request, the first processor can determine whether the storage location of the target write request meets the data forwarding condition, so as to determine whether to perform data forwarding processing on the request data of the target write request.
[0081] It's important to note that if a target write request and the first sniffing request have address conflicts, according to the ACE protocol, the target write request will be processed first, and only after the target write request is processed will the first sniffing request be processed. However, according to the CHI protocol, the first sniffing request will be processed first. It is precisely because of these differences between the ACE and CHI protocols that a system deadlock can easily occur when there is an address conflict between the target write request and the first sniffing request, thus preventing the system from proceeding.
[0082] To avoid system deadlock, the first processor can determine whether the request data of the target write request can be passed from the temporary storage location to the first sniffing request. If the request data can be passed to the first sniffing request, the target write request meets the data forwarding condition, and thus, data forwarding processing can be performed on the target write request data when there is an address conflict between the target write request and the first sniffing request. If the request data cannot be passed to the first sniffing request, the target write request does not meet the data forwarding condition, and no data forwarding processing is required.
[0083] In some embodiments, if the request data of the target write request is stored in a write request queue, a write request buffer, or a sniffing buffer, the request data can be passed to the first sniffing request through a data forwarding circuit, and the target write request satisfies the data forwarding condition.
[0084] In step S203, if the target write request meets the data forwarding condition, the request data of the target write request can be passed to the first sniffing request in the sniffing request queue, so that the first sniffing request does not need to wait for the target write request to be completed before it is executed.
[0085] In some embodiments, a data forwarding circuit can be used to implement data forwarding processing of the request data for the target write request.
[0086] This embodiment of the disclosure performs address conflict checks on at least one write request within the first processor and a first sniffing request from the interconnect bus in the sniffing request queue. If at least one write request has a target write request that conflicts with the address of the first sniffing request, it determines whether the target write request meets the data forwarding condition. If the target write request meets the data forwarding condition, the data forwarding circuit is used to pass the request data of the target write request to the first sniffing request, without waiting for the target write request to be completed before executing the first sniffing request. In this way, data consistency between multiple processors is guaranteed, and the first processor can respond quickly to the first sniffing request, effectively shortening the communication latency of cross-processor communication, realizing efficient interconnection between multiple processors in a multiprocessor system, and improving the performance of the multiprocessor system.
[0087] In some embodiments, if the target write request meets the data forwarding condition, the request data of the target write request is passed to the first sniffing request in the sniffing request queue, including one of the following:
[0088] If the target write request is stored in the sniff buffer and the target write request meets the data forwarding condition, retrieve the request data of the target write request from the sniff buffer and pass it to the first sniff request.
[0089] If the target write request is stored in the write request buffer, and the target write request meets the data forwarding condition, retrieve the request data of the target write request from the write request buffer and pass it to the first sniffing request;
[0090] If the target write request is stored in the write request queue and the target write request meets the data forwarding condition, retrieve the request data of the target write request from the write request queue and pass it to the first sniffing request.
[0091] It should be noted that within the first processor, the target write request and the request data of the target write request can be temporarily stored in the sniff buffer, the write request buffer, or the write request queue.
[0092] A write request queue can be used to store write requests that are pending or in progress, along with their request data. In some embodiments, a write request pending execution can be understood as a write request that is about to be sent via the interconnect bus. In some embodiments, a write request in progress can be understood as a write request that has been sent via the interconnect bus but for which no response has yet been received.
[0093] The write request buffer can be used to store write requests to be transferred to the write request queue, as well as the request data for those write requests.
[0094] The sniff buffer can be used to store write requests that are to be transferred to the write request buffer.
[0095] If it is determined that a target write request that conflicts with the address of the first sniffing request meets the data forwarding condition, and the target write request is stored in the sniffing buffer, the request data of the target write request can be obtained from the sniffing buffer and passed to the first sniffing request.
[0096] If it is determined that a target write request that conflicts with the address of the first sniffing request meets the data forwarding condition, and the target write request is stored in the write request buffer, the request data of the target write request can be obtained from the write request buffer and passed to the first sniffing request.
[0097] If a target write request that conflicts with the address of the first sniffing request is determined to meet the data forwarding condition, and the target write request is stored in the write request queue, the request data of the target write request can be obtained from the write request queue and passed to the first sniffing request.
[0098] This embodiment of the present disclosure, when it is determined that the target write request meets the data forwarding condition, obtains the request data of the target write request from the storage location of the target write request according to the storage location of the target write request, and passes the request data to the first sniffing request, thereby realizing the data forwarding of the request data of the target write request that meets the data forwarding condition inside the first processor, thereby realizing the rapid response of the first processor to the first sniffing request initiated by the second processor, and effectively shortening the communication latency of cross-processor communication.
[0099] In some embodiments, the method further includes one of the following:
[0100] After completing the transmission of the request data for the target write request in the write request queue, if the target write request has not been sent, cancel the sending of the target write request to the interconnect bus.
[0101] After completing the transmission of the target write request data to the write request queue, if the target write request has already been sent, delete the target write request and its request data upon receiving the response to the target write request.
[0102] In this embodiment, if the target write request is stored in the write request queue, and the request data of the target write request in the write request queue has already been passed to the first sniffing request, the target write request and its request data need to be deleted from the cache subsystem of the first processor. It should be noted that if the request data of the target write request in the write request queue has already been passed to the first sniffing request, the cache subsystem of the first processor will be considered to no longer store the request data. In this case, if the target write request in the write request queue is not processed, the target write request may be issued, potentially causing a failure in the multiprocessor system.
[0103] Based on this, after completing the transmission of the request data for the target write request in the write request queue, it can be determined whether the target write request has been executed. If the target write request has not been executed, it can be deleted from the write request queue to cancel sending the target write request to the interconnect bus. If the target write request has already been sent, it can wait for the interconnect bus to return a response to the target write request, and continue with subsequent processing after receiving the response.
[0104] Thus, after the request data for the target write request in the write request queue is transmitted, different processing is applied to the target write request depending on whether the target write request has been issued in the write request queue, so as to eliminate the adverse effects caused by the continued execution of the target write request.
[0105] In some embodiments, the method further includes:
[0106] Upon completion of the transmission of the request data for the target write request in the sniff buffer, a cancellation flag is added to the target write request in the sniff buffer; the cancellation flag is used to indicate the cancellation of sending the target write request to the interconnect bus.
[0107] The target write request marked with the cancel tag will continue to be transmitted to the write request queue;
[0108] Cancel the target write request that has been added to the write request queue with the cancellation mark.
[0109] In this embodiment of the disclosure, when the target write request is stored in the sniffing buffer and the request data of the target write request in the sniffing buffer has been passed to the first sniffing request, it is necessary to delete the target write request and the request data of the target write request in the cache subsystem of the first processor.
[0110] To minimize the impact on the internal workings of the first processor, after the request data for the target write request in the sniff buffer is transmitted, a cancellation flag can be added to the target write request in the sniff buffer, and the transmission of the target write request with the cancellation flag can continue.
[0111] Here, the cancellation flag can be used to indicate the cancellation of sending a target write request to the interconnect bus. If a target write request is marked with a cancellation flag, it means that the target write request has been cancelled and sent to the interconnect bus.
[0112] Once a target write request marked with a cancellation flag is transmitted to the write request queue, it can be deleted from the write request queue to cancel sending the target write request to the interconnect bus.
[0113] Thus, after the transmission of the target write request data to the sniff buffer is completed, a cancellation flag can be added to the target write request in the sniff buffer, and the target write request with the cancellation flag added can continue to be transmitted. After the target write request is transmitted to the write request queue, the target write request is deleted from the write request queue. This can eliminate the adverse effects caused by the issuance of the target write request, and the target write request can be processed in the first processor, reducing the impact on the internal workings of the first processor.
[0114] In some embodiments, the method further includes:
[0115] After completing the transmission of the request data for the target write request in the write request queue, a cancellation flag is added to the target write request within the target write request; the cancellation flag is used to indicate the cancellation of sending the target write request to the interconnect bus.
[0116] The target write request marked with the cancel tag will continue to be transmitted to the write request queue;
[0117] Cancel the target write request that has been added to the write request queue with the cancellation mark.
[0118] In this embodiment of the disclosure, if the target write request is stored in the write request buffer and the request data of the target write request in the write request buffer has been passed to the first sniffing request, the target write request and the request data of the target write request need to be deleted in the cache subsystem of the first processor.
[0119] To minimize the impact on the internal workings of the first processor, after completing the transmission of the request data for the target write request in the write request buffer, a cancellation flag can be added to the target write request in the write request buffer, and the transmission of the target write request with the cancellation flag added can continue.
[0120] Here, the cancellation flag can be used to indicate the cancellation of sending a target write request to the interconnect bus. If a target write request is marked with a cancellation flag, it means that the target write request has been cancelled and sent to the interconnect bus.
[0121] Once a target write request marked with a cancellation flag is transmitted to the write request queue, it can be deleted from the write request queue to cancel sending the target write request to the interconnect bus.
[0122] Thus, after the transmission of the target write request data to the write request buffer is completed, a cancellation flag can be added to the target write request in the write request buffer, and the target write request with the cancellation flag added can continue to be transmitted. After the target write request is transmitted to the write request queue, the target write request is deleted from the write request queue. This can eliminate the adverse effects caused by the issuance of the target write request, and the target write request can be processed in the first processor, reducing the impact on the internal workings of the first processor.
[0123] In some embodiments, the method further includes, prior to performing an address conflict check on the first sniffing request:
[0124] Obtain request-related information for at least one write request and request-related information for the first sniffing request; the request-related information is used to indicate at least the request time, request access address, and / or request source of the write request;
[0125] Based on the request information of at least one write request and the request information of the first sniffing request, determine whether the at least one write request and the first sniffing request meet the conflict conditions.
[0126] If a write request and the first sniffing request conflict, the first sniffing request will be processed first.
[0127] In this embodiment of the disclosure, in order to realize the interconnection between multiprocessor systems, when receiving at least one write request from the first processor and a first sniffing request from the interconnect bus, request-related information of at least one write request and request-related information of the first sniffing request are obtained, and based on the request-related information of at least one write request and request-related information of the first sniffing request, it is determined whether the at least one write request and the first sniffing request meet the conflict condition.
[0128] Here, the request-related information can at least indicate the time of the write request, the access address requested, and / or the source of the request.
[0129] In some embodiments, it can be determined whether at least one write request and the first sniffing request meet the conflict condition based on the request time and request access address of at least one write request, and the request time and request access address of the first sniffing request.
[0130] The first sniffing request and the write request can conflict if they access the same address simultaneously. For example, if the first sniffing request and the write request target the same address at the same time, then there is an address access conflict between them. To maintain cache consistency, the first sniffing request and the write request cannot be responded to at the same time.
[0131] If it is determined that the write request and the first sniffing request meet the conflict conditions, the first sniffing request can be processed first, and the write request can be processed after the first sniffing request is completed.
[0132] It should be noted that, when a write request and a first sniff request conflict, the ACE protocol stipulates that the write request within the first processor should be processed first, followed by the first sniff request from the interconnect bus. However, in order to support the CHI protocol and realize the interconnection of multiprocessor systems based on the CHI protocol, the embodiments of this disclosure can prioritize the processing of the first sniff request from the interconnect bus. In this way, the conversion from the ACE protocol to the CHI protocol can be realized in the multiprocessor system under the aforementioned conflict conditions.
[0133] This embodiment of the disclosure can use request-related information of at least one write request and request-related information of a first sniffing request to determine whether at least one write request and the first sniffing request meet conflict conditions. If the write request and the first sniffing request meet the conflict conditions, the first sniffing request is processed first. This can maintain cache consistency even when the write request and the first sniffing request meet the conflict conditions, and can also realize the conversion from ACE protocol to CHI protocol, thereby realizing the interconnection of multiprocessor systems. This is beneficial for the first processor to respond quickly to the first sniffing request from the interconnect bus and effectively shortens the communication latency between different processors in cross-processor systems.
[0134] In some embodiments, if a write request and a first sniffing request meet a conflict condition, the request-related information of the write request indicates one of the following:
[0135] The write request is a write request from the kernel of the first processor, and the request time and access address of the write request are the same as those of the first sniffing request.
[0136] The write request is the write request being processed within the first processor, and the request time and access address of the write request are the same as those of the first sniffing request.
[0137] A write request is a write request stored in the sniff buffer, and the request time and access address of the write request are the same as the request time of the first sniff request.
[0138] In this embodiment of the disclosure, if the request-related information of the write request indicates that the write request is a write request from the kernel of the first processor, and the request time and request access address of the write request are the same as those of the first sniffing request, it can be determined that the write request and the first sniffing request meet the conflict conditions. In this case, the first sniffing request can be processed first, and the write request can be processed after the first sniffing request has been processed.
[0139] It should be noted that, regarding address access conflicts between a write request from the kernel of the first processor and a first sniff request from the interconnect bus at the same address at the same time, according to the ACE protocol, the write request from the kernel of the first processor is usually processed first, followed by the first sniff request from the interconnect bus. In order to support the CHI protocol, this embodiment of the disclosure can process the first sniff request from the interconnect bus first, and then process the write request from the kernel of the first processor after the first sniff request has been processed.
[0140] If the request information of the write request indicates that the write request is a write request being processed in the first processor, and the request time and access address of the write request are the same as those of the first sniffing request, it can be determined that the write request and the first sniffing request meet the conflict condition.
[0141] It should be noted that, regarding address access conflicts between a write request being processed by the first processor at the same address and a first sniffing request from the interconnect bus at the same time, according to the ACE protocol, the first sniffing request from the interconnect bus is usually processed only after the write request being processed by the first processor has been completed. In this embodiment, as long as the write request being processed by the first processor has not yet received a response from the interconnect bus, the first sniffing request from the interconnect bus can be processed first, and the write request can be processed only after the first sniffing request has been completed.
[0142] If the request information of the write request indicates that the write request is a write request stored in the sniff buffer, and the request time and access address of the write request are the same as those of the first sniff request, it can be determined that the write request and the first sniff request meet the conflict condition.
[0143] It should be noted that, in the event of an address access conflict between a write request stored in the sniff buffer and a first sniff request from the interconnect bus at the same time and address, the first sniff request from the interconnect bus can be processed first, and the write request stored in the sniff buffer can be processed only after the first sniff request has been processed.
[0144] In this embodiment of the disclosure, when it is determined from the request-related information of the write request and the request-related information of the first sniffing request that the write request and the first sniffing request belong to any of the three situations mentioned above, it can be determined that there is an address access conflict between the write request and the first sniffing request, that is, the write request and the first sniffing request meet the conflict condition. By prioritizing the processing of the first sniffing request, it is possible to maintain buffer consistency and realize the conversion from the ACE protocol to the CHI protocol, thereby achieving bidirectional support for the ACE protocol and the CHI protocol within the first processor and between the first processor and the second processor.
[0145] In some embodiments, the method further includes: if the target write request does not meet the data forwarding condition, creating a buffer entry corresponding to the first sniffing request in the sniffing buffer.
[0146] In this embodiment of the disclosure, if it is determined that the target write request that conflicts with the address of the first sniffing request does not meet the data forwarding condition, the request data of the target write request may not be passed to the first sniffing request. Instead, a buffer table entry corresponding to the first sniffing request may be created in the sniffing buffer, and the first sniffing request may be stored in the sniffing buffer for processing.
[0147] It's important to note that in the processor's buffer, a buffer table entry is the basic unit for storing actual data or instruction information. The design and storage method of buffer table entries directly affect the efficiency and performance of the cache. An efficient buffer table entry design can reduce cache misses and improve data access speed.
[0148] It is worth noting that after the sniffing buffer creates the buffer table entry corresponding to the first sniffing request, the buffer table entry can record the entire lifecycle of the first sniffing request within the buffer subsystem.
[0149] In this embodiment of the disclosure, if it is determined that the target write request that conflicts with the address of the first sniffing request does not meet the data forwarding condition, that is, the request data of the target write request cannot be forwarded to the first sniffing request, a buffer table entry corresponding to the first sniffing request is created in the sniffing buffer, the first sniffing request is stored in the sniffing buffer, and the first sniffing request is processed after the target write request is processed.
[0150] This disclosure also provides a multiprocessor system, which may include:
[0151] Multiple processors, which are interconnected via an interconnect bus;
[0152] Each of the multiple processors includes a cache subsystem as described in one or more of the above-described technical solutions.
[0153] In this embodiment of the disclosure, the multiprocessor system may include multiple processors connected to each other via an interconnect bus.
[0154] Each processor may include a cache subsystem, which includes a sniffing request queue, a conflict checking circuit, and a data forwarding circuit. Each processor's cache subsystem can be used to execute the data processing methods shown in one or more of the above technical solutions. In this way, data consistency between multiple processors can be maintained, and the first processor can respond quickly to the first sniffing request. This effectively shortens the communication latency of cross-processor communication, realizes efficient interconnection between multiple processors in a multiprocessor system, and improves the performance of the multiprocessor system.
[0155] In some embodiments, such as Figure 3 As shown, Figure 3This is a schematic diagram of the overall architecture of a caching subsystem according to an exemplary embodiment. The data forwarding circuit can be located between the sniffing buffer and the external cluster sniffing request queue. When a sniffing request from the external cluster enters the sniffing buffer, it will first check for address conflicts. If there are any conflicts, the data forwarding circuit will be used to forward the data from the conflicting request to the external cluster sniffing request. The data will be sent from the conflicting request to the external cluster sniffing request queue.
[0156] like Figure 4 As shown, Figure 4 This is a schematic diagram of a sniffing buffer architecture according to an exemplary embodiment. Address conflict checks on sniffing requests from external clusters entering the sniffing buffer can be performed by a sniffing buffer circuit unit. This sniffing buffer circuit unit can receive read / write requests from the core, sniffing requests from other clusters, and sniffing requests from the L2 cache, and perform address conflict checks. If an address conflict exists but data forwarding is not required, an entry can be created in the sniffing buffer for sniffing requests from other clusters. If an address conflict exists and data forwarding is required, no entry needs to be created in the sniffing buffer for sniffing requests from other clusters; the request will directly wait in the external cluster's sniffing request queue for data forwarding.
[0157] It is worth noting that each request is maintained by a table entry, and the entire lifecycle of the request in the consistency maintenance unit after the table entry is created is contained within the table entry.
[0158] In some embodiments, to achieve the conversion from the ACE protocol to the CHI protocol, the address conflicts that need to be checked in the sniffing buffer include the following categories:
[0159] A. Write requests from the core at the same address at the same time; B. Sniffing requests from other clusters.
[0160] B. Sniffing requests from the second-level cache and sniffing requests from other clusters at the same time and address;
[0161] C. At the same time, sniffing requests from other clusters and write requests being processed in external interaction units originate from the same address;
[0162] D. Sniffing requests from other clusters and write requests in the sniffing buffer table entries at the same address at the same time;
[0163] It should be noted that, for the two types of address conflicts A and C mentioned above, the ACE protocol stipulates that write requests should be processed first before sniffing requests from other clusters are processed. However, in order to support the CHI protocol and realize multi-cluster interconnection based on the CHI protocol, this embodiment of the disclosure can choose to let sniffing requests from other clusters be processed first for these two types of address conflicts, and then process the two types of requests that conflict with them after they are processed.
[0164] In some embodiments, to maintain cache consistency and support two protocol specifications, the specific solutions for these types of address conflicts are as follows:
[0165] (a) At the same time, write request B from the core and sniffing request from other clusters are processed at the same address. Sniffing request from other clusters is processed first.
[0166] (b) At the same time, sniffing requests from the second-level cache and sniffing requests from other clusters at the same address will be processed first. However, the data write-back caused by the sniffing request will not be processed and will have to wait for the sniffing requests from other clusters to be processed.
[0167] (c) At the same time, sniffing requests from other clusters and write requests being processed in external interaction units will be processed first, provided that the write request has not yet received a response from the interconnect bus. Sniffing requests from other clusters will be processed first, and then the write request will be processed accordingly.
[0168] (d) At the same time, sniffing requests from the external cluster and write requests from the sniffing buffer table entries from the same address should be processed first, while the write requests should be processed after the sniffing requests have been processed.
[0169] To ensure that sniffing requests from other clusters receive the first data, a forward data path needs to be added within the cluster. This means that the data needed by the sniffing request is sent from the write request buffer to the sniffing request location, such as... Figure 5 As shown, Figure 5 This is a flowchart illustrating a data processing method according to an exemplary embodiment. Figure 2 The method includes:
[0170] Step S501: Receive sniffing request sent by the interconnect bus.
[0171] In step S502, the sniff buffer circuit unit checks for address conflict requests between sniff requests and write requests.
[0172] In step S503, the data forwarding circuit determines whether forwarding data is required based on the type of the write request.
[0173] In step S504, the data forwarding circuit forwards the first data to the sniffing request initiated by other clusters and updates the cache state.
[0174] like Figure 6 As shown, Figure 6 This is a schematic diagram illustrating a data forwarding process according to an exemplary embodiment. The write buffer stores write requests and write data to be sent to the write request queue for initiating an external network. The write request queue stores write requests and write data about to be initiated to the external network, as well as write requests and write data that are being processed or have begun processing but have not yet been completed.
[0175] The data sources for forwarding data are threefold: write data in the write request buffer, write data in the write request queue, and write data in the sniff buffer table. Sniff requests from the external cluster will undergo address conflict checks before creating an entry in the sniff buffer. If an address conflict is found with a write request entry in the write request buffer, write request queue, or sniff buffer, the conflicting write request will forward the data to the sniff request entry of the external cluster, provided that the data forwarding condition is met. At this point, the external cluster sniff request that has received the forwarded data will not create another entry in the sniff buffer.
[0176] Data forwarding requests require processing after data forwarding. If data is forwarded from an entry in the sniffing buffer, the request in the entry will be marked with a cancellation flag after the external cluster's sniffing request is completed, and then sent to the write request buffer and write request queue. In the write request queue, the request is cancelled, and the request ends. If data is forwarded from the write request buffer, the request in the write request buffer will be marked with a cancellation flag after the external cluster's sniffing request is completed, and then sent to the write request queue. In the write request queue, the request is cancelled, and the request ends. If data is forwarded from the write request queue, the request in the write request queue must wait for the external cluster's sniffing request to complete before processing. If the request has not yet been sent to the external cluster interconnect bus, it is cancelled; if it has already been sent, it waits for the external cluster interconnect bus to return a response.
[0177] Within the cluster, this solution achieves bidirectional support for the ACE and CHI protocols by handling address conflicts in specific scenarios and forwarding data, thus providing some assistance for realizing multi-cluster interconnection based on the CHI protocol.
[0178] Regarding the apparatus in the above embodiments, the specific manner in which each module performs its operation has been described in detail in the embodiments related to the method, and will not be elaborated upon here.
[0179] This disclosure also proposes a non-transitory computer-readable storage medium that, when the instructions in the storage medium are executed by a processor of a multiprocessor system, enables the processor to perform any of the data processing methods described above in this disclosure.
[0180] This disclosure provides a computer program product comprising a computer program or executable instructions stored in a computer-readable storage medium. A processor of a computer device reads the computer program or executable instructions from the computer-readable storage medium and executes the computer program or executable instructions, causing the computer device to perform any of the data processing methods described in this disclosure.
[0181] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This disclosure is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the following claims.
[0182] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this disclosure is limited only by the appended claims.
Claims
1. A data processing method, characterized in that, The method includes: In response to a first sniffing request in the sniffing request queue, an address conflict check is performed on the first sniffing request based on at least one write request from within the first processor; wherein the first sniffing request is a sniffing request from the interconnect bus, and the first sniffing request is sent by the interconnect bus after receiving a data processing request from the second processor; the second processor is connected to the first processor via the interconnect bus; the first processor is any processor in a multiprocessor system, and the second processor is any processor in the multiprocessor system other than the first processor; If there is an address conflict between the target write request and the first sniffing request in the at least one write request, determine whether the target write request meets the data forwarding condition; If the target write request satisfies the data forwarding condition, the request data of the target write request is passed to the first sniffing request in the sniffing request queue.
2. The method according to claim 1, characterized in that, If the target write request satisfies the data forwarding condition, the request data of the target write request is passed to the first sniffing request in the sniffing request queue, including one of the following: If the target write request is stored in the sniffing buffer and the target write request satisfies the data forwarding condition, the request data of the target write request is obtained from the sniffing buffer and passed to the first sniffing request; If the target write request is stored in the write request buffer and the target write request satisfies the data forwarding condition, the request data of the target write request is obtained from the write request buffer and passed to the first sniffing request. If the target write request is stored in the write request queue and the target write request satisfies the data forwarding condition, the request data of the target write request is obtained from the write request queue and passed to the first sniffing request.
3. The method according to claim 2, wherein, The method also includes one of the following: After completing the transmission of the request data for the target write request in the write request queue, if the target write request has not been sent, the transmission of the target write request to the interconnect bus is cancelled. After completing the transmission of the target write request data to the write request buffer, if the target write request has already been sent, delete the target write request and its request data upon receiving the response to the target write request.
4. The method according to claim 2, wherein, The method further includes: Upon completion of the transmission of the request data for the target write request within the sniff buffer, a cancellation flag is added to the target write request within the sniff buffer; the cancellation flag is used to indicate the cancellation of sending the target write request to the interconnect bus. The target write request marked with the cancellation flag will continue to be transmitted to the write request queue; Cancel sending the target write request that has been marked with the cancellation flag in the write request queue.
5. The method according to claim 2, wherein, The method further includes: Upon completion of the transmission of request data for the target write request within the write request queue, a cancellation flag is added to the target write request within the target write request; the cancellation flag is used to indicate the cancellation of sending the target write request to the interconnect bus. The target write request marked with the cancellation flag will continue to be transmitted to the write request queue; Cancel sending the target write request that has been marked with the cancellation flag in the write request queue.
6. The method according to claim 1, characterized in that, Before performing an address conflict check on the first sniffing request, the method further includes: Obtain request-related information of the at least one write request and request-related information of the first sniffing request; the request-related information is used to indicate at least the request time, request access address and / or request source of the write request; Based on the request-related information of the at least one write request and the request-related information of the first sniffing request, determine whether the at least one write request and the first sniffing request meet the conflict conditions. If the write request and the first sniffing request meet the conflict condition, the first sniffing request shall be processed first.
7. The method according to claim 6, wherein, If the write request and the first sniffing request meet the conflict condition, the request-related information of the write request indicates one of the following: The write request is a write request from the kernel of the first processor, and the request time and access address of the write request are the same as those of the first sniffing request. The write request is a write request being processed within the first processor, and the request time and access address of the write request are the same as those of the first sniffing request. The write request is a write request stored in the sniffing buffer, and the request time and access address of the write request are the same as those of the first sniffing request.
8. The method according to claim 1, characterized in that, The method further includes: If the target write request does not meet the data forwarding condition, a buffer entry corresponding to the first sniffing request is created in the sniffing buffer.
9. A caching subsystem, characterized in that, The cache subsystem, applied to the first processor, includes: A sniffing request queue is used to store first sniffing requests from the interconnect bus, which are sent by the interconnect bus after receiving a data processing request from the second processor; the first processor is any processor in a multiprocessor system, and the second processor is any processor in the multiprocessor system other than the first processor; the second processor is connected to the first processor via the interconnect bus. A conflict checking circuit, connected to the sniffing request queue, is used to perform address conflict checking on the first sniffing request based on at least one write request from the first processor. A data forwarding circuit, connected to a conflict checking circuit and the sniffing request queue, is used to determine whether the target write request meets the data forwarding condition if there is an address conflict between the target write request and the first sniffing request in at least one write request; if the target write request meets the data forwarding condition, the request data of the target write request is passed to the first sniffing request.
10. The caching subsystem according to claim 9, characterized in that, The caching subsystem includes: A write request queue is used to store at least one write request and the request data of the write request; the write request stored in the write request queue is a write request to be executed or is being executed. A write request buffer is used to store at least one write request and the request data of the write request; the write request stored in the write request buffer is a write request to be transmitted to the write request queue. The sniffing buffer is also used to store at least one write request and the request data of the write request; the write request stored in the sniffing buffer is a write request to be transmitted to the write request buffer. The data forwarding circuit is connected to the write request queue, the write request buffer, and the sniffing buffer, and is used to forward the request data of the target write request that meets the data forwarding condition in the write request queue, the write request buffer, or the sniffing buffer to the first sniffing request.
11. A multiprocessor system, characterized in that, include: Multiple processors are connected via an interconnect bus, and each processor includes a cache subsystem as described in claim 9 or 10.