Driving circuit and display device

Abstract

The application discloses a driving circuit and a display device. The driving circuit comprises a voltage control circuit configured to provide a first voltage signal to a gate control circuit and a source driving circuit, and to provide a second voltage signal to the gate control circuit and a gate driving circuit; the gate control circuit is configured to receive the first voltage signal and the second voltage signal, and to provide a gate control signal to a gate control signal terminal; the source driving circuit is configured to provide a data signal to a data signal terminal according to the first voltage signal; the gate driving circuit is configured to provide a scanning signal to a gate line according to the second voltage signal; and a switch control circuit is coupled to the gate control signal terminal and the data signal terminal, and is configured to provide the data signal to a data signal line in response to the gate control signal.

Description

Technical Field

[0001] This invention relates to the field of display technology, and in particular to driving circuits and display devices. Background Technology

[0002] Displays such as Liquid Crystal Displays (LCDs) typically consist of multiple pixels. Each pixel may include a red subpixel, a green subpixel, and a blue subpixel. By controlling the display data corresponding to each subpixel, the display brightness of each subpixel is controlled, thereby mixing the desired colors to display a color image. Summary of the Invention

[0003] The driving circuit provided in this embodiment includes:

[0004] A voltage control circuit is configured to provide a first voltage signal to a gating control circuit and a source drive circuit, and to provide a second voltage signal to the gating control circuit and the gate drive circuit.

[0005] The gating control circuit is configured to receive the first voltage signal and the second voltage signal, and provide a gating control signal to the gating control signal terminal;

[0006] The source drive circuit is configured to provide a data signal to the data signal terminal according to the first voltage signal;

[0007] The gate drive circuit is configured to provide a scan signal to the gate line according to the second voltage signal;

[0008] A switch control circuit, coupled to the gating control signal terminal and the data signal terminal, is configured to provide the data signal to the data signal line in response to the gating control signal.

[0009] In some possible implementations, the absolute value of the first voltage signal is less than the absolute value of the second voltage signal.

[0010] In some possible implementations, the first voltage signal includes: a first level signal and a second level signal;

[0011] The second voltage signal includes: a third-level signal and a fourth-level signal;

[0012] The first level signal and the third level signal are both high level signals;

[0013] The second level signal and the fourth level signal are both low level signals.

[0014] In some possible implementations, the absolute value of the voltage level of the first level signal is less than the absolute value of the voltage level of the third level signal;

[0015] The absolute value of the voltage level of the second level signal is less than the absolute value of the voltage level of the fourth level signal.

[0016] In some possible implementations, the gating control circuit includes:

[0017] A first input circuit, coupled to a first node, is configured to provide the second level signal or the third level signal to the first node in response to a signal at a first control signal terminal.

[0018] The second input circuit, coupled to the second node, is configured to provide the first level signal or the fourth level signal to the second node in response to a signal at the first control signal terminal.

[0019] The gating output circuit, coupled to the first node and the second node, is configured to provide the signal on the first node or the signal on the second node to the gating control signal terminal in response to a signal at the second control signal terminal.

[0020] Both the first control signal terminal and the second control signal terminal are coupled to the voltage control circuit and are configured to receive the first voltage signal and the second voltage signal provided by the voltage control circuit.

[0021] In some possible implementations, the first input circuit includes: a first transistor and a second transistor;

[0022] The gate of the first transistor is coupled to the first control signal terminal, the first terminal of the first transistor is coupled to the voltage control circuit, and the second terminal of the first transistor is coupled to the first node.

[0023] The gate of the second transistor is coupled to the first control signal terminal, the first terminal of the second transistor is coupled to the voltage control circuit, and the second terminal of the second transistor is coupled to the first node.

[0024] In some possible implementations, the second input circuit includes a third transistor and a fourth transistor;

[0025] The gate of the third transistor is coupled to the first control signal terminal, the first terminal of the third transistor is coupled to the voltage control circuit, and the second terminal of the third transistor is coupled to the second node.

[0026] The gate of the fourth transistor is coupled to the first control signal terminal, the first terminal of the fourth transistor is coupled to the voltage control circuit, and the second terminal of the fourth transistor is coupled to the second node.

[0027] In some possible implementations, the gating output circuit includes a fifth transistor and a sixth transistor;

[0028] The gate of the fifth transistor is coupled to the second control signal terminal, the first terminal of the fifth transistor is coupled to the first node, and the second terminal of the fifth transistor is coupled to the gating control signal terminal.

[0029] The gate of the sixth transistor is coupled to the second control signal terminal, the first terminal of the sixth transistor is coupled to the second node, and the second terminal of the sixth transistor is coupled to the gating control signal terminal.

[0030] In some possible implementations, the switch control circuit includes: a first switch transistor, a second switch transistor, a third switch transistor, and a fourth switch transistor;

[0031] The data signal terminal includes: a first data signal terminal and a second data signal terminal;

[0032] The gating control signal terminal includes: a first gating control signal terminal and a second gating control signal terminal;

[0033] The gates of the first and second switching transistors are both coupled to the first gating control signal terminal; the gates of the third and fourth switching transistors are both coupled to the second gating control signal terminal.

[0034] The first terminals of the first and third switching transistors are both coupled to the first data signal terminal; the first terminals of the second and fourth switching transistors are both coupled to the second data signal terminal.

[0035] The second terminals of the first switching transistor, the second switching transistor, the third switching transistor, and the fourth switching transistor are respectively coupled to different data signal lines.

[0036] The display device provided in this disclosure includes the driving circuit described above. Attached Figure Description

[0037] Figure 1 Some schematic diagrams of the drive circuit provided in the embodiments of this disclosure;

[0038] Figure 2 Other schematic diagrams of the drive circuit provided in the embodiments of this disclosure;

[0039] Figure 3 Some signal timing diagrams provided for embodiments of this disclosure;

[0040] Figure 4 Some structural schematic diagrams of the gating control circuit provided in the embodiments of this disclosure;

[0041] Figure 5 Other schematic diagrams of the gating control circuit provided in the embodiments of this disclosure;

[0042] Figure 6 Further schematic diagrams of the gating control circuit provided in the embodiments of this disclosure;

[0043] Figure 7 Further schematic diagrams of the gating control circuit provided in the embodiments of this disclosure;

[0044] Figure 8 Some structural schematic diagrams of the switch control circuit provided in the embodiments of this disclosure;

[0045] Figure 9 Other signal timing diagrams provided for embodiments of this disclosure;

[0046] Figure 10 Further signal timing diagrams provided for embodiments of this disclosure;

[0047] Figure 11 Some schematic diagrams showing the polarity of the sub-pixel input data signal when polarity is reversed, as provided in the embodiments of this disclosure;

[0048] Figure 12 Some schematic diagrams showing the polarity of the sub-pixel input data signal when polarity is reversed, as provided in the embodiments of this disclosure;

[0049] Figure 13 Some structural schematic diagrams of the display device provided in the embodiments of this disclosure. Detailed Implementation

[0050] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. Furthermore, the embodiments and features in the embodiments of this invention can be combined with each other without conflict. Based on the described embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this invention.

[0051] Unless otherwise defined, the technical or scientific terms used in this invention shall have the ordinary meaning understood by one of ordinary skill in the art to which this invention pertains. The terms "first," "second," and similar terms used in this invention do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as "comprising" or "including" mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect.

[0052] It should be noted that the dimensions and shapes of the figures in the accompanying drawings do not reflect actual proportions and are intended only to illustrate the content of the invention. Furthermore, the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout.

[0053] Multiplexer (MUX) technology can reduce the number of source driver chips (Integrated Circuits, ICs) by at least half, thus significantly reducing costs. It also reduces the number of traces, thereby minimizing the bezel of the display device and making it easier to achieve narrow bezels. Therefore, multiplexer (MUX) technology is widely used in display devices to meet the demand for high-resolution, narrow-bezel, and low-cost products. However, multiplexer (MUX) technology incurs certain losses, so reducing these losses is a problem that needs to be solved. For example, multiplexer technology uses a single data signal terminal of a switch control circuit to drive multiple data signal lines within the display panel. The power consumption required by the existing switch control circuit for controlling one charge and discharge cycle is:

[0054]

[0055] Where Pmux represents the power consumption required for the switch control circuit to control one charge and discharge cycle, Cmux represents the capacitance value of the pixel electrode corresponding to the charge and discharge cycle, Voutput represents the voltage difference during charge and discharge, vgh represents the voltage level of the third level signal VGH, and vgl represents the voltage level of the fourth level signal VGL. The voltage signal controlling the operation of the switch control circuit switches between vgh and vgl.

[0056] Based on the above problems, the driving circuit provided in the embodiments of this disclosure, such as Figure 1 As shown, it includes:

[0057] The voltage control circuit 10 is configured to provide a first voltage signal to the gating control circuit 20 and the source drive circuit 30, and to provide a second voltage signal to the gating control circuit 20 and the gate drive circuit 30.

[0058] The gating control circuit 20 is configured to receive a first voltage signal and a second voltage signal, and provide gating control signals to the gating control signal terminals (e.g., MUXA and MUXB in the figure);

[0059] The source drive circuit 30 is configured to transmit power to the data signal terminal (e.g., based on the first voltage signal) according to the first voltage signal. Figure 1 S1 and S2 in the middle provide data signals;

[0060] The gate drive circuit 40 is configured to provide a scan signal to the gate line GA according to the second voltage signal;

[0061] The switch control circuit 50, coupled to the gating control signal terminals (e.g., MUXA, MUXB in the figure) and the data signal terminals (e.g., S1, S2 in the figure), is configured to provide the data signal to the data signal line DA in response to the gating control signal.

[0062] This disclosure utilizes a voltage control circuit, a gating control circuit, a source drive circuit, a gate drive circuit, and a switching control circuit to work together to switch the voltage value of the gating control signal between the voltage values ​​of the first voltage signal and the second voltage signal. This significantly reduces the power consumption of the drive circuit, thereby reducing losses and saving costs. Furthermore, the first voltage signal provided by the voltage control circuit is multiplexed between the gating control circuit and the source drive circuit, and the second voltage signal provided by the voltage control circuit is multiplexed between the gating control circuit and the gate drive circuit, thereby simplifying the circuit structure and further reducing production costs.

[0063] In some embodiments of this disclosure, the absolute value of the first voltage signal is less than the absolute value of the second voltage signal.

[0064] In some embodiments of this disclosure, the first voltage signal includes: a first level signal VSN and a second level signal VSP; the second voltage signal includes: a third level signal VGH and a fourth level signal VGL; wherein, the first level signal VSN and the third level signal VGH are high level signals; and the second level signal VSP and the fourth level signal VGL are low level signals.

[0065] In some embodiments of this disclosure, the absolute value of the voltage level of the first level signal VSN, |vsn|, is less than the absolute value of the voltage level of the third level signal VGH, |vgh|; and the absolute value of the voltage level of the second level signal VSP, |vsp|, is less than the absolute value of the voltage level of the fourth level signal VGL, |vgl|.

[0066] For example, the voltage level of the first level signal VSN is vsn, the voltage level of the second level signal VSP is vsp, the voltage level of the third level signal VGH is vgh, and the voltage level of the fourth level signal VGL is vgl.

[0067] For example, such as Figure 1 As shown, the voltage control circuit 10 includes a main power supply PMIC and a level conversion circuit LS. The main power supply PMIC directly provides the first level signal VSN and the second level signal VSP to the gating control circuit 20 and the source drive circuit 30. The main power supply PMIC directly provides the third level signal VGH and the fourth level signal VGL to the level conversion circuit LS. The level conversion circuit LS provides the third level signal VGH and the fourth level signal VGL to the gating control circuit 20 and the gate drive circuit 30.

[0068] For example, as shown in Figure 2, the drive circuit may further include: a timing controller TCON;

[0069] The timing controller TCON provides the level conversion circuit LS with the odd / even frame control signal CTRL_T, the first signal Sig1, and the second signal Sig2. The level conversion circuit LS converts the odd / even frame control signal CTRL_T into the signal of the first control signal terminal CTRL_LS for output. The level conversion circuit LS converts the first signal Sig1 into the signal of the second control signal terminal MUXa for output. The level conversion circuit LS converts the second signal Sig2 into the signal of the second control signal terminal MUXb for output.

[0070] For example, such as Figure 3 The signal timing diagram shown represents the signal of the first control signal terminal CTRL_LS; FN represents the Nth display frame, and FN+1 represents the (N+1)th display frame. When the Nth display frame is an odd-numbered frame, the (N+1)th display frame is an even-numbered frame; when the Nth display frame is an even-numbered frame, the (N+1)th display frame is an odd-numbered frame. The following explanation uses the example where the Nth display frame FN is odd-numbered and the (N+1)th display frame FN+1 is even-numbered. In odd-numbered frames, the voltage value of the first control signal terminal CTRL_LS, ctrl_ls, is vgh. In even-numbered frames, the voltage value of the first control signal terminal CTRL_LS, ctrl_ls, is vgl. The voltage value of the first control signal terminal CTRL_LS switches between vgh and vgl.

[0071] In some embodiments of this disclosure, such as Figure 4 and Figure 5 As shown, the gating control circuit 20 includes:

[0072] The first input circuit 210, coupled to the first node N1, is configured to provide the second level signal VSP or the third level signal VGH to the first node N1 in response to the signal of the first control signal terminal CTRL_LS.

[0073] The second input circuit 220, coupled to the second node N2, is configured to provide the first level signal VSN or the fourth level signal VGL to the second node N2 in response to the signal of the first control signal terminal CTRL_LS.

[0074] The gating output circuit 230, coupled to the first node N1 and the second node N2, is configured to respond to the second control signal terminal (e.g., Figure 4 MUXa in Figure 5 The signal from MUXb will provide the signal on the first node N1 or the signal on the second node N2 to the gating control signal terminal (e.g., Figure 4 MUXA in Figure 5 MUXB in (the context of MUXB);

[0075] Among them, the first control signal terminal CTRL_LS and the second control signal terminal (e.g. Figure 4 MUXa in Figure 5 The MUXb in the circuit is coupled to the voltage control circuit 10 and is configured to receive the first voltage signal and the second voltage signal provided by the voltage control circuit 10.

[0076] In some embodiments of this disclosure, such as Figure 6 and Figure 7 As shown, the first input circuit 210 includes: a first transistor M1 and a second transistor M2; wherein, the gate of the first transistor M1 is coupled to the first control signal terminal CTRL_LS, the first terminal of the first transistor M1 is coupled to the voltage control circuit 10, and the second terminal of the first transistor M1 is coupled to the first node N1; the gate of the second transistor M2 is coupled to the first control signal terminal CTRL_LS, the first terminal of the second transistor M2 is coupled to the voltage control circuit, and the second terminal of the second transistor M2 is coupled to the first node N2.

[0077] For example, the first transistor M1 and the second transistor M2 can be turned on under the control of the effective level of the signal transmitted on the first control signal terminal CTRL_LS, and can be turned off under the control of the ineffective level of the signal transmitted on the first control signal terminal CTRL_LS. For instance, the first transistor M1 and the second transistor M2 can be configured as N-type transistors, in which case the effective level of the signal transmitted on the first control signal terminal CTRL_LS is high, and the ineffective level of the signal transmitted on the first control signal terminal CTRL_LS is low. Alternatively, the first transistor M1 and the second transistor M2 can be configured as P-type transistors, in which case the effective level of the signal transmitted on the first control signal terminal CTRL_LS is low, and the ineffective level of the signal transmitted on the first control signal terminal CTRL_LS is high.

[0078] For example, such as Figure 6 As shown, the first transistor M1 is an N-type transistor, and the second transistor M2 is a P-type transistor.

[0079] For example, such as Figure 7 As shown, the first transistor M1 is a P-type transistor, and the second transistor M2 is an N-type transistor.

[0080] In some embodiments of this disclosure, such as Figure 6 and Figure 7 As shown, the second input circuit 220 includes a third transistor M3 and a fourth transistor M4; wherein, the gate of the third transistor M3 is coupled to the first control signal terminal CTRL_LS, the first terminal of the third transistor M3 is coupled to the voltage control circuit 10, and the second terminal of the third transistor M3 is coupled to the second node N2; the gate of the fourth transistor M4 is coupled to the first control signal terminal CTRL_LS, the first terminal of the fourth transistor M4 is coupled to the voltage control circuit 10, and the second terminal of the fourth transistor M4 is coupled to the second node N2.

[0081] For example, the third transistor M3 and the fourth transistor M4 can be turned on under the control of the valid level of the signal transmitted on the first control signal terminal CTRL_LS, and can be turned off under the control of the invalid level of the signal transmitted on the first control signal terminal CTRL_LS. For example, the third transistor M3 and the fourth transistor M4 can be set as N-type transistors, then the valid level of the signal transmitted on the first control signal terminal CTRL_LS is a high level, and the invalid level of the signal transmitted on the first control signal terminal CTRL_LS is a low level. Alternatively, the third transistor M3 and the fourth transistor M4 can be set as P-type transistors, then the valid level of the signal transmitted on the first control signal terminal CTRL_LS is a low level, and the invalid level of the signal transmitted on the first control signal terminal CTRL_LS is a high level.

[0082] For example, such as Figure 6 As shown, the third transistor M3 is an N-type transistor, and the fourth transistor M4 is a P-type transistor.

[0083] For example, such as Figure 7 As shown, the third transistor M3 is a P-type transistor, and the fourth transistor M4 is an N-type transistor.

[0084] In some embodiments of this disclosure, such as Figure 6 and Figure 7 As shown, the gating output circuit 230 includes a fifth transistor M5 and a sixth transistor M6; wherein, the gate of the fifth transistor M5 is connected to the second control signal terminal (e.g., Figure 6 MUXa in Figure 7 In the MUXb) coupling, the first terminal of the fifth transistor M5 is coupled to the first node N1, and the second terminal of the fifth transistor M5 is coupled to the gating control signal terminal (e.g. Figure 6 MUXA in Figure 7 The gate of the sixth transistor M6 is coupled to the second control signal terminal (e.g., MUXB); the gate of the sixth transistor M6 is coupled to the second control signal terminal (e.g., MUXB). Figure 6 MUXa in Figure 7 In the MUXb) coupling, the first terminal of the sixth transistor M6 is coupled to the second node, and the second terminal of the sixth transistor M6 is coupled to the gating control signal terminal (e.g., Figure 6 MUXA in Figure 7 The MUXB in the middle is coupled.

[0085] For example, the fifth transistor M5 and the sixth transistor M6 can be turned on under the control of the effective level of the signal transmitted on the second control signal terminal, and can be turned off under the control of the ineffective level of the signal transmitted on the second control signal terminal. For instance, the fifth transistor M5 and the sixth transistor M6 can be configured as N-type transistors, in which case the effective level of the signal transmitted on the second control signal terminal is high, and the ineffective level of the signal transmitted on the second control signal terminal is low. Alternatively, the fifth transistor M5 and the sixth transistor M6 can be configured as P-type transistors, in which case the effective level of the signal transmitted on the second control signal terminal is low, and the ineffective level of the signal transmitted on the second control signal terminal is high.

[0086] For example, such as Figure 6 and Figure 7 As shown, the fifth transistor M5 is an N-type transistor, and the sixth transistor M6 is a P-type transistor.

[0087] In some embodiments of this disclosure, such as Figure 8As shown, the switch control circuit 50 includes: a first switch transistor T1, a second switch transistor T2, a third switch transistor T3, and a fourth switch transistor T4; wherein, the data signal terminals include: a first data signal terminal S1 and a second data signal terminal S2; the gating control signal terminals include: a first gating control signal terminal MUXA and a second gating control signal terminal MUXB; the gates of the first switch transistor T1 and the second switch transistor T2 are both coupled to the first gating control signal terminal MUXA; the gates of the third switch transistor T3 and the fourth switch transistor T4 are both coupled to the second gating control signal terminal MUXB; the first terminals of the first switch transistor T1 and the third switch transistor T3 are both coupled to the first data signal terminal S1; the first terminals of the second switch transistor T2 and the fourth switch transistor T4 are both coupled to the second data signal terminal S2; the second terminals of the first switch transistor T1, the second switch transistor T2, the third switch transistor T3, and the fourth switch transistor T4 are respectively coupled to different data signal lines.

[0088] For example, such as Figure 8 As shown, the first gating control signal line mux1 and the second gating control signal line mux2 are both coupled to the first gating control signal terminal MUXA; the third gating control signal line mux3 and the fourth gating control signal line mux4 are both coupled to the second gating control signal terminal MUXB; the gate of the first switching transistor T1 is coupled to the first gating control signal line mux1, the first terminal of the first switching transistor T1 is coupled to the first data signal terminal S1, and the second terminal of the first switching transistor T1 is coupled to the corresponding data signal line DA1; the gate of the second switching transistor T2 is coupled to the second gating control signal line mux2, and the second switching transistor... The first terminal of transistor T2 is coupled to the second data signal terminal S2, and the second terminal of the second switching transistor T2 is coupled to the corresponding data signal line DA2; the gate of the third switching transistor T3 is coupled to the third gating control signal line mux3, the first terminal of the third switching transistor T3 is coupled to the first data signal terminal S1, and the second terminal of the third switching transistor T3 is coupled to the corresponding data signal line DA3; the gate of the fourth switching transistor T4 is coupled to the fourth gating control signal line mux4, the first terminal of the fourth switching transistor T4 is coupled to the second data signal terminal S2, and the second terminal of the fourth switching transistor T4 is coupled to the corresponding data signal line DA4.

[0089] For example, the first electrode of the transistor described above can be its source, and the second electrode can be its drain. Alternatively, the first electrode can be its drain, and the second electrode can be its source. No limitation is made here.

[0090] For example, the following are examples Figure 8 Taking the switch control circuit 50 shown as an example, combined with... Figure 9The existing signal timing diagram shown is explained below; where ga represents the scan signal on the gate line GA, muxa represents the signal on the first gating control signal terminal MUXA, and muxb represents the signal on the second gating control signal terminal MUXB.

[0091] First, gate drive transistor T0 is turned on under the control of a high level scan signal ga. First switching transistor T1 is turned on under the control of a high level signal muxa transmitted on the first gating control signal line mux1. Second switching transistor T2 is turned on under the control of a high level signal muxa transmitted on the second gating control signal line mux2. Third switching transistor T3 is turned off under the control of a low level signal muxb transmitted on the third gating control signal line mux3. Fourth switching transistor T4 is turned off under the control of a low level signal muxb transmitted on the fourth gating control signal line mux4. The turned-on first switching transistor T1 provides the data signal from the first data signal terminal S1 to the data signal line DA1, and the turned-on gate drive transistor T0 provides the data signal from the data signal line DA1 to the pixel electrode DJ, charging the pixel electrode DJ. The turned-on second switching transistor T2 provides the data signal from the second data signal terminal S2 to the data signal line DA2, and the turned-on gate drive transistor T0 provides the data signal from the data signal line DA2 to the pixel electrode DJ, charging the pixel electrode DJ. Secondly, the gate driving transistor T0 is turned on under the control of the high level of the scan signal ga, the first switching transistor T1 is turned off under the control of the low level of the signal muxa transmitted on the first gating control signal line mux1, the second switching transistor T2 is turned off under the control of the low level of the signal muxa transmitted on the second gating control signal line mux2, the third switching transistor T3 is turned on under the control of the high level of the signal muxb transmitted on the third gating control signal line mux3, and the fourth switching transistor T4 is turned on under the control of the high level of the signal muxb transmitted on the fourth gating control signal line mux4. The turned-on third switching transistor T3 provides the data signal on the first data signal terminal S1 to the data signal line DA3, and the turned-on gate driving transistor T0 provides the data signal on the data signal line DA3 to the pixel electrode DJ, charging the pixel electrode DJ. The turned-on fourth switching transistor T4 provides the data signal on the second data signal terminal S2 to the data signal line DA4, and the turned-on gate driving transistor T0 provides the data signal on the data signal line DA4 to the pixel electrode DJ, charging the pixel electrode DJ. In the existing signal timing diagram, the voltage values ​​of signal muxa on the first gating control signal terminal MUXA and signal muxb on the second gating control signal terminal MUXB both switch between vgh and vgl. Here, vgh represents the voltage level of the third-level signal VGH, and vgl represents the voltage level of the fourth-level signal VGL. If the signal voltage values ​​switch between vgh and vgl, it will lead to excessive losses and is detrimental to cost.

[0092] In the embodiments disclosed herein, the following are examples: Figure 2 , Figure 6 , Figure 8 Taking the driving circuit shown as an example, combined with Figure 10 The signal timing diagram shown describes the operation of the driving circuit provided in the embodiments of this disclosure.

[0093] Among them, such as Figure 9 As shown, muxa represents the signal on the first gating control signal terminal MUXA, muxb represents the signal on the second gating control signal terminal MUXB, s1 represents the signal on the first data signal terminal S1, and s2 represents the signal on the second data signal terminal S2.

[0094] At the Nth display frame FN, which is an odd-numbered frame, the voltage value of the first control signal terminal CTRL_LS (ctrl_ls) is vgh, meaning the ctrl_ls signal is high. The first transistor M1 is turned on under the control of the high level of the ctrl_ls signal, while the second transistor M2 is turned off. The turned-on first transistor M1 provides the third-level signal VGH to the first node N1, resulting in a voltage value of vgh on node N1. The third transistor M3 is turned on under the control of the high level of the ctrl_ls signal, while the fourth transistor M4 is turned off. The turned-on third transistor M3 provides the first-level signal VSN to the second node N2, resulting in a voltage value of vsn on node N2.

[0095] When the signal at the second control signal terminal MUXa is high, the fifth transistor T5 is turned on under the control of the high-level signal, and the sixth transistor T6 is turned off under the control of the high-level signal. The turned-on fifth transistor T5 provides the signal on the first node N1 to the first gating control signal terminal MUXA, and the voltage value of the signal muxa at the first gating control signal terminal MUXA is vgh. At this time, the polarity of the data signal at the first data signal terminal S1 is positive, and the voltage value of the data signal at the first data signal terminal S1 is v1.

[0096] When the signal at the second control signal terminal MUXa is low, the fifth transistor T5 is turned off under the control of the low-level signal, and the sixth transistor T6 is turned on under the control of the low-level signal. The turned-on sixth transistor T6 provides the signal on the second node N2 to the first gating control signal terminal MUXA, and the voltage value of the signal muxa at the first gating control signal terminal MUXA is vsn. At this time, the polarity of the data signal at the first data signal terminal S1 is positive, and the voltage value of the data signal at the first data signal terminal S1 is v2.

[0097] Then, the voltage value of the signal muxa at the first gating control signal terminal MUXA switches between vgh and vsn. At this time, when charging with positive polarity, the power consumption required for the switching control circuit 50 to perform one charge / discharge cycle is:

[0098] P mux =C mux (vgh-vsn) 2 / 2

[0099] The following is based on Figure 2 , Figure 7 , Figure 8 Taking the driving circuit shown as an example, combined with Figure 10 The signal timing diagram shown describes the operation of the driving circuit provided in the embodiments of this disclosure.

[0100] At the Nth display frame FN, which is an odd-numbered frame, the voltage of the first control signal terminal CTRL_LS (ctrl_ls) is vgh, meaning the ctrl_ls signal is high. The first transistor M1 is off under the control of the high-level ctrl_ls signal, while the second transistor M2 is on, providing the second-level signal VSP to the first node N1, where the voltage value is vsp. The third transistor M3 is off under the control of the high-level ctrl_ls signal, while the fourth transistor M4 is on, providing the fourth-level signal VGL to the second node N2, where the voltage value is vgl.

[0101] When the signal at the second control signal terminal MUXb is high, the fifth transistor T5 is turned on under the control of the high-level signal, and the sixth transistor T6 is turned off under the control of the high-level signal. The turned-on fifth transistor T5 provides the signal on the first node N1 to the second gating control signal terminal MUXB, and the voltage value of the signal muxb at the second gating control signal terminal MUXB is vsp. At this time, the polarity of the data signal at the second data signal terminal S2 is negative, and the voltage value of the data signal at the second data signal terminal S2 is v4.

[0102] When the signal at the second control signal terminal MUXb is low, the fifth transistor T5 is turned off under the control of the low-level signal, and the sixth transistor T6 is turned on under the control of the low-level signal. The turned-on sixth transistor T6 provides the signal on the second node N2 to the second gating control signal terminal MUXB, and the voltage value of the signal at the second gating control signal terminal MUXB, muxb, is vgl. At this time, the polarity of the data signal at the second data signal terminal S2 is negative, and the voltage value of the data signal at the second data signal terminal S2 is v3.

[0103] Then, the voltage value of the signal muxb at the second gating control signal terminal MUXB switches between vsp and vgl. At this time, when charging with negative polarity, the power consumption required for the switching control circuit 50 to perform one charge / discharge cycle is:

[0104] P mux =C mux (vsp-vgl) 2 / 2

[0105] In summary, at the Nth display frame FN, Figure 6 The voltage value of the signal muxa at the first gate control signal terminal MUXA, as shown, switches between vgh and vsn. The signal at the second control signal terminal MUXa switches at the same frequency as the signal at the first gate control signal terminal MUXA. Figure 7 The voltage value of the signal muxb at the second gating control signal terminal MUXB, as shown, switches between vsp and vgl. The signal at the second control signal terminal MUXb switches at the same frequency as the signal at the second gating control signal terminal MUXB. Therefore, the driving circuit of this embodiment can significantly reduce energy consumption and save costs.

[0106] For example, when VGH is 12V, VGL is -8V, vsp is 6.2V, and vsn is -6.2V, the embodiments of this disclosure can save more than 30% of power consumption. Of course, the specific values ​​of VGH, VGL, vsp, and vsn can be set according to requirements and are not limited here.

[0107] The following is based on Figure 2 , Figure 6 , Figure 8 Taking the driving circuit shown as an example, combined with Figure 10 The signal timing diagram shown describes the operation of the driving circuit provided in the embodiments of this disclosure.

[0108] At the (N+1)th display frame FN, which is an even-numbered frame, the voltage of the first control signal terminal CTRL_LS (ctrl_ls) is vgl, meaning the ctrl_ls signal is low. The first transistor M1 is off under the control of the low-level ctrl_ls signal, while the second transistor M2 is on under the control of the low-level ctrl_ls signal. The on-state second transistor M2 provides the second-level signal VSP to the first node N1, where the voltage value is vsp. The third transistor M3 is off under the control of the low-level ctrl_ls signal, while the fourth transistor M4 is on under the control of the low-level ctrl_ls signal. The on-state fourth transistor M4 provides the fourth-level signal VGL to the second node N2, where the voltage value is vgl.

[0109] When the signal at the second control signal terminal MUXa is high, the fifth transistor T5 is turned on under the control of the high-level signal, and the sixth transistor T6 is turned off under the control of the high-level signal. The turned-on fifth transistor T5 provides the signal on the first node N1 to the first gating control signal terminal MUXA, and the voltage value of the signal muxa at the first gating control signal terminal MUXA is vsp. At this time, the polarity of the data signal at the first data signal terminal S1 is negative, and the voltage value of the data signal at the first data signal terminal S1 is v4.

[0110] When the signal at the second control signal terminal MUXa is low, the fifth transistor T5 is turned off under the control of the low-level signal, and the sixth transistor T6 is turned on under the control of the low-level signal. The turned-on sixth transistor T6 provides the signal on the second node N2 to the first gating control signal terminal MUXA, and the voltage value of the signal muxa at the first gating control signal terminal MUXA is vgl. At this time, the polarity of the data signal at the first data signal terminal S1 is negative, and the voltage value of the data signal at the first data signal terminal S1 is v3.

[0111] Then, the voltage value of the signal muxa at the first gating control signal terminal MUXA switches between vsp and vgl. At this time, when charging with negative polarity, the power consumption required for the switching control circuit 50 to perform one charge / discharge cycle is:

[0112] P mux =C mux (vsp-vgl) 2 / 2

[0113] The following is based on Figure 2 , Figure 7 , Figure 8 Taking the driving circuit shown as an example, combined with Figure 10The signal timing diagram shown describes the operation of the driving circuit provided in the embodiments of this disclosure.

[0114] At the (N+1)th display frame FN, which is an even-numbered frame, the voltage of the first control signal terminal CTRL_LS (ctrl_ls) is vgl, meaning the ctrl_ls signal is low. The first transistor M1 is turned on under the control of the low-level ctrl_ls signal, while the second transistor M2 is turned off. The turned-on first transistor M1 provides the third-level signal VGH to the first node N1, where the voltage value is vgh. The third transistor M3 is turned on under the control of the low-level ctrl_ls signal, while the fourth transistor M4 is turned off. The turned-on third transistor M3 provides the first-level signal VSN to the second node N2, where the voltage value is vsn.

[0115] When the signal at the second control signal terminal MUXb is high, the fifth transistor T5 is turned on under the control of the high-level signal, and the sixth transistor T6 is turned off under the control of the high-level signal. The turned-on fifth transistor T5 provides the signal at the first node N1 to the second gating control signal terminal MUXB, and the voltage value of the signal muxb at the second gating control signal terminal MUXB is vgh. At this time, the polarity of the data signal at the second data signal terminal S2 is positive, and the voltage value of the data signal at the second data signal terminal S2 is v1.

[0116] When the signal at the second control signal terminal MUXb is low, the fifth transistor T5 is turned off under the control of the low-level signal, and the sixth transistor T6 is turned on under the control of the low-level signal. The turned-on sixth transistor T6 provides the signal on the second node N2 to the second gating control signal terminal MUXB, and the voltage value of the signal muxb at the second gating control signal terminal MUXB is vsn. At this time, the polarity of the data signal at the second data signal terminal S2 is positive, and the voltage value of the data signal at the second data signal terminal S2 is v2.

[0117] Then, the voltage value of the signal muxb at the second gating control signal terminal MUXB switches between vgh and vsn. At this time, when charging with positive polarity, the power consumption required for the switching control circuit 50 to perform one charge / discharge cycle is:

[0118] P mux =C mux (vgh-vsn) 2 / 2

[0119] In summary, at the (N+1)th display frame FN; Figure 6 The voltage value of the signal muxa at the first gate control signal terminal MUXA, as shown, switches between vsp and vgl. The signal at the second control signal terminal MUXa switches at the same frequency as the signal at the first gate control signal terminal MUXA. Figure 7 The voltage value of the signal muxb at the second gating control signal terminal MUXB, as shown, switches between vgh and vsn. The signal at the second control signal terminal MUXb switches at the same frequency as the signal at the second gating control signal terminal MUXB. Therefore, the driving circuit of this embodiment can significantly reduce energy consumption and save costs.

[0120] For example, when VGH is 12V, VGL is -8V, vsp is 6.2V, and vsn is -6.2V, the embodiments of this disclosure can save more than 30% of power consumption. Of course, the specific values ​​of VGH, VGL, vsp, and vsn can be set according to requirements and are not limited here.

[0121] To achieve better display effects and improve the performance of liquid crystals, display panels can employ a column-flipping method to enhance the display effect of liquid crystal molecules. In practical applications, the flipping of liquid crystal molecules is driven by an electric field, causing their polarity to reverse. For example, Figure 11 and Figure 12 This illustrates the polarity of the data signal input to the sub-pixel SPX in two adjacent display frames when the display panel uses a column flip method. Figure 11 This illustrates the polarity of the data signals input to each sub-pixel SPX in the display panel before flipping during the Nth display frame FN (i.e., odd-numbered frame). Figure 12 This diagram illustrates the polarity of the data signals input to each sub-pixel SPX in the flipped display panel during the (N+1)th display frame (FN+1, i.e., an even-numbered frame). "+" represents a positive polarity, and "-" represents a negative polarity. For example, in column flipping mode, the data signals input to a column of sub-pixels have the same polarity, and columns of sub-pixels with positive and negative polarities alternate. Specifically, for the same sub-pixel SPX column, in the previous display frame (FN), the data signal input to that column has a positive polarity. In the next display frame (FN+1), the data signal input to that column has a negative polarity. And conversely, in the previous display frame (FN), the data signal input to that column had a negative polarity. In the next display frame (i.e., FN+1), the polarity of the data signal input to the SPX column of this sub-pixel will be positive.

[0122] For example, such as Figure 11 As shown, L1, L2, L3, L4, and L5 represent each row of sub-pixels. For the sub-pixel SPX columns corresponding to data signal lines DA1, DA3, and DA5, if the polarity of the data signals transmitted on data signal lines DA1, DA3, and DA5 is positive during the Nth display frame FN, then the polarity of the data signal input to the sub-pixel SPX column is positive. Similarly, for the sub-pixel SPX columns corresponding to data signal lines DA2 and DA4, if the polarity of the data signals transmitted on data signal lines DA2 and DA4 is negative during the Nth display frame FN, then the polarity of the data signal input to the sub-pixel SPX column is negative.

[0123] For example, such as Figure 12 As shown, L1, L2, L3, L4, and L5 represent each row of sub-pixels. For the sub-pixel SPX columns corresponding to data signal lines DA1, DA3, and DA5, in the (N+1)th display frame FN+1, if the polarity of the data signals transmitted on data signal lines DA1, DA3, and DA5 is negative, then the polarity of the data signal input to the sub-pixel SPX columns is negative. For the sub-pixel SPX columns corresponding to data signal lines DA2 and DA4, in the (N+1)th display frame FN+1, if the polarity of the data signals transmitted on data signal lines DA2 and DA4 is both positive and negative, then the polarity of the data signal input to the sub-pixel SPX columns is positive.

[0124] Based on the same inventive concept, this disclosure also provides a display device, including the driving circuit described above. The principle by which this display device solves the problem is similar to that of the aforementioned driving circuit; therefore, the implementation of this display device can refer to the implementation of the aforementioned driving circuit, and the repetitions will not be repeated here.

[0125] For example, such as Figure 13As shown, the display device may include a display panel; wherein the display panel 100 may include a plurality of pixel units arranged in an array, a plurality of gate lines (e.g., GA1, GA2, GA3, GA4), and a plurality of data signal lines (e.g., DA1, DA2, DA3). A gate driving circuit 40 is coupled to the gate lines GA1, GA2, GA3, and GA4 respectively, and a source driving circuit 30 is coupled to the data signal lines DA1, DA2, and DA3 respectively. A timing controller can input a scan signal to the gate driving circuit 40 through a level conversion circuit LS, thereby driving the gate lines GA1, GA2, GA3, and GA4. The source driving circuit 30 inputs data signals to the data signal lines, thereby charging the sub-pixels SPX, causing the sub-pixels SPX to input corresponding data signals, thus realizing the screen display function. Exemplarily, two source driving circuits 30 may be configured, with one source driving circuit 30 connected to half of the data signal lines and the other source driving circuit 30 connected to the other half of the data signal lines. Of course, the source drive circuit 30 can also be set to 3, 4 or more, which can be designed and determined according to the actual application requirements, and is not limited here.

[0126] For example, each pixel unit includes multiple sub-pixels (SPX). For instance, a pixel unit may include red, green, and blue sub-pixels, allowing for color mixing via red-green-blue blending to achieve color display. Alternatively, a pixel unit may include red, green, blue, and white sub-pixels, also allowing for color mixing via red-green-blue-white blending to achieve color display. Of course, in practical applications, the emission color of the sub-pixels within a pixel unit can be designed and determined according to the actual application environment, and is not limited here.

[0127] For example, as shown in Figure 13, each sub-pixel SPX includes a gate driving transistor T0 and a pixel electrode DJ. One row of sub-pixels SPX corresponds to one gate line, and one column of sub-pixels SPX corresponds to one data signal line. The gate of the gate driving transistor T0 is electrically connected to the corresponding gate line, the source of the gate driving transistor T0 is electrically connected to the corresponding data signal line, and the drain of the gate driving transistor T0 is electrically connected to the pixel electrode DJ. It should be noted that the pixel array structure of this disclosure can also be a dual-gate structure, that is, two gate lines are set between two adjacent rows of pixels. This arrangement can reduce the number of data signal lines by half, meaning that it includes data signal lines between adjacent columns of pixels, but does not include data signal lines between adjacent columns of pixels. The specific pixel arrangement structure and the arrangement of data signal lines and scan lines are not limited.

[0128] It should be noted that the display panel in this embodiment can be a liquid crystal display panel. Exemplarily, a liquid crystal display panel generally includes an upper substrate and a lower substrate of a cell, and liquid crystal molecules encapsulated between the upper and lower substrates. When displaying an image, a voltage difference exists between the data voltage applied to the pixel electrode of each sub-pixel SPX and the common electrode voltage on the common electrode. This voltage difference can form an electric field, causing the liquid crystal molecules to deflect under the influence of this electric field. Because different intensities of electric fields cause different degrees of deflection of the liquid crystal molecules, the transmittance of the sub-pixel SPX varies, enabling the sub-pixel SPX to achieve different grayscale brightness levels, thereby realizing image display.

[0129] The present invention uses a liquid crystal display panel as an example, and the pixel unit includes a red sub-pixel SPX, a green sub-pixel SPX, and a blue sub-pixel SPX. However, the reader should know that the colors of the sub-pixels SPX included in the liquid crystal display panel are not limited to these.

[0130] Grayscale, in general, divides the brightness variation between the darkest and brightest points into several parts to facilitate screen brightness control. For example, a displayed image may consist of three colors: red, green, and blue. Each color can be displayed at different brightness levels, and combinations of different brightness levels of red, green, and blue can form different colors. For instance, if an LCD panel has a grayscale bit depth of 6 bits, then red, green, and blue each have 64 (i.e., 2^34) grayscale values. 6 There are 64 gray levels, with gray values ​​ranging from 0 to 63. If the LCD panel has an 8-bit grayscale bit depth, then red, green, and blue each have 256 (i.e., 2^6) gray levels. 8 There are 256 gray levels, with gray values ​​ranging from 0 to 255. If the LCD panel has a 10-bit grayscale, then red, green, and blue each have 1024 (i.e., 2^35) grayscale values. 10 There are 1024 gray levels, with gray values ​​ranging from 0 to 1023. If the LCD panel has a 12-bit grayscale, then red, green, and blue each have 4096 (i.e., 2^3) gray levels. 12 There are 4096 gray levels, with gray values ​​ranging from 0 to 4093.

[0131] For example, taking a sub-pixel SPX as an example, the data voltage Vda of the data signal loaded on the data signal line corresponding to the sub-pixel SPX is provided to the pixel electrode corresponding to the sub-pixel SPX through the gate driving transistor T0. When the data voltage Vda of the data signal input to the pixel electrode of the sub-pixel SPX is greater than the common electrode voltage Vcom on the common electrode, the liquid crystal molecules at the sub-pixel SPX can be made positive, and the polarity corresponding to the data voltage Vda of the data signal in the sub-pixel SPX is positive. When the data voltage Vda of the data signal input to the pixel electrode of the sub-pixel SPX is less than the common electrode voltage Vcom on the common electrode, the liquid crystal molecules at the sub-pixel SPX can be made negative, and the polarity corresponding to the data voltage Vda of the data signal in the sub-pixel SPX is negative. For example, the common electrode voltage can be 8.3V. If a data voltage of 8.3V to 16V is input to the pixel electrode of the sub-pixel SPX, the liquid crystal molecules at the sub-pixel SPX can be made positive, and the data voltage of 8.3V to 16V is the corresponding positive polarity data voltage. If a data voltage of 0.6V to 8.3V is input to the pixel electrode of a sub-pixel SPX, the liquid crystal molecules at that sub-pixel SPX can be made negatively polarized. Therefore, the 0.6V to 8.3V data voltage corresponds to the negative polarity. For example, taking an 8-bit grayscale of 0 to 255 as an example, if a data voltage of 16V is input to the pixel electrode of a sub-pixel SPX, the sub-pixel SPX can correspond to the maximum grayscale value of the positive polarity. If a data voltage of 0.6V is input to the pixel electrode of a sub-pixel SPX, the sub-pixel SPX can correspond to the maximum grayscale value of the negative polarity.

[0132] In specific implementations, in the embodiments of this disclosure, the display device can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator. Other essential components of the display device are those that should be understood by those skilled in the art, and will not be described in detail here, nor should they be construed as limiting the present invention.

[0133] Although preferred embodiments of the invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including both the preferred embodiments and all changes and modifications falling within the scope of the invention.

[0134] Obviously, those skilled in the art can make various modifications and variations to the embodiments of this disclosure without departing from the spirit and scope of the embodiments of this disclosure. Therefore, if these modifications and variations to the embodiments of this disclosure fall within the scope of the claims of this invention and their equivalents, then this invention also intends to include these modifications and variations.

Claims

1. A driving circuit, characterized in that, include: A voltage control circuit is configured to provide a first voltage signal to a gating control circuit and a source drive circuit, and to provide a second voltage signal to the gating control circuit and the gate drive circuit. The gating control circuit is configured to receive the first voltage signal and the second voltage signal, and provide a gating control signal to the gating control signal terminal; The source drive circuit is configured to provide a data signal to the data signal terminal according to the first voltage signal; The gate drive circuit is configured to provide a scan signal to the gate line according to the second voltage signal; A switch control circuit, coupled to the gating control signal terminal and the data signal terminal, is configured to provide the data signal to the data signal line in response to the gating control signal. The absolute value of the first voltage signal is less than the absolute value of the second voltage signal; The first voltage signal includes: a first level signal and a second level signal; The second voltage signal includes: a third-level signal and a fourth-level signal; The first level signal and the third level signal are both high level signals; The second level signal and the fourth level signal are both low level signals; The gating control circuit includes: A first input circuit, coupled to a first node, is configured to provide the second level signal or the third level signal to the first node in response to a signal at a first control signal terminal. The second input circuit, coupled to the second node, is configured to provide the first level signal or the fourth level signal to the second node in response to a signal at the first control signal terminal. A gating output circuit, coupled to the first node and the second node, is configured to provide a signal on the first node or a signal on the second node to the gating control signal terminal in response to a signal at the second control signal terminal. The first control signal terminal and the second control signal terminal are both coupled to the voltage control circuit and are configured to receive the first voltage signal and the second voltage signal provided by the voltage control circuit. The first input circuit includes: a first transistor and a second transistor; The gate of the first transistor is coupled to the first control signal terminal, the first terminal of the first transistor is coupled to the voltage control circuit, and the second terminal of the first transistor is coupled to the first node. The gate of the second transistor is coupled to the first control signal terminal, the first terminal of the second transistor is coupled to the voltage control circuit, and the second terminal of the second transistor is coupled to the first node; The second input circuit includes: a third transistor and a fourth transistor; The gate of the third transistor is coupled to the first control signal terminal, the first terminal of the third transistor is coupled to the voltage control circuit, and the second terminal of the third transistor is coupled to the second node. The gate of the fourth transistor is coupled to the first control signal terminal, the first terminal of the fourth transistor is coupled to the voltage control circuit, and the second terminal of the fourth transistor is coupled to the second node. The gating output circuit includes: a fifth transistor and a sixth transistor; The gate of the fifth transistor is coupled to the second control signal terminal, the first terminal of the fifth transistor is coupled to the first node, and the second terminal of the fifth transistor is coupled to the gating control signal terminal. The gate of the sixth transistor is coupled to the second control signal terminal, the first terminal of the sixth transistor is coupled to the second node, and the second terminal of the sixth transistor is coupled to the gating control signal terminal.

2. The driving circuit as described in claim 1, characterized in that, The absolute value of the voltage level of the first level signal is less than the absolute value of the voltage level of the third level signal; The absolute value of the voltage level of the second level signal is less than the absolute value of the voltage level of the fourth level signal.

3. The driving circuit as described in claim 1, characterized in that, The switch control circuit includes: a first switch transistor, a second switch transistor, a third switch transistor, and a fourth switch transistor; The data signal terminal includes: a first data signal terminal and a second data signal terminal; The gating control signal terminal includes: a first gating control signal terminal and a second gating control signal terminal; The gates of the first and second switching transistors are both coupled to the first gating control signal terminal; the gates of the third and fourth switching transistors are both coupled to the second gating control signal terminal. The first terminals of the first and third switching transistors are both coupled to the first data signal terminal; the first terminals of the second and fourth switching transistors are both coupled to the second data signal terminal. The second terminals of the first switching transistor, the second switching transistor, the third switching transistor, and the fourth switching transistor are respectively coupled to different data signal lines.

4. A display device, characterized in that, Includes the driving circuit as described in any one of claims 1-3.

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