Semiconductor package structure and method of manufacturing the same

Abstract

The application provides a semiconductor packaging structure and a preparation method thereof, which adopts a ceramic packaging core plate as a basic support, forms a first recess on the ceramic substrate and a first through hole below the first recess, embeds a first chip face down into the first recess, and realizes bonding connection with the first chip through a first metal layer in the first through hole, so as to improve the wiring density and integration, forms a multilayer build-up structure, sets a second recess in the outer build-up layer and embeds a second chip, forms a metal column on the upper layer wiring structure and realizes bonding connection of a third chip with the metal column. The preparation method realizes 3D integration of the multi-chip and the ceramic core plate system, effectively solves the warping deformation problem of the high stack number packaging substrate, significantly improves the heat conduction performance of the packaging structure, embeds the chip on the ceramic core plate to improve the wiring density, and greatly improves the integration and performance of the ceramic core plate structure through the multi-chip packaging.

Description

Technical Field

[0001] This invention relates to the field of semiconductor packaging technology, and in particular to a semiconductor packaging structure and its fabrication method. Background Technology

[0002] As semiconductor technology rapidly advances towards high power, high integration, and miniaturization, packaging substrates face the dual challenges of heat dissipation and structural stability. On the one hand, the power consumption of high-power devices such as AI chips and high-performance computing processors continues to rise, leading to a sharp increase in heat flux density per unit area. On the other hand, to meet the demand for higher integration, advanced packaging technologies generally adopt multilayer stacked structures of 14-20 layers and miniaturize metal circuits to the 2μm-8μm level. This high-density interconnect structure not only significantly increases thermal resistance, making it more difficult to dissipate heat in a timely manner, but also generates greater thermomechanical stress during temperature changes due to the difference in the coefficient of thermal expansion (CTE) between different materials. This requires a breakthrough balance between high thermal conductivity and excellent dimensional stability in next-generation packaging substrates. It is necessary to use high thermal conductivity media materials to improve heat dissipation efficiency, and to enhance mechanical rigidity and reduce thermal deformation by optimizing the core board structure and material formulation. Summary of the Invention

[0003] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a semiconductor packaging structure and its preparation method, which solves the problems of warpage and insufficient thermal conductivity of high-layer-count packaging substrates in the prior art.

[0004] To achieve the above and other related objectives, the present invention provides a method for fabricating a semiconductor packaging structure, the method comprising:

[0005] S1, a ceramic encapsulation core board is provided. The ceramic encapsulation core board includes a ceramic substrate. The ceramic substrate has a front side and a back side. The ceramic encapsulation core board also includes at least one first groove formed at a preset position on the front side of the ceramic substrate and a plurality of first through holes penetrating the ceramic substrate from a preset position at the bottom of the first groove.

[0006] S2, forming a first metal layer that fills the first through hole;

[0007] S3, forming a plurality of second through holes penetrating the ceramic substrate;

[0008] S4, the first chip to be packaged is embedded into the first groove with its front side facing down, and the first chip is bonded to the first metal layer through the first bump on its front side.

[0009] S5, forming a first dielectric layer that fills the second through hole and covers the front and back sides of the obtained structure;

[0010] S6, forming a third through-hole penetrating the first dielectric layer, forming a micro-blind hole penetrating the first dielectric layer on the back side of the obtained structure and exposing the surface of the first metal layer;

[0011] S7, forming a second metal layer that fills the third through hole and the micro blind hole and covers the front and back sides of the obtained structure;

[0012] S8, the second metal layer is etched using photolithography, while retaining the second metal layer in the third through hole and the preset areas at both ends, as well as the second metal layer in the micro blind hole and the preset area below it;

[0013] S9, at least one layer is formed on the front and back sides of the obtained structure, the layer is electrically connected to the second metal layer, and the outer layer of the layer includes a second dielectric layer and a third metal layer;

[0014] S10, at least one second groove is formed at a predetermined position in the second dielectric layer on the front side of the obtained structure;

[0015] S11, the second chip to be packaged is embedded into the second groove with the front side facing up, and the front side of the second chip has a second protrusion;

[0016] S12, an upper layer wiring structure is formed on the front side of the obtained structure. The upper layer wiring structure includes a third dielectric layer and a fourth metal layer. The fourth metal layer is electrically connected to the second bump and the added layer. A lower layer wiring structure is formed on the back side of the obtained structure. The lower layer wiring structure includes a fourth dielectric layer and a fifth metal layer. The fifth metal layer is electrically connected to the added layer.

[0017] S13, a plurality of metal pillars are formed on the fourth metal layer;

[0018] S14, the third chip to be packaged is bonded to the metal pillar.

[0019] Optionally, in step S13, the method for forming a plurality of metal pillars on the fourth metal layer includes:

[0020] S131, forming a first solder resist layer covering the front side of the obtained structure;

[0021] S132, forming a plurality of metal pillars that penetrate the first solder resist layer and are in contact with the fourth metal layer;

[0022] Step S13 further includes forming a second solder resist layer on the back side of the obtained structure, and opening a window in the second solder resist layer to expose the surface of the fifth metal layer to form a solder pad.

[0023] After step S13, the method further includes the step of implanting solder balls on the solder pads.

[0024] Optionally, the ceramic encapsulation core board is formed using a multilayer co-fired ceramic process, and the ceramic encapsulation core board further includes at least one metal layer embedded in the ceramic substrate.

[0025] Optionally, the ceramic encapsulation core board is formed using 3D printing or laser drilling.

[0026] Optionally, the ceramic substrate is made of Al2O3, AlN, or Si3N4.

[0027] Optionally, the first dielectric layer, the second dielectric layer, the third dielectric layer, and the fourth dielectric layer are all ABF.

[0028] Optionally, in step S2, the method for forming a first metal layer that fills the first through-hole includes:

[0029] S21, a first seed layer is formed on the sidewall of the first through hole, the bottom wall and sidewall of the first groove, and the surface of the ceramic substrate;

[0030] S22, forming a first metal layer that fills the first through hole;

[0031] S23, remove the first seed layer and the first metal layer outside the first through hole.

[0032] Optionally, in step S5, a first dielectric layer is formed by using a vacuum hot pressing process to fill the second through hole and cover the front and back sides of the obtained structure.

[0033] Optionally, in step S7, the method for forming a second metal layer that fills the third through-hole and the micro-blind hole and covers the front and back sides of the resulting structure includes:

[0034] S71, deposit a second seed layer on the sidewall of the third through hole, the sidewall and bottom wall of the micro blind hole, and the surface of the first dielectric layer;

[0035] S72, an electroplating process is used to form a second metal layer that fills the third through hole and the micro blind hole, and covers the front and back sides of the resulting structure.

[0036] The present invention also provides a semiconductor packaging structure, which is prepared by the semiconductor packaging structure preparation method described in any one of the above claims, wherein the semiconductor packaging structure comprises:

[0037] A ceramic encapsulation core board, wherein the ceramic encapsulation core board has a front side and a back side facing each other;

[0038] The first chip is embedded face down inside the front of the ceramic encapsulation core board;

[0039] At least one augmentation layer is formed on the front and back sides of the ceramic encapsulation core board, the augmentation layer including an outer augmentation layer located on the outer side, and the augmentation layer is electrically connected to the first chip;

[0040] A second chip embedded within the external layer on the front side;

[0041] An upper wiring structure is formed on the second chip and the outer layer on the front side, and the upper wiring structure is electrically connected to the second chip and the outer layer.

[0042] A lower layer wiring structure is formed below the outer layer on the back side, and the lower layer wiring structure is electrically connected to the layer.

[0043] Several metal pillars that are in contact with and connected to the upper wiring structure;

[0044] A third chip bonded to the metal pillar.

[0045] As described above, the semiconductor packaging structure and its fabrication method of the present invention have the following beneficial effects: By using a ceramic packaging core board as a basic support, forming a first groove on the ceramic substrate and a first through-hole below it, embedding the first chip face down into the first groove, and achieving bonding connection with the first chip through the first metal layer in the first through-hole, the wiring density and integration are improved. By forming a multi-layer build-up structure, the number of wiring layers is increased, meeting the requirements of high-performance processors for high-layer packaging. A second groove is set in the build-up layer and a second chip is embedded therein, further improving the wiring structure. Finally, metal pillars are formed on the upper wiring structure and a third chip is bonded to the metal pillars. This fabrication method realizes 3D integration of multiple chips with the ceramic core board system, effectively solves the warpage and deformation problem of high-layer packaging substrates, significantly improves the thermal conductivity of the packaging structure, and increases wiring density by embedding chips on the ceramic core board. Through multi-chip packaging, the integration and performance of the ceramic core board structure are greatly improved, meeting the requirements of modern semiconductor devices for high power, high frequency, and high integration, and greatly improving the overall performance and stability of semiconductor packaging. Attached Figure Description

[0046] Figure 1 The diagram shows a flow chart of the method for fabricating the semiconductor packaging structure of the present invention.

[0047] Figures 2 to 20 The diagram shows the structural schematics of each step in the fabrication method of the semiconductor packaging structure of the present invention.

[0048] Component designation explanation

[0049] 10 Ceramic Encapsulation Core Board

[0050] 11 Ceramic substrate

[0051] 111 Front

[0052] 112 Back

[0053] 12 First through hole

[0054] 13 First Groove

[0055] 14 Metal Layer

[0056] 15 First Seed Layer

[0057] 16 First metal layer

[0058] 17 Second through hole

[0059] 18 First Chip

[0060] 19 First protrusion

[0061] 191 Fill layer

[0062] 20 First dielectric layer

[0063] 21 Third through hole

[0064] 22 micro blind holes

[0065] 23 Second Seed Layer

[0066] 24 Second metal layer

[0067] 25 Three-story additions

[0068] 26 additional layers

[0069] 261 Second Dielectric Layer

[0070] 262 Third Metal Layer

[0071] 27 Second Groove

[0072] 28 Second Chip

[0073] 29 Second convex point

[0074] 30 Chip bonding film

[0075] 31 Upper-layer cabling structure

[0076] 311 Third Dielectric Layer

[0077] 312 Fourth Metal Layer

[0078] 32 Lower layer wiring structure

[0079] 321 Fourth Dielectric Layer

[0080] 322 Fifth Metal Layer

[0081] 33 First solder resist layer

[0082] 34 Metal Columns

[0083] 35 Second solder resist layer

[0084] 36 pads

[0085] 37 Third Chip

[0086] 38 Second convex point

[0087] 39 Surface treatment layer

[0088] 40 welding balls

[0089] Steps S1 to S14 Detailed Implementation

[0090] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0091] Please see Figures 1 to 20 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0092] This embodiment provides a method for fabricating a semiconductor packaging structure, such as... Figure 1 As shown, the preparation method includes:

[0093] S1, a ceramic encapsulation core board is provided. The ceramic encapsulation core board includes a ceramic substrate. The ceramic substrate has a front side and a back side. The ceramic encapsulation core board also includes at least one first groove formed at a preset position on the front side of the ceramic substrate and a plurality of first through holes penetrating the ceramic substrate from a preset position at the bottom of the first groove.

[0094] S2, forming a first metal layer that fills the first through hole;

[0095] S3, forming a plurality of second through holes penetrating the ceramic substrate;

[0096] S4, the first chip to be packaged is embedded into the first groove with its front side facing down, and the first chip is bonded to the first metal layer through the first bump on its front side.

[0097] S5, forming a first dielectric layer that fills the second through hole and covers the front and back sides of the obtained structure;

[0098] S6, forming a third through-hole penetrating the first dielectric layer, forming a micro-blind hole penetrating the first dielectric layer on the back side of the obtained structure and exposing the surface of the first metal layer;

[0099] S7, forming a second metal layer that fills the third through hole and the micro blind hole and covers the front and back sides of the obtained structure;

[0100] S8, the second metal layer is etched using photolithography, while retaining the second metal layer in the third through hole and the preset areas at both ends, as well as the second metal layer in the micro blind hole and the preset area below it;

[0101] S9, at least one layer is formed on the front and back sides of the obtained structure, the layer is electrically connected to the second metal layer, and the outer layer of the layer includes a second dielectric layer and a third metal layer;

[0102] S10, at least one second groove is formed at a predetermined position in the second dielectric layer on the front side of the obtained structure;

[0103] S11, the second chip to be packaged is embedded into the second groove with the front side facing up, and the front side of the second chip has a second protrusion;

[0104] S12, an upper layer wiring structure is formed on the front side of the obtained structure. The upper layer wiring structure includes a third dielectric layer and a fourth metal layer. The fourth metal layer is electrically connected to the second bump and the added layer. A lower layer wiring structure is formed on the back side of the obtained structure. The lower layer wiring structure includes a fourth dielectric layer and a fifth metal layer. The fifth metal layer is electrically connected to the added layer.

[0105] S13, a plurality of metal pillars are formed on the fourth metal layer;

[0106] S14, the third chip to be packaged is bonded to the metal pillar.

[0107] The semiconductor packaging structure fabrication method of this embodiment uses a ceramic packaging core board as a basic support, forms a first groove on the ceramic substrate and a first through-hole below it, embeds a first chip face down into the first groove, and achieves bonding connection with the first chip through a first metal layer in the first through-hole, thereby improving wiring density and integration. By forming a multi-layer build-up structure, the number of wiring layers is increased, meeting the high stack-up packaging requirements of high-performance processors. A second groove is set in the build-up layer and a second chip is embedded therein to further improve the wiring structure. Finally, metal pillars are formed on the upper wiring structure and a third chip is bonded to the metal pillars. This fabrication method achieves 3D integration of multiple chips with the ceramic core board system, effectively solves the warpage and deformation problem of high stack-up packaging substrates, significantly improves the thermal conductivity of the packaging structure, and increases wiring density by embedding chips on the ceramic core board. Through multi-chip packaging, the integration and performance of the ceramic core board structure are greatly improved, meeting the requirements of modern semiconductor devices for high power, high frequency, and high integration, and greatly improving the overall performance and stability of semiconductor packaging.

[0108] The method for fabricating the semiconductor packaging structure of this embodiment will be described in detail below with reference to the specific accompanying drawings.

[0109] like Figure 2 and Figure 3 As shown, step S1 is performed first, providing a ceramic encapsulation core board 10. The ceramic encapsulation core board 10 includes a ceramic substrate 11, which has a front side 111 and a back side 112. The ceramic encapsulation core board 10 also includes at least one first groove 13 formed at a preset position on the front side 111 of the ceramic substrate 11 and a plurality of first through holes 12 penetrating the ceramic substrate 11 from a preset position at the bottom of the first groove 13.

[0110] The ceramic substrate 11 is a type of inorganic packaging substrate. Its higher hardness compared to organic packaging substrates results in less warpage in high-layer structures. In integrated circuit photolithography, less warpage means greater tolerance for depth of focus in the photolithography system, thus avoiding problems such as insufficient energy or dimensional deviations in ultra-fine lines caused by defocusing due to substrate surface undulations in high-resolution photolithography systems. Simultaneously, the ceramic substrate 11 has a good matching coefficient of thermal expansion with the copper foil, effectively avoiding thermal stress caused by temperature differences and ensuring the stability of the packaging structure. Furthermore, the thermal conductivity of the ceramic substrate 11 is at least 40 times that of organic packaging substrates. In high-performance computing processors, this superior thermal conductivity prevents processor throttling due to overheating during prolonged high-frequency operation, thus avoiding performance degradation and application service interruptions.

[0111] As an example, the ceramic encapsulation core plate 10 can be formed using 3D printing or laser drilling processes, resulting in a structure as shown below. Figure 2 As shown; the ceramic encapsulation core board 10 can also be formed using a multilayer co-fired ceramic process. The ceramic encapsulation core board 10 further includes at least one metal layer 14 embedded in the ceramic substrate 11, forming a structure as shown. Figure 3 As shown, this embodiment uses... Figure 2 The following explanation of the semiconductor packaging structure preparation method will be based on the structure of the ceramic packaging core board 10 shown.

[0112] Furthermore, as an example, the multilayer co-fired ceramic process includes, but is not limited to, high-temperature calcined ceramic process (HTCC), low-temperature calcined ceramic process (LTCC), and active metal brazing ceramic substrate process (AMB). The material of the metal layer 14 includes, but is not limited to, tungsten, tungsten-molybdenum alloy, and molybdenum-manganese alloy, preferably tungsten. Tungsten can serve as a thermal barrier layer to reduce the direct thermal shock of high temperature to the ceramic substrate 11. Moreover, the thermal expansion coefficients of ceramic and tungsten are relatively close. By designing the tungsten layer, the interfacial stress can be reduced, and delamination or cracking can be avoided.

[0113] As an example, the material of the ceramic substrate 11 can be alumina (Al2O3), aluminum nitride (AlN) or silicon nitride (Si3N4), and the thickness of the ceramic substrate 11 can be 200μm to 5mm. The material and thickness can be selected according to specific functions and application scenarios, and no excessive restrictions are imposed here.

[0114] It should be noted that in this embodiment, the front and back sides of the structure obtained in the subsequent steps of the semiconductor packaging structure preparation method are defined based on the front side 111 and back side 112 of the ceramic substrate 11.

[0115] like Figure 6 As shown, step S2 is then performed to form a first metal layer 16 that fills the first through hole 12.

[0116] As a specific example, a method for forming a first metal layer 16 that fills the first through-hole 12 includes:

[0117] S21, as Figure 4 As shown, a first seed layer 15 is formed on the sidewall of the first via 12, the bottom and sidewalls of the first groove 13, and the surface of the ceramic substrate 11 using processes such as chemical copper deposition, physical vapor deposition, or plasma-enhanced atomic layer deposition. The first seed layer 15 can be one or more metal layers, preferably one copper layer, or two or more metal layers with the upper metal layer being a copper layer. The thickness of the copper layer is preferably 0.5 μm to 1.0 μm.

[0118] S22, as Figure 5 As shown, a first metal layer 16 filling the first through hole 12 is formed by, for example, electroplating or a metal conductive adhesive filling process.

[0119] S23, as Figure 6 As shown, the first seed layer 15 and the first metal layer 16 outside the first via 12 are removed using, for example, an excimer laser etching process or a plasma etching process.

[0120] like Figure 7 As shown, step S3 is then performed to form a plurality of second through holes 17 penetrating the ceramic substrate 11.

[0121] As an example, the second through hole 17 may be formed using laser (picosecond or femtosecond) drilling processes, including but not limited to.

[0122] like Figure 8 As shown, step S4 is then performed, in which the first chip 18 to be packaged is embedded face down into the first groove 13, and the first chip 18 is bonded to the first metal layer 16 through the first bump 19 on the front side.

[0123] As an example, a hot-press bonding process is used to bond the first bump 19 to the first metal layer 16 to form a high-precision, high-strength, and high-reliability interconnect.

[0124] As an example, the size of the first groove 13 formed in step S1 is slightly larger than the size of the first chip 18, so as to embed the first chip 18 into the first groove 13.

[0125] As an example, such as Figure 8 As shown, a filling layer 191 is formed between the front side of the first chip 18 and the first groove 13. The material of the filling layer 191 is an insulating material such as a non-conductive film or a non-conductive paste, which provides additional mechanical support for the first chip 18, prevents the first chip 18 from being damaged by physical impact during use, and can also avoid short circuit failure of the first chip 18.

[0126] like Figure 9 As shown, step S5 is then performed to form a first dielectric layer 20 that fills the second through hole 17 and covers the front and back sides of the resulting structure.

[0127] As a preferred example, the first dielectric layer 20, which fills the second through-hole 17 and covers the front and back sides of the resulting structure, is formed using a vacuum hot pressing process. This improves the filling quality and enhances the interface bonding strength. Preferably, in this embodiment, the first dielectric layer 20 is ABF (Ajinomoto Build-up Film) to achieve fine wiring, improve the input / output pin (I / O) density and wiring flexibility of the package structure. The thickness of the first dielectric layer 20 can be exemplarily 20μm to 1mm, and can be set as needed in practice. No excessive limitation is made here.

[0128] like Figure 10 As shown, step S6 is then performed to form a third through-hole 21 that penetrates the first dielectric layer 20 and to form a micro-blind hole 22 that penetrates the first dielectric layer 20 on the back side of the obtained structure and exposes the surface of the first metal layer 16.

[0129] As an example, the third through hole 21 and the micro blind hole 22 can be formed using CO2 laser drilling or UV laser drilling to achieve precise aperture control, meet the requirements of different aperture ranges of the third through hole 21 and the micro blind hole 22, ensure dimensional accuracy and consistency, and meet the requirements of semiconductor packaging for fine structure and reliable performance. The cross-sectional diameter of the formed third through hole 21 is, for example, 100μm to 1mm, and the cross-sectional diameter of the micro blind hole 20 is, for example, 10μm to 500μm.

[0130] like Figure 12 As shown, step S7 is then performed to form a second metal layer 24 that fills the third through hole 21 and the micro blind hole 22 and covers the front and back sides of the obtained structure.

[0131] As a specific example, such as Figure 11 and Figure 12 As shown, the method for forming a second metal layer 24 that fills the third through-hole 21 and the micro-blind hole 22 and covers the front and back sides of the resulting structure includes:

[0132] S71, such as Figure 11 As shown, by way of example, a second seed layer 23 is deposited on the sidewall of the third via 21, the sidewall and bottom wall of the micro-blind via 22, and the surface of the first dielectric layer 20 by chemical copper deposition, physical vapor deposition or plasma-enhanced atomic layer deposition. The second seed layer 23 can be one or more metal layers, preferably one copper layer, or two or more metal layers with the upper metal layer being a copper layer. The thickness of the copper layer is preferably 0.5 μm to 1.0 μm.

[0133] S72, such as Figure 12As shown, an electroplating process is used to form a second metal layer 24 that fills the third through hole 21 and the micro blind hole 22, and covers the front and back sides of the obtained structure. The second metal layer 24 is preferably electroplated with copper. The thickness of the second metal layer 24 covering the front and back sides of the obtained structure is, for example, 10 μm to 1 mm.

[0134] like Figure 13 As shown, step S8 is then performed, where the second metal layer 24 is etched using photolithography, retaining the second metal layer 24 within the third via 21 and its predetermined areas at both ends, as well as the second metal layer 24 within the micro-blind via 22 and its predetermined area below it. It should be noted that the second metal layer 24 retained in this step is not limited to the aforementioned areas, but also exists in other circuit regions of the semiconductor package structure. Figure 13 (Not shown).

[0135] As an example, the second metal layer 24 is etched using photolithography, and the process also includes steps of thinning and planarizing the surface of the second metal layer 24 to reduce the difficulty of the photolithography process and improve the film quality.

[0136] like Figure 14 As shown, step S9 is then performed to form at least one augmentation layer on the front and back sides of the obtained structure. The augmentation layer is electrically connected to the second metal layer 24. The outer augmentation layer 26 in the augmentation layer includes a second dielectric layer 261 and a third metal layer 262.

[0137] As an example, the added layer includes an added layer dielectric layer and an added layer metal layer. Preferably, an added layer seed layer is formed below the added layer metal layer.

[0138] As an example, the additive layer can be fabricated through processes such as laminating the additive dielectric layer, laser drilling, desmearing, plated hole metallization (PTH), dry film lamination, exposure, development, electroplating, film removal, and flash etching. The above process flow can be repeated according to the target number of stacks. Figure 14 As shown, this embodiment illustrates an example with three additional layers 25 formed on both the front and back sides of the structure. It should be noted that, located as shown... Figure 14 The outermost layer of the structure shown is the outer layer 26. Preferably, in this embodiment, the added dielectric layer (including the second dielectric layer 261) is ABF to achieve fine-grained wiring, improve I / O density and wiring flexibility.

[0139] like Figure 15 As shown, step S10 is then performed, in which at least one second groove 27 is formed at a predetermined position in the second dielectric layer 261 on the front side of the obtained structure using, for example, a laser grooving process.

[0140] like Figure 16 As shown, step S11 is then performed, in which the second chip 28 to be packaged is embedded in the second groove 27 with its front side facing up, and the front side of the second chip 28 has a second protrusion 29.

[0141] As an example, the size of the second groove 27 formed in step S10 is slightly larger than the size of the second chip 28, so as to embed the second chip 28 into the second groove 27.

[0142] like Figure 17 As shown, step S12 is then performed, forming an upper wiring structure 31 on the front side of the obtained structure. The upper wiring structure 31 includes a third dielectric layer 311 and a fourth metal layer 312. The fourth metal layer 312 is electrically connected to the second bump 29 and the added layer. A lower wiring structure 32 is formed on the back side of the obtained structure. The lower wiring structure 32 includes a fourth dielectric layer 321 and a fifth metal layer 322. The fifth metal layer 322 is electrically connected to the added layer.

[0143] As an example, both the third dielectric layer 311 and the fourth dielectric layer 321 are ABF to achieve fine routing, improve input / output pin (I / O) density and routing flexibility.

[0144] As an example, the upper wiring structure 31 and the lower wiring structure 32 can be fabricated through processes such as laminating a dielectric layer, laser drilling, Desmearing, PTH, applying dry film, exposure, development, electroplating, film removal, and flash etching.

[0145] like Figure 18 As shown, step S13 is then performed to form a plurality of metal pillars 34 on the fourth metal layer 312.

[0146] As a preferred example, a method for forming a plurality of metal pillars 34 on the fourth metal layer 312 includes:

[0147] S131, forming a first solder resist layer 33 covering the front side of the resulting structure.

[0148] S132, forming a plurality of metal pillars 34 that penetrate the first solder mask layer 33 and are in contact with the fourth metal layer 312. The metal pillars 34 can be formed, for example, by electroplating copper, nickel or tin.

[0149] Step S13, by way of example, also includes forming a second solder mask layer 35 on the back side of the obtained structure, and opening a window in the second solder mask layer 35 to expose the surface of the fifth metal layer 322 to form a pad 36.

[0150] As a further example, in step S131, the first solder resist layer 33 and the through hole of a preset size can be formed by processes such as solder resist coating, solder resist exposure, solder resist development, and solder resist windowing. The solder resist windowing method can be, for example, ultraviolet (UV) windowing to improve the windowing accuracy. In step S132, copper is electroplated in the through hole to form the metal pillar 34. The second solder resist layer 35 and the solder pad 36 can be formed by processes such as solder resist coating, solder resist exposure, and solder resist development.

[0151] As a further example, such as Figure 19 As shown, a second solder resist layer 35 is formed on the back side of the obtained structure. After the second solder resist layer 35 is opened to expose the surface of the fifth metal layer 322, the method further includes a step of surface treatment of the fifth metal layer 322 to form a surface treatment layer 39.

[0152] As a further example, the fifth metal layer 322 can be surface-treated using ENEPIG (electrochemical nickel plating and electroless palladium plating), OSP (organic solder mask) or ENIG (electro-free nickel immersion gold plating) processes to improve the soldering performance of the pads 36 and prevent oxidation and corrosion.

[0153] like Figure 20 As shown, step S14 is then performed to bond the third chip 37 to be packaged to the metal pillar 34.

[0154] Specifically, the third chip 37 is thermally bonded to the metal pillar 34 via the third bump 38 on the front side to form a high-precision, high-strength, and high-reliability interconnect.

[0155] As an example, such as Figure 20 As shown, after step S13, the method further includes the step of implanting solder balls 40 onto the solder pad 36.

[0156] As a further example, the solder balls 40 can be formed using a solder paste printing process or a ball-planting process. The formed solder balls 40 are solder balls used to achieve contact connection between the package structure and the PCB (Printed Circuit Board).

[0157] This completes the fabrication of the semiconductor packaging structure in this embodiment, and the formed semiconductor packaging structure is as follows: Figure 16 As shown.

[0158] This embodiment also provides a semiconductor packaging structure, such as Figure 20 As shown, the semiconductor package structure can be prepared using the above-described method, but is not limited to it; other suitable methods may also be used. The semiconductor package structure includes:

[0159] A ceramic encapsulation core board 10, the ceramic encapsulation core board 10 having opposing front and back sides;

[0160] The first chip 18 is embedded face down inside the front of the ceramic encapsulation core board 10;

[0161] At least one augmentation layer is formed on the front and back sides of the ceramic encapsulation core board 10, the augmentation layer including an outer augmentation layer 26 located on the outer side, the augmentation layer being electrically connected to the first chip 18;

[0162] The second chip 28 is embedded within the external layer 26 on the front side;

[0163] An upper wiring structure 31 is formed on the second chip 28 and the outer layer 26 on the front side, and the upper wiring structure 31 is electrically connected to the second chip 28 and the outer layer.

[0164] A lower layer wiring structure 32 is formed below the outer layer 26 on the back side, and the lower layer wiring structure 32 is electrically connected to the layer.

[0165] Several metal pillars 34 that are in contact with and connected to the upper wiring structure 31;

[0166] A third chip 37 is bonded to the metal pillar 34.

[0167] The semiconductor packaging structure of this embodiment uses a ceramic packaging core as a basic support and embeds a first chip inside it to form a multi-layer add-on structure, including an outer add-on layer, an upper wiring structure, and a lower wiring structure. This significantly improves the wiring density and integration. By embedding a second chip into the outer add-on layer and forming an upper wiring structure electrically connected to the add-on layer, the packaging efficiency is further optimized. Then, the metal pillars are bonded to the third chip, completing the high-density integration and high-reliability interconnection of multiple chips. This structure effectively solves the warpage and heat dissipation problems of high-layer-count packaging substrates, significantly improves the thermal conductivity and integration of the packaging structure, and meets the requirements of modern semiconductor devices for high power, high frequency, and high integration.

[0168] As an example, such as Figure 20 As shown, the semiconductor packaging structure further includes:

[0169] A first solder mask layer 33 covers the upper wiring structure 31, and the metal pillar 34 penetrates the first solder mask layer 33 and is in contact with the upper wiring structure 31.

[0170] The second solder mask layer 35 covers the lower wiring structure 32, and the solder pad 36 formed by opening the second solder mask layer 35;

[0171] Solder balls 40 are embedded in the solder pad 36.

[0172] As an example, such as Figure 20 As shown, this embodiment demonstrates the example of forming three additional layers 25 on both the front and back sides of the structure. The actual number of additional layers can be designed according to requirements, and no excessive restrictions are imposed here.

[0173] As an example, the beneficial effects that the semiconductor packaging structure of this embodiment can achieve can be found in the detailed description of the preparation method, and will not be repeated here.

[0174] In summary, the semiconductor packaging structure and its fabrication method of the present invention utilize a ceramic packaging core board as a basic support. A first groove is formed on the ceramic substrate, and a first through-hole is formed below it. A first chip is embedded face down in the first groove, and a first metal layer within the first through-hole achieves bonding connection with the first chip, thereby improving wiring density and integration. By forming a multi-layered build-up structure, the number of wiring layers is increased, meeting the high-layer packaging requirements of high-performance processors. A second groove is set in the build-up layer, and a second chip is embedded therein to further improve the wiring structure. Finally, metal pillars are formed on the upper wiring structure, and a third chip is bonded to the metal pillars. This fabrication method achieves 3D integration of multiple chips with the ceramic core board system, effectively solving the warpage and deformation problem of high-layer packaging substrates, significantly improving the thermal conductivity of the packaging structure, and increasing wiring density by embedding chips on the ceramic core board. Multi-chip packaging greatly improves the integration and performance of the ceramic core board structure, meeting the demands of modern semiconductor devices for high power, high frequency, and high integration, and significantly improving the overall performance and stability of semiconductor packaging. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has high industrial applicability.

[0175] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for fabricating a semiconductor packaging structure, characterized in that, The preparation method includes: S1, a ceramic encapsulation core board is provided. The ceramic encapsulation core board includes a ceramic substrate. The ceramic substrate has a front side and a back side. The ceramic encapsulation core board also includes at least one first groove formed at a preset position on the front side of the ceramic substrate and a plurality of first through holes penetrating the ceramic substrate from a preset position at the bottom of the first groove. S2, forming a first metal layer that fills the first through hole; S3, forming a plurality of second through holes penetrating the ceramic substrate; S4, the first chip to be packaged is embedded into the first groove with its front side facing down, and the first chip is bonded to the first metal layer through the first bump on its front side. S5, forming a first dielectric layer that fills the second through hole and covers the front and back sides of the obtained structure; S6, forming a third through-hole penetrating the first dielectric layer, forming a micro-blind hole penetrating the first dielectric layer on the back side of the obtained structure and exposing the surface of the first metal layer; S7, forming a second metal layer that fills the third through hole and the micro blind hole and covers the front and back sides of the obtained structure; S8, the second metal layer is etched using photolithography, while retaining the second metal layer in the third through hole and the preset areas at both ends, as well as the second metal layer in the micro blind hole and the preset area below it; S9, at least one layer is formed on the front and back sides of the obtained structure, the layer is electrically connected to the second metal layer, and the outer layer of the layer includes a second dielectric layer and a third metal layer; S10, at least one second groove is formed at a predetermined position in the second dielectric layer on the front side of the obtained structure; S11, the second chip to be packaged is embedded into the second groove with the front side facing up, and the front side of the second chip has a second protrusion; S12, an upper layer wiring structure is formed on the front side of the obtained structure. The upper layer wiring structure includes a third dielectric layer and a fourth metal layer. The fourth metal layer is electrically connected to the second bump and the added layer. A lower layer wiring structure is formed on the back side of the obtained structure. The lower layer wiring structure includes a fourth dielectric layer and a fifth metal layer. The fifth metal layer is electrically connected to the added layer. S13, a plurality of metal pillars are formed on the fourth metal layer; S14, the third chip to be packaged is bonded to the metal pillar.

2. The method for preparing a semiconductor packaging structure according to claim 1, characterized in that: In step S13, the method for forming a plurality of metal pillars on the fourth metal layer includes: S131, forming a first solder resist layer covering the front side of the obtained structure; S132, forming a plurality of metal pillars that penetrate the first solder resist layer and are in contact with the fourth metal layer; Step S13 further includes forming a second solder resist layer on the back side of the obtained structure, and opening a window in the second solder resist layer to expose the surface of the fifth metal layer to form a solder pad. After step S13, the method further includes the step of implanting solder balls on the solder pads.

3. The method for fabricating a semiconductor packaging structure according to claim 1, characterized in that: The ceramic encapsulation core board is formed using a multilayer co-fired ceramic process, and the ceramic encapsulation core board further includes at least one metal layer embedded in the ceramic substrate.

4. The method for preparing a semiconductor packaging structure according to claim 1, characterized in that: The ceramic encapsulation core board is formed using 3D printing or laser drilling.

5. The method for fabricating a semiconductor packaging structure according to claim 1, characterized in that: The ceramic substrate is made of Al2O3, AlN, or Si3N4.

6. The method for fabricating a semiconductor packaging structure according to claim 1, characterized in that: The first dielectric layer, the second dielectric layer, the third dielectric layer, and the fourth dielectric layer are all ABF.

7. The method for fabricating a semiconductor packaging structure according to claim 1, characterized in that: In step S2, the method for forming a first metal layer that fills the first through-hole includes: S21, a first seed layer is formed on the sidewall of the first through hole, the bottom wall and sidewall of the first groove, and the surface of the ceramic substrate; S22, forming a first metal layer that fills the first through hole; S23, remove the first seed layer and the first metal layer outside the first through hole.

8. The method for preparing a semiconductor packaging structure according to claim 1, characterized in that: In step S5, a first dielectric layer is formed by using a vacuum hot pressing process to fill the second through hole and cover the front and back sides of the obtained structure.

9. The method for preparing a semiconductor packaging structure according to claim 1, characterized in that, In step S7, the method for forming a second metal layer that fills the third through-hole and the micro-blind hole and covers the front and back sides of the resulting structure includes: S71, deposit a second seed layer on the sidewall of the third through hole, the sidewall and bottom wall of the micro blind hole, and the surface of the first dielectric layer; S72, an electroplating process is used to form a second metal layer that fills the third through hole and the micro blind hole, and covers the front and back sides of the resulting structure.

10. A semiconductor packaging structure, characterized in that, The semiconductor package structure is prepared by the method for preparing the semiconductor package structure according to any one of claims 1 to 9, wherein the semiconductor package structure comprises: A ceramic encapsulation core board, wherein the ceramic encapsulation core board has a front side and a back side facing each other; The first chip is embedded face down inside the front of the ceramic encapsulation core board; At least one augmentation layer is formed on the front and back sides of the ceramic encapsulation core board, the augmentation layer including an outer augmentation layer located on the outer side, and the augmentation layer is electrically connected to the first chip; A second chip embedded within the external layer on the front side; An upper wiring structure is formed on the second chip and the outer layer on the front side, and the upper wiring structure is electrically connected to the second chip and the outer layer. A lower layer wiring structure is formed below the outer layer on the back side, and the lower layer wiring structure is electrically connected to the layer. Several metal pillars that are in contact with and connected to the upper wiring structure; A third chip bonded to the metal pillar.

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