Solar cell, photovoltaic module and method for preparing solar cell

Abstract

This application relates to a solar cell, a photovoltaic module, and a method for fabricating a solar cell. The solar cell includes: a semiconductor substrate having a first side and a second side disposed opposite to each other; a conductive layer disposed on one side of the first side; the conductive layer is made of a transparent conductive oxide, wherein at least a portion of the conductive layer has a surface roughness of less than or equal to 10 nm on the side facing away from the semiconductor substrate. Therefore, the solar cell, photovoltaic module, and method for fabricating a solar cell provided by this application have a low series resistance.

Description

Technical Field

[0001] This application relates to the field of photovoltaic technology, and in particular to solar cells, photovoltaic modules, and methods for preparing solar cells. Background Technology

[0002] Solar cells, also known as photovoltaic cells, are semiconductor devices that directly convert sunlight into electrical energy. Because they are green and environmentally friendly products that do not cause pollution, and because solar energy is a renewable resource, solar cells are a new type of battery with broad development prospects.

[0003] In related technologies, heterojunction back contact (HBC) solar cells place the metal electrodes on the back side of the cell, so that the light-facing side of the cell is not blocked by the metal electrodes, increasing the light absorption area and thus improving the photoelectric conversion efficiency. However, the series resistance of the aforementioned HBC cells needs to be improved. Summary of the Invention

[0004] Therefore, it is necessary to provide a solar cell, a photovoltaic module, and a method for fabricating a solar cell with low series resistance.

[0005] In a first aspect, embodiments of this application provide a solar cell, comprising:

[0006] A semiconductor substrate having a first surface and a second surface disposed opposite to each other;

[0007] A conductive layer is disposed on one side of the first surface; the material of the conductive layer includes a transparent conductive oxide.

[0008] In this case, the surface roughness of at least a portion of the conductive layer on the side facing away from the semiconductor substrate is less than or equal to 10 nm.

[0009] The solar cell proposed in this application has a low series resistance because the surface roughness of at least a portion of the conductive layer on the side facing away from the semiconductor substrate is less than or equal to 10 nm.

[0010] In one embodiment, the series resistance of the solar cell is less than or equal to 0.55 Ω·cm. 2 .

[0011] In one embodiment, the solar cell further includes a conductive sacrificial layer;

[0012] A conductive sacrificial layer is disposed on the side of the conductive layer that is away from the semiconductor substrate.

[0013] In one embodiment, the solar cell includes an electrode disposed on the side of the conductive sacrificial layer away from the semiconductor substrate and electrically connected to the conductive sacrificial layer. The contact resistance between the electrode and the conductive sacrificial layer is in the range of 1 mΩ·cm. 2 -3mΩ·cm 2 .

[0014] In one embodiment, the solar cell includes an electrode disposed on the side of the conductive layer opposite to the semiconductor substrate and electrically connected to the conductive layer, wherein the contact resistance between the electrode and the conductive layer is less than or equal to 1 mΩ·cm. 2 -3mΩ·cm 2 .

[0015] In one embodiment, the conductive layer is made of an alkali-resistant material, and the side of the conductive layer facing away from the semiconductor substrate is configured as an alkali-resistant side; and / or,

[0016] The materials for the conductive sacrificial layer include amphoteric oxides.

[0017] In one embodiment, the thickness of the conductive layer ranges from 30 nm to 110 nm; and / or,

[0018] The thickness of the conductive sacrificial layer ranges from 5 nm to 10 nm; and / or,

[0019] The thickness of the conductive layer is greater than the thickness of the conductive sacrificial layer.

[0020] In one embodiment, the material of the conductive layer includes an indium-containing transparent conductive material; and / or,

[0021] The materials used for the conductive sacrificial layer include indium-free transparent conductive materials.

[0022] In one embodiment, the solar cell includes a first polarity region and a second polarity region with different polarities, and a conductive layer is located in the first polarity region and the second polarity region. The conductive layer located in the first polarity region is configured as a first conductive layer, and the conductive layer located in the second polarity region is configured as a second conductive layer. The first conductive layer and the second conductive layer are arranged alternately.

[0023] The solar cell includes a first doped semiconductor layer and a second doped semiconductor layer. The first doped semiconductor layer is located in a first polar region and disposed between a first conductive layer and a semiconductor substrate. The second doped semiconductor layer is located in a second polar region and disposed between a second conductive layer and a semiconductor substrate.

[0024] In one embodiment, the conductive layer includes multiple sub-conductive layers, which are stacked along the thickness direction of the semiconductor substrate.

[0025] The multilayer subconductive layer includes a first subconductive layer and a second subconductive layer, which are arranged alternately. The subconductive layer that is furthest from the semiconductor substrate is the first subconductive layer, which includes an alkali-resistant material.

[0026] Under preset acid etching conditions, the etching rate of the second sub-conductive layer is greater than that of the first sub-conductive layer.

[0027] In one embodiment, the conductive sacrificial layer includes multiple sub-conductive sacrificial layers, which are stacked along the thickness direction of the semiconductor substrate;

[0028] Under preset acidic etching conditions, the etching rate of the multilayer sub-conductive sacrificial layer increases sequentially along the direction from the conductive sacrificial layer to the conductive layer; and / or,

[0029] Under preset alkaline etching conditions, the etching rate of the multilayer sub-conductive sacrificial layer decreases sequentially along the direction from the conductive sacrificial layer to the conductive layer.

[0030] In one embodiment, the thickness of the multilayer subconductive sacrificial layer increases sequentially along the direction from the conductive sacrificial layer to the conductive layer.

[0031] Secondly, embodiments of this application provide a photovoltaic module, including the solar cell of the first aspect.

[0032] Thirdly, embodiments of this application provide a method for preparing a solar cell, comprising:

[0033] A semiconductor substrate is provided, the semiconductor substrate having a first surface and a second surface disposed opposite to each other;

[0034] A conductive material layer and a conductive sacrificial material layer are sequentially stacked on one side of the first surface;

[0035] A mask layer is formed on the side of the partially conductive sacrificial material layer that faces away from the semiconductor substrate;

[0036] Simultaneously remove the conductive material layer and conductive sacrificial material layer exposed outside the mask layer, and retain the conductive material layer and conductive sacrificial material layer covered by the mask layer. The retained conductive material layer forms a conductive layer.

[0037] Remove the mask layer and at least a portion of the thickness of the conductive sacrificial material layer.

[0038] The method for fabricating a solar cell provided in this application uses a conductive sacrificial material layer as a sacrificial layer. When removing the mask layer, at least a portion of the conductive sacrificial material layer is removed, thereby completely removing the mask layer. This allows the conductive layer and the mask layer to be completely separated, achieving residue-free removal of the mask layer. This prevents residual mask layers from hindering carrier transport and from adversely affecting the series resistance of the solar cell, resulting in a lower series resistance of the solar cell.

[0039] In one embodiment, removing the mask layer and at least a portion of the thickness of the conductive sacrificial material layer includes: simultaneously removing the mask layer and at least a portion of the thickness of the conductive sacrificial material layer.

[0040] In one embodiment, the mask layer comprises an acid-resistant material; and / or,

[0041] The conductive material layer includes an alkali-resistant material, and the side of the conductive material layer facing away from the semiconductor substrate is configured as an alkali-resistant side; and / or,

[0042] The materials used in the conductive sacrificial material layer include amphoteric oxides.

[0043] In one embodiment, the simultaneous removal of the conductive material layer and the conductive sacrificial material layer exposed outside the mask layer includes: under preset acid etching conditions, simultaneously removing the conductive material layer and the conductive sacrificial material layer exposed outside the mask layer.

[0044] In one embodiment, under preset acid etching conditions, the ratio of the etching rate of either the conductive material layer or the conductive sacrificial material layer to the etching rate of the mask layer is greater than or equal to 100.

[0045] In one embodiment, the etching reagent for the preset acidic etching conditions includes hydrochloric acid, with a volume concentration ranging from 20% to 37%; and / or,

[0046] The preset acid etching temperature range is 20℃-40℃; and / or,

[0047] The preset acid etching time range is 100s-800s.

[0048] In one embodiment, removing the mask layer and at least a portion of the thickness of the conductive sacrificial material layer includes: removing the mask layer and at least a portion of the thickness of the conductive sacrificial material layer under preset alkaline etching conditions.

[0049] In one embodiment, under preset alkaline etching conditions, the ratio of the etching rate of either the mask layer or the conductive sacrificial material layer to the etching rate of the conductive material layer is greater than or equal to 100.

[0050] In one embodiment, the etching reagent for the preset alkaline etching conditions includes a hydroxide with a volume concentration ranging from 1% to 5%; and / or,

[0051] The etching reagents used in the preset alkaline etching conditions include hydrogen peroxide, with a volume concentration ranging from 1% to 10%; and / or,

[0052] The preset alkaline etching conditions have a temperature range of 30℃-80℃; and / or,

[0053] The preset time range for alkaline etching conditions is 100s-400s.

[0054] In one embodiment, removing the mask layer and at least a portion of the thickness of the conductive sacrificial material layer includes:

[0055] Remove the mask layer and a portion of the conductive sacrificial material layer, leaving another portion of the conductive sacrificial material layer, and form a conductive sacrificial layer.

[0056] In one embodiment, removing the mask layer and at least a portion of the thickness of the conductive sacrificial material layer includes:

[0057] Remove the mask layer and all conductive sacrificial material layers to expose the conductive layer.

[0058] In one embodiment, the thickness of the conductive sacrificial material layer ranges from 5 nm to 20 nm; and / or,

[0059] The sum of the thicknesses of the conductive material layer and the conductive sacrificial material layer ranges from 35 nm to 130 nm; and / or,

[0060] The ratio of the thickness of the conductive material layer to the sum of the thicknesses of the conductive material layer and the conductive sacrificial material layer ranges from 80% to 90%; and / or,

[0061] The ratio of the conductive sacrificial material layer to the sum of the thicknesses of the conductive material layer and the conductive sacrificial material layer ranges from 10% to 20%; and / or,

[0062] The thickness of the conductive material layer is greater than the thickness of the conductive sacrificial material layer.

[0063] In one embodiment, the conductive sacrificial material layer includes multiple sub-conductive sacrificial material layers, which are stacked along the thickness direction of the semiconductor substrate;

[0064] Under preset acidic etching conditions, the etching rate of the multilayer sub-conductive sacrificial material layer increases sequentially along the direction from the conductive sacrificial material layer to the conductive material layer; and / or,

[0065] Under preset alkaline etching conditions, the etching rate of the multilayer sub-conductive sacrificial material layer decreases sequentially from the conductive sacrificial material layer to the conductive material layer.

[0066] In one embodiment, the thickness of the multilayer subconductive sacrificial material layer increases sequentially along the direction from the conductive sacrificial material layer to the conductive material layer.

[0067] Fourthly, embodiments of this application provide a solar cell prepared using the solar cell preparation method of the third aspect. Attached Figure Description

[0068] Figure 1 A cross-sectional view of a solar cell provided in an embodiment of this application.

[0069] Figure 2 Another cross-sectional view of a solar cell provided in an embodiment of this application.

[0070] Figure 3 A top view of a solar cell provided in an embodiment of this application.

[0071] Figure 4 Another top view of a solar cell provided in an embodiment of this application.

[0072] Figure 5 This is a schematic diagram of the structure after providing a semiconductor substrate, as provided in an embodiment of this application.

[0073] Figure 6 This is a schematic diagram of the structure after the formation of the conductive sacrificial material layer, as provided in an embodiment of this application.

[0074] Figure 7 This is a schematic diagram of the structure after the mask layer is formed, as provided in an embodiment of this application.

[0075] Figure 8 This is another structural diagram after the formation of the mask layer, provided in an embodiment of this application.

[0076] Figure 9 This is a schematic diagram of the structure after removing the conductive material layer and the conductive sacrificial material layer exposed outside the mask layer, as provided in an embodiment of this application.

[0077] Figure 10 This is a schematic diagram of the structure after removing the mask layer and a portion of the conductive sacrificial material layer, as provided in an embodiment of this application.

[0078] Figure 11 This is another structural diagram of the embodiment provided in this application after removing the mask layer and a conductive sacrificial material layer of a certain thickness.

[0079] Figure 12This is a schematic diagram of the structure after removing the mask layer and all conductive sacrificial material layers, as provided in an embodiment of this application.

[0080] Figure 13 This is a schematic flowchart illustrating the method for fabricating a solar cell according to an embodiment of this application.

[0081] Figure 14 A scanning electron microscope (SEM) image of the side of the first transparent conductive layer of the N-type region facing away from the semiconductor substrate, as provided in the related art.

[0082] Figure 15 A scanning electron microscope (SEM) image of the side of the first conductive layer facing away from the semiconductor substrate, provided in an embodiment of this application.

[0083] Explanation of reference numerals in the attached figures:

[0084] 100, Solar cell; 100a, First polar region; 100b, Second polar region; 110, Semiconductor substrate; 111, First surface; 112, Second surface; 121, First doped semiconductor layer; 122, Second doped semiconductor layer; 131, First passivation layer; 132, Second passivation layer; 133, Third passivation layer; 140, Conductive layer; 140a, Conductive material layer; 141, First conductive layer; 142, Second conductive layer; 1431, First sub-conductive layer; 1432, Second sub-conductive layer; 150, Electrode; 151, First electrode; 152, Second electrode; 160, Antireflection layer; 170, Conductive sacrificial layer; 170a, Conductive sacrificial material layer; 171, First conductive sacrificial layer; 172, Second conductive sacrificial layer; 173, Sub-conductive sacrificial layer; 173a, Sub-conductive sacrificial material layer; 180, Mask layer. Detailed Implementation

[0085] To make the above-mentioned objectives, features, and advantages of this application more apparent and understandable, the specific embodiments of this application are described in detail below with reference to the accompanying drawings. Many specific details are set forth in the following description to provide a thorough understanding of this application. However, this application can be implemented in many other ways different from those described herein, and those skilled in the art can make similar modifications without departing from the spirit of this application. Therefore, this application is not limited to the specific embodiments disclosed below.

[0086] Furthermore, where the terms "first" and "second" appear, these terms are for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined with "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, where the term "multiple" appears, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0087] In this application, unless otherwise expressly specified and limited, the use of descriptions such as "above" or "below" the second feature indicates that the first and second features are in direct contact or indirect contact via an intermediate medium. Furthermore, "above," "on top of," and "over" the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. Similarly, "below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.

[0088] It should be noted that if an element is referred to as being "fixed to" or "set on" another element, it can be directly on the other element or there may be an intervening element. If an element is considered to be "connected to" another element, it can be directly connected to the other element or there may be an intervening element. If so, the terms "vertical," "horizontal," "upper," "lower," "left," "right," and similar expressions used in this application are for illustrative purposes only and do not represent the only possible implementation.

[0089] In related technologies, HBC cells have N-type regions and P-type regions. HBC cells include a semiconductor substrate with a first surface and a second surface disposed opposite to each other. A tunneling oxide layer and a polycrystalline silicon layer are sequentially disposed on the first surface located in the N-type region, and an intrinsic amorphous silicon layer and a microcrystalline silicon layer are sequentially disposed on the first surface located in the P-type region.

[0090] In the fabrication process of an HBC battery, a tunneling oxide layer and a polycrystalline silicon layer are first formed on the first surface of the N-type region, and an intrinsic amorphous silicon layer and a microcrystalline silicon layer are formed on the first surface of the P-type region. Then, a transparent conductive layer is formed on one side of the first surface, and a mask layer is formed on the transparent conductive layer. The transparent conductive layer exposed outside the mask layer is removed, and the remaining transparent conductive layer forms a first transparent conductive layer and a second transparent conductive layer. The first transparent conductive layer is located in the N-type region, and the second transparent conductive layer is located in the P-type region, with the first and second transparent conductive layers spaced apart. Afterward, the mask layer is removed. The material of the mask layer may include ink.

[0091] However, when using ink to form the mask layer, the ink needs to be dried. The dried ink is in close contact with the transparent conductive layer, which increases the difficulty of removing the mask layer from the transparent conductive layer. This makes it easy for the mask layer to remain on the transparent conductive layer. The mask layer will hinder the transport of charge carriers, resulting in an increase in the contact resistance between the transparent conductive layer and the subsequently formed metal electrode, which in turn increases the series resistance of the HBC battery.

[0092] To address the aforementioned issues, this application provides a solar cell, a photovoltaic module, and a method for fabricating a solar cell, wherein the series resistance of the solar cell is low.

[0093] The following will combine Figures 1-13 The solar cell 100, photovoltaic module, and method for preparing the solar cell 100 provided in the embodiments of this application will be described.

[0094] This application provides a method for fabricating a solar cell 100, see [link to relevant documentation]. Figure 13 The method for preparing the solar cell 100 may include:

[0095] S100: Provides a semiconductor substrate having a first side and a second side disposed opposite to each other.

[0096] See Figure 5 A semiconductor substrate 110 is provided, which may have a first surface 111 and a second surface 112 disposed opposite to each other along the thickness direction of the semiconductor substrate 110. The semiconductor substrate 110 can provide support for subsequently formed film layers.

[0097] For example, at least one of the first surface 111 and the second surface 112 of the semiconductor substrate 110 may be texturized to form a textured structure on the first surface 111 and the second surface 112.

[0098] For example, the textured structure can be prepared using wet chemical etching, such as using an alkaline solution, like NaOH solution. Alternatively, the textured structure can be prepared using chemical etching, laser etching, mechanical methods, or plasma etching.

[0099] For example, before texturing the semiconductor substrate 110, at least one of the first surface 111 and the second surface 112 may be polished.

[0100] S200: A conductive material layer and a conductive sacrificial material layer are sequentially stacked on one side of the first surface.

[0101] See Figure 6 After providing the semiconductor substrate 110, a conductive material layer 140a and a conductive sacrificial material layer 170a may be sequentially stacked on the first surface 111.

[0102] For example, a conductive material layer 140a can be formed using a deposition process.

[0103] For example, the deposition process may include atomic layer deposition (ALD), physical vapor deposition (PVD), chemical vapor deposition (CVD), or reactive plasma deposition (RPD), etc. Other structural layers in the embodiments of this disclosure may also be formed by deposition, which will not be described in detail here.

[0104] S300: A mask layer is formed on the side of a partially conductive sacrificial material layer that faces away from the semiconductor substrate.

[0105] See Figure 7 After the conductive material layer 140a and the conductive sacrificial material layer 170a are sequentially stacked on the first surface 111, a mask layer 180 may be formed on the side of the conductive sacrificial material layer 170a that is away from the semiconductor substrate 110.

[0106] For example, the material of the mask layer 180 may include at least one of ink and photoresist.

[0107] For example, the mask layer 180 can be formed by printing (e.g., screen printing).

[0108] S400: Simultaneously remove the conductive material layer and conductive sacrificial material layer exposed outside the mask layer, retain the conductive material layer and conductive sacrificial material layer covered by the mask layer, and the retained conductive material layer forms a conductive layer.

[0109] See Figure 9 After forming a mask layer 180 on the side of the conductive sacrificial material layer 170a facing away from the semiconductor substrate 110, the conductive material layer 140a and the conductive sacrificial material layer 170a exposed outside the mask layer 180 may be removed simultaneously, while retaining the conductive material layer 140a and the conductive sacrificial material layer 170a covered by the mask layer 180. The retained conductive material layer 140a forms the conductive layer 140. Thus, the conductive material layer 140a and the conductive sacrificial material layer 170a exposed outside the mask layer 180 can be removed during the same patterning process, simplifying the patterning process of the conductive material layer 140a and the conductive sacrificial material layer 170a and reducing fabrication costs.

[0110] S500: Remove the mask layer and at least a portion of the thickness of the conductive sacrificial material layer.

[0111] See Figure 10 and 12After simultaneously removing the conductive material layer 140a and the conductive sacrificial material layer 170a exposed outside the mask layer 180, the process may include removing the mask layer 180 and at least a portion of the thickness of the conductive sacrificial material layer 170a. Thus, because the conductive sacrificial material layer 170a is disposed between the mask layer 180 and the conductive material layer 140a, the conductive sacrificial material layer 170a can completely separate the mask layer 180 and the conductive layer 140a, preventing residues from easily remaining on the conductive sacrificial material layer 170a even if the mask layer 180 is in close contact with the conductive sacrificial material layer 170a. On material layer 170a, by using conductive sacrificial material layer 170a as a sacrificial layer, at least a portion of the thickness of conductive sacrificial material layer 170a is removed when removing mask layer 180. This allows for complete removal of mask layer 180, enabling complete separation of conductive layer 140 and mask layer 180. This achieves residue-free removal of mask layer 180, preventing residual mask layer 180 from hindering carrier transport and negatively impacting the series resistance of solar cell 100, resulting in a lower series resistance of solar cell 100. For example, since there is no residual mask layer 180 in solar cell 100, the series resistance of solar cell 100 can be less than or equal to 0.55 Ω·cm. 2 .

[0112] In some embodiments, after the conductive material layer 140a and the conductive sacrificial material layer 170a are sequentially stacked on the first surface 111, the conductive material layer 140a and the conductive sacrificial material layer 170a may be subjected to an annealing process. For example, the annealing temperature may be 200°C and the annealing time may be 10 minutes.

[0113] In some embodiments, removing the mask layer 180 and the conductive sacrificial material layer 170a with at least a partial thickness may include simultaneously removing the mask layer 180 and the conductive sacrificial material layer 170a with at least a partial thickness. In this way, the mask layer 180 and the conductive sacrificial material layer 170a with at least a partial thickness can be removed in the same removal process, which can simplify the removal process of the mask layer 180 and the conductive sacrificial material layer 170a with at least a partial thickness and reduce the manufacturing cost.

[0114] In other embodiments, removing the mask layer 180 and the conductive sacrificial material layer 170a of at least a partial thickness may include removing the mask layer 180 and the conductive sacrificial material layer 170a of at least a partial thickness in a stepwise manner, i.e., the mask layer 180 may be removed in one removal process and the conductive sacrificial material layer 170a of at least a partial thickness may be removed in another removal process.

[0115] In some embodiments, one of the mask layer 180 and the conductive material layer 140a is made of an acid-resistant material, and the other is made of an alkali-resistant material. The mask layer 180 includes an acid-resistant material, and may also include an acid-resistant but not alkali-resistant material. The conductive material layer 140a includes an alkali-resistant material, and the side of the conductive material layer 140a facing away from the semiconductor substrate 110 is configured as an alkali-resistant side. This allows for selective etching of either the mask layer 180 or the conductive material layer 140a. The mask layer 180 can be etched under preset alkaline etching conditions, and is almost unetched under preset acidic etching conditions. The conductive material layer 140a can be etched under preset acidic etching conditions, and is almost unetched under preset alkaline etching conditions. Alternatively, the mask layer 180 may include an alkali-resistant material, or a material that is alkali-resistant but not acid-resistant. The conductive material layer 140a may include an acid-resistant material, and the side of the conductive material layer 140a facing away from the semiconductor substrate 110 may be configured as an acid-resistant side. This embodiment of the application uses an example where the mask layer 180 is made of an acid-resistant but not alkali-resistant material, and the side of the conductive material layer 140a facing away from the semiconductor substrate 110 is configured as an alkali-resistant but not acid-resistant side.

[0116] In some embodiments, the material of the conductive sacrificial layer 170 includes an amphoteric oxide, and the conductive sacrificial layer 170 can be etched under preset acidic etching conditions or preset alkaline etching conditions.

[0117] In some embodiments, the simultaneous removal of the conductive material layer 140a and the conductive sacrificial material layer 170a exposed outside the mask layer 180 may include simultaneously removing the conductive material layer 140a and the conductive sacrificial material layer 170a exposed outside the mask layer 180 under preset acid etching conditions. Since the mask layer 180 is an acid-resistant but not alkali-resistant material, the side of the conductive material layer 140a facing away from the semiconductor substrate 110 is configured as an alkali-resistant but not acid-resistant side, and the material of the conductive sacrificial layer 170 is an amphoteric oxide, under preset acid etching conditions, the conductive material layer 140a and the conductive sacrificial material layer 170a exposed outside the mask layer 180 can be simultaneously removed with almost no damage to the mask layer 180, so that the mask layer 180 provides better protection for the covered conductive material layer 140a and the conductive sacrificial material layer 170a.

[0118] In some embodiments, under preset acid etching conditions, the ratio of the etching rate of either the conductive material layer 140a or the conductive sacrificial material layer 170a to the etching rate of the mask layer 180 is greater than or equal to 100. Thus, under preset acid etching conditions, the etching rate of either the conductive material layer 140a or the conductive sacrificial material layer 170a differs significantly from the etching rate of the mask layer 180. This allows for the simultaneous removal of the conductive material layer 140a and the conductive sacrificial material layer 170a exposed outside the mask layer 180 with almost no damage to the mask layer 180, thereby providing better protection for the covered conductive material layer 140a and the conductive sacrificial material layer 170a.

[0119] For example, the etching reagent for the preset acid etching conditions includes hydrochloric acid, and the volume concentration of hydrochloric acid is in the range of 20%-37%. This can avoid the volume concentration of hydrochloric acid being too low, which is beneficial to improving the etching efficiency of hydrochloric acid. In addition, it can also avoid the volume concentration of hydrochloric acid being too high, which is beneficial to reduce over-etching of the sidewalls of the conductive layer 140 and the conductive sacrificial layer 170.

[0120] For example, the volume concentration of hydrochloric acid can be 20%, 25%, 30%, 35%, 37%, or any value between 20% and 37%.

[0121] For example, the preset acid etching temperature range is 20℃-40℃, which can avoid the preset acid etching temperature being too low, thus improving the etching efficiency of hydrochloric acid. In addition, it can also avoid the preset acid etching temperature being too high, thus reducing over-etching of the sidewalls of the conductive layer 140 and the conductive sacrificial layer 170.

[0122] For example, the preset acid etching temperature can be 20℃, 25℃, 30℃, 35℃, 40℃, or any value between 20℃ and 40℃.

[0123] For example, the preset acid etching time range is 100s-800s, which can avoid the preset acid etching time being too short, and is beneficial for the first conductive layer 141 and the second conductive layer 142 ( Figure 9 It completely isolates the conductive layer 140 and the conductive sacrificial layer 170. In addition, it can avoid the time of the preset acid etching conditions being too long, which helps to reduce the over-etching of the sidewalls of the conductive layer 140 and the conductive sacrificial layer 170.

[0124] For example, the preset acid etching time can be 100s, 200s, 400s, 600s, 800s, or any value between 100s and 800s.

[0125] In some embodiments, removing the mask layer 180 and at least a portion of the conductive sacrificial material layer 170a may include removing the mask layer 180 and at least a portion of the conductive sacrificial material layer 170a under preset alkaline etching conditions. Since the mask layer 180 is an acid-resistant but not alkali-resistant material, the side of the conductive material layer 140a facing away from the semiconductor substrate 110 is configured as an alkali-resistant but not acid-resistant side, and the material of the conductive sacrificial layer 170 is an amphoteric oxide, under preset alkaline etching conditions, the mask layer 180 and at least a portion of the conductive sacrificial material layer 170a can be removed simultaneously with almost no damage to the conductive layer 140, which is beneficial for improving the electrical performance of the conductive layer 140.

[0126] In some embodiments, under preset alkaline etching conditions, the ratio of the etching rate of either the mask layer 180 or the conductive sacrificial material layer 170a to the etching rate of the conductive material layer 140a is greater than or equal to 100. Thus, under preset alkaline etching conditions, the etching rate of either the mask layer 180 or the conductive sacrificial material layer 170a differs significantly from the etching rate of the conductive material layer 140a. This allows for the simultaneous removal of the mask layer 180 and at least a portion of the thickness of the conductive sacrificial material layer 170a with almost no damage to the conductive layer 140, which is beneficial for improving the electrical performance of the conductive layer 140.

[0127] For example, the etching reagent for the preset alkaline etching conditions includes hydroxide, and the volume concentration of hydroxide is in the range of 1%-5%. This can avoid the volume concentration of hydroxide being too low, thereby improving the etching efficiency of hydroxide. In addition, it can also avoid the volume concentration of hydroxide being too high, which helps to reduce the preparation cost of etching reagent.

[0128] For example, the volume concentration of hydroxide can be 1%, 2%, 3%, 4%, 5%, or any value between 1% and 5%.

[0129] For example, the hydroxide may include at least one of sodium hydroxide (NaOH) and potassium hydroxide (KOH).

[0130] For example, the etching reagent for the preset alkaline etching conditions includes hydrogen peroxide. By adding hydrogen peroxide to the hydroxide, the mask layer 180 and the conductive sacrificial material layer 170a can be more easily dissolved in the hydroxide, thereby promoting the etching reaction and improving etching efficiency. The volume concentration of hydrogen peroxide can be in the range of 1%-10%, which avoids the hydrogen peroxide volume concentration being too low, thus improving the etching efficiency of the hydroxide. In addition, it avoids the hydrogen peroxide volume concentration being too high, thus preventing the etching rate from being too fast and making it impossible to accurately control the etching rate.

[0131] For example, the volume concentration of hydrogen peroxide can be 1%, 2%, 5%, 8%, 10%, or any value between 1% and 10%.

[0132] For example, the preset alkaline etching conditions are set in a temperature range of 30℃-80℃. This avoids the preset alkaline etching conditions being too low, which helps to improve the etching efficiency of the etching reagent. In addition, it also avoids the preset alkaline etching conditions being too high, which can prevent the etching rate from being too fast and thus making it impossible to accurately control the etching rate.

[0133] For example, the preset temperature for alkaline etching conditions can be 30℃, 50℃, 70℃, 80℃, or any value between 30℃ and 80℃.

[0134] For example, the preset alkaline etching time range is 100s-400s, which can avoid the preset alkaline etching time being too short, which is conducive to the complete removal of the mask layer. In addition, it can also avoid the preset alkaline etching time being too long, which is conducive to improving production efficiency and reducing the damage of etching reagent to the conductive layer 140.

[0135] For example, the preset time for alkaline etching conditions can be 100s, 200s, 300s, 400s, or any value between 100s and 400s.

[0136] For example, both the conductive material layer 140a and the conductive sacrificial material layer 170a include a transparent conductive material.

[0137] For example, the conductive material layer 140a may be made of indium-containing transparent conductive materials, such as ITO (indium tin oxide), IWO (indium tungsten oxide), ICO (indium cerium oxide), IMO (indium molybdenum oxide), and SCOT (indium zirconium, titanium, and calcium oxide). This application will use ITO as an example to illustrate the conductive material layer 140a. ITO has good alkali resistance.

[0138] For example, the material of the conductive sacrificial material layer 170a includes an indium-free transparent conductive material. For instance, aluminum zinc oxide (AZO), i.e., aluminum-doped zinc oxide. Aluminum zinc oxide (AZO) is an amphoteric oxide, and its raw materials are abundant and inexpensive.

[0139] It should be noted that indium is expensive, resulting in higher prices for indium-containing transparent conductive materials and lower prices for indium-free transparent conductive materials. Etching indium-containing transparent conductive materials is more difficult than etching indium-free materials. However, the conductivity of indium-containing transparent conductive materials can be superior to that of indium-free materials.

[0140] In some embodiments, see Figure 10Removing the mask layer 180 and at least a portion of the thickness of the conductive sacrificial material layer 170a may include removing the mask layer 180 and a portion of the thickness of the conductive sacrificial material layer 170a, retaining another portion of the thickness of the conductive sacrificial material layer 170a, and forming a conductive sacrificial layer 170. In this way, by forming the conductive sacrificial layer 170, a portion of the thickness of the conductive layer 140 can be replaced, thereby reducing the thickness of the conductive layer 140, i.e., reducing the thickness of the indium-containing transparent conductive material, thereby reducing the amount of indium material used and reducing manufacturing costs. In addition, since the thickness of the indium-containing transparent conductive material is reduced, the etching difficulty of the conductive sacrificial material layer 170a formed by the indium-containing transparent conductive material can be reduced.

[0141] In other embodiments, see Figure 12 Removing the mask layer 180 and at least a portion of the thickness of the conductive sacrificial material layer 170a may include removing the mask layer 180 and all of the conductive sacrificial material layer 170a to expose the conductive layer 140, thereby completely removing the conductive sacrificial material layer 170a and thus better preventing mask layer 180 residue.

[0142] For example, the thickness of the conductive sacrificial material layer 170a is in the range of 5nm-20nm, which can avoid the conductive sacrificial material layer 170a being too thin, so that the conductive sacrificial material layer 170a has a good isolation effect between the conductive material layer 140a and the mask layer 180, which is beneficial to prevent the mask layer 180 from being residual. In addition, the thickness of the conductive sacrificial material layer 170a is avoided being too thick, thereby reducing the fabrication cost of the conductive sacrificial material layer 170a.

[0143] For example, the thickness of the conductive sacrificial material layer 170a can be 5 nm, 10 nm, 15 nm, 20 nm, or any value between 5 nm and 20 nm.

[0144] For example, the thickness of the conductive material layer 140a ranges from 30nm to 110nm. For instance, the thickness of the conductive material layer 140a can be 30nm, 50nm, 70nm, 100nm, 110nm, or any value between 30nm and 110nm.

[0145] For example, the sum of the thicknesses of the conductive material layer 140a and the conductive sacrificial material layer 170a ranges from 35nm to 130nm. For instance, the sum of the thicknesses of the conductive material layer 140a and the conductive sacrificial material layer 170a can be 35nm, 50nm, 70nm, 100nm, 130nm, or any value between 35nm and 130nm.

[0146] For example, the ratio of the thickness of the conductive material layer 140a to the sum of the thicknesses of the conductive material layer 140a and the conductive sacrificial material layer 170a ranges from 80% to 90%. For instance, the ratio of the thickness of the conductive material layer 140a to the sum of the thicknesses of the conductive material layer 140a and the conductive sacrificial material layer 170a can be 80%, 82%, 85%, 87%, 90%, or any value between 80% and 90%.

[0147] For example, the ratio of the thickness of the conductive sacrificial material layer 170a to the sum of the thicknesses of the conductive material layer 140a and the conductive sacrificial material layer 170a is in the range of 10%-20%. This can prevent the thickness of the conductive sacrificial material layer 170a from being too small, so that the conductive sacrificial material layer 170a has a better isolation effect on the conductive material layer 140a and the mask layer 180, which is beneficial to prevent the mask layer 180 from remaining. In addition, it can prevent the thickness of the conductive sacrificial material layer 170a from being too large, so that the conductive sacrificial material layer 170a can be removed completely and quickly.

[0148] For example, the ratio of the thickness of the conductive sacrificial material layer 170a to the sum of the thicknesses of the conductive material layer 140a and the conductive sacrificial material layer 170a can be 10%, 12%, 15%, 17%, 20%, or any value between 10% and 20%.

[0149] In some embodiments, the thickness of the conductive material layer 140a is greater than the thickness of the conductive sacrificial material layer 170a, resulting in a higher thickness of the conductive layer 140, which is beneficial to improving the conductivity of the transparent conductive structure. Alternatively, the thickness of the conductive sacrificial layer 170a can be made smaller, which can also improve the conductivity of the transparent conductive structure.

[0150] In some embodiments, see Figure 2The conductive layer 140 includes multiple sub-conductive layers stacked along the thickness direction of the semiconductor substrate 110. The multiple sub-conductive layers include a first sub-conductive layer 1431 and a second sub-conductive layer 1432, which are alternately arranged along the thickness direction of the semiconductor substrate 110. Each of the first and second sub-conductive layers is at least one layer. The first sub-conductive layer 1431 is the one furthest from the semiconductor substrate 110 among the multiple sub-conductive layers. The first sub-conductive layer 1431 includes an alkali-resistant material, such that the surface of the conductive layer 140 facing away from the semiconductor substrate 110 is configured as an alkali-resistant surface. The first sub-conductive layer 1431 also includes an alkali-resistant but not acid-resistant material, such that the surface of the conductive layer 140 facing away from the semiconductor substrate 110 is configured as an alkali-resistant but not acid-resistant surface. For example, the material of the second sub-conductive layer 1432 includes an amphoteric oxide. Under the preset acid etching conditions, the etching rate of the second sub-conductive layer 1432 is greater than that of the first sub-conductive layer 1431. Thus, a composite film is formed by the first sub-conductive layer 1431 and the second sub-conductive layer 1432. The larger etching rate of the second sub-conductive layer 1432 is beneficial to accelerate the etching rate of the acid etching reagent on the conductive layer 140 and improve the etching efficiency.

[0151] It should be noted that the conductive layer 140 can be a single-layer film, or the conductive layer 140 can be a composite film composed of multiple sub-conductive layers stacked together.

[0152] It should be noted that, under the preset acid etching conditions, when etching the conductive sacrificial material layer 170a, as the etching proceeds, the acid etching reagent is gradually consumed, the volume concentration of the acid etching reagent gradually decreases, and the etching efficiency of the acid etching reagent gradually decreases.

[0153] In some embodiments, see Figure 8 The conductive sacrificial material layer 170a includes multiple sub-conductive sacrificial material layers 173a, which are stacked along the thickness direction of the semiconductor substrate 110. Under preset acid etching conditions, the etching rate of the multiple sub-conductive sacrificial material layers 173a increases sequentially from the conductive sacrificial material layer 170a to the conductive material layer 140a. This avoids the gradual consumption of acid etching reagent as etching time increases, which would lead to a gradual decrease in the etching efficiency of the conductive sacrificial material layer 170a. As a result, the acid etching reagent has a high etching efficiency for all multiple sub-conductive sacrificial material layers 173a, which is beneficial to improving production efficiency.

[0154] In some embodiments, under preset alkaline etching conditions, the etching rate of the multilayer sub-conductive sacrificial material layer 173a decreases sequentially along the direction from the conductive sacrificial material layer 170a to the conductive material layer 140a. Thus, the etching rate is faster when removing the outer sub-conductive sacrificial material layer 173a, which is beneficial for improving production efficiency. The etching rate is slower when removing the inner sub-conductive sacrificial material layer 173a, which is beneficial for retaining the inner sub-conductive sacrificial material layer 173a. The retained sub-conductive sacrificial material layer 173a forms the sub-conductive sacrificial layer 173 of the conductive sacrificial layer 170. By forming the conductive sacrificial layer 170, a portion of the conductive layer 140 can be replaced, reducing the thickness of the conductive layer 140 and thus reducing the amount of indium material used, lowering manufacturing costs. It also reduces the etching difficulty of the conductive sacrificial material layer 170a formed from indium-containing transparent conductive material. The principle has been explained and will not be repeated here. The distance between the outer subconductive sacrificial material layer 173a and the semiconductor substrate 110 is greater than the distance between the inner subconductive sacrificial material layer 173a and the semiconductor substrate 110.

[0155] In some embodiments, the thickness of the multilayer sub-conductive sacrificial material layer 173a increases sequentially along the direction from the conductive sacrificial material layer 170a to the conductive material layer 140a. This results in a smaller thickness for the outer sub-conductive sacrificial material layer 173a, making it easier to etch away. Conversely, a larger thickness for the inner sub-conductive sacrificial material layer 173a makes it less likely to be completely removed, thus facilitating the retention of the inner sub-conductive sacrificial material layer 173a. The retained sub-conductive sacrificial material layer 173a forms the sub-conductive sacrificial layer 173 of the conductive sacrificial layer 170. By forming the conductive sacrificial layer 170, a portion of the conductive layer 140 can be replaced, reducing the thickness of the conductive layer 140 and consequently reducing the amount of indium material used, lowering manufacturing costs, and reducing the etching difficulty of the conductive sacrificial material layer 170a formed from indium-containing transparent conductive material. The principle has been explained and will not be repeated here. The distance between the outer subconductive sacrificial material layer 173a and the semiconductor substrate 110 is greater than the distance between the inner subconductive sacrificial material layer 173a and the semiconductor substrate 110.

[0156] In some embodiments, see Figure 6 The solar cell 100 includes a first polarity region 100a and a second polarity region 100b with different polarities. See some examples. Figure 3 The first polarity region 100a and the second polarity region 100b can be set alternately. See other examples. Figure 4 and Figure 6 The first polarity region 100a and the second polarity region 100b can be arranged adjacent to each other. This embodiment of the application is illustrated by taking the arrangement of the first polarity region 100a and the second polarity region 100b adjacent to each other.

[0157] See Figure 3 and Figure 4 Both the first polar region 100a and the second polar region 100b can be interdigitated.

[0158] In some embodiments, see Figure 6 Before the conductive material layer 140a and the conductive sacrificial material layer 170a are sequentially formed on the first surface 111, a first doped semiconductor layer 121 may be formed on the first surface 111. The first doped semiconductor layer 121 is located in the first polar region 100a. The first doped semiconductor layer 121 has a low resistance, which can effectively reduce current loss and increase conductivity.

[0159] In some embodiments, see Figure 6 Before the conductive material layer 140a and the conductive sacrificial material layer 170a are sequentially formed on the first surface 111, a first passivation layer 131 may be formed on the first surface 111. The first passivation layer 131 is located in the first polar region 100a and is situated between the first doped semiconductor layer 121 and the semiconductor substrate 110. The first passivation layer 131 can improve the photoelectric conversion efficiency by reducing the surface recombination rate, thereby increasing the open-circuit voltage and conversion efficiency of the solar cell 100.

[0160] In some embodiments, see Figure 6 After the first doped semiconductor layer 121 is formed on the first surface 111, and before the conductive material layer 140a and the conductive sacrificial material layer 170a are sequentially formed on the first surface 111, a second doped semiconductor layer 122 may be formed on the first surface 111. The second doped semiconductor layer 122 is located in the second polar region 100b. The second doped semiconductor layer 122 has a lower resistance, which can effectively reduce current loss and increase conductivity.

[0161] In some embodiments, see Figure 6 After the first doped semiconductor layer 121 is formed on the first surface 111, and before the conductive material layer 140a and the conductive sacrificial material layer 170a are sequentially formed on the first surface 111, a second passivation layer 132 may be formed on the first surface 111. The second passivation layer 132 is located in the second polar region 100b and is situated between the second doped semiconductor layer 122 and the semiconductor substrate 110. The second passivation layer 132 can improve the photoelectric conversion efficiency by reducing the surface recombination rate, thereby increasing the open-circuit voltage and conversion efficiency of the solar cell 100.

[0162] In an embodiment where the solar cell 100 includes a first polarity region 100a and a second polarity region 100b with different polarities, see [link to previous document]. Figure 6A conductive material layer 140a and a conductive sacrificial material layer 170a are sequentially stacked on the first surface 111. This may include sequentially stacking the conductive material layer 140a and the conductive sacrificial material layer 170a on the side of the first doped semiconductor layer 121 and the second doped semiconductor layer 122 opposite to the semiconductor substrate 110. See also... Figure 9 The conductive material layer 140a and the conductive sacrificial material layer 170a covered by the mask layer 180 may be retained, which may include retaining the conductive material layer 140a located in the first polarity region 100a and forming a first conductive layer 141, and retaining the conductive material layer 140a located in the second polarity region 100b and forming a second conductive layer 142. The first conductive layer 141 and the second conductive layer 142 are spaced apart, thereby preventing leakage between the first conductive layer 141 and the second conductive layer 142.

[0163] See Figure 10 In an embodiment where the solar cell 100 includes a first polarity region 100a and a second polarity region 100b with different polarities, retaining a conductive sacrificial material layer 170a of a different thickness may include retaining the conductive sacrificial material layer 170a located in the first polarity region 100a and forming a first conductive sacrificial layer 171, and retaining the conductive sacrificial material layer 170a located in the second polarity region 100b and forming a second conductive sacrificial layer 172. The first conductive sacrificial layer 171 and the second conductive sacrificial layer 172 are spaced apart, thereby preventing leakage between the first conductive sacrificial layer 171 and the second conductive sacrificial layer 172.

[0164] See Figure 11 In embodiments where the conductive sacrificial material layer 170a includes multiple sub-conductive sacrificial material layers 173a, retaining another portion of the thickness of the conductive sacrificial material layer 170a may include retaining at least one sub-conductive sacrificial material layer 173a and forming at least one sub-conductive sacrificial layer 173.

[0165] The solar cell 100 provided in the embodiments of this application will be described below.

[0166] This application provides a solar cell 100, fabricated using the method described in the above embodiments. During the fabrication of the solar cell 100, a conductive sacrificial material layer 170a is provided between the mask layer 180 and the conductive material layer 140a. The conductive sacrificial material layer 170a completely separates the mask layer 180 and the conductive material layer 140a. Even if the mask layer 180 is in close contact with the conductive sacrificial material layer 170a and residues easily remain on it, by using the conductive sacrificial material layer 170a as a sacrificial layer, at least a portion of the thickness of the conductive sacrificial material layer 170a is removed when removing the mask layer 180. This allows for complete removal of the mask layer 180, enabling complete separation of the conductive layer 140 and the mask layer 180. This achieves residue-free removal of the mask layer 180, preventing residual mask layer 180 from hindering carrier transport and preventing adverse effects of residual mask layer 180 on the series resistance of the solar cell 100. This reduces the series resistance of the solar cell 100 from 0.7 Ω·cm. 2 Reduced to 0.55 Ω·cm 2 The following measures result in a lower series resistance for the solar cell 100. Furthermore, by avoiding damage to the side of the conductive layer 140 facing away from the semiconductor substrate 110 during the removal of the residual mask layer 180, damage to the grains of the conductive layer 140 during mask layer 180 removal is prevented. This avoids adverse effects on the contact resistance between the conductive layer 140 and the subsequently formed electrode 150, thus reducing the contact resistance between the conductive layer 140 and the subsequently formed electrode 150. Consequently, the series resistance of the solar cell 100 is lower. Additionally, damage to the side of the conductive layer 140 facing away from the semiconductor substrate 110 is avoided, further reducing the surface roughness of this side. This ensures that the surface roughness of at least a portion of the conductive layer 140 facing away from the semiconductor substrate 110 is less than or equal to 10 nm.

[0167] For example, the surface roughness of at least a portion of the conductive layer 140 on the side facing away from the semiconductor substrate 110 can be any value of 4nm, 6nm, 8nm, 10nm or less than 10nm.

[0168] See Figure 1 The solar cell 100 may include a semiconductor substrate 110, which can provide support for subsequently formed film layers. The semiconductor substrate 110 can be used to receive incident light and generate photogenerated carriers.

[0169] For example, the semiconductor substrate 110 has a first surface 111 and a second surface 112 disposed opposite to each other, and at least one of the first surface 111 and the second surface 112 can be used to receive sunlight. In this embodiment, the second surface 112 is used to receive sunlight as an example, that is, the second surface 112 is close to the light-facing surface of the solar cell 100, and the first surface 111 is close to the back surface of the solar cell 100.

[0170] For example, the semiconductor substrate 110 can be a silicon substrate, and the material of the silicon substrate can include at least one of monocrystalline silicon and polycrystalline silicon. This application embodiment uses monocrystalline silicon as an example for illustration.

[0171] For example, the semiconductor substrate 110 can be doped with N-type ions, which can be at least one of phosphorus, arsenic, and antimony. Alternatively, the semiconductor substrate 110 can be doped with P-type ions, which can be at least one of aluminum and boron. This application embodiment uses N-type doping of the semiconductor substrate 110 as an example for illustration.

[0172] In some embodiments, at least a portion of at least one of the first surface 111 and the second surface 112 may have a textured surface. The textured surface may be a pyramidal textured surface, a pitted textured surface, etc. The textured surface has a low reflectivity to incident light, thus resulting in a high absorption and utilization rate of incident light, leading to a high photoelectric conversion efficiency of the solar cell 100. In other embodiments, at least one of the first surface 111 and the second surface 112 may not have a textured surface.

[0173] See Figure 1 The solar cell 100 includes a conductive layer 140 disposed on one side of the first surface 111. The conductive layer 140 can collect the charge carriers of the cell and transfer them to the electrode 150.

[0174] See Figure 2 In an embodiment that retains a portion of the conductive sacrificial material layer 170a, the retained conductive sacrificial material layer 170a can form a conductive sacrificial layer 170, which is disposed on the side of the conductive layer 140 facing away from the semiconductor substrate 110. The conductive layer 140 and the conductive sacrificial layer 170 can together form a transparent conductive structure. By forming the conductive sacrificial layer 170, a portion of the conductive layer 140 can be replaced, reducing the thickness of the conductive layer 140, i.e., reducing the thickness of the indium-containing transparent conductive material, thereby reducing the amount of indium material used and lowering manufacturing costs. In addition, since the thickness of the indium-containing transparent conductive material is reduced, the etching difficulty of the conductive sacrificial material layer 170a formed by the indium-containing transparent conductive material can be reduced.

[0175] In some embodiments, see Figure 2 The solar cell 100 includes an electrode 150 disposed on the side of the conductive sacrificial layer 170 facing away from the semiconductor substrate 110, and the electrode 150 is electrically connected to the conductive sacrificial layer 170, forming an ohmic contact. During the fabrication of the solar cell 100, by using the conductive sacrificial material layer 170a as the sacrificial layer, a portion of the conductive sacrificial material layer 170a is removed during the removal of the mask layer 180, achieving residue-free removal of the mask layer 180. This results in a contact resistance between the electrode 150 and the conductive sacrificial layer 170 ranging from 1 mΩ·cm. 2 -3mΩ·cm 2 This results in a lower contact resistance between the electrode 150 and the conductive sacrificial layer 170, which in turn lowers the series resistance of the solar cell 100, making the series resistance of the solar cell 100 less than or equal to 0.55 Ω·cm. 2 .

[0176] For example, the contact resistance between electrode 150 and conductive sacrificial layer 170 can be 1 mΩ·cm. 2 1.5mΩ·cm 2 2mΩ·cm 2 2.3mΩ·cm 2 2.5mΩ·cm 2 2.7mΩ·cm 2 3mΩ·cm 2 Or between 1mΩ·cm 2 -3mΩ·cm 2 Any value between.

[0177] See Figure 1 In an embodiment where the conductive sacrificial material layer 170a is completely removed, the solar cell 100 includes an electrode 150 disposed on the side of the conductive layer 140 facing away from the semiconductor substrate 110, and the electrode 150 is electrically connected to the conductive layer 140, forming an ohmic contact. During the fabrication of the solar cell 100, by using the conductive sacrificial material layer 170a as a sacrificial layer, and removing the conductive sacrificial material layer 170a during the removal of the mask layer 180, residue-free removal of the mask layer 180 can be achieved, resulting in a contact resistance between the electrode 150 and the conductive layer 140 ranging from 1 mΩ·cm. 2 -3mΩ·cm 2 This results in a lower contact resistance between the electrode 150 and the conductive layer 140, which in turn lowers the series resistance of the solar cell 100, making the series resistance of the solar cell 100 less than or equal to 0.55 Ω·cm. 2 .

[0178] For example, the contact resistance between electrode 150 and conductive layer 140 can be 1 mΩ·cm. 2 1.5mΩ·cm 2 2mΩ·cm 2 2.3mΩ·cm 2 2.5mΩ·cm 2 2.7mΩ·cm 2 3mΩ·cm 2 Or between 1mΩ·cm 2 -3mΩ·cm 2 Any value between.

[0179] For example, the thickness of the conductive layer 140 is in the range of 30nm-110nm, which can avoid the conductive layer 140 being too thin, so that the conductive layer 140 has a better transport effect on charge carriers. In addition, it can also avoid the conductive layer 140 being too thick, which helps to reduce the fabrication cost of the conductive layer 140.

[0180] For example, the thickness of the conductive layer 140 can be 30nm, 50nm, 70nm, 100nm, 110nm, or any value between 30nm and 110nm.

[0181] For example, the thickness of the conductive sacrificial layer 170 is in the range of 5nm-10nm, which can avoid the conductive sacrificial layer 170 being too thin. This is beneficial to reduce the thickness of the conductive layer 140 by setting the conductive sacrificial layer 170, which is beneficial to reduce the manufacturing cost. In addition, it can also avoid the conductive sacrificial layer 170 being too thick, which prevents the conductive sacrificial layer 170 from having too large a proportion in the transparent conductive structure, which is beneficial to improve the conductivity of the transparent conductive structure.

[0182] For example, the thickness of the conductive sacrificial layer 170 can be 5nm, 6nm, 7nm, 8nm, 9nm, 10nm or any value between 5nm and 10nm.

[0183] For example, the thickness of the conductive layer 140 is greater than the thickness of the conductive sacrificial layer 170. Thus, the conductive layer 140 has a larger thickness and the conductive sacrificial layer 170 has a smaller thickness, which is beneficial to improving the conductivity of the transparent conductive structure.

[0184] See Figure 3 and Figure 4 The solar cell 100 includes a first polarization region 100a and a second polarization region 100b. The first polarization region 100a and the second polarization region 100b are arranged adjacent to each other. Alternatively, the first polarization region 100a and the second polarization region 100b are arranged at intervals. This application embodiment is described with the first polarization region 100a and the second polarization region 100b arranged adjacent to each other as an example.

[0185] See Figure 1 In an embodiment where the solar cell 100 includes a first polarity region 100a and a second polarity region 100b, a conductive layer 140 is located in both polarity regions 100a and 100b. The conductive layer 140 in the first polarity region 100a is configured as a first conductive layer 141, and the conductive layer 140 in the second polarity region 100b is configured as a second conductive layer 142. The first conductive layer 141 and the second conductive layer 142 are spaced apart. The first conductive layer 141 can collect charge carriers from the cell and transport them to the first electrode 151. Additionally, the first conductive layer 141 can also have an anti-reflection effect. The second conductive layer 142 can collect charge carriers from the cell and transport them to the second electrode 152. Additionally, the second conductive layer 142 can also have an anti-reflection effect.

[0186] See Figure 1 Electrodes 150 are located in a first polar region 100a and a second polar region 100b. The electrode 150 located in the first polar region 100a is configured as the first electrode 151, and the electrode 150 located in the second polar region 100b is configured as the second electrode 152. The first electrode 151 and the second electrode 152 are spaced apart. The first electrode 151 and the second electrode 152 can collect and transport charge carriers, thereby realizing the conversion of solar energy into electrical energy.

[0187] For example, at least one of the first electrode 151 and the second electrode 152 may be made of metallic materials such as silver, copper, tin, and nickel.

[0188] For example, the first conductive layer 141 may be located only in the first polar region 100a and not extend into the second polar region 100b, thereby making the distance between the first conductive layer 141 and the second conductive layer 142 larger, which is beneficial to prevent short circuits between the first conductive layer 141 and the second conductive layer 142. In other examples, the first conductive layer 141 may extend from the first polar region 100a to the second polar region 100b, thereby making the area of ​​the first conductive layer 141 larger, which is beneficial to improving the transport of charge carriers by the first conductive layer 141.

[0189] For example, the second conductive layer 142 may be located only in the second polar region 100b and not extend into the first polar region 100a, thereby making the distance between the first conductive layer 141 and the second conductive layer 142 larger, which is beneficial to prevent short circuits between the first conductive layer 141 and the second conductive layer 142. In other examples, the second conductive layer 142 may extend from the second polar region 100b to the first polar region 100a, thereby making the area of ​​the second conductive layer 142 larger, which is beneficial to improving the transport of charge carriers by the second conductive layer 142.

[0190] It should be noted that in the embodiment where the semiconductor substrate 110 has a textured structure, the textured structure of the semiconductor substrate 110 will increase the surface roughness of the side of the corresponding conductive layer 140 facing away from the semiconductor substrate 110.

[0191] For example, at least a portion of the first surface 111 may be polished, and the surface roughness of the conductive layer 140 on the side facing away from the semiconductor substrate 110 corresponding to the polished surface may be less than or equal to 10 nm. For instance, the first surface 111 of the first polar region 100a may be polished, and the first surface 111 of the second polar region 100b may have a textured structure, and the surface roughness of the conductive layer 140 on the side facing away from the semiconductor substrate 110 in the first polar region 100a may be less than or equal to 10 nm.

[0192] See Figure 14 In related technologies, the side of the first transparent conductive layer facing away from the semiconductor substrate is damaged during mask removal. Figure 14 It can be seen that the surface roughness of the side of the first transparent conductive layer facing away from the semiconductor substrate is larger. (See also...) Figure 15 In this embodiment, since it is not necessary to damage the side of the first conductive layer 141 facing away from the semiconductor substrate 110 in order to remove the residual mask layer 180, damage to the grains of the first conductive layer 141 is avoided during the removal of the mask layer 180. Figure 15 It can be seen that the surface roughness of the side of the conductive layer 140 facing away from the semiconductor substrate 110 is small, and the first conductive layer 141 is relatively dense.

[0193] See Figure 1 The solar cell 100 includes a first doped semiconductor layer 121 and a second doped semiconductor layer 122. The first doped semiconductor layer 121 is located in a first polar region 100a and is disposed between a first conductive layer 141 and a semiconductor substrate 110. The first doped semiconductor layer 121 has low resistance, which can effectively reduce current loss and increase conductivity. The second doped semiconductor layer 122 is located in a second polar region 100b and is disposed between a second conductive layer 142 and a semiconductor substrate 110. The second doped semiconductor layer 122 has low resistance, which can effectively reduce current loss and increase conductivity.

[0194] See Figure 1The solar cell 100 includes a first passivation layer 131, which is disposed on a first surface 111 and between a first doped semiconductor layer 121 and a semiconductor substrate 110. The first passivation layer 131 can improve photoelectric conversion efficiency by reducing the surface recombination rate, thereby increasing the open-circuit voltage and conversion efficiency of the solar cell 100. The first passivation layer 131 is in contact with the first surface 111 located in the first polar region 100a.

[0195] See Figure 1 The solar cell 100 includes a second passivation layer 132, which is located in the second polar region 100b. The second passivation layer 132 is situated between the second doped semiconductor layer 122 and the semiconductor substrate 110. The second passivation layer 132 can improve photoelectric conversion efficiency by reducing the surface recombination rate, thereby increasing the open-circuit voltage and conversion efficiency of the solar cell 100. The second passivation layer 132 is in contact with the first surface 111 located in the second polar region 100b.

[0196] For example, a portion of the second passivation layer 132 and a portion of the second doped semiconductor layer 122 may extend from the first polar region 100a to the second polar region 100b, and extend to the side of the first doped semiconductor layer 121 away from the semiconductor substrate 110.

[0197] For example, the doping type of the first doped semiconductor layer 121 is opposite to that of the second doped semiconductor layer 122. One of the first doped semiconductor layer 121 and the second doped semiconductor layer 122 may be N-type doped, and the other may be P-type doped.

[0198] For example, the first passivation layer 131 may include tunneling oxide or intrinsic amorphous silicon.

[0199] For example, the material of the first doped semiconductor layer 121 includes doped polycrystalline silicon, doped amorphous silicon, or doped microcrystalline silicon.

[0200] For example, the first passivation layer 131 may include a tunneling oxide, and the first doped semiconductor layer 121 may include doped polysilicon.

[0201] For example, the first passivation layer 131 may include intrinsic amorphous silicon, and the first doped semiconductor layer 121 may include a doped amorphous silicon layer or a doped microcrystalline silicon layer.

[0202] For example, the material of the second passivation layer 132 includes intrinsic amorphous silicon.

[0203] For example, the material of the second doped semiconductor layer 122 includes doped microcrystalline silicon or doped amorphous silicon.

[0204] In some embodiments, see Figure 11 The conductive sacrificial layer 170 includes multiple sub-conductive sacrificial layers 173, which are stacked along the thickness direction of the semiconductor substrate 110. Under preset acid etching conditions, the etching rate of the multiple sub-conductive sacrificial layers 173 increases sequentially along the direction from the conductive sacrificial layer 170 to the conductive layer 140. In this way, the etching efficiency of the conductive sacrificial material layer 170a can be gradually reduced due to the gradual consumption of acid etching reagent as the etching time increases. This ensures that the acid etching reagent has a high etching efficiency for the multiple sub-conductive sacrificial material layers 173a, which is beneficial to improving production efficiency.

[0205] In some embodiments, under preset alkaline etching conditions, the etching rate of the multilayer sub-conductive sacrificial layer 173 decreases sequentially along the direction from the conductive sacrificial layer 170 to the conductive layer 140. This makes it difficult for the inner sub-conductive sacrificial layer 173 to be etched away, which is beneficial to retain the inner sub-conductive sacrificial material layer 173a and form a conductive sacrificial layer 170 to replace part of the thickness of the conductive layer 140. This can reduce the thickness of the conductive layer 140, thereby reducing the amount of indium material used, reducing manufacturing costs, and also reducing the etching difficulty of the conductive sacrificial material layer 170a formed by indium-containing transparent conductive material.

[0206] In some embodiments, the thickness of the multilayer sub-conductive sacrificial layer 173 increases sequentially along the direction from the conductive sacrificial layer 170 to the conductive layer 140. This results in a larger thickness of the inner sub-conductive sacrificial layer 173, making it less likely to be completely removed. This facilitates the retention of the inner sub-conductive sacrificial material layer 173a and the formation of a conductive sacrificial layer 170 to replace part of the thickness of the conductive layer 140. This reduces the thickness of the conductive layer 140, thereby reducing the amount of indium material used, lowering manufacturing costs, and also reducing the etching difficulty of the conductive sacrificial material layer 170a formed by the indium-containing transparent conductive material.

[0207] In some embodiments, see Figure 1 The solar cell 100 includes a third passivation layer 133, which is located on the second surface 112.

[0208] For example, the third passivation layer 133 includes one or more of intrinsic amorphous silicon, doped microcrystalline silicon, doped amorphous silicon, tunneling oxide, doped polycrystalline silicon, silicon oxide, aluminum oxide, silicon nitride, and silicon oxynitride.

[0209] In some embodiments, see Figure 1 The solar cell 100 includes an antireflection layer 160, which is located on the side of the third passivation layer 133 away from the semiconductor substrate 110.

[0210] For example, the antireflective layer 160 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, magnesium fluoride, and transparent conductive oxide.

[0211] The photovoltaic modules provided in the embodiments of this application are described below.

[0212] This application provides a photovoltaic module, which includes the solar cell 100 described in the above embodiments. The photovoltaic module may have at least one solar cell 100. This application describes an example where the photovoltaic module has multiple solar cells 100, with the multiple solar cells 100 collectively forming a battery string layer.

[0213] In some embodiments, the photovoltaic module may include a first encapsulation and a second encapsulation located on both sides of the cell string layer, which encapsulate the cell string layer to protect it. The first and second encapsulations may include an encapsulating adhesive layer and a cover plate, with the encapsulating adhesive layer located on the side of the cover plate facing the cell string layer. The cover plate protects the cell string layer, and the encapsulating adhesive layer connects the cover plate and the cell string layer.

[0214] For example, the solar cell 100 may include a heterojunction solar cell (HJT), a back contact cell (BC), a tunnel oxide passivating contact cell (TOPCON), a heterojunction back contact cell (HBC), or a hybrid fully passivated back contact cell (hybrid HBC), etc. This application uses a heterojunction back contact cell as an example for illustration.

[0215] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0216] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A solar cell, characterized in that, include: A semiconductor substrate having a first surface and a second surface disposed opposite to each other; A conductive layer is disposed on one side of the first surface; The material of the conductive layer includes a transparent conductive oxide; Wherein, the surface roughness of at least a portion of the conductive layer on the side opposite to the semiconductor substrate is less than or equal to 10 nm; The solar cell also includes a conductive sacrificial layer; The conductive sacrificial layer is disposed on the side of the conductive layer opposite to the semiconductor substrate; The conductive layer is made of an alkali-resistant but non-acid-resistant material, and the side of the conductive layer facing away from the semiconductor substrate is configured as an alkali-resistant but non-acid-resistant side. The material of the conductive sacrificial layer includes amphoteric oxides.

2. The solar cell according to claim 1, characterized in that, The solar cell includes an electrode disposed on the side of the conductive sacrificial layer opposite to the semiconductor substrate and electrically connected to the conductive sacrificial layer. The contact resistance between the electrode and the conductive sacrificial layer is in the range of 1 mΩ·cm. 2 -3mΩ·cm 2 .

3. The solar cell according to claim 1, characterized in that, The solar cell includes an electrode disposed on the side of the conductive layer opposite to the semiconductor substrate and electrically connected to the conductive layer. The contact resistance between the electrode and the conductive layer is less than or equal to 1 mΩ·cm. 2 -3mΩ·cm 2 .

4. The solar cell according to claim 1 or 2, characterized in that, The conductive layer is made of an indium-containing transparent conductive material; and / or, The material of the conductive sacrificial layer includes an indium-free transparent conductive material.

5. The solar cell according to claim 1 or 2, characterized in that, The thickness of the conductive layer ranges from 30 nm to 110 nm; and / or, The thickness of the conductive sacrificial layer ranges from 5 nm to 10 nm; and / or, The thickness of the conductive layer is greater than the thickness of the conductive sacrificial layer.

6. The solar cell according to any one of claims 1-3, characterized in that, The solar cell includes a first polarity region and a second polarity region with different polarities. The conductive layer is located in the first polarity region and the second polarity region. The conductive layer located in the first polarity region is configured as a first conductive layer, and the conductive layer located in the second polarity region is configured as a second conductive layer. The first conductive layer and the second conductive layer are arranged at intervals. The solar cell includes a first doped semiconductor layer and a second doped semiconductor layer. The first doped semiconductor layer is located in the first polar region and disposed between the first conductive layer and the semiconductor substrate. The second doped semiconductor layer is located in the second polar region and disposed between the second conductive layer and the semiconductor substrate.

7. The solar cell according to any one of claims 1-3, characterized in that, The conductive layer includes multiple sub-conductive layers, which are stacked along the thickness direction of the semiconductor substrate; The multilayer subconductive layer includes a first subconductive layer and a second subconductive layer, which are arranged alternately. The first subconductive layer is the one furthest from the semiconductor substrate among the multilayer subconductive layers, and the first subconductive layer includes an alkali-resistant material. Under preset acid etching conditions, the etching rate of the second sub-conductive layer is greater than that of the first sub-conductive layer.

8. The solar cell according to claim 1 or 2, characterized in that, The conductive sacrificial layer includes multiple sub-conductive sacrificial layers, which are stacked along the thickness direction of the semiconductor substrate; Under preset acidic etching conditions, the etching rate of the multilayer sub-conductive sacrificial layer increases sequentially along the direction from the conductive sacrificial layer to the conductive layer; and / or, Under preset alkaline etching conditions, the etching rate of the multilayer sub-conductive sacrificial layer decreases sequentially along the direction from the conductive sacrificial layer to the conductive layer.

9. The solar cell according to claim 8, characterized in that, The thickness of the multilayer sub-conductive sacrificial layer increases sequentially along the direction from the conductive sacrificial layer to the conductive layer.

10. The solar cell according to any one of claims 1-3, characterized in that, The series resistance of the solar cell is less than or equal to 0.55 Ω·cm. 2 .

11. A photovoltaic module, characterized in that, Includes the solar cell described in any one of claims 1-10.

12. A method for preparing a solar cell, characterized in that, include: A semiconductor substrate is provided, the semiconductor substrate having a first surface and a second surface disposed opposite to each other; A conductive material layer and a conductive sacrificial material layer are sequentially stacked on one side of the first surface; A mask layer is formed on the side of the conductive sacrificial material layer that faces away from the semiconductor substrate; Simultaneously remove the conductive material layer and the conductive sacrificial material layer exposed outside the mask layer, retain the conductive material layer and the conductive sacrificial material layer covered by the mask layer, and the retained conductive material layer forms a conductive layer; Remove the mask layer and at least a portion of the thickness of the conductive sacrificial material layer; The mask layer comprises an acid-resistant but non-alkali-resistant material; The conductive material layer includes an alkali-resistant but non-acid-resistant material, and the side of the conductive material layer facing away from the semiconductor substrate is configured as an alkali-resistant but non-acid-resistant side. The material of the conductive sacrificial material layer includes amphoteric oxides.

13. The method for preparing a solar cell according to claim 12, characterized in that, The removal of the mask layer and at least a portion of the conductive sacrificial material layer includes: simultaneously removing the mask layer and at least a portion of the conductive sacrificial material layer.

14. The method for preparing a solar cell according to claim 12 or 13, characterized in that, The simultaneous removal of the conductive material layer and the conductive sacrificial material layer exposed outside the mask layer includes: simultaneously removing the conductive material layer and the conductive sacrificial material layer exposed outside the mask layer under preset acid etching conditions.

15. The method for preparing a solar cell according to claim 14, characterized in that, Under the preset acid etching conditions, the ratio of the etching rate of either the conductive material layer or the conductive sacrificial material layer to the etching rate of the mask layer is greater than or equal to 100.

16. The method for preparing a solar cell according to claim 14, characterized in that, The etching reagent for the preset acid etching conditions includes hydrochloric acid, and the volume concentration of the hydrochloric acid is in the range of 20%-37%. And / or, The temperature range of the preset acid etching conditions is 20℃-40℃; and / or, The time range of the preset acid etching conditions is 100s-800s.

17. The method for preparing a solar cell according to claim 12 or 13, characterized in that, The removal of the mask layer and at least a portion of the conductive sacrificial material layer comprises: removing the mask layer and at least a portion of the conductive sacrificial material layer under preset alkaline etching conditions.

18. The method for preparing a solar cell according to claim 17, characterized in that, Under the preset alkaline etching conditions, the ratio of the etching rate of either the mask layer or the conductive sacrificial material layer to the etching rate of the conductive material layer is greater than or equal to 100.

19. The method for preparing a solar cell according to claim 17, characterized in that, The etching reagent under the preset alkaline etching conditions includes a hydroxide, wherein the volume concentration of the hydroxide ranges from 1% to 5%; and / or, The etching reagent for the preset alkaline etching conditions includes hydrogen peroxide, wherein the volume concentration of the hydrogen peroxide is in the range of 1%-10%; and / or, The temperature range of the preset alkaline etching conditions is 30℃-80℃; and / or, The time range of the preset alkaline etching conditions is 100s-400s.

20. The method for preparing a solar cell according to claim 12 or 13, characterized in that, The removal of the mask layer and at least a portion of the thickness of the conductive sacrificial material layer includes: Remove the mask layer and a portion of the conductive sacrificial material layer, leaving another portion of the conductive sacrificial material layer, to form a conductive sacrificial layer; or, Remove the mask layer and all of the conductive sacrificial material layers to expose the conductive layer.

21. The method for preparing a solar cell according to claim 12 or 13, characterized in that, The thickness of the conductive sacrificial material layer ranges from 5 nm to 20 nm; and / or, The sum of the thicknesses of the conductive material layer and the conductive sacrificial material layer ranges from 35 nm to 130 nm; and / or, The ratio of the thickness of the conductive material layer to the sum of the thicknesses of the conductive material layer and the conductive sacrificial material layer ranges from 80% to 90%; and / or, The ratio of the conductive sacrificial material layer to the sum of the thicknesses of the conductive material layer and the conductive sacrificial material layer ranges from 10% to 20%; and / or, The thickness of the conductive material layer is greater than the thickness of the conductive sacrificial material layer.

22. The method for preparing a solar cell according to claim 12 or 13, characterized in that, The conductive sacrificial material layer includes multiple sub-conductive sacrificial material layers, which are stacked along the thickness direction of the semiconductor substrate; Under preset acidic etching conditions, the etching rate of the multilayer sub-conductive sacrificial material layer increases sequentially along the direction from the conductive sacrificial material layer to the conductive material layer; and / or, Under preset alkaline etching conditions, the etching rate of the multilayer sub-conductive sacrificial material layer decreases sequentially along the direction from the conductive sacrificial material layer to the conductive material layer.

23. The method for preparing a solar cell according to claim 22, characterized in that, The thickness of the multilayer sub-conductive sacrificial material layer increases sequentially along the direction from the conductive sacrificial material layer to the conductive material layer.

24. A solar cell, characterized in that, The solar cell is prepared using the method described in any one of claims 13-23.

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