A tbc cell and method of making the same

Abstract

The application relates to a TBC battery and a preparation method thereof, which comprises the following steps: S1, depositing a tunneling oxide layer and a polysilicon layer, S2, depositing a doped source layer of impurities of a first conductive type and a mask layer, S3, opening the mask and cleaning, S4, one-step co-doping and S5, texturing: forming a textured pyramid structure with gradually reduced doping concentration. The application simplifies the process flow, significantly reduces the series resistance, improves the current density, improves the passivation performance and the UV decay resistance of the TBC battery, and improves the conversion efficiency of the battery.

Description

Technical Field

[0001] This application relates to the technical field of solar cells, and in particular to a TBC cell and its preparation method. Background Technology

[0002] A solar cell is a device that directly converts solar energy into electrical energy, and its working principle is based on the photovoltaic effect. An IBC (Interdigitated Back Contact) cell and a TOPcon (Tunnel Oxide Passivated Contact) cell can be stacked to form a TBC cell. The TBC cell incorporates the tunnel oxide passivated contact technology of the TOPcon cell and the technology of preparing P-regions and N-regions arranged in an interdigitated pattern on the back of the IBC cell. Current process routes require two high-temperature doping processes, two amorphous silicon formation processes, two laser processes, and multiple masking processes to prepare the N+ regions, local P+ regions, and the isolation regions between them (the structure combining these three is usually called a PIN structure). This process is cumbersome and time-consuming, severely impacting production capacity and incurring additional manufacturing costs. Furthermore, the excessive high-temperature processes in current routes, including two high-temperature doping processes (phosphorus doping temperature 700-1000℃, boron doping temperature 900-1200℃), significantly affect the minority carrier lifetime of the substrate silicon wafer, thus adversely impacting cell efficiency.

[0003] Currently, the relevant technologies require two high-temperature doping processes, two amorphous silicon formation processes, two laser processes, and multiple masking processes. The processes are cumbersome and time-consuming, which seriously affects production capacity and causes additional manufacturing costs. Moreover, the existing process routes involve too many high-temperature processes, including two high-temperature doping processes. In addition, some TBC battery processes require additional high-temperature and wet processes to manufacture FSF, so the FSF manufacturing process is directly omitted.

[0004] Existing crystalline silicon solar cell technology has the following problems: 1. In order to reduce the high temperature and wet process, the preparation of FSF is not carried out, which leads to efficiency loss; 2. The BSG thickness is relatively thick, with a thickness of >100nm, resulting in a high oxygen content in the silicon wafer, serious BO recombination, and high boron or phosphorus expansion temperature; 3. It requires multiple high temperature, film opening, masking, and wet process processes, which are complicated, polluting, and time-consuming, making it difficult to introduce mass production processes and reducing cell efficiency. Summary of the Invention

[0005] The CVD mentioned in this application refers to Chemical Vapor Deposition.

[0006] The BSG mentioned in this application refers to borosilicate glass.

[0007] The PSG mentioned in this application refers to phosphosilicate glass.

[0008] The FSF mentioned in this application refers to the Front Surface Field.

[0009] The BSF mentioned in this application refers to the Front Surface Field.

[0010] To simplify the process flow and precisely adjust the phosphorus and boron doping levels of the front and back surface fields, significantly reduce series resistance, increase current density, improve the passivation performance and UV degradation resistance of TBC cells, and improve cell conversion efficiency, this application provides a TBC cell and its preparation method.

[0011] In a first aspect, this application provides a method for preparing a TBC battery, which adopts the following technical solution:

[0012] A method for preparing a TBC battery includes the following steps:

[0013] S1. Deposition of tunneling oxide layer and polysilicon layer: A tunneling oxide layer and a polysilicon layer are sequentially deposited on the surface of the substrate silicon wafer;

[0014] S2. Deposit a dopant source layer and a mask layer for impurities of the first conductivity type: deposit a dopant source layer and a mask layer for impurities of the first conductivity type sequentially on the outside of the polycrystalline silicon layer on the back side of the substrate silicon wafer, and deposit a dopant source layer and a mask layer for impurities of the first conductivity type sequentially on the outside of the monocrystalline silicon layer on the front side of the substrate silicon wafer.

[0015] S3. Film opening and cleaning: Remove the dopant source layer and mask layer of the first conductivity type impurities on the back side of the substrate silicon wafer to form a reserved area;

[0016] S4, One-step co-doping: The source layer of dopants with different conductivity types of impurities is co-doped in one step to form the back P-region and N-region as well as the front surface field.

[0017] S5. Texturing: Forming a textured pyramid structure where the doping concentration gradually decreases from the side furthest from the substrate silicon wafer to the side closest to the substrate silicon wafer. Specifically, the doping concentration at the apex of the pyramid structure is higher than that at the base. The height of the pyramid structure is 0.1 μm-3 μm, and the doping concentration decreases by 10⁻¹⁰ for every 0.01 micrometers from the apex to the base. 4 times.

[0018] Optionally, the height of the pyramid structure can be 0.3μm, 0.5μm, 0.8μm, 1μm, 1.5μm, 2μm, 2.5μm, 3μm, etc.

[0019] Optionally, the substrate silicon wafer is an N-type silicon wafer or a P-type silicon wafer.

[0020] By adopting the above technical solution, a tunneling oxide layer and a polycrystalline silicon layer are first deposited sequentially on the back side of the substrate silicon wafer, followed by the sequential deposition of a dopant source layer and a mask layer for impurities of the first conductivity type. The dopant source layer and mask layer for the first conductivity type impurities on the back side of the substrate silicon wafer are located outside the polycrystalline silicon layer. Part of the dopant source layer and mask layer for the first conductivity type impurities are removed through a film-opening and cleaning step to create reserved space. Through a one-step co-doping process, two dopant source layers for the first conductivity type impurities with different electrical properties can be simultaneously formed on the back side of the silicon wafer, i.e., the P-region on the back side. Along with the N-region, the front surface field of the substrate silicon wafer is formed simultaneously, without the need for multiple masking and mask removal processes. This allows for precise adjustment of the phosphorus and boron doping levels of the front and back surface fields. After texturing, the textured pyramid retains the original FSF, enhancing the textured pyramid tip or passivating the textured surface. At the same time, it promotes the movement of charge carriers from the front surface to the back field, which can significantly reduce the series resistance of the TBC cell, increase the current density, and improve the UV degradation resistance of the TBC cell. Therefore, it simplifies the TBC cell process flow, shortens the process time, reduces the high temperature, and improves the cell conversion efficiency.

[0021] Optionally, before texturing in step S5, an etching step is included on the front side of the substrate silicon wafer. A mixed acid solution containing HNO3 is used to etch the front side, with an acid concentration of 1%-30%. In step S5, texturing is performed using a texturing mixed solution with a concentration of 1%-30% to form a textured pyramid structure on the surface of the substrate silicon wafer. The doped material is located at the apex of the pyramid structure or the entire pyramid structure.

[0022] By adopting the above technical solution, the front side of the substrate silicon wafer is first etched, that is, acid is used to remove the phosphosilicate glass layer or borosilicate glass layer and polycrystalline silicon layer on the front side. Then, texturing is performed, that is, alkaline solution and texturing additives are used to react with monocrystalline silicon to form anisotropic pyramid structure, thereby ensuring the formation of pyramid structure.

[0023] Optionally, in the S1 deposition of the tunneling oxide layer and the polycrystalline silicon layer, the thickness of the tunneling oxide layer deposited on the surface of the substrate silicon wafer is 0.5nm-20nm, and the deposition thickness of the polycrystalline silicon layer is 50nm-400nm.

[0024] By adopting the above technical solution, the surface of the substrate silicon wafer includes a front side and a back side. When depositing a tunneling oxide layer and a polysilicon layer on the back side of the substrate silicon wafer, some equipment will inevitably deposit a tunneling oxide layer and a polysilicon layer of the same thickness on the front side. The polysilicon layer on the front side can block the diffusion of impurities on the front side, thereby better forming a pyramid doping concentration gradient.

[0025] Optionally, the thickness of the tunneling oxide layer can be 0.5 nm, 1 nm, 3 nm, 5 nm, 7 nm, 10 nm, 12 nm, 15 nm, 18 nm, 20 nm, etc., and the deposition thickness of the polycrystalline silicon layer can be 50 nm, 100 nm, 150 nm, 200 nm, 250 nm, 300 nm, 350 nm, 400 nm, etc.

[0026] Optionally, in S2, the dopant source layer for depositing the first conductivity type impurity and the mask layer, the thickness of the dopant source layer for depositing the first conductivity type impurity on the outside of the polycrystalline silicon layer on the back side of the substrate silicon wafer by CVD is 10nm-100nm, and the thickness of the mask layer is 2nm-200nm.

[0027] Optionally, the thickness of the dopant source layer for the first conductivity type impurity deposited on the polycrystalline silicon layer on the back side of the substrate silicon wafer can be 10 nm, 20 nm, 30 nm, 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, 100 nm, etc.; the thickness of the mask layer can be 2 nm, 5 nm, 10 nm, 20 nm, 30 nm, 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, 100 nm, 150 nm, 200 nm, etc.

[0028] Optionally, S2, the dopant source layer for depositing the first conductivity type impurity and the mask layer, further includes: sequentially depositing a 5nm-60nm dopant source layer for the first conductivity type impurity and a 2nm-200nm mask layer on the outer side of the single crystal silicon layer on the front side of the substrate silicon wafer.

[0029] Optionally, the deposition thickness of the dopant source layer of the first conductivity type impurity deposited on the front side of the substrate silicon wafer can be 5 nm, 10 nm, 15 nm, 20 nm, 30 nm, 35 nm, 40 nm, 45 nm, 50 nm, 55 nm, 60 nm, etc., and the deposition thickness of the mask layer can be 2 nm, 10 nm, 20 nm, 30 nm, 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, 100 nm, 150 nm, 200 nm, etc.

[0030] Optionally, the doping concentration of the dopant source layer for the first conductivity type impurity is 1*10. 17 -9*10 21 cm -3 The diffusion depth is 0.005 μm-3 μm. The doping concentration can be 1*10⁻⁶. 16 cm -3 1*10 17 cm-3 1*10 18 cm -3 1*10 19 cm -3 1*10 20 cm -3 1*10 21 cm -3 9*10 21 cm -3 The diffusion depths are 0.005μm, 0.01μm, 0.1μm, 1μm, 2μm, and 3μm.

[0031] Optionally, the dopant source layer of the first conductivity type impurity is a phosphorus-containing silicon oxide layer or a boron-containing silicon oxide layer, and the mask layer is composed of one or more of silicon nitride, silicon oxynitride, and silicon oxide.

[0032] Optionally, in step S3, film opening and cleaning, the dopant source layer and mask layer of some first conductivity type impurities on the back side of the substrate silicon wafer are removed by means of laser, etching paste, photolithography or plasma etching.

[0033] Optionally, S4, the one-step co-doping, is a phosphorus expansion or boron expansion process. When the dopant source layer of the first conductivity type impurity is a phosphorus-containing silicon oxide layer, the one-step co-doping is a boron expansion process, the boron expansion temperature is 600℃-1000℃, and the boron expansion time is 5min-180min; when the dopant source layer of the first conductivity type impurity is a boron-containing silicon oxide layer, the one-step co-doping is a phosphorus expansion process, the phosphorus expansion temperature is 600℃-1000℃, and the phosphorus expansion time is 5min-180min.

[0034] Optionally, the boron diffusion temperature can be 600℃, 650℃, 700℃, 750℃, 800℃, 850℃, 900℃, 950℃, 1000℃, etc., and the boron diffusion time can be 5 min, 10 min, 20 min, 30 min, 40 min, 50 min, 60 min, 70 min, 80 min, 90 min, 100 min, 110 min, 120 min, 130 min, 140 min, 150 min, 160 min, 170 min, 180 min, etc.; the phosphorus diffusion temperature can be 600℃, 650℃, 700℃, 750℃, 800℃, 850℃, 900℃, 950℃, 1000℃, etc., and the phosphorus diffusion time can be 5 min, 10 min, 20 min, 30 min, 40 min, 50 min, 60 min, 70 min, 80 min, 90 min, 100 min, 110 min, etc. min, 120 min, 130 min, 140 min, 150 min, 160 min, 170 min, 180 min, etc.

[0035] By adopting the above technical solution, within the time and temperature range of boron or phosphorus diffusion in this application, simultaneous doping of the FSF on the front side of the substrate silicon wafer and the P and N regions on the back side can be achieved simultaneously without multiple masking processes, simplifying the process steps and shortening the overall process time, while ensuring improved cell conversion efficiency.

[0036] Optionally, in S2, the dopant source layer and mask layer for depositing the first type of conductivity impurity, the thickness of the dopant source layer for depositing the first type of conductivity impurity on the outside of the polysilicon layer on the back side of the substrate silicon wafer by CVD is 10nm-100nm, and the thickness of the mask layer is 2nm-200nm.

[0037] Optionally, the S2 deposition of the dopant source layer and mask layer for the first conductivity type impurity further includes: sequentially depositing a 5nm-60nm dopant source layer and a 2nm-200nm mask layer for the first conductivity type impurity on the outer side of the single crystal silicon layer on the front side of the substrate silicon wafer.

[0038] Optionally, the doping concentration of the dopant source layer for the first conductivity type impurity on the front side of the substrate silicon wafer after high-temperature diffusion is 1*10. 16 -1*10 21 cm -3 The diffusion depth is 0.005μm-3μm. The size of the pyramid's apex accounts for 1 / 50 to 1 / 10 of the total pyramid structure size, and the concentration at the apex is 10 times that at the base. 2 ~105 times.

[0039] Optionally, the deposition temperature for CVD is 150-800℃.

[0040] Optionally, the tunneling oxide layer is a phosphorus silicon oxide layer or a borosilicate layer, and the mask layer is composed of one or more of silicon nitride, silicon oxynitride, and silicon oxide.

[0041] Optionally, in step S3, film opening and cleaning, the dopant source layer and mask layer of some first conductivity type impurities on the back side of the substrate silicon wafer are removed by means of laser, etching paste, photolithography or plasma etching.

[0042] Optionally, the back side is laser-etched with a wavelength of 200 nm to 1064 nm and a power of ≥1W, and then acid-washed and water-washed in a cleaning machine, and dried; or in a screen printing machine, an etching paste is applied according to the N-area pattern on the back side, screen-printed and left to stand for ≥0.5 min, and then water-washed and dried in a cleaning machine.

[0043] Secondly, this application provides a TBC battery, which adopts the following technical solution:

[0044] A TBC (Transient Carbon Cell) includes a substrate silicon wafer having a front side facing the sun during normal operation and a back side opposite to the front side. The back side of the substrate silicon wafer is provided with a tunneling oxide layer, a first conductivity type impurity polycrystalline silicon region, a second conductivity type impurity polycrystalline silicon region, a gap region, a first dielectric layer, and a metal electrode. The first conductivity type impurity polycrystalline silicon region and the second conductivity type impurity polycrystalline silicon region have opposite electrical properties. The metal electrode forms an ohmic contact with either the first conductivity type impurity polycrystalline silicon region or the second conductivity type impurity polycrystalline silicon region. The front side of the substrate silicon wafer is provided with a front surface field and a second dielectric layer sequentially from the inside out.

[0045] The doping concentration of the dopant source layer in the front surface field after high-temperature diffusion is 1*10. 16 -1*10 21 cm -3 The diffusion depth is 0.005μm-3μm; the doping concentration of the second conductivity type impurity polycrystalline silicon region is 1*10. 19 -1*10 22 cm -3 The doping concentration of the region where the metal electrode contacts the polycrystalline silicon region with impurities of the first conductivity type or the second conductivity type is 5*10. 18 -1*10 21 cm -3 The doping concentration of the gap region is 1*10. 15 -1*10 20 cm-3 .

[0046] In summary, this application has the following beneficial effects:

[0047] 1. A dopant source layer of the first conductivity type impurity is deposited on the front and back sides of the cell using CVD. A high-temperature step is used to simultaneously form the FSF, N-region, and P-region of the TBC cell, while reducing the high-temperature temperature. After texturing, the original FSF is retained at the tip or the entire pyramid of the textured surface, enhancing the passivation of the textured tip or surface and promoting the movement of charge carriers from the front surface to the back surface. This process is compatible with both single and double insertion processes. Post-texturing does not require a thicker BSG layer, reducing the oxygen content of the silicon wafer. It allows for flexible adjustment of doping concentration, shortening the TBC cell process and time. It eliminates the need for additional thermal processes, heating / cooling processes, wet processes, and film opening processes, which helps reduce the series resistance of solar cells, improves the conversion efficiency, enhances the UV resistance of TBC cells, simplifies the process steps and time, saves production costs, and facilitates large-scale production.

[0048] 2. After CVD deposition of the dopant source layer of the first conductivity type impurity, the high temperature can be reduced; subsequent texturing does not require a thicker BSG layer, reducing the oxygen content of the silicon wafer, reducing BO recombination in the cell, and improving cell efficiency. Attached Figure Description

[0049] Figure 1 This is a schematic diagram of the TBC battery structure.

[0050] Figure 2 This is a schematic flowchart of the preparation method of the TBC battery in Example 1.1.

[0051] Figure 3 This is a schematic flowchart of the preparation method of the TBC battery in Example 2.1.

[0052] Figure 4 This is a schematic diagram of the textured doped structure of a TBC battery.

[0053] Explanation of reference numerals in the attached figures: 1. Second dielectric layer; 2. Front surface field; 3. Substrate silicon wafer; 4. Tunneling oxide layer; 5. Second conductivity type impurity polysilicon region; 6. First dielectric layer; 7. Electrode; 8. Gap region; 9. First conductivity type impurity polysilicon region. Detailed Implementation

[0054] Unless otherwise specified, the experimental methods described in the following embodiments of the present invention are generally performed under conventional conditions or as recommended by the manufacturer. All commonly used chemical reagents used in the embodiments are commercially available products.

[0055] Examples 1.1-1.3 (N-type backside deposition)

[0056] Example 1.1

[0057] like Figure 1 As shown, a TBC battery includes a substrate silicon wafer 3, which is an N-type silicon wafer. The substrate silicon wafer has a front side facing the sun during normal operation and a back side opposite to the front side. The back side of the substrate silicon wafer is provided with a tunneling oxide layer 4, a second conductivity type impurity polycrystalline silicon region 5, a first dielectric layer 6, a metal electrode 7, a gap region 8, and a first conductivity type impurity polycrystalline silicon region 9. The first conductivity type impurity polycrystalline silicon region 9 and the second conductivity type impurity polycrystalline silicon region 5 have opposite electrical properties. The metal electrode 7 forms an ohmic contact with the first conductivity type impurity polycrystalline silicon region 9 or the second conductivity type impurity polycrystalline silicon region 5. The front side of the substrate silicon wafer 3 is provided with a front surface field 2 and a second dielectric layer 1 from the inside to the outside.

[0058] The doping concentration of the dopant source layer after high-temperature diffusion in the front surface field is 1*10. 16 -1*10 21 cm -3 The diffusion depth is 0.005μm-3μm; the doping concentration of the second conductivity type impurity polycrystalline silicon region is 1*10. 19 -1*10 22 cm -3 The doping concentration of the region where the metal electrode contacts the polycrystalline silicon region containing impurities of the first conductivity type or the second conductivity type is 5*10. 18 -1*10 21 cm -3 The doping concentration in the gap region is 1*10. 15 -1*10 20 cm -3 .

[0059] like Figure 2 As shown, a method for preparing a TBC battery includes the following steps:

[0060] 1. Cleaning and polishing: The substrate silicon wafer 3 is cleaned and polished. The resistivity of the substrate silicon wafer 3 is 0.1Ωcm and the thickness is 100μm.

[0061] 2. CVD deposition of tunneling SiOx and Poly layers: On the device obtained after cleaning and polishing, a 3nm tunneling oxide layer 4 and a 60nm polycrystalline silicon layer are sequentially deposited in an LPCVD furnace tube.

[0062] 3. CVD deposition of dopant source layer and mask layer for first conductivity type impurities on the back side: In a PECVD furnace tube, using PH3, SiH4, and N2O as deposition raw materials, at a deposition temperature of 300℃ and a time of 5min, a phosphorus-containing silicon oxide layer with a thickness of 20nm is deposited on the polycrystalline silicon layer; at a deposition temperature of 300℃, a silicon oxide mask layer with a thickness of 10nm is deposited on the phosphorus-containing silicon oxide layer.

[0063] 4. Film opening and cleaning: The back side of the device obtained in step 3 is opened using a laser with a wavelength of 500 nm and a power of 1W. Then, it is acid-washed and water-washed and dried in a cleaning machine to reserve space for the diffusion of dopant sources in the polycrystalline silicon region 5 of the second conductivity type.

[0064] 5. Boron expansion: The device obtained in step 4 is placed in a boron expansion tube for boron expansion. The boron expansion temperature is 700 ℃ and the boron expansion time is 10 min, so that the back PSG becomes a barrier layer and an N-region diffusion layer. The back side of the substrate silicon wafer 3 forms a second conductivity type impurity polysilicon region 5 and a first conductivity type impurity polysilicon region 9 with opposite electrical properties. The front surface field 2 is formed on the front side of the substrate silicon wafer 3.

[0065] 6. Gap region preparation: The back side of the device obtained in step 5 is laser-cut with a wavelength of 500 nm and a power of 1 W. Then, it is acid-washed and water-washed in a cleaning machine and dried to obtain the Gap region 8.

[0066] 7. Acid etching, texturing, and removal of PSG and BSG: The device obtained in step 6 is sequentially subjected to acid etching and front-side texturing. A mixed acid solution containing HNO3 with a concentration of 20% is used to etch the front side. Then, a mixed solution of 20% alkaline solution and texturing solution is used for etching to form a textured pyramid structure on the surface of the substrate silicon wafer 3 (e.g., ...). Figure 4 As shown), the height of the pyramid structure is 2 μm. The doping concentration decreases by 100 times for every 0.01 micrometers from the top to the bottom of the pyramid. Then, it is placed in acid to remove BSG and PSG on the front, side and back sides. The device is then cleaned using RCA standard to remove surface contaminants.

[0067] 8. Passivation and antireflection: A passivation and antireflection dielectric layer is deposited on the surface of the device obtained in step 7 to form a second dielectric layer 1 and a first dielectric layer 6;

[0068] 9. Metallization: A metal electrode 7 is placed on the back side of the device obtained in step 8 to obtain a TBC battery structure.

[0069] Example 1.2

[0070] Reference Figure 2 A method for preparing a TBC battery differs from Example 1.1 in that the process parameters are different.

[0071] Specifically, the following steps are included:

[0072] 1. Cleaning and polishing: The substrate silicon wafer 3 is cleaned and polished. The resistivity of the substrate silicon wafer 3 is 0.1Ωcm and the thickness is 100μm.

[0073] 2. CVD deposition of tunneling SiOx and Poly layers: On the device obtained after cleaning and polishing, a 3nm tunneling oxide layer 4 and a 50nm polycrystalline silicon layer are sequentially deposited in the LPCVD furnace tube.

[0074] 3. CVD deposition of dopant source layer and mask layer for first conductivity type impurities on the back side: In a PECVD furnace tube, PH3, SiH4, and N2O are used as deposition raw materials. The deposition temperature is 200℃ and the time is 90min. A phosphorus-containing silicon oxide layer with a thickness of 10 nm is deposited on the polycrystalline silicon layer. The deposition temperature is 800℃. A silicon oxide mask layer with a thickness of 2 nm is deposited on the phosphorus-containing silicon oxide layer.

[0075] 4. Film opening and cleaning: The back side of the device obtained in step 3 is opened using a laser with a wavelength of 200 nm and a power of ≥1W. Then, it is acid-washed and water-washed in a cleaning machine and dried to reserve deposition space for the second type of conductivity impurity polycrystalline silicon region 5.

[0076] 5. Boron expansion: The device obtained in step 4 is placed in a boron expansion tube for boron expansion. The boron expansion temperature is 600 ℃ and the boron expansion time is 180 min, so that the back PSG becomes a barrier layer and an N-region diffusion layer. The back side of the substrate silicon wafer 3 forms a second conductivity type impurity polysilicon region 5 and a first conductivity type impurity polysilicon region 9 with opposite electrical properties, and the front surface field 2 is formed on the front side of the substrate silicon wafer 3.

[0077] 6. Gap region preparation: The back side of the device obtained in step 5 is laser-cut with a wavelength of 200 nm and a power of ≥1W. Then, it is acid-washed and water-washed in a cleaning machine and dried to obtain the Gap region 8.

[0078] 7. Acid etching, texturing, and removal of PSG and BSG: The device obtained in step 6 is subjected to acid etching and front-side texturing. The front side is etched with a mixed acid solution containing HNO3 at a concentration of 20%. Then, a 1% texturing mixed solution is used to etch, forming a textured pyramid structure on the surface of the substrate silicon wafer 3. The height of the pyramid structure is 0.1 μm, and the doping concentration decreases by a factor of 10 for every 0.01 micrometers from the top to the bottom of the pyramid. Then, the device is immersed in acid to remove BSG and PSG from the front, sides, and back. Finally, the device is cleaned using RCA standard cleaning to remove surface contaminants.

[0079] 8. Passivation and antireflection: A passivation and antireflection dielectric layer is deposited on the surface of the device obtained in step 7 to form a second dielectric layer 1 and a first dielectric layer 6;

[0080] 9. Metallization: A metal electrode 7 is placed on the back side of the device obtained in step 8 to obtain a TBC battery structure.

[0081] Example 1.3

[0082] Reference Figure 2 A method for preparing a TBC battery differs from Example 1.1 in that the process parameters are different.

[0083] Specifically, the following steps are included:

[0084] 1. Cleaning and polishing: The substrate silicon wafer 3 is cleaned and polished. The resistivity of the substrate silicon wafer 3 is 0.1Ωcm and the thickness is 100μm.

[0085] 2. CVD deposition of tunneling SiOx and Poly layers: On the device obtained after cleaning and polishing, a 3nm tunneling oxide layer 4 and a 400nm polycrystalline silicon layer are sequentially deposited in an LPCVD furnace tube.

[0086] 3. CVD deposition of dopant source layer and mask layer for first conductivity type impurities on the back side: In a PECVD furnace tube, PH3, SiH4, and N2O are used as deposition raw materials. The deposition temperature is 800℃ and the time is 5min. A phosphorus-containing silicon oxide layer with a thickness of 100 nm is deposited on the polycrystalline silicon layer. The deposition temperature is 200℃. A silicon oxide mask layer with a thickness of 200 nm is deposited on the phosphorus-containing silicon oxide layer to form the polycrystalline silicon region 9 with first conductivity type impurities.

[0087] 4. Film opening and cleaning: The back side of the device obtained in step 3 is opened using a laser with a wavelength of 1064 nm and a power of ≥1W. Then, it is acid-washed and water-washed in a cleaning machine and dried to reserve deposition space for the second type of conductivity impurity polysilicon region 5.

[0088] 5. Boron expansion: The device obtained in step 4 is placed in a boron expansion tube for boron expansion. The boron expansion temperature is 1000 ℃ and the boron expansion time is 5 min, so that the back PSG becomes a barrier layer and an N-region diffusion layer. The back side of the substrate silicon wafer 3 forms a second conductivity type impurity polysilicon region 5 and a first conductivity type impurity polysilicon region 9 with opposite electrical properties. The front surface field 2 is formed on the front side of the substrate silicon wafer 3.

[0089] 6. Film opening and cleaning: The back side of the device obtained in step 5 is opened using a laser with a wavelength of 1064 nm and a power of ≥1W. Then, it is acid-washed and water-washed in a cleaning machine and dried to obtain the gap area 8.

[0090] 7. Acid etching, texturing, and removal of PSG and BSG: The device obtained in step 6 is subjected to acid etching and front-side texturing. A mixed acid solution containing HNO3 with a concentration of 30% is used to etch the front side. Then, a 10% texturing mixed solution is used to etch, forming a textured pyramid structure on the surface of the substrate silicon wafer 3. The height of the pyramid structure is 3μm, and the doping concentration decreases by 10 μm for every 0.01 μm from the top to the bottom of the pyramid. 4 Then, immerse the device in acid to remove BSG and PSG from the front, sides, and back; then perform RCA standard cleaning to remove surface contaminants.

[0091] 8. Passivation and antireflection: A passivation and antireflection dielectric layer is deposited on the surface of the device obtained in step 7 to form a second dielectric layer 1 and a first dielectric layer 6;

[0092] 9. Metallization: A metal electrode 7 is placed on the back side of the device obtained in step 8 to obtain a TBC battery structure.

[0093] Example 1.4

[0094] like Figure 1 As shown, a TBC battery includes a substrate silicon wafer 3, which is a P-type silicon wafer. The substrate silicon wafer has a front side facing the sun during normal operation and a back side opposite to the front side. The back side of the substrate silicon wafer is provided with a tunneling oxide layer 4, a second conductivity type impurity polycrystalline silicon region 5, a first dielectric layer 6, a metal electrode 7, a gap region 8, and a first conductivity type impurity polycrystalline silicon region 9. The first conductivity type impurity polycrystalline silicon region 9 and the second conductivity type impurity polycrystalline silicon region 5 have opposite electrical properties. The metal electrode 7 forms an ohmic contact with the first conductivity type impurity polycrystalline silicon region 9 or the second conductivity type impurity polycrystalline silicon region 5. The front side of the substrate silicon wafer 3 is provided with a front surface field 2 and a second dielectric layer 1 from the inside to the outside.

[0095] like Figure 2 As shown, a method for preparing a TBC battery includes the following steps:

[0096] 1. Cleaning and polishing: The substrate silicon wafer 3 is cleaned and polished. The resistivity of the substrate silicon wafer 3 is 0.1Ωcm and the thickness is 100μm.

[0097] 2. CVD deposition of tunneling SiOx and Poly layers: On the device obtained after cleaning and polishing, a 3nm tunneling oxide layer 4 and a 60nm polycrystalline silicon layer are sequentially deposited in an LPCVD furnace tube.

[0098] 3. CVD deposition of dopant source layer and mask layer for first conductivity type impurities on the back side: In a PECVD furnace tube, using BH3, SiH4, and N2O as deposition raw materials, at a deposition temperature of 300℃ and a time of 5min, a 20nm thick boron-containing silicon oxide layer is deposited on the polycrystalline silicon layer; at a deposition temperature of 300℃, a 10nm thick silicon oxide mask layer is deposited on the boron-containing silicon oxide layer.

[0099] 4. Film opening and cleaning: The back side of the device obtained in step 3 is opened using a laser with a wavelength of 500 nm and a power of 1W. Then, it is acid-washed and water-washed and dried in a cleaning machine to reserve space for the diffusion of dopant sources in the polycrystalline silicon region 5 of the second conductivity type.

[0100] 5. Phosphorus diffusion: The device obtained in step 4 is placed in a phosphorus diffusion tube for phosphorus diffusion. The phosphorus diffusion temperature is 700 ℃ and the phosphorus diffusion time is 10 min, so that the back side BSG becomes a barrier layer and an N-region diffusion layer. The back side of the substrate silicon wafer 3 forms a second conductivity type impurity polysilicon region 5 and a first conductivity type impurity polysilicon region 9 with opposite electrical properties. The front surface field 2 is formed on the front side of the substrate silicon wafer 3.

[0101] 6. Gap region preparation: The back side of the device obtained in step 5 is laser-cut with a wavelength of 500 nm and a power of 1 W. Then, it is acid-washed and water-washed in a cleaning machine and dried to obtain the Gap region 8.

[0102] 7. Acid etching, texturing, and removal of PSG and BSG: The device obtained in step 6 is subjected to acid etching and front-side texturing. A mixed acid solution containing HNO3 with a concentration of 20% is used to etch the front side. Then, a 20% texturing mixed solution is used to etch, forming a textured pyramid structure on the surface of the substrate silicon wafer 3 (e.g., Figure 4 As shown), the height of the pyramid structure is 2 μm. The doping concentration decreases by 100 times for every 0.01 micrometers from the top to the bottom of the pyramid. Then, it is placed in acid to remove BSG and PSG on the front, side and back sides. The device is then cleaned using RCA standard to remove surface contaminants.

[0103] 8. Passivation and antireflection: A passivation and antireflection dielectric layer is deposited on the surface of the device obtained in step 7 to form a second dielectric layer 1 and a first dielectric layer 6;

[0104] 9. Metallization: A metal electrode 7 is placed on the back side of the device obtained in step 8 to obtain a TBC battery structure.

[0105] The difference between Example 1.4 and Example 1.1 is that the substrate silicon wafer 3 is a P-type substrate silicon wafer; the dopant source layer for the first conductivity type impurity deposited on the back side in step 3 is a boron-containing silicon oxide layer; and step 5 is a phosphorus diffusion process.

[0106] Example 1.5

[0107] A method for preparing a TBC battery differs from that in Example 1.1 in that step 6, which prepares the Gap region, is not performed; all other steps are the same.

[0108] Example 1.6

[0109] A method for preparing a TBC battery differs from that in Example 1.1 in that...

[0110] 2. CVD deposition of tunneling SiOx and Poly layers: On the device obtained after cleaning and polishing, a 3nm tunneling oxide layer 4 and a 300nm polycrystalline silicon layer are sequentially deposited in an LPCVD furnace tube.

[0111] 3. CVD deposition of the dopant source layer and mask layer for the first conductivity type impurities on the back side: In a PECVD furnace tube, using PH3, SiH4, and N2O as deposition materials, a phosphorus-containing silicon oxide layer with a thickness of 40 nm is deposited on the polycrystalline silicon layer at a deposition temperature of 450℃ and a time of 30 min; a silicon oxide mask layer with a thickness of 10 nm is then deposited on the phosphorus-containing silicon oxide layer at a deposition temperature of 450℃. The remaining steps are the same.

[0112] Examples 2.1-2.3 (using a P-type substrate, a dopant source layer and a mask layer of impurities of the first conductivity type are deposited on both the front and back sides of the substrate silicon wafer)

[0113] Example 2.1

[0114] Reference Figure 1 A TBC (Transient Carbon Cell) includes a substrate silicon wafer, which is a P-type silicon wafer. The substrate silicon wafer has a front side facing the sun during normal operation and a back side opposite to the front side. The back side of the substrate silicon wafer is provided with a tunneling oxide layer, a first conductivity type impurity polycrystalline silicon region, a second conductivity type impurity polycrystalline silicon region, a gap region, a first dielectric layer, and a metal electrode. The first conductivity type impurity polycrystalline silicon region and the second conductivity type impurity polycrystalline silicon region have opposite electrical properties. The metal electrode forms an ohmic contact with either the first conductivity type impurity polycrystalline silicon region or the second conductivity type impurity polycrystalline silicon region. The front side of the substrate silicon wafer is provided with a front surface field and a second dielectric layer from the inside to the outside.

[0115] The doping concentration of the dopant source layer in the front surface field after high-temperature diffusion is 1*10. 16 -1*10 21 cm -3 The diffusion depth is 0.005μm-3μm; the doping concentration of the second conductivity type impurity polycrystalline silicon region is 1*10. 19 -1*10 22 cm -3The doping concentration of the region where the metal electrode contacts the polycrystalline silicon region with impurities of the first conductivity type or the second conductivity type is 5*10. 18 -1*10 21 cm -3 The doping concentration of the gap region is 1*10. 15 -1*10 20 cm -3 .

[0116] like Figure 3 As shown, a method for preparing a TBC battery includes the following steps:

[0117] 1. Cleaning and polishing: Cleaning and polishing the silicon substrate;

[0118] 2. CVD deposition of tunneling SiOx and Poly layers: A 5 nm tunneling SiOx layer and a 60 nm Poly layer are sequentially deposited on the device obtained in step 1 in an LPCVD furnace tube.

[0119] 3. CVD deposition of dopant source layer and mask layer for first conductivity type impurities on the back side: Using BH3, SiH4, and N2O as deposition raw materials, a 50nm thick boron-containing silicon oxide layer is deposited on the polycrystalline silicon layer at a deposition temperature of 400℃ and a time of 20min; a 30nm thick silicon oxide mask layer is deposited on the boron-containing silicon oxide layer at a deposition temperature of 400℃.

[0120] 4. CVD deposition of dopant source layer and mask layer for first conductivity type impurities on the front side: Using BH3, SiH4, and N2O as deposition materials, the deposition temperature is 400℃ and the time is 20 min to deposit a 30 nm thick boron-containing silicon oxide layer on the front side of the substrate silicon wafer; the deposition temperature is 200℃ to deposit a 5 nm thick silicon oxide mask layer on the boron-containing silicon oxide layer.

[0121] 5. Film opening and cleaning: The back side of the device obtained in step 3 is opened using a laser with a wavelength of 500 nm and a power of 1W. Then, it is acid-washed and water-washed in a cleaning machine and dried to provide space for the diffusion of dopant sources of the second conductivity type impurities.

[0122] 6. Phosphorus diffusion: The device obtained in step 5 is placed in a phosphorus diffusion tube for phosphorus diffusion. The phosphorus diffusion temperature is 800℃ and the phosphorus diffusion time is 20 min. The back silicon oxide mask layer is a P-region barrier layer, and the back BSG forms a P-region diffusion layer. At the same time, N-doped FSF is diffused on the front side and forms a N-region on the back side.

[0123] 7. Preparation of gap region: The back side of the device obtained in step 5 is opened with a laser at a wavelength of 800nm ​​and a power of ≥1W. Then, it is acid-washed and water-washed in a cleaning machine and dried to obtain the gap region.

[0124] 8. Acid etching, texturing, and removal of PSG and BSG: The device obtained in step 7 is subjected to acid etching and front-side texturing. A mixed acid solution containing HNO3 with a concentration of 20% is used to etch the front side. Then, a 20% texturing mixed solution is used to etch, forming a textured pyramid structure on the surface of the substrate silicon wafer 3 (e.g., Figure 4 As shown), the height of the pyramid structure is 2 μm. The doping concentration decreases by 100 times for every 0.01 micrometers from the top to the bottom of the pyramid. Then, it is placed in acid to remove BSG and PSG on the front, side and back sides. The device is then cleaned using RCA standard to remove surface contaminants.

[0125] 9. Passivation and Anti-reflection: A passivation and anti-reflection dielectric layer is deposited on the surface of the device obtained in step 8, including a second dielectric layer and a first dielectric layer;

[0126] 10. Metallization: A back metal electrode is disposed on the device obtained in step 9 to obtain the TBC battery structure.

[0127] Example 2.2

[0128] Reference Figure 3 The preparation method of a TBC battery differs from that in Example 2.1 in that the preparation process parameters are different, and specifically includes the following steps:

[0129] 1. Cleaning and polishing: Cleaning and polishing the silicon substrate;

[0130] 2. CVD deposition of tunneling SiOx and Poly layers: A 0.5 nm tunneling SiOx layer and a 400 nm Poly layer are sequentially deposited on the device obtained in step 1 in an LPCVD furnace tube.

[0131] 3. CVD deposition of dopant source layer and mask layer for first conductivity type impurities on the back side: Using BH3, SiH4, and N2O as deposition raw materials, a 10nm thick boron-containing silicon oxide layer is deposited on the polycrystalline silicon layer at a deposition temperature of 200℃ and a time of 30min; a 200nm thick silicon oxide mask layer is deposited on the boron-containing silicon oxide layer at a deposition temperature of 600℃.

[0132] 4. CVD deposition of dopant source layer and mask layer for first conductivity type impurities on the front side: Using BH3, SiH4, and N2O as deposition materials, the deposition temperature is 200℃ and the time is 20 min to deposit a 5 nm thick boron-containing silicon oxide layer on the front side of the substrate silicon wafer; the deposition temperature is 400℃ to deposit a 200 nm thick silicon oxide mask layer on the boron-containing silicon oxide layer.

[0133] 5. Film opening and cleaning: The back side of the device obtained in step 3 is opened using a laser with a wavelength of 500 nm and a power of 1W. Then, it is acid-washed and water-washed in a cleaning machine and dried to provide space for the diffusion of dopant sources of the second conductivity type impurities.

[0134] 6. Phosphorus diffusion: Place the device obtained in step 5 into a phosphorus diffusion tube for phosphorus diffusion. The phosphorus diffusion temperature is 600℃ and the phosphorus diffusion time is 120 min. The back silicon oxide mask layer is the P-region barrier layer. The back BSG forms the P-region diffusion layer. At the same time, the front diffusion forms the N-doped FSF, which is connected to the back N-region.

[0135] 7. Preparation of gap region: The back side of the device obtained in step 5 is opened with a laser at a wavelength of 800nm ​​and a power of ≥1W. Then, it is acid-washed and water-washed in a cleaning machine and dried to obtain the gap region.

[0136] 8. Acid etching, texturing, and removal of PSG and BSG: The device obtained in step 7 is subjected to acid etching and front-side texturing. A mixed acid solution containing HNO3 with a concentration of 20% is used to etch the front side. Then, a 20% texturing mixed solution is used to etch, forming a textured pyramid structure on the surface of the substrate silicon wafer 3 (e.g., Figure 4 As shown), the height of the pyramid structure is 0.2 μm. The doping concentration decreases by 100 times for every 0.01 micrometers from the top to the bottom of the pyramid. Then, it is placed in acid to remove BSG and PSG on the front, side and back sides. The device is then cleaned using RCA standard to remove surface contaminants.

[0137] 9. Passivation and Anti-reflection: A passivation and anti-reflection dielectric layer is deposited on the surface of the device obtained in step 8, including a second dielectric layer and a first dielectric layer;

[0138] 10. Metallization: A back metal electrode is disposed on the device obtained in step 9 to obtain the TBC battery structure.

[0139] Example 2.3

[0140] Reference Figure 3 A TBC battery and its preparation method differ from Example 2.1 in that the preparation process parameters are different, specifically including the following steps:

[0141] 1. Cleaning and polishing: Cleaning and polishing the silicon substrate;

[0142] 2. CVD deposition of tunneling SiOx and Poly layers: A 20 nm tunneling SiOx layer and a 50 nm Poly layer are sequentially deposited on the device obtained in step 1 in an LPCVD furnace tube.

[0143] 3. CVD deposition of dopant source layer and mask layer for first conductivity type impurities on the back side: Using BH3, SiH4, and N2O as deposition raw materials, a 100nm thick boron-containing silicon oxide layer is deposited on the polycrystalline silicon layer at a deposition temperature of 600℃ and a time of 30min; a 2nm thick silicon oxide mask layer is deposited on the boron-containing silicon oxide layer at a deposition temperature of 200℃.

[0144] 4. CVD deposition of dopant source layer and mask layer for first conductivity type impurities on the front side: Using BH3, SiH4, and N2O as deposition materials, the deposition temperature is 400℃ and the time is 40 min to deposit a 60 nm thick boron-containing silicon oxide layer on the front side of the substrate silicon wafer; the deposition temperature is 200℃ to deposit a 2 nm thick silicon oxide mask layer on the boron-containing silicon oxide layer.

[0145] 5. Film opening and cleaning: The back side of the device obtained in step 3 is opened using a laser with a wavelength of 500 nm and a power of 1W. Then, it is acid-washed and water-washed in a cleaning machine and dried to provide space for the diffusion of dopant sources of the second conductivity type impurities.

[0146] 6. Phosphorus diffusion: Place the device obtained in step 5 into a phosphorus diffusion tube for phosphorus diffusion. The phosphorus diffusion temperature is 1000℃ and the phosphorus diffusion time is 5 min. The back silicon oxide mask layer is the P-region barrier layer. The back BSG forms the P-region diffusion layer. At the same time, the front diffusion forms the N-doped FSF, which is connected to the back N-region.

[0147] 7. Preparation of gap region: The back of the device obtained in step 5 is laser-cut with a wavelength of 800nm ​​and a power of 1W. Then, it is acid-washed and water-washed in a cleaning machine and dried to obtain the gap region.

[0148] 8. Acid etching, texturing, and removal of PSG and BSG: The device obtained in step 7 is subjected to acid etching and front-side texturing. A mixed acid solution containing HNO3 with a concentration of 20% is used to etch the front side. Then, a 20% texturing mixed solution is used to etch, forming a textured pyramid structure on the surface of the substrate silicon wafer 3 (e.g., Figure 4 As shown), the pyramid structure has a height of 3 μm, and the doping concentration decreases by 10 for every 0.01 μm from the top to the bottom. 4 Then, immerse the device in acid to remove BSG and PSG from the front, sides, and back; then perform RCA standard cleaning to remove surface contaminants.

[0149] 9. Passivation and Anti-reflection: A passivation and anti-reflection dielectric layer is deposited on the surface of the device obtained in step 8, including a second dielectric layer and a first dielectric layer;

[0150] 10. Metallization: A back metal electrode is disposed on the device obtained in step 9 to obtain the TBC battery structure.

[0151] Example 2.4

[0152] Reference Figure 1 A TBC (Transient-Brain Cell) includes a substrate silicon wafer, which is an N-type silicon wafer. The substrate silicon wafer has a front side facing the sun during normal operation and a back side opposite to the front side. The back side of the substrate silicon wafer is provided with a tunneling oxide layer, a first conductivity type impurity polycrystalline silicon region, a second conductivity type impurity polycrystalline silicon region, a gap region, a first dielectric layer, and a metal electrode. The first conductivity type impurity polycrystalline silicon region and the second conductivity type impurity polycrystalline silicon region have opposite electrical properties. The metal electrode forms an ohmic contact with either the first conductivity type impurity polycrystalline silicon region or the second conductivity type impurity polycrystalline silicon region. The front side of the substrate silicon wafer is provided with a front surface field and a second dielectric layer from the inside to the outside.

[0153] like Figure 3 As shown, a method for preparing a TBC battery includes the following steps:

[0154] 1. Cleaning and polishing: Cleaning and polishing the silicon substrate;

[0155] 2. CVD deposition of tunneling SiOx and Poly layers: A 5 nm tunneling SiOx layer and a 60 nm Poly layer are sequentially deposited on the device obtained in step 1 in an LPCVD furnace tube.

[0156] 3. CVD deposition of dopant source layer and mask layer for first conductivity type impurities on the back side: Using PH3, SiH4, and N2O as deposition raw materials, a phosphorus-containing silicon oxide layer with a thickness of 50 nm was deposited on the polycrystalline silicon layer at a deposition temperature of 400℃ and a time of 20 min; a silicon oxide mask layer with a thickness of 30 nm was deposited on the phosphorus-containing silicon oxide layer at a deposition temperature of 400℃.

[0157] 4. CVD deposition of dopant source layer and mask layer for first conductivity type impurities on the front side: Using PH3, SiH4, and N2O as deposition materials, the deposition temperature is 400℃ and the time is 20 min to deposit a 30 nm thick phosphorus-containing silicon oxide layer on the front side of the substrate silicon wafer; the deposition temperature is 200℃ to deposit a 5 nm thick silicon oxide mask layer on the phosphorus-containing silicon oxide layer.

[0158] 5. Film opening and cleaning: The back side of the device obtained in step 3 is opened using a laser with a wavelength of 500 nm and a power of 1W. Then, it is acid-washed and water-washed in a cleaning machine and dried to provide space for the diffusion of dopant sources of the second conductivity type impurities.

[0159] 6. Boron diffusion: The device obtained in step 5 is placed in a phosphorus diffusion tube for boron diffusion. The boron diffusion temperature is 800℃ and the boron diffusion time is 20 min. The back silicon oxide mask layer is a P-region barrier layer, and the back BSG forms a P-region diffusion layer. At the same time, N-doped FSF is diffused on the front side and forms a N-region on the back side.

[0160] 7. Preparation of gap region: The back side of the device obtained in step 5 is opened with a laser at a wavelength of 800nm ​​and a power of ≥1W. Then, it is acid-washed and water-washed in a cleaning machine and dried to obtain the gap region.

[0161] 8. Acid etching, texturing, and removal of PSG and BSG: The device obtained in step 7 is subjected to acid etching and front-side texturing. A mixed acid solution containing HNO3 with a concentration of 20% is used to etch the front side. Then, a 20% texturing mixed solution is used to etch, forming a textured pyramid structure on the surface of the substrate silicon wafer 3 (e.g., Figure 4 As shown), the height of the pyramid structure is 2 μm. The doping concentration decreases by 100 times for every 0.01 micrometers from the top to the bottom of the pyramid. Then, it is placed in acid to remove BSG and PSG on the front, side and back sides. The device is then cleaned using RCA standard to remove surface contaminants.

[0162] 9. Passivation and Anti-reflection: A passivation and anti-reflection dielectric layer is deposited on the surface of the device obtained in step 8, including a second dielectric layer and a first dielectric layer;

[0163] 10. Metallization: A back metal electrode is disposed on the device obtained in step 9 to obtain the TBC battery structure.

[0164] The difference between Example 2.4 and Example 2.1 is that the substrate silicon wafer is an N-type silicon wafer, the deposited layers in steps 3 and 4 are both phosphorus-containing silicon oxide layers, and step 6 is a boron diffusion process.

[0165] Example 2.5

[0166] A method for preparing a TBC battery differs from Example 2.1 in that step 7, which involves preparing the gap region, is not performed.

[0167] Example 2.6

[0168] A method for preparing a TBC battery, based on Example 2.1, differs from Example 2.1 in that...

[0169] 2. CVD deposition of tunneling SiOx and Poly layers: On the device obtained after cleaning and polishing, a 3nm tunneling oxide layer 4 and a 300nm polycrystalline silicon layer are sequentially deposited in an LPCVD furnace tube.

[0170] 3. CVD deposition of dopant source layer and mask layer for first conductivity type impurities on the back side: In a PECVD furnace tube, PH3, SiH4, and N2O are used as deposition raw materials. The deposition temperature is 450℃ and the time is 30min. A phosphorus-containing silicon oxide layer with a thickness of 40nm is deposited on the polycrystalline silicon layer. At the deposition temperature of 450℃, a silicon oxide mask layer with a thickness of 10nm is deposited on the phosphorus-containing silicon oxide layer.

[0171] 4. CVD deposition of dopant source layer and mask layer for first conductivity type impurities on the front side: Using PH3, SiH4, and N2O as deposition materials, at a deposition temperature of 400℃ and a time of 20 min, a 10nm thick boron-silicon oxide layer is deposited on the front side of the substrate silicon wafer; at a deposition temperature of 400℃, a 40nm thick silicon oxide mask layer is deposited on the phosphorus-containing silicon oxide layer; the remaining steps are the same.

[0172] Comparative Example 1

[0173] A method for preparing a TBC battery containing FSF includes the following steps:

[0174] Cleaning → LPCVD formation of tunneling oxide layer and intrinsic amorphous silicon layer → High-temperature boron doping to complete doping and crystallization (Emitter) → Masking → Laser opening of BSG (N-region) and cleaning → Reverse etching → LPCVD formation of intrinsic amorphous silicon layer → High-temperature phosphorus doping to complete doping (BSF) → Masking → Front cleaning → FSF → Annealing → Laser opening of gap region → Texturing → Removal of silicon oxide compounds and RCA standard cleaning → Passivation antireflection layer formation → Metallization.

[0175] Comparative Example 2

[0176] A method for preparing a TBC battery differs from Example 1.1 in that the height of the pyramid structure is 5 μm.

[0177] Comparative Example 3

[0178] A method for preparing a TBC battery differs from that in Example 1.1 in that the height of the pyramid structure is 0.01 μm.

[0179] Comparative Example 4

[0180] A method for preparing a TBC battery differs from Example 1.1 in that texturing is not performed.

[0181] Comparative Example 5

[0182] A method for preparing a TBC battery differs from Example 2.1 in that texturing is not performed.

[0183] Comparative Example 6

[0184] A TBC battery differs from Example 1.1 in that the doping concentration is the same at the top and bottom of the pyramid structure formed by texturing.

[0185] Comparative Example 7

[0186] A TBC battery differs from Example 1.1 in that it has an undoped pyramid structure or no structure in which the concentration gradually decreases from the pyramid tip to the silicon substrate.

[0187] Comparative Example 8

[0188] A method for preparing a TBC cell differs from that in Example 1.1 in that no tunneling oxide layer and polycrystalline silicon layer are deposited on the front side of the substrate silicon wafer, so that no doping is performed on the front side of the substrate silicon wafer during the subsequent boron diffusion process.

[0189] Comparative Example 9

[0190] A method for preparing a TBC cell differs from that in Example 2.1 in that no tunneling oxide layer and polycrystalline silicon layer are deposited on the front side of the substrate silicon wafer, so that no doping is performed on the front side of the substrate silicon wafer during the subsequent boron diffusion process.

[0191] Performance testing

[0192] The batteries in Examples 1.1-1.3, Examples 2.1-2.3 and Comparative Example 1 were tested under the same conditions, and the test results are shown in Table 1.

[0193] Table 1 Test results of the examples and comparative examples

[0194]

[0195] Combining Examples 2.1-2.3 and Examples 1.1-1.3, and in conjunction with the appendix... Figure 2-3As can be seen, when a dopant source layer and a mask layer of the first conductivity type impurity are deposited on the front side of the silicon substrate (i.e., Examples 2.1-2.3), the pyramid structure formed by texturing after high-temperature one-step co-doping, with the mask layer playing a role in preventing the second conductivity type impurity from doping the front side of the silicon substrate during high-temperature diffusion, results in a higher concentration at the pyramid's apex than at its base. Furthermore, the pyramid has the same dopant source as the polycrystalline silicon region of the first conductivity type impurity on the back side of the silicon substrate, allowing the textured pyramid to retain its original FSF (free surface fairing), enhancing the textured pyramid apex or passivation, and simultaneously promoting the movement of charge carriers from the front surface to the back surface. This can significantly reduce the side base resistance loss and the total series resistance of the BC cell, increase the current density, and improve the UV degradation resistance of the BC cell. When the dopant source layer and mask layer of the first conductivity type impurity are not deposited on the front side of the silicon substrate (i.e., Examples 1.1-1.3), after high-temperature one-step co-doping, the polycrystalline silicon region on the front side of the silicon substrate with the second conductivity type impurity has the same dopant source as the polycrystalline silicon region on the back side of the silicon substrate. The pyramid structure formed after texturing can enhance the textured pyramid tip or textured passivation, and at the same time promote the movement of charge carriers on the front surface to the back field, increase the current density, and improve the UV degradation resistance of the BC cell.

[0196] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these modifications and improvements all fall within the scope of protection of the present invention. Therefore, the scope of protection of this patent should be determined by the appended claims.

Claims

1. A method for preparing a TBC battery, characterized in that: Includes the following steps: S1. Deposit tunneling oxide layer and polysilicon layer: Deposit tunneling oxide layer and polysilicon layer sequentially on the surface of the substrate silicon wafer; S2. Deposit a dopant source layer and a mask layer for impurities of the first conductivity type: Sequentially deposit a dopant source layer and a mask layer for impurities of the first conductivity type on the outer side of the polysilicon layer on the back side of the substrate silicon wafer. S3. Film opening and cleaning: Remove the dopant source layer and mask layer of the first conductivity type impurities on the back side of the substrate silicon wafer to form a reserved area; S4, One-step co-doping: The source layer of dopants with different conductivity types of impurities is co-doped in one step to form the back P-region and N-region as well as the front surface field. S5. Texturing: Forming a textured pyramid structure where the doping concentration gradually decreases from the side furthest from the substrate silicon wafer to the side closest to the substrate silicon wafer. Specifically, the doping concentration at the apex of the pyramid structure is higher than that at the base. The height of the pyramid structure is 0.1 μm to 3 μm, and the doping concentration decreases by 10⁻¹⁰ for every 0.01 micrometers from the apex to the base. 4 times.

2. The method for preparing a TBC battery according to claim 1, characterized in that: Before texturing in step S5, an etching step is included on the front side of the substrate silicon wafer. A mixed acid solution containing HNO3 is used to etch the front side, with an acid concentration of 1% to 30%. In step S5, texturing is performed using a texturing mixed solution with a concentration of 1% to 30% to form a textured pyramid structure on the surface of the substrate silicon wafer. Impurities of the first conductivity type or impurities of different conductivity types are located at the top of the pyramid structure or the entire pyramid structure.

3. The method for preparing a TBC battery according to claim 1, characterized in that: In S1, the deposited tunneling oxide layer and the polycrystalline silicon layer, the thickness of the tunneling oxide layer deposited on the surface of the substrate silicon wafer is 0.5nm~20nm, and the deposition thickness of the polycrystalline silicon layer is 50nm~400nm.

4. The method for preparing a TBC battery according to claim 1, characterized in that: In S2, the dopant source layer and mask layer for depositing the first type of conductivity impurity, the thickness of the dopant source layer for depositing the first type of conductivity impurity on the outside of the polycrystalline silicon layer on the back side of the substrate silicon wafer by CVD is 10nm~100nm, and the thickness of the mask layer is 2nm~200nm.

5. The method for preparing a TBC battery according to claim 1, characterized in that: The S2 method, which involves depositing a dopant source layer and a mask layer for depositing impurities of the first conductivity type, further includes: sequentially depositing a dopant source layer of the first conductivity type of impurities (5nm~60nm) and a mask layer (2nm~200nm) on the outer side of the single-crystal silicon layer on the front side of the substrate silicon wafer.

6. The method for preparing a TBC battery according to claim 5, characterized in that: The doping concentration of the dopant source layer of the first conductivity type impurity on the front side of the substrate silicon wafer after high-temperature diffusion is 1×10⁻⁶. 16 ~1×10 21 cm -3 The diffusion depth is 0.005μm~3μm, the size of the pyramid's apex is 1 / 50~1 / 10 of the total pyramid size, and the concentration at the apex is 10 times that at the base. 2 ~10 5 times.

7. A method for preparing a TBC battery according to any one of claims 4 to 5, characterized in that: The dopant source layer of the first conductivity type impurity is a phosphorus-containing silicon oxide layer or a boron-containing silicon oxide layer, and the mask layer is composed of one or more of silicon nitride, silicon oxynitride, and silicon oxide.

8. The method for preparing a TBC battery according to claim 1, characterized in that: In step S3, film opening and cleaning, the dopant source layer and mask layer of some first conductivity type impurities on the back side of the substrate silicon wafer are removed by means of laser, etching paste, photolithography or plasma etching.

9. The method for preparing a TBC battery according to claim 7, characterized in that: S4, the one-step co-doping process, is either phosphorus expansion or boron expansion. When the dopant source layer of the first conductivity type impurity is a phosphorus-containing silicon oxide layer, the one-step co-doping is a boron expansion process, the boron expansion temperature is 600℃~1000℃, and the boron expansion time is 5min~180min; when the dopant source layer of the first conductivity type impurity is a boron-containing silicon oxide layer, the one-step co-doping is a phosphorus expansion process, the phosphorus expansion temperature is 600℃~1000℃, and the phosphorus expansion time is 5min~180min.

10. A TBC battery manufactured using the method described in any one of claims 1 to 9, characterized in that: The substrate includes a silicon wafer (3) having a front side facing the sun during normal operation and a back side opposite to the front side. The back side of the substrate is provided with a tunneling oxide layer (4), a first conductivity type impurity polysilicon region (9), a second conductivity type impurity polysilicon region (5), a gap region (8), a first dielectric layer (6), and a metal electrode (7). The first conductivity type impurity polysilicon region (9) and the second conductivity type impurity polysilicon region (5) have opposite electrical properties. The metal electrode (7) forms an ohmic contact with either the first conductivity type impurity polysilicon region (9) or the second conductivity type impurity polysilicon region (5). The front side of the substrate (3) is provided with a front surface field (2) and a second dielectric layer (1) from the inside to the outside. The doping concentration of the dopant source layer after high-temperature diffusion in the front surface field (2) is 1×10 16 ~1×10 21 cm -3 The diffusion depth is 0.005μm~3μm; the doping concentration of the second conductivity type impurity polycrystalline silicon region (5) is 1×10 19 ~1×10 22 cm -3 The doping concentration of the region where the metal electrode (7) contacts the first conductivity type impurity polycrystalline silicon region (9) or the second conductivity type impurity polycrystalline silicon region (5) is 5 × 10⁻⁶. 18 ~1×10 21 cm -3 The doping concentration of the gap region (8) is 1×10⁻⁶. 15 ~1×10 20 cm -3 .

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