Back contact cell against hot spot effect and method for manufacturing the same

Abstract

The application discloses a back contact cell with anti-hot spot effect and a preparation method thereof, and belongs to the field of solar cells. The back contact cell comprises a silicon substrate, and a plurality of first regions and a plurality of second regions with opposite polarities are alternately arranged on the back surface of the silicon substrate. A fourth region is arranged on the side edge of the first region close to the second region. The fourth region comprises a gradually light-doped area in composite contact with the first doped layer. The gradually light-doped area is provided with a heavy-doped area in composite contact with the second passivation layer away from the back surface of the silicon substrate. The application has the beneficial effect that the leakage channel formed on the fourth region is adjusted to be the heavy-doped area and the gradually light-doped area by using a laser beam and improving the process, so that the leakage capacity of a single leakage channel is significantly enhanced, thereby reducing the number of required leakage channels, reducing the carrier recombination of a single leakage channel in normal operation, and achieving the goals of high anti-hot spot and high photoelectric conversion efficiency.

Description

Technical Field

[0001] This invention relates to the field of solar cells, and more specifically, to a back-contact solar cell resistant to hot spot effects and its preparation method. Background Technology

[0002] Hot spot effect refers to the phenomenon where, when some cells in a solar cell module are shaded, the inability to output current leads to a voltage increase, resulting in localized hot spots on those cells. Back-contact solar cells, due to the absence of electrodes on their front side, minimize optical losses and increase short-circuit current density, thus exhibiting high photoelectric conversion efficiency. However, existing back-contact solar cells face a technical challenge: how to effectively prevent hot spot effect while improving photoelectric conversion efficiency. To prevent hot spot effect, existing back-contact solar cells typically employ the Zener breakdown principle, overlapping portions of the first and second doped layers to form leakage channels and release heat. However, this method requires a large number of leakage channels to achieve effective hot spot prevention, and a large number of leakage channels can lead to increased carrier recombination during normal operation, reducing photoelectric conversion efficiency.

[0003] Furthermore, the TBC battery fabrication process requires a high concentration of doped layers. Excessive doping concentration leads to severe Auger recombination, reducing minority carrier lifetime and consequently affecting battery efficiency. The concentration threshold also limits the leakage capability of individual leakage channels, resulting in weak leakage capability in reverse bias. To achieve the required leakage capability, a large number of leakage channels are needed. However, the doping concentration threshold limits the barrier height of the PN junction of the leakage channels. In forward bias, carriers can easily recombine across the barrier of the leakage channel, further reducing cell efficiency; the more channels, the greater the efficiency loss. For example, the invention patent CN117976743A discloses a solar cell, battery module, and photovoltaic system. The solar cell includes a silicon wafer, a first doped layer, and a second doped layer. The second doped layer forms a leakage recombination contact structure with the first doped layer at a predetermined location, which can reduce the risk of hot spots while ensuring that the conversion efficiency of the solar cell does not suffer excessive loss. However, even with effective control of hot spots, a 0.3% efficiency loss is still a relatively large value for solar cells. Therefore, how to achieve efficient hot spot prevention in back-contact solar cells while avoiding efficiency loss caused by excessive leakage channels has become an urgent technical problem to be solved.

[0004] In view of this, the inventors conducted in-depth research to address this need, which led to the present invention. Summary of the Invention

[0005] To improve the hot spot effect in existing back-contact solar cells, and to address the problem of increased carrier recombination and reduced photoelectric conversion efficiency caused by improving the hot spot effect, this application provides a back-contact solar cell with anti-hot spot effect and its fabrication method, the technical solution of which is as follows:

[0006] A back-contact battery resistant to hot spot effect includes a silicon substrate. The back side of the silicon substrate has a plurality of first regions and a plurality of second regions, the first regions and second regions having opposite polarities and alternating along a first direction. A third region is provided at the connection point of each of the first and second regions. The first, second, and third regions all extend along a second direction, which intersects the first direction perpendicularly. The first region includes a first passivation layer and a first doped layer sequentially stacked on the back side of the silicon substrate. The second region includes a second passivation layer and a second doped layer sequentially stacked on the back side of the silicon substrate. A fourth region is provided on the side of the first region near the second region, and the fourth region is uniformly distributed along the second direction on the side of the first region. The fourth region includes a gradient lightly doped region in composite contact with the first doped layer, and a heavily doped region in composite contact with the second passivation layer is provided away from the back side of the silicon substrate from the gradient lightly doped region.

[0007] By configuring the fourth region as a heavily doped region in composite contact with the first doped region and a gradually lightly doped region in composite contact with the second doped region, wherein the heavily doped region and the second doped layer form a high-barrier vertical junction, and the gradually lightly doped region and the second doped layer form an auxiliary lateral junction, both exhibiting a strong Zener breakdown effect. Furthermore, the stacked design of the heavily doped region and the gradually lightly doped region creates a dual-channel conductivity capability of lateral light-doped conductivity and vertical heavy-doped conductivity, with the ratio of lateral light-doped conductivity to vertical heavy-doped conductivity ranging from 0.5:1 to 2:1.

[0008] Preferably, the doping element in the heavily doped region is boron, and the doping concentration is 1×10⁻⁶. 21 ~1×10 23 cm -3 The vertical doping depth is 10~20nm; the doping element in the gradient light doping region is boron, and the gradient doping concentration along the first doped layer from the outside to the inside is 1×10⁻⁶. 21 cm -3 Up to 1×10 17 cm -3 .

[0009] Preferably, the barrier height formed by the heavily doped region and the second doped layer is 0.1~0.5 eV higher than the barrier height formed by the gradually lightly doped region and the second doped layer.

[0010] By creating a barrier height difference of 0.1~0.5eV, it is difficult for charge carriers in a single leakage channel, which are in a forward bias state during normal operation, to cross the barrier. This further reduces charge carrier recombination within the single leakage channel during normal operation, thereby achieving efficient hot spot prevention and high photoelectric conversion efficiency. Moreover, when the barrier height of the vertical junction is higher than that of the horizontal junction, the probability of charge carrier recombination during normal operation is lower than that of the horizontal junction, while its reverse leakage capability is also higher. This further enhances the leakage capability of a single leakage channel while further reducing efficiency loss.

[0011] Preferably, the first passivation layer is a tunneling oxide layer with a thickness of 3-10 nm, and the first doped layer is a boron-doped polycrystalline silicon layer with a doping thickness of 150-350 nm and a doping concentration of 5 × 10⁻⁶ nm. 19 ~1×10 20 cm -3 The second passivation layer is a tunneling oxide layer with a thickness of 3-10 nm; the second doped layer is a phosphorus-doped polycrystalline silicon layer with a doping thickness of 150-300 nm and a doping concentration of 1×10⁻⁶. 20 ~1×10 22 cm -3 .

[0012] Preferably, the front side of the silicon substrate includes, from the inside out, a front passivation layer and a front antireflection layer; the back side of the silicon substrate includes, from the inside out, a first region / second region, a back passivation layer, a back antireflection layer, and an electrode; the first region and the second region have opposite polarities and are arranged alternately along the first direction; a third region is provided at the connection between the first region and the second region; the first region, the second region, and the third region all extend along the second direction, which intersects the first direction perpendicularly; a fourth region is provided on the side of the first region near the second region, and the fourth region is uniformly distributed on the side of the first region along the second direction; the fourth region includes a gradient lightly doped region that is in composite contact with the first doped layer; the gradient lightly doped region is provided away from the back side of the silicon substrate and has a heavily doped region that is in composite contact with the second passivation layer; the electrode includes a first electrode and a second electrode; the first electrode penetrates the back antireflection layer and the back passivation layer to form an ohmic contact with the first doped layer; the second electrode penetrates the back antireflection layer and the back passivation layer to form an ohmic contact with the second doped layer.

[0013] This application also provides a method for preparing the above-mentioned back contact battery, comprising the following steps:

[0014] Step 1: Select a silicon substrate and place it in a tank-type alkaline solution for polishing;

[0015] Step 2: Sequentially deposit the first passivation layer and the first doped layer on the entire back side of the silicon substrate;

[0016] Step 3: Deposit a BSG layer on the back side of the silicon substrate;

[0017] Step four: Use a laser beam to ablate the back side of the silicon substrate at intervals, and use an alkaline solution to etch the silicon substrate to form an unablated first region, a second region exposing the silicon substrate, and a third region exposing the silicon substrate, respectively.

[0018] Step 5: Use a laser beam to irradiate the side portion of the BSG layer near the second region in the first region to form the fourth region. After being irradiated by the laser beam, the boron element in the BSG layer diffuses longitudinally into the first doped layer to form a heavily doped region.

[0019] Step 6: Anneal the heavily doped region to redistribute boron elements within the first doped layer, forming a gradually lightly doped region.

[0020] Step 7: Sequentially deposit the second passivation layer, the second doped layer, and the PSG layer on the entire back side of the silicon substrate;

[0021] Step 8: Use a laser beam to ablate the PSG layers in the first and third regions on the back side of the silicon substrate, and use strong acid to etch the front and side surfaces of the silicon substrate to expose the silicon substrate on the front and side surfaces respectively.

[0022] Step 9: Clean the surfaces of the first and third regions with alkaline solution and strong acid respectively, and simultaneously texturize the front side of the silicon substrate and the third region to expose the silicon substrate in the third region, and clean the PSG in the second region.

[0023] Step 10: Deposit a front passivation layer and a back passivation layer on the front and back sides of the silicon substrate;

[0024] Step 11: Deposit antireflective layers on the front and back sides of the silicon substrate;

[0025] Step 12: Perform paste printing and metal sintering on the silicon substrate.

[0026] Preferably, in step three, the thickness of the BSG layer deposited on the back side of the silicon substrate is 50~100nm; in step seven, the thickness of the PSG layer deposited on the back side of the silicon substrate is 50~100nm.

[0027] Preferably, step four specifically includes: using the laser beam to ablate the BSG layers in the second and third regions, wherein the laser beam is a pulsed laser with a pulse width of 5-30 ps, ​​a wavelength of 355 nm or 532 nm, a spot size of 150-300 μm, and an energy density of 4 × 10⁻⁶.3 j / m 2 ~9×10 3 j / m 2 The overlap rate is 10-80%; after etching with NaOH, the surface of the first region still has a BSG layer of 10-40 nm, and the surface height of the first region is 1-5 μm higher than the surface height of the second region.

[0028] Preferably, step five specifically includes: irradiating the BSG layer in the fourth region with the laser beam, wherein the BSG layer serves as a boron source for longitudinal diffusion into the first doped layer; the laser beam is a pulsed laser with a pulse width of 5-30 ps, ​​a wavelength of 355 nm or 532 nm, a spot size of 150-300 μm, and an energy density of 3.55 × 10⁻⁶. 3 j / m 2 ~6.5×10 3 j / m 2 The overlap rate is 10-80%.

[0029] The BSG layer, acting as an isolation layer, blocks longitudinal conductivity, rendering the heavily doped region non-conductive. Therefore, by irradiating the BSG layer with a laser in step five, the remaining BSG isolation layer can be modified into an active layer, enabling the heavily doped region in the fourth region to conduct electricity. Simultaneously, the conductivity of a single leakage channel is significantly improved, while controlling the doping concentration to 1×10⁻⁶. 21 ~1×10 23 cm -3 Furthermore, doping depths of 10-20 nm are easily achievable in industrial-scale production, and the Zener breakdown effect of the heavily doped region is relatively good.

[0030] Preferably, step six specifically includes: annealing the heavily doped region to redistribute boron elements within the first doped layer, with an annealing temperature of 800~1000℃ and an annealing time of 30~90min.

[0031] The gradient effect of the lightly doped region can be achieved by annealing the vertically doped region. However, step seven, which involves the sequential deposition of the second passivation layer, the second doped layer, and the PSG layer, also requires deposition at a high temperature. Therefore, step six can be omitted. However, since the main purpose of step seven is to deposit other substances, and the process parameters are mainly focused on depositing other substances, the annealing effect is not as good as annealing alone, and the conductivity of the leakage channel is also not as good as annealing alone. However, the conductivity of the leakage channel is still significantly improved compared to the heavily doped state. From a cost perspective, it can be eliminated.

[0032] Preferably, step eight specifically includes: ablating the PSG layers in the first region and the third region using the laser beam, wherein the laser beam is a pulsed laser with a pulse width of 5-30 ps, ​​a wavelength of 355 nm or 532 nm, a spot size of 150-300 μm, and an energy density of 2 × 10⁻⁶. 3 j / m 2 ~4×10 3 j / m 2 The overlap rate is 10-50%; the strong acid is etched using HF and HNO3.

[0033] Preferably, in step nine, alkaline solution and strong acid are used to clean the second doped layer and the remaining BSG layer on the surface of the first region and the second doped layer in the third region, respectively, and simultaneously texturing is performed on the front side of the silicon substrate and the third region to expose the silicon substrate in the third region and clean the PSG in the second region; after texturing, the reflectivity of the textured surface on the front side of the silicon substrate is 5~10%, and the surface height of the second region is 1~3μm higher than the surface height of the third region.

[0034] Preferably, in step ten, an ALD process is used to deposit a front passivation layer and a back passivation layer with a thickness of 4-10 nm on the front and back sides of the silicon substrate, respectively; in step eleven, a PECVD process is used to deposit a front antireflection layer and a back antireflection layer with a thickness of 50-100 nm on the front and back sides of the silicon substrate, respectively.

[0035] The beneficial effects of adopting the technical solution of this invention are as follows:

[0036] (1) By using laser beams and process improvements, the leakage channels formed in the fourth region are adjusted to heavily doped regions and gradually lightly doped regions, which significantly enhances the leakage capacity of a single leakage channel. This reduces the number of leakage channels required and also reduces carrier recombination during normal operation of a single leakage channel, achieving the goals of efficient hot spot prevention and high photoelectric conversion efficiency.

[0037] (2) The barrier height formed by the heavily doped region and the second doped layer is 0.1~0.5eV higher than the barrier height formed by the gradually lightly doped region and the second doped layer. This makes it difficult for the carriers in the leakage channel, which are in a forward bias state during normal operation, to cross the barrier. This further reduces the recombination of carriers in the cell during normal operation, thereby achieving efficient hot spot prevention and high photoelectric conversion efficiency. Attached Figure Description

[0038] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0039] Figure 1 This is a schematic diagram of the side structure of the single-crystal silicon wafer in Example 2;

[0040] Figure 2 This is a schematic diagram of the back structure of the single-crystal silicon wafer in Example 2;

[0041] Figure 3 This is a process flow diagram of the back contact battery preparation method in Example 2.

[0042] Explanation of reference numerals in the attached figures: 1. Silicon substrate; 2. Front passivation layer; 3. Front antireflection layer; 4. First region; 41. First passivation layer; 42. First doped layer; 5. Second region; 51. Second passivation layer; 52. Second doped layer; 6. Third region; 7. Fourth region; 71. Heavily doped region; 72. Gradient lightly doped region; 8. Back passivation layer; 9. Back antireflection layer; 10. First electrode; 11. Second electrode. Detailed Implementation

[0043] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, not all of them. Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to represent selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0044] This embodiment utilizes a laser beam and process improvements to adjust the leakage channel formed in the fourth region into a heavily doped region and a gradually lightly doped region, significantly enhancing the leakage capability of a single leakage channel. This reduces the required number of leakage channels while also decreasing carrier recombination during normal operation of a single leakage channel, achieving the goals of efficient hot spot prevention and high photoelectric conversion efficiency. The specific implementation method is as follows:

[0045] A back-contact battery resistant to hot spot effect includes a silicon substrate. The back side of the silicon substrate has a plurality of first regions and a plurality of second regions, the first regions and second regions having opposite polarities and alternating along a first direction. A third region is provided at the connection point of each of the first and second regions. The first, second, and third regions all extend along a second direction, which intersects the first direction perpendicularly. The first region includes a first passivation layer and a first doped layer sequentially stacked on the back side of the silicon substrate. The second region includes a second passivation layer and a second doped layer sequentially stacked on the back side of the silicon substrate. A fourth region is provided on the side of the first region near the second region, and the fourth region is uniformly distributed along the second direction on the side of the first region. The fourth region includes a gradient lightly doped region in composite contact with the first doped layer, and a heavily doped region in composite contact with the second passivation layer is provided away from the back side of the silicon substrate from the gradient lightly doped region.

[0046] By configuring the fourth region as a heavily doped region in composite contact with the first doped region and a gradually lightly doped region in composite contact with the second doped region, wherein the heavily doped region and the second doped layer form a high-barrier vertical junction, and the gradually lightly doped region and the second doped layer form an auxiliary lateral junction, both exhibiting strong Zener breakdown effects. Furthermore, the stacked design of the heavily doped region and the gradually lightly doped region creates a dual-channel conductivity capability of lateral light-doped conductivity and vertical heavy-doped conductivity, with the ratio of lateral light-doped conductivity to vertical heavy-doped conductivity ranging from 0.5:1 to 2:1.

[0047] In a preferred embodiment, the doping element in the heavily doped region is boron, and the doping concentration is 1×10⁻⁶. 21 ~1×10 23 cm -3 The vertical doping depth is 10~20nm; the doping element in the gradient light doping region is boron, and the gradient doping concentration along the first doped layer from the outside to the inside is 1×10⁻⁶. 21 cm -3 Up to 1×10 17 cm -3 .

[0048] In a preferred embodiment, the barrier height formed by the heavily doped region and the second doped layer is 0.1~0.5 eV higher than the barrier height formed by the gradually lightly doped region and the second doped layer.

[0049] By creating a barrier height difference of 0.1~0.5eV, it is difficult for charge carriers in a single leakage channel, which are in a forward bias state during normal operation, to cross the barrier. This further reduces charge carrier recombination within the single leakage channel during normal operation, thereby achieving efficient hot spot prevention and high photoelectric conversion efficiency. Moreover, when the barrier height of the vertical junction is higher than that of the horizontal junction, the probability of charge carrier recombination during normal operation is lower than that of the horizontal junction, while its reverse leakage capability is also higher. This further enhances the leakage capability of a single leakage channel while further reducing efficiency loss.

[0050] In a preferred embodiment, the first passivation layer is a tunneling oxide layer with a thickness of 3-10 nm, and the first doped layer is a boron-doped polysilicon layer with a doping thickness of 150-350 nm and a doping concentration of 5 × 10⁻⁶ nm. 19 ~1×10 20 cm -3 The second passivation layer is a tunneling oxide layer with a thickness of 3-10 nm; the second doped layer is a phosphorus-doped polycrystalline silicon layer with a doping thickness of 150-300 nm and a doping concentration of 1×10⁻⁶. 20 ~1×10 22 cm -3 .

[0051] In a preferred embodiment, the front side of the silicon substrate includes, from the inside out, a front passivation layer and a front antireflection layer; the back side of the silicon substrate includes, from the inside out, a first region / second region, a back passivation layer, a back antireflection layer, and an electrode; the first region and the second region have opposite polarities and are arranged alternately along the first direction; a third region is provided at the connection between the first region and the second region; the first region, the second region, and the third region all extend along the second direction, which intersects the first direction perpendicularly; a fourth region is provided on the side of the first region near the second region, and the fourth region is uniformly distributed on the side of the first region along the second direction; the fourth region includes a gradient lightly doped region that is in composite contact with the first doped layer, and a heavily doped region that is in composite contact with the second passivation layer is provided away from the back side of the silicon substrate; the electrode includes a first electrode and a second electrode; the first electrode penetrates the back antireflection layer and the back passivation layer to form an ohmic contact with the first doped layer, and the second electrode penetrates the back antireflection layer and the back passivation layer to form an ohmic contact with the second doped layer.

[0052] This application also provides a method for preparing the above-mentioned back contact battery, comprising the following steps:

[0053] Step 1: Select a silicon substrate and place it in a tank-type alkaline solution for polishing;

[0054] Step 2: Sequentially deposit the first passivation layer and the first doped layer on the entire back side of the silicon substrate;

[0055] Step 3: Deposit a BSG layer on the back side of the silicon substrate;

[0056] Step four: Use a laser beam to ablate the back side of the silicon substrate at intervals, and use an alkaline solution to etch the silicon substrate to form an unablated first region, a second region exposing the silicon substrate, and a third region exposing the silicon substrate, respectively.

[0057] Step 5: Use a laser beam to irradiate the side portion of the BSG layer near the second region in the first region to form the fourth region. After being irradiated by the laser beam, the boron element in the BSG layer diffuses longitudinally into the first doped layer to form a heavily doped region.

[0058] Step 6: Anneal the heavily doped region to redistribute boron elements within the first doped layer, forming a gradually lightly doped region.

[0059] Step 7: Sequentially deposit the second passivation layer, the second doped layer, and the PSG layer on the entire back side of the silicon substrate;

[0060] Step 8: Use a laser beam to ablate the PSG layers in the first and third regions on the back side of the silicon substrate, and use strong acid to etch the front and side surfaces of the silicon substrate to expose the silicon substrate on the front and side surfaces respectively.

[0061] Step 9: Clean the surfaces of the first and third regions with alkaline solution and strong acid respectively, and simultaneously texturize the front side of the silicon substrate and the third region to expose the silicon substrate in the third region, and clean the PSG in the second region.

[0062] Step 10: Deposit a front passivation layer and a back passivation layer on the front and back sides of the silicon substrate;

[0063] Step 11: Deposit antireflective layers on the front and back sides of the silicon substrate;

[0064] Step 12: Perform paste printing and metal sintering on the silicon substrate.

[0065] In a preferred embodiment, in step three, a BSG layer with a thickness of 50-100 nm is deposited on the back side of the silicon substrate; in step seven, a PSG layer with a thickness of 50-100 nm is deposited on the back side of the silicon substrate.

[0066] In a preferred embodiment, step four specifically includes: ablating the BSG layers of the second and third regions using the laser beam, wherein the laser beam is a pulsed laser with a pulse width of 5-30 ps, ​​a wavelength of 355 nm or 532 nm, a spot size of 150-300 μm, and an energy density of 4 × 10⁻⁶. 3 j / m 2 ~9×10 3 j / m 2 The overlap rate is 10-80%; after etching with NaOH, the surface of the first region still has a BSG layer of 10-40 nm, and the surface height of the first region is 1-5 μm higher than the surface height of the second region.

[0067] In a preferred embodiment, step five specifically includes: irradiating the BSG layer in the fourth region with a laser beam, wherein the BSG layer serves as a boron source for longitudinal diffusion into the first doped layer; the laser beam is a pulsed laser with a pulse width of 5-30 ps, ​​a wavelength of 355 nm or 532 nm, a spot size of 150-300 μm, and an energy density of 3.55 × 10⁻⁶. 3 j / m 2 ~6.5×10 3 j / m 2 The overlap rate is 10-80%.

[0068] The BSG layer, acting as an isolation layer, blocks longitudinal conductivity, rendering the heavily doped region non-conductive. Therefore, by irradiating the BSG layer with a laser in step five, the remaining BSG isolation layer can be modified into an active layer, enabling the heavily doped region in the fourth region to conduct electricity. Simultaneously, the conductivity of a single leakage channel is significantly improved, while controlling the doping concentration to 1×10⁻⁶. 21 ~1×10 23 cm -3 Furthermore, doping depths of 10-20 nm are easily achievable in industrial-scale production, and the Zener breakdown effect of the heavily doped region is relatively good.

[0069] As a preferred embodiment, step six specifically includes: annealing the heavily doped region to redistribute boron elements within the first doped layer, with an annealing temperature of 800~1000℃ and an annealing time of 30~90min.

[0070] The gradient effect of the lightly doped region can be achieved by annealing the vertically doped region. However, step seven, which involves the sequential deposition of the second passivation layer, the second doped layer, and the PSG layer, also requires deposition at a high temperature. Therefore, step six can be omitted. However, since the main purpose of step seven is to deposit other substances, and the process parameters are mainly focused on depositing other substances, the annealing effect is not as good as annealing alone, and the conductivity of the leakage channel is also not as good as annealing alone. However, the conductivity of the leakage channel is still significantly improved compared to the heavily doped state. From a cost perspective, it can be eliminated.

[0071] In a preferred embodiment, step eight specifically includes: ablating the PSG layers in the first region and the third region using the laser beam, wherein the laser beam is a pulsed laser with a pulse width of 5-30 ps, ​​a wavelength of 355 nm or 532 nm, a spot size of 150-300 μm, and an energy density of 2 × 10⁻⁶. 3 j / m 2 ~4×10 3 j / m 2 The overlap rate is 10-50%; the strong acid is etched using HF and HNO3.

[0072] In a preferred embodiment, in step nine, alkaline solution and strong acid are used to clean the second doped layer and the remaining BSG layer on the surface of the first region and the second doped layer in the third region, respectively. Simultaneously, texturing is performed on the front side of the silicon substrate and the third region to expose the silicon substrate in the third region and clean the PSG in the second region. After texturing, the reflectivity of the textured surface on the front side of the silicon substrate is 5~10%, and the surface height of the second region is 1~3μm higher than the surface height of the third region.

[0073] In a preferred embodiment, step ten uses ALD process to deposit a front passivation layer and a back passivation layer with a thickness of 4~10nm on the front and back sides of the silicon substrate, respectively; step eleven uses PECVD process to deposit a front antireflection layer and a back antireflection layer with a thickness of 50~100nm on the front and back sides of the silicon substrate, respectively.

[0074] The following examples further illustrate the beneficial effects of the hot spot-resistant back contact battery and its preparation method according to the present invention.

[0075] Example 1:

[0076] This embodiment 1 provides a back contact battery resistant to hot spot effect, the preparation method of which includes the following steps:

[0077] Step 1: Select a single-crystal silicon wafer with a resistivity of 30 Ω·cm and polish it in a tank alkaline solution.

[0078] Step two: Sequentially deposit a 3nm first passivation layer and a 150nm first doped layer on the entire back side of the single-crystal silicon wafer, with a doping concentration of 5E19cm⁻¹. -3 ;

[0079] Step 3: Deposit another 50nm thick BSG layer on the back of the single-crystal silicon wafer;

[0080] Step four involves ablating the BSG layers in the second and third regions on the back side of the single-crystal silicon wafer using a laser beam. The laser beam is a pulsed laser with a pulse width of 5 ps, a wavelength of 355 nm, a spot size of 150 μm, and an energy density of 4 × 10⁻⁶. 3 j / m 2 The overlap rate is 10%; NaOH is used to etch the single crystal silicon wafer, and a 10nm BSG layer exists on the surface of the first region, and the surface height of the first region is 1μm higher than the surface height of the second region;

[0081] Step 5: Irradiate the BSG layer in the fourth region on the back side of the single-crystal silicon wafer with a laser beam. After irradiation, the boron element in the BSG layer diffuses longitudinally into the first doped layer, forming a heavily doped region. The laser beam is a pulsed laser with a pulse width of 5 ps, a wavelength of 355 nm, a spot size of 150 μm, and an energy density of 3.55 × 10⁻⁶. 3 j / m 2 The overlap rate is 10%;

[0082] Step 6: Anneal the heavily doped region to redistribute boron elements within the first doped layer. The annealing temperature is 800℃ and the annealing time is 30 minutes to form a gradually lightly doped region.

[0083] Step 7: Sequentially deposit a 3nm second passivation layer and a 150nm second doped layer on the entire back side of the single-crystal silicon wafer, with a doping concentration of 1E20cm⁻¹. -3 And a PSG layer with a thickness of 50nm;

[0084] Step 8: A laser beam is used to ablate the PSG layers in the first and third regions on the back side of the single-crystal silicon wafer. The laser beam is a pulsed laser with a pulse width of 5 ps, a wavelength of 355 nm, a spot size of 150 μm, and an energy density of 2 × 10⁻⁶. 3 j / m 2 The overlap rate is 10%; and HF and HNO3 are used to etch the front and side surfaces of the monocrystalline silicon wafer to expose the front and side surfaces of the monocrystalline silicon wafer respectively.

[0085] Step 9: The second doped layer and the remaining BSG layer on the surface of the first region and the second doped layer in the third region are cleaned with alkaline solution and strong acid, respectively. At the same time, the front side of the silicon substrate and the third region are texturized to expose the silicon substrate in the third region. The PSG in the second region is cleaned. After texturization, the surface reflectivity of the textured surface of the silicon substrate is 5%, and the surface height of the second region is 1 μm higher than that of the third region.

[0086] Step 10: ALD process is used to deposit a 4nm thick passivation layer on the front and back sides of the single-crystal silicon wafer, respectively.

[0087] Step 11: Deposit antireflection layers with a thickness of 50nm on the front and back sides of the single-crystal silicon wafer using PECVD process.

[0088] Step 12: Perform paste printing and metal sintering on the monocrystalline silicon wafer.

[0089] Example 2:

[0090] This embodiment 2 provides a back contact battery resistant to hot spot effect, the preparation method of which includes the following steps:

[0091] Step 1: Select a single-crystal silicon wafer with a resistivity of 30 Ω·cm and polish it in a tank alkaline solution.

[0092] Step two: Sequentially deposit a 5nm first passivation layer and a 200nm first doped layer on the entire back side of the single-crystal silicon wafer, with a doping concentration of 7E19cm⁻¹. -3 ;

[0093] Step 3: Deposit another 80nm thick BSG layer on the back of the single-crystal silicon wafer;

[0094] Step four involves ablating the BSG layers in the second and third regions on the back side of the single-crystal silicon wafer using a laser beam. The laser beam is a pulsed laser with a pulse width of 10 ps, ​​a wavelength of 532 nm, a spot size of 200 μm, and an energy density of 6 × 10⁻⁶. 3 j / m 2 The overlap rate is 30%; NaOH is used to etch the single crystal silicon wafer, and a 30nm BSG layer exists on the surface of the first region, and the surface height of the first region is 2μm higher than the surface height of the second region;

[0095] Step 5: Irradiate the BSG layer in the fourth region on the back side of the single-crystal silicon wafer with a laser beam. After irradiation, the boron element in the BSG layer diffuses longitudinally into the first doped layer, forming a heavily doped region. The laser beam is a pulsed laser with a pulse width of 10 ps, ​​a wavelength of 532 nm, a spot size of 200 μm, and an energy density of 4.5 × 10⁻⁶.3 j / m 2 The overlap rate is 30%;

[0096] Step 6: Anneal the heavily doped region to redistribute boron elements within the first doped layer. The annealing temperature is 900℃ and the annealing time is 60 min to form a gradually lightly doped region.

[0097] Step 7: Sequentially deposit a 5nm second passivation layer and a 200nm second doped layer on the entire back side of the single-crystal silicon wafer, with a doping concentration of 1E21cm⁻¹. -3 And a PSG layer with a thickness of 80nm;

[0098] Step 8: A laser beam is used to ablate the PSG layers in the first and third regions on the back side of the single-crystal silicon wafer. The laser beam is a pulsed laser with a pulse width of 10 ps, ​​a wavelength of 532 nm, a spot size of 200 μm, and an energy density of 3 × 10⁻⁶. 3 j / m 2 The overlap rate is 30%; and HF and HNO3 are used to etch the front and side surfaces of the monocrystalline silicon wafer to expose the front and side surfaces of the monocrystalline silicon wafer respectively.

[0099] Step 9: The second doped layer and the remaining BSG layer on the surface of the first region and the second doped layer in the third region are cleaned with alkaline solution and strong acid, respectively. At the same time, the front side of the silicon substrate and the third region are texturized to expose the silicon substrate in the third region. The PSG in the second region is cleaned. After texturization, the surface reflectivity of the textured surface of the silicon substrate is 8%, and the surface height of the second region is 2 μm higher than that of the third region.

[0100] Step 10: ALD process is used to deposit a passivation layer with a thickness of 5nm on the front and back sides of the single crystal silicon wafer, respectively.

[0101] Step 11: Deposit antireflection layers with a thickness of 70nm on the front and back sides of the single-crystal silicon wafer using PECVD process.

[0102] Step 12: Perform paste printing and metal sintering on the monocrystalline silicon wafer.

[0103] Example 3:

[0104] This embodiment 3 provides a back contact battery resistant to hot spot effect, the preparation method of which includes the following steps:

[0105] Step 1: Select a single-crystal silicon wafer with a resistivity of 30 Ω·cm and polish it in a tank alkaline solution.

[0106] Step two: Sequentially deposit an 8nm first passivation layer and a 250nm first doped layer on the entire back side of the single-crystal silicon wafer, with a doping concentration of 9E19cm⁻¹. -3 ;

[0107] Step 3: Deposit another 90nm thick BSG layer on the back of the single-crystal silicon wafer;

[0108] Step four involves ablating the BSG layers in the second and third regions on the back side of the single-crystal silicon wafer using a laser beam. The laser beam is a pulsed laser with a pulse width of 20 ps, ​​a wavelength of 532 nm, a spot size of 250 μm, and an energy density of 8 × 10⁻⁶. 3 j / m 2 The overlap rate is 50%; NaOH is used to etch the single crystal silicon wafer, and a 40nm BSG layer exists on the surface of the first region, and the surface height of the first region is 4μm higher than the surface height of the second region;

[0109] Step 5: Irradiate the BSG layer in the fourth region on the back side of the single-crystal silicon wafer with a laser beam. After irradiation, the boron element in the BSG layer diffuses longitudinally into the first doped layer, forming a heavily doped region. The laser beam is a pulsed laser with a pulse width of 20 ps, ​​a wavelength of 532 nm, a spot size of 250 μm, and an energy density of 5.5 × 10⁻⁶. 3 j / m 2 The overlap rate is 60%;

[0110] Step 6: Anneal the heavily doped region to redistribute boron elements within the first doped layer. The annealing temperature is 900℃ and the annealing time is 80 min to form a gradually lightly doped region.

[0111] Step 7: Sequentially deposit an 8nm second passivation layer and a 250nm second doped layer on the entire back side of the single-crystal silicon wafer, with a doping concentration of 1E21cm⁻¹. -3 And a PSG layer with a thickness of 90nm;

[0112] Step 8: A laser beam is used to ablate the PSG layers in the first and third regions on the back side of the single-crystal silicon wafer. The laser beam is a pulsed laser with a pulse width of 20 ps, ​​a wavelength of 532 nm, a spot size of 250 μm, and an energy density of 3 × 10⁻⁶. 3 j / m 2 The overlap rate is 40%; and HF and HNO3 are used to etch the front and side surfaces of the monocrystalline silicon wafer to expose the front and side surfaces of the monocrystalline silicon wafer respectively.

[0113] Step 9: The second doped layer and the remaining BSG layer on the surface of the first region and the second doped layer in the third region are cleaned with alkaline solution and strong acid, respectively. At the same time, the front side of the silicon substrate and the third region are texturized to expose the silicon substrate in the third region. The PSG in the second region is cleaned. After texturization, the surface reflectivity of the textured surface of the silicon substrate is 9%, and the surface height of the second region is 2 μm higher than that of the third region.

[0114] Step 10: ALD process is used to deposit a passivation layer with a thickness of 8nm on the front and back sides of the single crystal silicon wafer, respectively.

[0115] Step 11: Deposit antireflection layers with a thickness of 80nm on the front and back sides of the single-crystal silicon wafer using PECVD process.

[0116] Step 12: Perform paste printing and metal sintering on the monocrystalline silicon wafer.

[0117] Example 4:

[0118] This embodiment 4 provides a back contact battery resistant to hot spot effect, the preparation method of which includes the following steps:

[0119] Step 1: Select a single-crystal silicon wafer with a resistivity of 30 Ω·cm and polish it in a tank alkaline solution.

[0120] Step two: Sequentially deposit a 10nm first passivation layer and a 350nm first doped layer on the entire back side of the single-crystal silicon wafer, with a doping concentration of 1E20cm⁻¹. -3 ;

[0121] Step 3: Deposit another 100nm thick BSG layer on the back of the single-crystal silicon wafer;

[0122] Step four involves ablating the BSG layers in the second and third regions on the back of the single-crystal silicon wafer using a laser beam. The laser beam is a pulsed laser with a pulse width of 30 ps, ​​a wavelength of 532 nm, a spot size of 300 μm, and an energy density of 9 × 10⁻⁶. 3 j / m 2 The overlap rate is 80%; NaOH is used to etch the single crystal silicon wafer, and a 40nm BSG layer exists on the surface of the first region, and the surface height of the first region is 5μm higher than the surface height of the second region;

[0123] Step 5: Irradiate the BSG layer in the fourth region on the back side of the single-crystal silicon wafer with a laser beam. After irradiation, the boron element in the BSG layer diffuses longitudinally into the first doped layer, forming a heavily doped region. The laser beam is a pulsed laser with a pulse width of 30 ps, ​​a wavelength of 532 nm, a spot size of 300 μm, and an energy density of 6.5 × 10⁻⁶.3 j / m 2 The overlap rate is 80%;

[0124] Step 6: Anneal the heavily doped region to redistribute boron elements within the first doped layer. The annealing temperature is 1000℃ and the annealing time is 90 min to form a gradually lightly doped region.

[0125] Step 7: Sequentially deposit a 10nm second passivation layer and a 300nm second doped layer on the entire back side of the single-crystal silicon wafer, with a doping concentration of 1E22cm⁻¹. -3 And a PSG layer with a thickness of 100nm;

[0126] Step 8: A laser beam is used to ablate the PSG layers in the first and third regions on the back side of the single-crystal silicon wafer. The laser beam is a pulsed laser with a pulse width of 30 ps, ​​a wavelength of 532 nm, a spot size of 300 μm, and an energy density of 4 × 10⁻⁶. 3 j / m 2 The overlap rate is 50%; and HF and HNO3 are used to etch the front and side surfaces of the monocrystalline silicon wafer to expose the front and side surfaces of the monocrystalline silicon wafer respectively.

[0127] Step 9: The second doped layer and the remaining BSG layer on the surface of the first region and the second doped layer in the third region are cleaned with alkaline solution and strong acid, respectively. At the same time, the front side of the silicon substrate and the third region are texturized to expose the silicon substrate in the third region. The PSG in the second region is cleaned. After texturization, the surface reflectivity of the textured surface of the silicon substrate is 10%, and the surface height of the second region is 3 μm higher than that of the third region.

[0128] Step 10: ALD process is used to deposit a 10nm thick passivation layer on the front and back sides of the single-crystal silicon wafer, respectively.

[0129] Step 11: Deposit antireflection layers with a thickness of 100nm on the front and back sides of the single-crystal silicon wafer using PECVD process.

[0130] Step 12: Perform paste printing and metal sintering on the monocrystalline silicon wafer.

[0131] Comparative Example 1:

[0132] Comparative Example 1 provides a back-contact battery with resistance to hot spot effects, comprising a silicon substrate. The front side of the silicon substrate, from the inside out, includes a front passivation layer and a front anti-reflection layer. The back side of the silicon substrate, from the inside out, includes a first region / second region, a back passivation layer, a back anti-reflection layer, and an electrode. The first and second regions have opposite polarities and are alternately arranged along a first direction. A third region is provided at the connection between the first and second regions. The first, second, and third regions all extend along a second direction, which intersects the first direction perpendicularly. The electrode includes a first electrode and a second electrode. The first electrode penetrates the back anti-reflection layer to form an ohmic contact with the second doped layer, and the second electrode penetrates the back anti-reflection layer to form an ohmic contact with the first doped layer. The fabrication method includes the following steps:

[0133] Step 1: Select a single-crystal silicon wafer with a resistivity of 30 Ω·cm and polish it in a tank alkaline solution.

[0134] Step two: Sequentially deposit a 5nm first passivation layer and a 200nm first doped layer on the entire back side of the single-crystal silicon wafer, with a doping concentration of 7E19cm⁻¹. -3 ;

[0135] Step 3: Deposit another 80nm thick BSG layer on the back of the single-crystal silicon wafer;

[0136] Step four involves ablating the BSG layers in the second and third regions on the back side of the single-crystal silicon wafer using a laser beam. The laser beam is a pulsed laser with a pulse width of 10 ps, ​​a wavelength of 532 nm, a spot size of 200 μm, and an energy density of 6 × 10⁻⁶. 3 j / m 2 The overlap rate is 30%; NaOH is used to etch the single crystal silicon wafer. A 30nm BSG layer exists on the surface of the first region. The second and third regions expose the single crystal silicon wafer, and the surface height of the first region is 2μm higher than that of the second region.

[0137] Step 5: Sequentially deposit a 5nm second passivation layer and a 200nm second doped layer on the entire back side of the single-crystal silicon wafer, with a doping concentration of 1E21cm⁻¹. -3 And a PSG layer with a thickness of 80nm;

[0138] Step six: A laser beam is used to ablate the PSG layers in the first and third regions on the back side of the single-crystal silicon wafer. The laser beam is a pulsed laser with a pulse width of 10 ps, ​​a wavelength of 532 nm, a spot size of 200 μm, and an energy density of 3 × 10⁻⁶. 3 j / m 2The overlap rate is 30%; and HF and HNO3 are used to etch the front and side surfaces of the monocrystalline silicon wafer to expose the front and side surfaces of the monocrystalline silicon wafer respectively.

[0139] Step 7: Use alkaline solution and strong acid to clean the second doped layer and the remaining BSG layer on the surface of the first region and the second doped layer in the third region, respectively. Simultaneously, texturing is performed on the front side of the single crystal silicon wafer and the third region to expose the silicon substrate in the third region. The PSG in the second region is cleaned. After texturing, the surface reflectivity of the textured surface on the front side of the single crystal silicon wafer is 8%, and the surface height of the second region is 2μm higher than the surface height of the third region.

[0140] Step 8: Deposit a passivation layer with a thickness of 5nm on the front and back sides of the single-crystal silicon wafer using the ALD process.

[0141] Step 9: Deposit antireflection layers with a thickness of 70nm on the front and back sides of the single-crystal silicon wafer using PECVD process.

[0142] Step 10: Perform paste printing and metal sintering on the monocrystalline silicon wafer.

[0143] Comparative Example 2:

[0144] Comparative Example 2 provides a back-contact solar cell resistant to hot spot effects, comprising a silicon substrate. The front side of the silicon substrate, from the inside out, includes a front passivation layer and a front anti-reflection layer. The back side of the silicon substrate, from the inside out, includes a first region / second region, a back passivation layer, a back anti-reflection layer, and an electrode. The first and second regions have opposite polarities and are alternately arranged along a first direction. A third region is provided at the connection between the first and second regions. The first, second, and third regions all extend along a second direction, which intersects the first direction perpendicularly. A fourth region is provided on the side of the first region near the second region, and the fourth regions are uniformly distributed along the second direction on the side of the first region. The fourth region includes a stacked first doped region and a second doped region. The electrode includes a first electrode and a second electrode. The first electrode penetrates the back anti-reflection layer to form an ohmic contact with the second doped layer, and the second electrode penetrates the back anti-reflection layer to form an ohmic contact with the first doped layer. The fabrication method includes the following steps:

[0145] Step 1: Select a single-crystal silicon wafer with a resistivity of 30 Ω·cm and polish it in a tank alkaline solution.

[0146] Step two: Sequentially deposit a 5nm first passivation layer and a 200nm first doped layer on the entire back side of the single-crystal silicon wafer, with a doping concentration of 7E19cm⁻¹. -3 ;

[0147] Step 3: Deposit another 80nm thick BSG layer on the back of the single-crystal silicon wafer;

[0148] Step four involves ablating the BSG layers in the second and third regions on the back side of the single-crystal silicon wafer using a laser beam. The laser beam is a pulsed laser with a pulse width of 10 ps, ​​a wavelength of 532 nm, a spot size of 200 μm, and an energy density of 6 × 10⁻⁶. 3 j / m 2 The overlap rate is 30%; NaOH is used to etch the single crystal silicon wafer. A 30nm BSG layer exists on the surface of the first region. The second and third regions expose the single crystal silicon wafer, and the surface height of the first region is 2μm higher than that of the second region.

[0149] Step 5: Sequentially deposit a 5nm second passivation layer and a 200nm second doped layer on the entire back side of the single-crystal silicon wafer, with a doping concentration of 1E21cm⁻¹. -3 And a PSG layer with a thickness of 80nm;

[0150] Step six: A laser beam is used to ablate the PSG layers in the first and third regions on the back side of the single-crystal silicon wafer. The laser beam is a pulsed laser with a pulse width of 10 ps, ​​a wavelength of 532 nm, a spot size of 200 μm, and an energy density of 3 × 10⁻⁶. 3 j / m 2 The overlap rate is 30%; and HF and HNO3 are used to etch the front and side surfaces of the monocrystalline silicon wafer to expose the front and side surfaces of the monocrystalline silicon wafer respectively.

[0151] Step 7: The second doped layer and the remaining BSG layer on the surface of the first region and the second doped layer in the third region are cleaned with alkaline solution and strong acid, respectively. At the same time, the front side of the silicon substrate and the third region are texturized to expose the silicon substrate in the third region. The PSG in the second region is cleaned. After texturization, the surface reflectivity of the textured surface of the silicon substrate is 8%, and the surface height of the second region is 2 μm higher than that of the third region.

[0152] Step 8: Deposit a passivation layer with a thickness of 5nm on the front and back sides of the single-crystal silicon wafer using the ALD process.

[0153] Step 9: Deposit antireflection layers with a thickness of 70nm on the front and back sides of the single-crystal silicon wafer using PECVD process.

[0154] Step 10: Perform paste printing and metal sintering on the monocrystalline silicon wafer.

[0155] The performance of the solar cells obtained in the above embodiments and comparative examples is tested below, and the results are as follows:

[0156] Table 1. Electrical performance test results of the solar cells prepared in the examples and comparative examples.

[0157] Example EFF (%) Isc(A) Voc(mV) FF(%) Rs(mohm) Rsh(ohm) URev2 = -7V: IRev2(A) Example 1 26.58 16.049 745.3 85.25 2.1 1208 26.5 Example 2 26.63 16.059 745.8 85.29 2.1 1352 28.4 Example 3 26.61 16.052 746.1 85.25 2.1 1314 27.9 Example 4 26.60 16.048 745.6 85.27 2.1 1197 26.9 Comparative Example 1 26.67 16.065 746.5 85.32 2.1 1513 0.1 Comparative Example 2 26.44 16.045 743.5 85.02 2.1 1405 19.1

[0158] Table 2. Hot spot temperature test results of solar cells prepared in the examples and comparative examples.

[0159] Example Under the condition of completely blocking 1 piece Example 1 113℃ Example 2 102℃ Example 3 105℃ Example 4 111℃ Comparative Example 1 158℃ Comparative Example 2 115℃

[0160] Examples 1-4 are back-contact batteries in this application where the leakage channel formed in the fourth region is adjusted to a heavily doped region and a gradually lightly doped region by utilizing a laser beam and process improvements. Comparative Example 1 is a back-contact battery without a leakage channel, and Comparative Example 2 is a back-contact battery with only a leakage channel but without utilizing a laser beam and process improvements. As shown in Tables 1-2, the battery electrical performance data obtained by the embodiments of this application are significantly better than those of Comparative Example 2, thus significantly enhancing the leakage capability. This reduces the number of required leakage channels while also reducing carrier recombination during normal operation of a single leakage channel, achieving the goal of high photoelectric conversion efficiency. Since Comparative Example 1 does not have leakage current, IRev2 is very small, but the hot spot temperature is significantly higher than that of the embodiments of this application. In addition, the hot spot effect temperature of the embodiments of this application is also lower than that of Comparative Examples 1-2, achieving the goal of highly efficient hot spot effect prevention.

[0161] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the invention by those skilled in the art. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the invention should be included within the scope of protection of the invention.

Claims

1. A back contact battery resistant to hot spot effect, characterized in that, The device includes a silicon substrate, on the back side of which are provided a plurality of first regions and a plurality of second regions, the first regions and the second regions having opposite polarities and being arranged alternately along a first direction, a third region being provided at the connection between the first regions and the second regions, the first regions, the second regions and the third regions all extending along a second direction, the second direction being perpendicular to the first direction; The first region includes a first passivation layer and a first doped layer sequentially stacked on the back side of the silicon substrate. The second region includes a second passivation layer and a second doped layer sequentially stacked on the back side of the silicon substrate. A fourth region is disposed on the side of the first region near the second region, and the fourth region is uniformly distributed on the side of the first region along the second direction. The fourth region includes a gradient lightly doped region that is in composite contact with the first doped layer. A heavily doped region that is in composite contact with the second passivation layer is disposed away from the back side of the silicon substrate. The doping concentration of the heavily doped region is 1×10⁻⁶. 21 ~1×10 23 cm -3 The doping concentration of the gradient lightly doped region is 1 × 10⁻⁶ from the outside to the inside of the heavily doped region. 21 cm -3 Up to 1×10 17 cm -3 .

2. The back contact battery with anti-hot spot effect according to claim 1, characterized in that, The heavily doped region is doped with boron, and the doping depth is 10~20nm; the lightly doped region is also doped with boron.

3. The back contact battery with anti-hot spot effect according to claim 2, characterized in that, The barrier height formed by the heavily doped region and the second doped layer is 0.1~0.5eV higher than the barrier height formed by the gradually lightly doped region and the second doped layer.

4. The back contact battery with anti-hot spot effect according to claim 1, characterized in that, The first passivation layer is a tunneling oxide layer with a thickness of 3-10 nm, and the first doped layer is a boron-doped polysilicon layer with a doping thickness of 150-350 nm and a doping concentration of 5 × 10⁻⁶. 19 ~1×10 20 cm -3 The second passivation layer is a tunneling oxide layer with a thickness of 3-10 nm; the second doped layer is a phosphorus-doped polycrystalline silicon layer with a doping thickness of 150-300 nm and a doping concentration of 1×10⁻⁶. 20 ~1×10 22 cm -3 .

5. The back contact battery with anti-hot spot effect according to claim 1, characterized in that, The front side of the silicon substrate, from the inside out, includes a front passivation layer and a front antireflection layer. The back side of the silicon substrate, from the inside out, includes a first region / second region, a back passivation layer, a back antireflection layer, and an electrode. The first region and the second region have opposite polarities and are arranged alternately along the first direction. A third region is provided at the connection between the first region and the second region. The first region, the second region, and the third region all extend along the second direction, which intersects the first direction perpendicularly. A fourth region is provided on the side of the first region near the second region, and the fourth region is evenly distributed on the side of the first region along the second direction. The fourth region includes a gradient lightly doped region that is in composite contact with the first doped layer. A heavily doped region that is in composite contact with the second passivation layer is provided away from the back side of the silicon substrate. The electrode includes a first electrode and a second electrode. The first electrode penetrates the back antireflection layer and the back passivation layer to form an ohmic contact with the first doped layer. The second electrode penetrates the back antireflection layer and the back passivation layer to form an ohmic contact with the second doped layer.

6. A method for preparing a back contact battery according to any one of claims 1 to 5, characterized in that, Includes the following steps: Step 1: Select a silicon substrate and place it in a tank-type alkaline solution for polishing; Step 2: Sequentially deposit the first passivation layer and the first doped layer on the entire back side of the silicon substrate; Step 3: Deposit a BSG layer on the back side of the silicon substrate; Step four: Use a laser beam to ablate the back side of the silicon substrate at intervals, and use an alkaline solution to etch the silicon substrate to form an unablated first region, a second region exposing the silicon substrate, and a third region exposing the silicon substrate, respectively. Step 5: Use a laser beam to irradiate the side portion of the BSG layer near the second region in the first region to form the fourth region. After being irradiated by the laser beam, the boron element in the BSG layer diffuses longitudinally into the first doped layer to form a heavily doped region. Step 6: Anneal the heavily doped region to redistribute boron elements within the first doped layer, forming a gradually lightly doped region. Step 7: Sequentially deposit the second passivation layer, the second doped layer, and the PSG layer on the entire back side of the silicon substrate; Step 8: Use a laser beam to ablate the PSG layers in the first and third regions on the back side of the silicon substrate, and use strong acid to etch the front and side surfaces of the silicon substrate to expose the silicon substrate on the front and side surfaces respectively. Step 9: Clean the surfaces of the first and third regions with alkaline solution and strong acid respectively, and simultaneously texturize the front side of the silicon substrate and the third region to expose the silicon substrate in the third region, and clean the PSG in the second region. Step 10: Deposit a front passivation layer and a back passivation layer on the front and back sides of the silicon substrate; Step 11: Deposit antireflective layers on the front and back sides of the silicon substrate; Step 12: Perform paste printing and metal sintering on the silicon substrate.

7. The method for preparing a back contact battery according to claim 6, characterized in that, Step four specifically includes: using the laser beam to ablate the BSG layers in the second and third regions. The laser beam is a pulsed laser with a pulse width of 5-30 ps, ​​a wavelength of 355 nm or 532 nm, a spot size of 150-300 μm, and an energy density of 4 × 10⁻⁶. 3 j / m 2 ~9×10 3 j / m 2 The overlap rate is 10-80%; after the alkaline etching, there is a 10-40 nm BSG layer on the surface of the first region, and the surface height of the first region is 1-5 μm higher than the surface height of the second region.

8. The method for preparing a back contact battery according to claim 6, characterized in that, Step five specifically includes: irradiating the BSG layer in the fourth region with the laser beam, wherein the BSG layer serves as a boron source for longitudinal diffusion into the first doped layer; the laser beam is a pulsed laser with a pulse width of 5-30 ps, ​​a wavelength of 355 nm or 532 nm, a spot size of 150-300 μm, and an energy density of 3.55 × 10⁻⁶. 3 j / m 2 ~6.5×10 3 j / m 2 The overlap rate is 10-80%.

9. The method for preparing a back contact battery according to claim 6, characterized in that, Step six specifically includes: annealing the heavily doped region to redistribute boron elements within the first doped layer, with an annealing temperature of 800~1000℃ and an annealing time of 30~90min.

10. The method for preparing a back contact battery according to claim 6, characterized in that, Step eight specifically includes: using the laser beam to ablate the PSG layers in the first region and the third region. The laser beam is a pulsed laser with a pulse width of 5-30 ps, ​​a wavelength of 355 nm or 532 nm, a spot size of 150-300 μm, and an energy density of 2 × 10⁻⁶. 3 j / m 2 ~4×10 3 j / m 2 The overlap rate is 10-50%.

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