Display panel and display device

Abstract

This disclosure provides a display panel and a display device thereof. The display area includes a plurality of sub-pixels, at least one edge virtual sub-pixel in at least one row of sub-pixels, and at least one edge virtual sub-pixel in at least one column of sub-pixels. A pixel driving unit is configured to drive a first sub-pixel to display an image. A color filter substrate includes a black matrix layer and a color resist layer formed on the color filter substrate. The black matrix layer has a plurality of opening regions. The orthographic projections of the first color resist layer, the second color resist layer, and the third color resist layer on the color filter substrate overlap with the orthographic projections of the opening regions on the color filter substrate. The orthographic projections of the pixel driving unit corresponding to the edge virtual sub-pixel on the substrate substrate do not overlap with the orthographic projections of the first color resist layer, the second color resist layer, and the third color resist layer on the substrate substrate. The orthographic projections of the pixel driving unit corresponding to the edge virtual sub-pixel on the substrate substrate do not overlap with the orthographic projections of the opening regions on the substrate substrate.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to display panels and display devices thereof. Background Technology

[0002] In the field of display technology, pixel arrays in liquid crystal displays (LCDs) or organic light-emitting diode (OLED) displays typically include multiple rows of gate lines and multiple columns of interlaced data lines. Driving the gate lines can be achieved through bonded integrated driver circuits. In recent years, with the continuous improvement of amorphous silicon thin-film transistor (TFT) or oxide TFT fabrication processes, gate line driving circuits can also be directly integrated onto the TFT array substrate to form a gate-on-array (GOA) for driving the gate lines. For example, a GOA composed of multiple cascaded shift register units can be used to provide scan signals to multiple rows of gate lines in the pixel array, thereby controlling the sequential opening of multiple rows of gate lines, and simultaneously providing data signals from the data lines to the corresponding pixel units in the pixel array to form the grayscale voltages required for each grayscale level of the displayed image in each pixel unit, thus displaying a frame of image. Current display panels increasingly employ GOA technology to drive the gate lines. GOA technology helps achieve narrow bezel designs in display panels and can reduce the production cost of display panels. Summary of the Invention

[0003] The display panel provided in this embodiment includes:

[0004] The substrate includes the display area and the non-display area;

[0005] The display area includes a plurality of sub-pixels; the plurality of sub-pixels includes a first sub-pixel and an edge virtual sub-pixel; at least one row of the sub-pixels has at least one edge virtual sub-pixel, and at least one column of the sub-pixels has at least one edge virtual sub-pixel;

[0006] Multiple pixel driving units are configured to correspond one-to-one with the first sub-pixel and the edge virtual sub-pixel; wherein, the pixel driving unit is configured to drive the first sub-pixel to display the image;

[0007] A color filter substrate includes a black matrix layer and a color resist layer formed on the color filter substrate; the black matrix layer has a plurality of opening regions; the color resist layer includes a plurality of first color resist layers, a plurality of second color resist layers and a plurality of third color resist layers; the orthographic projections of the first color resist layers, the second color resist layers and the third color resist layers on the color filter substrate overlap with the orthographic projections of the opening regions on the color filter substrate.

[0008] The orthographic projection of the pixel driving unit corresponding to the edge virtual sub-pixel on the substrate does not overlap with the orthographic projections of the first color resist layer, the second color resist layer, and the third color resist layer on the substrate; the orthographic projection of the pixel driving unit corresponding to the edge virtual sub-pixel on the substrate does not overlap with the orthographic projection of the opening region on the substrate.

[0009] In some possible implementations, edge virtual sub-pixels in the same column of sub-pixels are closer to the corner edge of the display area in a first direction than the first sub-pixel; edge virtual sub-pixels in the same row of sub-pixels are closer to the corner edge of the display area in a second direction than the first sub-pixel.

[0010] In some possible implementations, the number of open areas per column and the number of open areas per row decrease along the direction close to the corner edge of the display area;

[0011] The color resist layer includes multiple color resist units, and each color resist unit includes: a first color resist layer, a second color resist layer and a third color resist layer; wherein the first color resist layer, the second color resist layer and the third color resist layer in each color resist unit have the same orthographic projection on the substrate.

[0012] The area of ​​each color resist unit gradually decreases along the direction close to the corner edge of the display area.

[0013] In some possible implementations, the pixel driving unit includes: a first sub-driving unit, and / or, a second sub-driving unit;

[0014] The first sub-driving unit includes a first driving transistor; the gate of the first driving transistor is coupled to a gate line, the first electrode of the first driving transistor is coupled to a data line, and the second electrode of the first driving transistor is coupled to a pixel electrode.

[0015] The second sub-driving unit includes a second driving transistor; the gate of the second driving transistor is coupled to the gate line, the first electrode of the second driving transistor is coupled to the data line, and the second electrode of the second driving transistor is coupled to the pixel electrode;

[0016] The pixel driving unit has the same shape as the orthographic projection of the substrate.

[0017] In some possible implementations, multiple sub-pixels near the corner edge of the display area are arranged in a stepped manner to form a multi-level pixel ladder, each level of the pixel ladder being composed of at least one sub-pixel; in some of the pixel ladders, at least one edge virtual sub-pixel is provided every other level of the pixel ladder.

[0018] In some possible implementations, the substrate further includes: a plurality of cascaded shift register units, a plurality of anti-static units, and at least one common electrode line; wherein each stage of the shift register unit corresponds to one row of the sub-pixels;

[0019] The anti-static unit and the cascaded shift register unit are located on different sides of the common electrode line in the projection of the substrate, respectively, in the projection of the anti-static unit on the substrate. The projection of the anti-static unit in the projection of the substrate is located between the projection of the common electrode line in the projection of the substrate and the projection of the sub-pixel in the projection of the substrate.

[0020] Each sub-pixel in each pixel ladder is electrically connected to at least one of the anti-static units; the anti-static unit is located at the end of the pixel ladder in a first direction, and the anti-static unit is located between at most two rows of sub-pixels in a second direction.

[0021] In some possible implementations, the antistatic unit corresponding to the nth pixel step is located at the end of the nth pixel step in the first direction, where n is an integer not less than 1 and i is an integer not less than 1.

[0022] In some possible implementations, the antistatic unit corresponding to the nth pixel step is located at the end of the (n+i)th pixel step in the first direction, where n is an integer not less than 1 and i is an integer not less than 1.

[0023] In some possible implementations, the anti-static unit corresponding to the nth pixel step includes a first anti-static unit located at the end of the nth pixel step in the first direction and a first anti-static unit located at the end of the (n+i)th pixel step in the first direction, wherein n is an integer not less than 1 and i is an integer not less than 1.

[0024] In some possible implementations, the substrate further includes: multiple data conduction signal lines; the sub-pixels in each pixel step are connected to the corresponding anti-static unit through the data conduction signal lines;

[0025] The data conduction signal lines are arranged in an S-shape, and / or a zigzag shape, and / or a lightning bolt shape.

[0026] In some possible implementations, the shift register unit includes: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, and a tenth transistor;

[0027] Wherein, the first transistor and the second transistor are disposed opposite to each other along the first direction; the third transistor and the fourth transistor are disposed opposite to each other along the first direction; the orthographic projections of the third transistor and the fourth transistor on the substrate are located between the orthographic projections of the first transistor and the fifth transistor on the substrate; the sixth transistor and the seventh transistor are disposed opposite to each other along the first direction; the orthographic projections of the eighth transistor, the ninth transistor, and the tenth transistor on the substrate are arranged sequentially at intervals along the second direction.

[0028] The first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, the ninth transistor, and the tenth transistor each include a plurality of active layers; the plurality of active layers are arranged at intervals along the second direction; the spacing between the plurality of active layers arranged at intervals along the second direction is no greater than 3 micrometers;

[0029] The width of the plurality of active layers along the second direction is no greater than 5 micrometers.

[0030] In some possible implementations, the non-display area includes: a silver paste area, a data fan-out line area, and a GOA signal line area;

[0031] The data fan-out line area is located between the display area and the GOA signal line area, the GOA signal line area is located between the data fan-out line area and the silver paste area, and the data fan-out line area is adjacent to the GOA signal line area;

[0032] The data fan-out signal line includes: a first extension line and a first lift line;

[0033] The angle between the first extension line and the first lifting line is the first included angle.

[0034] In some possible implementations, the first included angle is between 20 degrees and 35 degrees.

[0035] In some possible implementations, the GOA signal line area includes multiple GOA signal lines; wherein, the GOA signal lines include: a second extension line and a second lift line;

[0036] The second extension line is arranged parallel to the first extension line, and the second lifting line is arranged parallel to the first lifting line.

[0037] In some possible implementations, the starting end of the data fan-out signal line is located on the lower side of the anti-static unit; the data fan-out signal line includes a first sub-data fan-out signal line and a second sub-data fan-out signal line, wherein the extension direction of the starting end of the first sub-data fan-out signal line has an angle not equal to 90 degrees with the second direction, and / or, the extension direction of the starting end of the second sub-data fan-out signal line extends along the first direction.

[0038] In some possible implementations, the orthographic projection of the first sub-data fan-out signal line onto the substrate is closer to the display area than the orthographic projection of the second sub-data fan-out signal line onto the substrate.

[0039] In some possible implementations, it also includes:

[0040] A gate conductive layer is located on the substrate.

[0041] A gate insulating layer is located on the side of the gate conductive layer opposite to the substrate.

[0042] A semiconductor layer is located on the side of the gate insulating layer opposite to the substrate; the semiconductor layer includes a plurality of the active layers;

[0043] An etching barrier layer is located on the side of the semiconductor layer opposite to the substrate.

[0044] The source / drain layer, located on the side of the etch barrier layer away from the substrate, includes data lines, data fan-out lines, GOA signal lines, and data conduction signal lines.

[0045] A first insulating layer is located on the side of the source / drain layer opposite to the substrate.

[0046] A common electrode layer is located on the side of the first insulating layer away from the substrate.

[0047] The second insulating layer is located on the side of the common electrode layer that is away from the substrate.

[0048] The pixel electrode layer is located on the side of the second insulating layer away from the substrate.

[0049] In some possible implementations, it further includes: a plurality of transition units; the transition unit includes a first transition hole and a second transition hole; wherein the first transition hole exposes the gate conductive layer and the second transition hole exposes the source / drain layer;

[0050] The pixel electrode layer is connected to the gate conductive layer through the first adapter hole and to the source / drain layer through the second adapter hole.

[0051] In some possible implementations, the adapter unit is also used to connect the GOA signal line to the shift register unit, and / or the adapter unit is located within the shift register unit.

[0052] The display device provided in this disclosure includes the display panel described above. Attached Figure Description

[0053] Figure 1 These are some structural schematic diagrams of the display panel in the embodiments of this disclosure;

[0054] Figure 2 These are some other structural schematic diagrams of the display panel in the embodiments of this disclosure;

[0055] Figure 3 These are further structural schematic diagrams of the display panel in the embodiments of this disclosure;

[0056] Figure 4 These are further structural schematic diagrams of the display panel in the embodiments of this disclosure;

[0057] Figure 5 These are further structural schematic diagrams of the display panel in the embodiments of this disclosure;

[0058] Figure 6 These are some structural schematic diagrams of the color resist unit in the embodiments of this disclosure;

[0059] Figure 7 These are some structural schematic diagrams of the pixel driving unit in the embodiments of this disclosure;

[0060] Figure 8 These are other structural schematic diagrams of the pixel driving unit in the embodiments of this disclosure;

[0061] Figure 9 These are further structural schematic diagrams of the display panel in the embodiments of this disclosure;

[0062] Figure 10 These are further structural schematic diagrams of the display panel in the embodiments of this disclosure;

[0063] Figure 11 These are further structural schematic diagrams of the display panel in the embodiments of this disclosure;

[0064] Figure 12 These are further structural schematic diagrams of the display panel in the embodiments of this disclosure;

[0065] Figure 13 These are some structural schematic diagrams of the shifter register in the embodiments of this disclosure;

[0066] Figure 14 Here are some equivalent circuit diagrams of the shifter register in the embodiments of this disclosure;

[0067] Figure 15 These are some other structural schematic diagrams of the shifter register in the embodiments of this disclosure;

[0068] Figure 16 These are further structural schematic diagrams of the shifter register in the embodiments of this disclosure;

[0069] Figure 17 These are further structural schematic diagrams of the shifter register in the embodiments of this disclosure;

[0070] Figure 18 These are further structural schematic diagrams of the shifter register in the embodiments of this disclosure;

[0071] Figure 19 These are further structural schematic diagrams of the display panel in the embodiments of this disclosure;

[0072] Figure 20 These are further structural schematic diagrams of the display panel in the embodiments of this disclosure;

[0073] Figure 21 These are further structural schematic diagrams of the display panel in the embodiments of this disclosure;

[0074] Figure 22 These are further structural schematic diagrams of the display panel in the embodiments of this disclosure;

[0075] Figure 23 These are further structural schematic diagrams of the display panel in the embodiments of this disclosure;

[0076] Figure 24 These are further structural schematic diagrams of the display panel in the embodiments of this disclosure;

[0077] Figure 25 These are further structural schematic diagrams of the display panel in the embodiments of this disclosure. Detailed Implementation

[0078] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. Furthermore, the embodiments and features in the embodiments of this disclosure can be combined with each other without conflict. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0079] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that an element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect.

[0080] It should be noted that the dimensions and shapes of the figures in the accompanying drawings do not reflect actual proportions and are intended only to illustrate the content of the invention. Furthermore, the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout.

[0081] In some embodiments of this disclosure, the display device may include a display panel and a timing controller. The display panel may include a substrate (i.e., an array substrate), and the substrate may include a display area and a non-display area. The display area may include multiple pixel units arranged in an array. Exemplarily, each pixel unit includes multiple sub-pixels of different colors. For example, a pixel unit may include red, green, and blue sub-pixels, allowing for color mixing to achieve color display. Alternatively, a pixel unit may include red, green, blue, and white sub-pixels, also allowing for color mixing to achieve color display. Of course, in practical applications, the emission color of the sub-pixels in a pixel unit can be designed and determined according to the actual application environment, and is not limited here.

[0082] In some embodiments of this disclosure, the display area may further include multiple gate lines and multiple data lines. Each sub-pixel may include a transistor and a pixel electrode. One row of sub-pixels corresponds to one gate line, and one column of sub-pixels corresponds to one data line. The gate of the transistor is coupled to the corresponding gate line, the source of the transistor is coupled to the corresponding data line, and the drain of the transistor is coupled to the pixel electrode. It should be noted that the pixel array structure of this disclosure may also be a dual-gate structure, i.e., two gate lines are arranged between two adjacent rows of pixels. This arrangement can reduce the number of data lines by half, i.e., it includes data lines between adjacent columns of pixels, but does not include data lines between adjacent columns of pixels. The specific pixel arrangement structure, data lines, and gate line arrangement are not limited.

[0083] In some embodiments of this disclosure, the non-display area may include a gate driving circuit and a source driving circuit. The gate driving circuit is coupled to a gate line, and the source driving circuit is coupled to a data line. Furthermore, a timing controller may be coupled to both the gate driving circuit and the source driving circuit. Generally, the gate driving circuit is located in the non-display areas on the left and right sides of the display panel. Exemplarily, the timing controller can acquire display data of the image to be displayed in the current display frame. The timing controller can input a control signal to the gate driving circuit, so that the gate driving circuit can output a gate scan signal to each gate line according to the input control signal, thereby driving each gate line to control the conduction of transistors in the coupled sub-pixels. Additionally, the timing controller inputs the acquired display data to the source driving circuit, so that the source driving circuit can input a data voltage to the coupled data line according to the input display data, thereby inputting the voltage on the data line to the sub-pixel through the conducting transistor to charge the sub-pixel, thus charging each sub-pixel with the corresponding data voltage to achieve the image display function.

[0084] It should be noted that the display panel in this embodiment can be a liquid crystal display panel. Exemplarily, a liquid crystal display panel generally includes an upper substrate (e.g., a color filter substrate) and a lower substrate (e.g., a substrate substrate) for a cell, and liquid crystal molecules encapsulated between the upper substrate (e.g., the color filter substrate) and the lower substrate (e.g., the substrate substrate). When displaying an image, a voltage difference exists between the data voltage applied to the pixel electrode of each sub-pixel and the common electrode voltage on the common electrode. This voltage difference can form an electric field, causing the liquid crystal molecules to deflect under the action of this electric field. Because different intensities of electric fields cause different degrees of deflection of the liquid crystal molecules, the transmittance of the sub-pixels differs, enabling the sub-pixels to achieve different grayscale brightness levels, thereby realizing image display. Of course, the display panel in this embodiment can also be an OLED display panel, and is not limited thereto.

[0085] This disclosure provides a display panel, such as... Figures 1 to 5 As shown, it includes:

[0086] The substrate 100 includes a display area AA and a non-display area BB;

[0087] The display area AA includes multiple sub-pixels; the multiple sub-pixels include a first sub-pixel spx1 and an edge virtual sub-pixel spx2; at least one row of sub-pixels has at least one edge virtual sub-pixel spx2, and at least one column of sub-pixels has at least one edge virtual sub-pixel spx2;

[0088] Multiple pixel driving units 10 are configured to correspond one-to-one with the first sub-pixel spx1 and the edge virtual sub-pixel spx2; wherein, the pixel driving unit 10 is configured to drive the first sub-pixel spx1 for display of the image;

[0089] The color filter substrate 200 includes a black matrix layer 20 and a color resist layer 30 formed on the color filter substrate 200; the black matrix layer 20 has a plurality of opening regions K1; the color resist layer 30 includes a plurality of first color resist layers 31, a plurality of second color resist layers 32 and a plurality of third color resist layers 33; the orthographic projection of the first color resist layer 31, the second color resist layer 32 and the third color resist layer 33 on the color filter substrate 200 overlaps with the orthographic projection of the opening regions K1 on the color filter substrate 200.

[0090] The orthographic projection of the pixel driving unit 10, which is configured corresponding to the edge virtual sub-pixel spx2, onto the substrate 100 does not overlap with the orthographic projections of the first color resist layer 31, the second color resist layer 32, and the third color resist layer 33 onto the substrate 100; the orthographic projection of the pixel driving unit 10, which is configured corresponding to the edge virtual sub-pixel spx2, onto the substrate 100 does not overlap with the orthographic projection of the opening region K1 onto the substrate 100.

[0091] The embodiments disclosed herein achieve the following: by ensuring that the orthographic projection of the pixel driving unit corresponding to the edge virtual sub-pixel on the substrate does not overlap with the orthographic projection of the first color resist layer, the second color resist layer, and the third color resist layer on the substrate; and by ensuring that the orthographic projection of the pixel driving unit corresponding to the edge virtual sub-pixel on the substrate does not overlap with the orthographic projection of the opening area on the substrate; thereby, the normal display of the display panel can be maintained without affecting the display panel, and the space utilization rate is also improved, meeting the requirement of narrow bezels for the display panel.

[0092] For example, the orthographic projection of some pixel driving units on the substrate does not overlap with the orthographic projections of the first color resist layer, the second color resist layer, and the third color resist layer on the substrate; the orthographic projection of some pixel driving units on the substrate does not overlap with the orthographic projection of the opening region on the substrate; the orthographic projection of the black matrix layer on the substrate overlaps with the orthographic projection of the portion of pixel driving units on the substrate.

[0093] For example, a pixel unit may include a red sub-pixel, a green sub-pixel, and a blue sub-pixel, wherein the red, green, and blue sub-pixels in the pixel unit have the same orthographic projection onto the substrate, and therefore have the same area as the opening area corresponding to the red, green, and blue sub-pixels; or, a pixel unit may also include a red, green, blue, and white sub-pixels, wherein the red, green, blue, and white sub-pixels in the pixel unit have the same orthographic projection onto the substrate, and therefore have the same area as the opening area corresponding to the red, green, blue, and white sub-pixels.

[0094] In some embodiments of this disclosure, such as Figure 1 and Figure 2As shown, the edge virtual sub-pixel spx2 in the same column of sub-pixels is closer to the corner edge FA1 of the display area than the first sub-pixel spx1 in the first direction F1; the edge virtual sub-pixel spx2 in the same row of sub-pixels is closer to the corner edge FA1 of the display area than the first sub-pixel spx1 in the second direction F2.

[0095] For example, the edge virtual sub-pixel spx2 in the same column of sub-pixels is aligned with the first sub-pixel spx1 along the first direction F1; the edge virtual sub-pixel spx2 in the same row of sub-pixels is aligned with the first sub-pixel spx1 along the second direction F2.

[0096] In some embodiments of this disclosure, such as Figures 4 to 6 As shown, the number of opening regions K1 in each column and the number of opening regions K1 in each row decrease along the direction of the corner edge FA1 near the display area; wherein, the color resist layer 30 includes a plurality of color resist units 3, each color resist unit 3 including: a first color resist layer 31, a second color resist layer 32 and a third color resist layer 33; wherein, the first color resist layer 31, the second color resist layer 32 and the third color resist layer 33 in each color resist unit 3 have the same orthographic projection on the substrate; wherein, the area of ​​each color resist unit 3 gradually decreases along the direction of the corner edge FA1 near the display area.

[0097] For example, the opening region is correspondingly provided with multiple color resist units, and the orthographic projection of the first color resist layer, the second color resist layer and the third color resist layer in each color resist unit onto the substrate overlaps with the orthographic projection of the opening region onto the substrate; and the orthographic projections of the opening regions corresponding to the first color resist layer, the second color resist layer and the third color resist layer in the color resist unit onto the substrate are the same; that is, the area and shape of the opening regions corresponding to the first color resist layer, the second color resist layer and the third color resist layer in the color resist unit are approximately the same.

[0098] For example, such as Figure 4 As shown, the area of ​​each column opening region K1 and the area of ​​each row opening region K1 gradually decrease along the direction of the corner edge FA1 near the display area AA.

[0099] In some embodiments of this disclosure, such as Figure 7 As shown, the pixel driving unit 10 includes: a first sub-driving unit 11; the first sub-driving unit 11 includes a first driving transistor T1; wherein, the gate of the first driving transistor T1 is coupled to the gate line GA, the first electrode of the first driving transistor T1 is coupled to the data line DA, and the second electrode of the first driving transistor T1 is coupled to the pixel electrode PE.

[0100] For example, by making the pixel driving unit include only the first sub-driving unit, the space occupancy rate can be further reduced, saving space and thus better achieving a narrow bezel.

[0101] In some embodiments of this disclosure, such as Figure 8 As shown, the pixel driving unit 10 includes: a first sub-driving unit 11 and a second sub-driving unit 12; the second sub-driving unit 12 includes a second driving transistor T2; wherein, the gate of the first driving transistor T1 is coupled to the gate line GA, the first electrode of the first driving transistor T1 is coupled to the data line DA, and the second electrode of the first driving transistor T1 is coupled to the pixel electrode PE; the gate of the second driving transistor T2 is coupled to the gate line GA, the first electrode of the second driving transistor T2 is coupled to the data line DA, and the second electrode of the second driving transistor T2 is coupled to the pixel electrode PE; the pixel driving unit 10 has the same shape in its orthographic projection onto the substrate 100. For example, in a display panel incorporating Dual-Rate Driving (DRD) technology, the subpixels on the substrate are designed in groups of two to form a pixel unit; while the color resist layers on the opposing substrate are designed in groups of three to form a color resist unit; each color resist layer corresponds to one subpixel. In the prior art, to ensure the correspondence between the color resist layers and subpixels and to keep the arrangement design relatively simple, the number of subpixels in each pixel unit is usually... The design is based on the least common multiple of the number of color resist layers in each color resist unit; that is, the array is arranged in groups of six sub-pixels and in groups of six color resist layers. This design is relatively simple and easy to arrange, but it will have a significant impact on the corner areas of the display panel (such as the R-corner area, where R-corner is the rounded corner of an arc tangent to two intersecting straight lines, for example, the rounded corner of an arc tangent to the long side and the short side of the display panel). In other words, the bezels of the corner areas of the display panel will become larger, affecting the aesthetics and the realization of narrow bezels.

[0102] The embodiments of this disclosure include a pixel driving unit comprising a first sub-driving unit and / or a second sub-driving unit, wherein each first sub-driving unit and the second sub-driving unit corresponds to a sub-pixel. The arrangement of the pixel driving units in an array is equivalent to the arrangement of the sub-pixels in an array. When the pixel driving unit contains only the first or second sub-driving unit, the array arrangement is designed with one sub-pixel as a group. When the pixel driving unit contains both the first and second sub-driving units, the array arrangement is designed with two sub-pixels as a group. In the border or corner areas, this disclosure reduces the number of arrayed sub-pixels by setting edge virtual sub-pixels, making it easier to control the number of sub-pixels near the border, thus facilitating the implementation of narrow borders.

[0103] In some embodiments of this disclosure, such as Figures 9 to 12 As shown, multiple sub-pixels spx near the corner edge of the display area are arranged in a stepped manner to form a multi-level pixel ladder (e.g. Figure 12 J1, J2, J3, J4, J5, J6), each pixel step (e.g. Figure 12 J1, J2, J3, J4, J5, and J6 in the image are composed of at least one sub-pixel spx; in some pixel steps (e.g.) Figure 9 In J10, J11, J12, J13, J14, J15, and J16, at least one edge virtual sub-pixel is provided every one pixel step interval (e.g., ...). Figure 9 (spx2_10, spx2_12, spx2_14, spx2_16).

[0104] For example, such as Figure 9 As shown, pixel staircase J10 is provided with an edge virtual sub-pixel spx2_10; pixel staircase J12 is provided with an edge virtual sub-pixel spx2_12; pixel staircase J14 is provided with an edge virtual sub-pixel spx2_14; pixel staircase J16 is provided with an edge virtual sub-pixel spx2_16; wherein, pixel staircase J10 and pixel staircase J12 are separated by one pixel staircase J11; pixel staircase J12 and pixel staircase J14 are separated by one pixel staircase J13; pixel staircase J14 and pixel staircase J16 are separated by one pixel staircase J15; for example, as... Figure 9 As shown, the edge virtual sub-pixel spx2_10 is located at the end of pixel staircase J10 near the common electrode line 50; the edge virtual sub-pixel spx2_12 is located at the end of pixel staircase J12 near the common electrode line 50; the edge virtual sub-pixel spx2_14 is located at the end of pixel staircase J14 near the common electrode line 50; the edge virtual sub-pixel spx2_14 is located at the end of pixel staircase J14 near the common electrode line 50.

[0105] In some embodiments of this disclosure, such as Figures 9 to 12 As shown, the substrate 100 further includes: multiple cascaded shift register units 40, multiple anti-static units (ESD), and at least one common electrode line 50; wherein each shift register unit 40 corresponds to a row of sub-pixels spx.

[0106] The orthographic projection of the anti-static unit ESD on the substrate 100 and the orthographic projection of the cascaded shift register unit 40 on the substrate 100 are located on different sides of the orthographic projection of the common electrode line 50 on the substrate 100, respectively; the orthographic projection of the anti-static unit ESD on the substrate 100 is located between the orthographic projection of the common electrode line 50 on the substrate 100 and the orthographic projection of the sub-pixel spx on the substrate 100.

[0107] Each pixel step (e.g.) Figure 12 The sub-pixels spx in J1, J2, J3, J4, J5, and J6 are each electrically connected to at least one anti-static unit (ESD); the ESD unit is located in the pixel step (e.g., in the first direction F1) on the first direction F1. Figure 12 At the end of J1, J2, J3, J4, J5, J6, the antistatic unit ESD is located between at most two rows of sub-pixels spx in the second direction F2.

[0108] For example, such as Figure 11 and Figure 12 As shown, anti-static unit ESD1 is located at the end of pixel staircase J2 in the first direction F1, anti-static unit ESD2 is located at the end of pixel staircase J4 in the first direction F1, and anti-static unit ESD3 is located at the end of pixel staircase J6 in the first direction F1. Anti-static units ESD1, ESD2, and ESD3 have two edges in the second direction F2, and the distance between the two edges does not exceed two rows of sub-pixels. That is, the width of the orthogonal projection of anti-static units ESD1, ESD2, and ESD3 onto the substrate along the first direction F1 is less than the width of the orthogonal projection of two rows of sub-pixels onto the substrate along the first direction F1.

[0109] In some embodiments of this disclosure, such as Figures 9 to 12 As shown, the substrate 100 further includes: multiple data conduction signal lines (e.g., Figure 10 51 in Figure 12 (51-1, 51-2, 51-3, 51-4, 51-5, 51-6); each pixel step (e.g.) Figure 12 The sub-pixels spx in J1, J2, J3, J4, J5, and J6 are connected via data pass-through signal lines (e.g., ...). Figure 10 51 in Figure 12 The numbers 51-1, 51-2, 51-3, 51-4, 51-5, and 51-6 in the model and their corresponding anti-static units (e.g., [missing information]). Figure 10 ESD in Figure 11 The ESD1, ESD2, and ESD3 lines are connected; among them, the data conduction signal lines (e.g., Figure 12 The numbers 51-1, 51-2, 51-3, 51-4, 51-5, and 51-6 are arranged in an S-shape, and / or a zigzag shape, and / or a lightning bolt shape.

[0110] In some embodiments of this disclosure, the antistatic unit corresponding to the nth pixel step is located at the end of the nth pixel step in the first direction, where n is an integer not less than 1 and i is an integer not less than 1.

[0111] In some embodiments of this disclosure, the anti-static unit corresponding to the nth pixel step is located at the end of the (n+i)th pixel step in the first direction, where n is an integer not less than 1 and i is an integer not less than 1.

[0112] In some embodiments of this disclosure, the anti-static unit corresponding to the nth pixel step includes a first anti-static unit located at the end of the nth pixel step in the first direction and a first anti-static unit located at the end of the (n+i)th pixel step in the first direction, wherein n is an integer not less than 1 and i is an integer not less than 1.

[0113] For example, such as Figure 11 and Figure 12 As shown, the anti-static unit ESD1 corresponding to the first pixel step J1 is located at the end of the second pixel step J2 in the first direction F1. The sub-pixels in the first pixel step J1 are connected to the anti-static unit ESD1 via data conduction signal line 51-1. The anti-static unit ESD2 corresponding to the second pixel step J2 is located at the end of the fourth pixel step J4 in the first direction F1. The sub-pixels in the second pixel step J2 are connected to the anti-static unit ESD2 via data conduction signal line 51-2. The anti-static unit ESD2 corresponding to the third pixel step J3 is located at the end of the fourth pixel step J4 in the first direction F1. The sub-pixels in the third pixel step J3 are connected to the anti-static unit ESD2 via data conduction signal line 51-3. The anti-static unit ESD2, corresponding to the 4th pixel step J4, is located at the end of the 4th pixel step J4 in the first direction F1. The corresponding anti-static unit ESD3 is located at the end of the 6th pixel step J6 in the first direction F1. Some sub-pixels in the 4th pixel step J4 are connected to the anti-static unit ESD2 via data conduction signal line 51-4, and some sub-pixels in the 4th pixel step J4 are connected to the anti-static unit ESD3 via data conduction signal line 51-5. The anti-static unit ESD3, corresponding to the 5th pixel step J5, is located at the end of the 6th pixel step J6 in the first direction F1. The sub-pixels in the 5th pixel step J5 are connected to the anti-static unit ESD3 via data conduction signal line 51-6.

[0114] For example, such as Figures 9 to 12 As shown, the substrate 100 also includes multiple data fan-out signal lines 52 and virtual data fan-out lines 53; data conduction signal lines (e.g. Figure 10 51 in Figure 12 51-1, 51-2, 51-3, 51-4, 51-5, and 51-6 in the series pass through an anti-static unit (e.g., Figure 10 ESD in Figure 11The ESD1, ESD2, and ESD3 signals are electrically connected to the data fan-out signal line 52. It should be noted that the anti-static unit (e.g., Figure 10 ESD in Figure 11 The ESD1, ESD2, and ESD3 lines can prevent electrostatic discharge (ESD1, ESD2, and ESD3) from accumulating and causing electrostatic breakdown, which can affect display quality and display effect. Among these, the data conduction signal lines (e.g., Figure 10 51 in Figure 12 The orthographic projections of sub-pixels 51-1, 51-2, 51-3, 51-4, 51-5, and 51-6 on the substrate 100 are located between the orthographic projections of the sub-pixels 51-1, 51-2, 51-3, 51-4, 51-5, and 51-6 on the substrate 100 and the data fan-out signal line 52 on the substrate 100; the orthographic projections of the data fan-out signal line 52 on the substrate 100 are located within the anti-static unit (e.g., Figure 10 ESD in Figure 11 The ESD1, ESD2, and ESD3 data points are projected onto the substrate 100, and the virtual data fan-out line 53 is projected onto the substrate 100. It should be noted that the virtual fan-out line can reduce the problem of uneven data fan-out lines near the shift register caused by some process steps (such as exposure and etching), mainly due to the size difference between multiple data fan-out lines.

[0115] In some embodiments of this disclosure, such as Figure 13 and Figure 14 As shown, the shift register unit 40 includes: a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, and a tenth transistor M10; wherein, the first transistor and the second transistor are arranged opposite each other along a first direction F1; the third transistor and the fourth transistor are arranged opposite each other along the first direction F1; the orthographic projections of the third transistor and the fourth transistor onto the substrate are located between the orthographic projections of the first transistor and the fifth transistor onto the substrate; the sixth transistor and the seventh transistor are arranged opposite each other along the first direction F1; and the orthographic projections of the eighth, ninth, and tenth transistors onto the substrate are arranged sequentially at intervals along a second direction F2. For example, the orthographic projections of the first transistor M1 and the second transistor M2 onto the substrate are the same; the orthographic projections of the sixth transistor M6 and the seventh transistor M7 onto the substrate are the same.

[0116] For example, such as Figure 13 and Figure 14As shown, the shift register unit 40 further includes: a twelfth transistor M12, a thirteenth transistor M13, a fourteenth transistor M14, a fifteenth transistor M15, a sixteenth transistor M16, a seventeenth transistor M17, and an eighteenth transistor M18; wherein, the twelfth transistor M12 and the thirteenth transistor M13 have the same orthographic projection on the substrate, and the twelfth transistor M12 and the thirteenth transistor M13 are arranged opposite each other along the second direction F2; the fifteenth transistor M15 and the sixteenth transistor M16 have the same orthographic projection on the substrate, and the fifteenth transistor M15 and the sixteenth transistor M16 are arranged opposite each other along the first direction F1; the seventeenth transistor M17 and the eighteenth transistor M18 have the same orthographic projection on the substrate, and the seventeenth transistor M17 and the eighteenth transistor M18 are arranged opposite each other along the first direction F1.

[0117] For example, such as Figure 14The equivalent circuit diagram of the shift register unit shown is as follows: the gate of the third transistor M3 is coupled to its first electrode; the gate of the first transistor M1 is coupled to the third node PU; the first electrode of the first transistor M1 is coupled to the first node PD1; and the second electrode of the first transistor M1 is coupled to the first level signal terminal LVGL. The gate of the second transistor M2 is coupled to the first electrode of the first capacitor C1; the first electrode of the second transistor M2 is coupled to the second node PD2; and the second electrode of the second transistor M2 is coupled to the first level signal terminal LVGL. The first electrode of the third transistor M3 is coupled to the first output control signal terminal Out_C(n-1); and the second electrode of the third transistor M3 is coupled to the first electrode of the eighth transistor M8. The gate of the fourth transistor M4 is coupled to the second node PD2, the first terminal of the fourth transistor M4 is coupled to the second terminal of the third transistor M3, and the second terminal of the fourth transistor M4 is coupled to the first level signal terminal LVGL; the gate of the fifth transistor M5 is coupled to the first node PD1, the first terminal of the fifth transistor M5 is coupled to the second terminal of the third transistor M3, and the second terminal of the fifth transistor M5 is coupled to the first level signal terminal LVGL; the gate of the sixth transistor M6 is coupled to the first node PD1, the first terminal of the thirteenth transistor M13A is coupled to the first cascade output terminal Gout(n), and the second terminal of the sixth transistor M6 is coupled to the second level signal terminal VGL; the gate of the seventh transistor M7 is coupled to the second node P... The seventh transistor M7 is coupled to D2. Its first terminal is coupled to the first cascaded output terminal Gout(n), and its second terminal is coupled to the second-level signal terminal VGL. The gate of the eighth transistor M8 is coupled to the third output control signal terminal Out_C(n+1), and its second terminal is coupled to the first-level signal terminal LVGL. The gate of the ninth transistor M9 is coupled to the first electrode of the first capacitor C1, its first terminal is coupled to the first clock signal terminal CLK, and its second terminal is coupled to the first cascaded output terminal Gout(n). The second electrode of the first capacitor C1 is coupled to the first cascaded output terminal Gout(n). The gate of the tenth transistor M10 is coupled to the first... The first electrode of capacitor C1 is coupled; the first electrode of the tenth transistor M10 is coupled to the first clock signal terminal CLK; the second electrode of the tenth transistor M10 is coupled to the second output control signal terminal Out_C(n); the gate of the eleventh transistor M11 is coupled to the second cascaded output terminal Gout(n+1); the first electrode of the eleventh transistor M11 is coupled to the second electrode of the ninth transistor M9; the second electrode of the eleventh transistor M11 is coupled to the second level signal terminal VGL; the gate of the twelfth transistor M12 is coupled to the second node PD2; the first electrode of the twelfth transistor M12 is coupled to the second output control signal terminal Out_C(n); the second electrode of the twelfth transistor M12 is coupled to the first level signal terminal LVGL.The gate of the thirteenth transistor M13 is coupled to the first node PD1, the first terminal of the thirteenth transistor M13 is coupled to the second output control signal terminal Out_C(n), and the second terminal of the thirteenth transistor M13 is coupled to the first level signal terminal LVGL. The gate of the fourteenth transistor M14 is coupled to the reset signal terminal T_RST, the first terminal of the fourteenth transistor M14 is coupled to the second terminal of the first transistor M1, and the second terminal of the fourteenth transistor M14 is coupled to the first level signal terminal LVGL. The gate of the fifteenth transistor M15 is coupled to the first output control signal terminal Out_C(n-1), the first terminal of the fifteenth transistor M15 is coupled to the first node PD1, and the second terminal of the fifteenth transistor M15 is coupled to the first level signal terminal LVGL. VGL is coupled; the gate of the sixteenth transistor M16 is coupled to the first output control signal terminal Out_C(n-1), the first terminal of the sixteenth transistor M16 is coupled to the second node PD2, and the second terminal of the sixteenth transistor M16 is coupled to the first level signal terminal LVGL; the gate of the seventeenth transistor M17 is coupled to the first terminal of the seventeenth transistor M17, the first terminal of the seventeenth transistor M17 is coupled to the second clock signal terminal CLKB, and the second terminal of the seventeenth transistor M17 is coupled to the first node PD1; the gate of the eighteenth transistor M18 is coupled to the first terminal of the eighteenth transistor M18, the first terminal of the eighteenth transistor M18 is coupled to the first clock signal terminal CLK, and the second terminal of the eighteenth transistor M18 is coupled to the second node PD2.

[0118] For example, the first terminal of the transistor is the source and the second terminal is the drain; or the first terminal is the drain and the second terminal is the source; this is not limited here.

[0119] In some embodiments of this disclosure, such as Figures 15 to 18 As shown, the first transistor, second transistor, third transistor, fourth transistor, fifth transistor, sixth transistor, seventh transistor, eighth transistor, ninth transistor, and tenth transistor each include multiple active layers 60; the multiple active layers 60 are arranged at intervals along the second direction F2; the spacing d between the multiple active layers 60 arranged at intervals along the second direction F2 is no greater than 3 micrometers.

[0120] In some embodiments of this disclosure, such as Figure 17 and Figure 18 As shown, the width c of the multiple active layers 60 along the second direction F2 is no greater than 5 micrometers.

[0121] For example, by controlling the position of the transistors in the shift register unit, controlling the spacing of the active layers of the transistors arranged at intervals along the second direction F2, and the width of the active layers, the size of the shift register unit can be reduced, further saving space and making it easier to achieve a narrow bezel.

[0122] In some embodiments of this disclosure, such as Figures 19 to 21 As shown, the non-display area BB includes: a silver paste area 70, a data fan-out line area 80, and a GOA signal line area 90; wherein, the data fan-out line area 80 is located between the display area AA and the GOA signal line area 90, the GOA signal line area 90 is located between the data fan-out line area 80 and the silver paste area 70, and the data fan-out line area 80 is adjacent to the GOA signal line area 90.

[0123] For example, such as Figure 19 and Figure 20 As shown, the distance d' between the edge of the GOA signal line region 90 and the edge of the adjacent silver paste region 70 is not less than 150 micrometers.

[0124] In some embodiments of this disclosure, such as Figures 19 to 21 As shown, the data fan-out signal line 52 includes a first extension line 52-1 and a first riser line 52-2; wherein, the angle between the first extension line 52-1 and the first riser line 52-2 is a first angle e. The GOA signal line area 90 includes multiple GOA signal lines 91; wherein, the GOA signal line 91 includes a second extension line 91-1 and a second riser line 91-2; the second extension line 91-1 is arranged parallel to the first extension line 52-1, and the second riser line 91-2 is arranged parallel to the first riser line 52-2.

[0125] For example, the first included angle e is located between 20 degrees and 35 degrees. For instance, the first included angle e can be 20 degrees, 23 degrees, 26 degrees, 29 degrees, 30 degrees, 35 degrees, etc., and is not limited here.

[0126] For example, such as Figure 21 As shown, f represents the distance that multiple data fan-out signal lines can rise.

[0127] For example, multiple GOA signal lines in the GOA signal line area can be used to input the required signals to the first level signal terminal LVGL, the second level signal terminal VGL, the first output control signal terminal Out_C(n-1), the second output control signal terminal Out_C(n), the third output control signal terminal Out_C(n+1), the first clock signal terminal CLK, and the second clock signal terminal CLKB in the shift register unit.

[0128] In some embodiments of this disclosure, as shown in 21, the starting end of the data fan-out signal line (e.g. Figure 21Q1 and Q2 are located below the ESD protection unit; the data fan-out signal line includes a first sub-data fan-out signal line 52_q1 and a second sub-data fan-out signal line 52_q2, wherein the extension direction of the starting end Q1 of the first sub-data fan-out signal line 52_q1 has an angle not equal to 90 degrees with the second direction F2, and / or the extension direction of the starting end Q2 of the second sub-data fan-out signal line 52_q2 extends along the first direction F1.

[0129] In some embodiments of this disclosure, such as Figure 21 As shown, the orthographic projection of the first sub-data fan-out signal line 52_q1 onto the substrate 100 is closer to the display area than the orthographic projection of the second sub-data fan-out signal line 52_q2 onto the substrate. Optionally, the first sub-data fan-out signal line 52_q1 is electrically connected to the ESD protection unit closest to the data fan-out signal line along the first direction F1.

[0130] This embodiment of the present disclosure extends the starting end Q2 of the second sub-data fan-out signal line along the first direction F1, and / or the extending direction of the starting end Q1 of the first sub-data fan-out signal line has an angle not equal to 90 degrees with the second direction F2, wherein the projection of the first sub-data fan-out signal line on the substrate is closer to the display area than the projection of the second sub-data fan-out signal line on the substrate. This allows the signal lines such as the common electrode signal line, data fan-out signal line, and GOA signal line to have space for setting the raised line portion, thus meeting the distance requirements between the silver paste area and the signal line under the narrow bezel constraint and avoiding short circuits in the signal lines.

[0131] In some embodiments of this disclosure, such as Figure 22 As shown, it also includes:

[0132] A gate conductive layer 110 is located on a substrate 100;

[0133] The gate insulating layer 120 is located on the side of the gate conductive layer 110 that is away from the substrate 100.

[0134] Semiconductor layer 130 is located on the side of gate insulating layer 120 away from substrate 100; semiconductor layer 130 includes multiple active layers;

[0135] An etch barrier layer 140 is located on the side of the semiconductor layer 130 away from the substrate 100.

[0136] The source / drain layer 150 is located on the side of the etch barrier layer 140 away from the substrate 100.

[0137] The first insulating layer 160 is located on the side of the source / drain layer 150 away from the substrate 100;

[0138] The common electrode layer 170 is located on the side of the first insulating layer 160 that is away from the substrate 100.

[0139] The second insulating layer 180 is located on the side of the common electrode layer 170 that is away from the substrate 100.

[0140] The pixel electrode layer 190 is located on the side of the second insulating layer 180 away from the substrate 100.

[0141] For example, the gate conductive layer may include gate lines and the gates of the aforementioned transistors; the source-drain layer may include data lines, virtual data fan-out signal lines, data fan-out signal lines, GOA signal lines, data turn-on signal lines, and the source-drain electrodes of the aforementioned transistors; the common electrode layer may include common electrode lines; and the pixel electrode layer may include pixel electrodes.

[0142] For example, the gate conductive layer, source / drain layer, common electrode layer, and pixel electrode layer can be made of conductive materials. For instance, conductive materials may include metals such as aluminum, molybdenum, and titanium, or alloys, or metal oxides such as indium tin oxide (ITO). The embodiments of this disclosure do not limit the materials of each functional layer.

[0143] For example, the material of the semiconductor layer may include oxides, amorphous silicon, or low-temperature polycrystalline silicon, etc., and is not limited thereto.

[0144] For example, the gate insulating layer, the etch barrier layer, the first insulating layer, and the second insulating layer are all formed of insulating materials. As needed, organic insulating materials, such as polyimide and resin materials, can be selected, or inorganic insulating materials, such as silicon oxide, silicon nitride, and silicon oxynitride, can be selected. The embodiments of this disclosure do not specifically limit the materials of each functional layer.

[0145] In some embodiments of this disclosure, such as Figures 23 to 25 As shown, it also includes: multiple transition units (e.g., K1 and K2 in the figure); wherein, the transition unit includes a first transition hole K1 and a second transition hole K2; wherein, the first transition hole K1 exposes the gate conductive layer 110, and the second transition hole K2 exposes the source drain layer 150; the pixel electrode layer 190 is connected to the gate conductive layer 110 through the first transition hole K1 and to the source drain layer 150 through the second transition hole K2.

[0146] For example, such as Figure 23 As shown, the width of the first adapter hole in the second direction is no greater than 7 micrometers; the width of the second adapter hole in the second direction is no less than 5 micrometers.

[0147] For example, by controlling the size of the first via K1 and the second via K2, and by using an ICP etching process, this disclosure can reduce the overall size of all vias to about 12.5µm, thereby further achieving a narrow bezel.

[0148] In some embodiments of this disclosure, such as Figure 24 and Figure 25 As shown, the switching units (e.g., K1 and K2 in the figure) are also used to connect the GOA signal line to the shift register unit 40, and / or the switching units (e.g., K1 and K2 in the figure) are located inside the shift register unit 40.

[0149] For example, the GOA signal line is connected to the second clock signal terminal CLKB in the shift register unit 40 through an adapter hole, so that the second clock signal terminal CLKB provides the required signal to the seventeenth transistor M17; the GOA signal line is connected to the first clock signal terminal CLK in the shift register unit 40 through an adapter hole, so that the first clock signal terminal CLK provides the required signal to the eighteenth transistor M18.

[0150] For example, the first adapter hole K1 located in the shift register unit 40 connects the gate of the sixteenth transistor in the gate conductive layer 110 to the pixel electrode in the pixel electrode layer 190; the second adapter hole K2 located in the shift register unit 40 connects the source and drain stages of the sixteenth transistor M16 in the source and drain layer 150 to the pixel electrode in the pixel electrode layer 190.

[0151] Based on the same disclosed concept, this disclosure also provides a display device, including the display panel described above. The principle by which this display device solves the problem is similar to that of the aforementioned display panel; therefore, the implementation of this display device can refer to the implementation of the aforementioned display panel, and the repetitions will not be repeated here.

[0152] In specific implementations, in the embodiments of this disclosure, the display device can be any product or component with a display function, such as a mobile phone, electronic watch, tablet computer, television set, monitor, laptop computer, digital photo frame, or navigator. Other essential components of the display device are those that should be understood by those skilled in the art and will not be described in detail here, nor should they be construed as limiting this disclosure.

[0153] Although preferred embodiments of the invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including both the preferred embodiments and all changes and modifications falling within the scope of the invention.

[0154] Obviously, those skilled in the art can make various modifications and variations to the embodiments of the present invention without departing from the spirit and scope of the embodiments of the present invention. Thus, if these modifications and variations to the embodiments of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention also intends to include these modifications and variations.

Claims

1. A display panel, wherein, include: The substrate includes the display area and the non-display area; The display area includes multiple sub-pixels; the multiple sub-pixels include a first sub-pixel and edge virtual sub-pixels; At least one row of the sub-pixels has at least one edge virtual sub-pixel, and at least one column of the sub-pixels has at least one edge virtual sub-pixel; Multiple pixel driving units are configured to correspond one-to-one with the first sub-pixel and the edge virtual sub-pixel; wherein, the pixel driving unit is configured to drive the first sub-pixel to display the image; A color filter substrate includes a black matrix layer and a color resist layer formed on the color filter substrate; the black matrix layer has a plurality of opening regions; the color resist layer includes a plurality of first color resist layers, a plurality of second color resist layers and a plurality of third color resist layers; the orthographic projections of the first color resist layers, the second color resist layers and the third color resist layers on the color filter substrate overlap with the orthographic projections of the opening regions on the color filter substrate. The orthographic projection of the pixel driving unit corresponding to the edge virtual sub-pixel on the substrate does not overlap with the orthographic projections of the first color resist layer, the second color resist layer, and the third color resist layer on the substrate; the orthographic projection of the pixel driving unit corresponding to the edge virtual sub-pixel on the substrate does not overlap with the orthographic projection of the opening region on the substrate. Multiple sub-pixels near the corner edge of the display area are arranged in a stepped manner to form a multi-level pixel ladder, each level of the pixel ladder consisting of at least one sub-pixel; in some of the pixel ladders, at least one edge virtual sub-pixel is provided every other level of the pixel ladder; The substrate further includes: multiple cascaded shift register units, multiple anti-static units, and at least one common electrode line; wherein each shift register unit corresponds to one row of the sub-pixels; The anti-static unit and the cascaded shift register unit are located on different sides of the common electrode line in the projection of the substrate, respectively, in the projection of the anti-static unit on the substrate. The projection of the anti-static unit in the projection of the substrate is located between the projection of the common electrode line in the projection of the substrate and the projection of the sub-pixel in the projection of the substrate. Each sub-pixel in each pixel ladder is electrically connected to at least one of the anti-static units; the anti-static unit is located at the end of the pixel ladder in a first direction, and the anti-static unit is located between at most two rows of sub-pixels in a second direction.

2. The display panel as claimed in claim 1, wherein, The edge virtual sub-pixel in the same column of sub-pixels is closer to the corner edge of the display area in a first direction than the first sub-pixel; the edge virtual sub-pixel in the same row of sub-pixels is closer to the corner edge of the display area in a second direction than the first sub-pixel.

3. The display panel as claimed in claim 1, wherein, The number of open areas in each column and the number of open areas in each row decrease along the direction close to the corner edge of the display area; The color resist layer includes multiple color resist units, and each color resist unit includes: a first color resist layer, a second color resist layer and a third color resist layer; wherein the first color resist layer, the second color resist layer and the third color resist layer in each color resist unit have the same orthographic projection on the substrate. The area of ​​each color resist unit gradually decreases along the direction close to the corner edge of the display area.

4. The display panel as claimed in claim 1, wherein, The pixel driving unit includes: a first sub-driving unit, and / or, a second sub-driving unit; The first sub-driving unit includes a first driving transistor; the gate of the first driving transistor is coupled to a gate line, the first electrode of the first driving transistor is coupled to a data line, and the second electrode of the first driving transistor is coupled to a pixel electrode. The second sub-driving unit includes a second driving transistor; the gate of the second driving transistor is coupled to the gate line, the first electrode of the second driving transistor is coupled to the data line, and the second electrode of the second driving transistor is coupled to the pixel electrode; The pixel driving unit has the same shape as the orthographic projection of the substrate.

5. The display panel as claimed in claim 1, wherein, The anti-static unit corresponding to the nth pixel step is located at the end of the nth pixel step in the first direction, where n is an integer not less than 1 and i is an integer not less than 1.

6. The display panel as claimed in claim 1, wherein, The anti-static unit corresponding to the nth pixel step is located at the end of the (n+i)th pixel step in the first direction, where n is an integer not less than 1 and i is an integer not less than 1.

7. The display panel as claimed in claim 1, wherein, The anti-static unit corresponding to the nth pixel step includes a first anti-static unit located at the end of the nth pixel step in the first direction and a first anti-static unit located at the end of the (n+i)th pixel step in the first direction, where n is an integer not less than 1 and i is an integer not less than 1.

8. The display panel as claimed in claim 1, wherein, The substrate further includes: multiple data conduction signal lines; the sub-pixels in each pixel staircase are connected to the corresponding anti-static unit through the data conduction signal lines; The data conduction signal lines are arranged in an S-shape, and / or a zigzag shape, and / or a lightning bolt shape.

9. The display panel according to any one of claims 1-8, wherein, The shift register unit includes: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, and a tenth transistor; Wherein, the first transistor and the second transistor are disposed opposite to each other along the first direction; the third transistor and the fourth transistor are disposed opposite to each other along the first direction; the orthographic projections of the third transistor and the fourth transistor on the substrate are located between the orthographic projections of the first transistor and the fifth transistor on the substrate; the sixth transistor and the seventh transistor are disposed opposite to each other along the first direction; the orthographic projections of the eighth transistor, the ninth transistor, and the tenth transistor on the substrate are arranged sequentially at intervals along the second direction. The first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, the ninth transistor, and the tenth transistor each include a plurality of active layers; the plurality of active layers are arranged at intervals along the second direction; the spacing between the plurality of active layers arranged at intervals along the second direction is no greater than 3 micrometers; The width of the plurality of active layers along the second direction is no greater than 5 micrometers.

10. The display panel as claimed in claim 9, wherein, The non-display area includes: a silver paste area, a data fan-out line area, and a GOA signal line area; The data fan-out line area is located between the display area and the GOA signal line area, the GOA signal line area is located between the data fan-out line area and the silver paste area, and the data fan-out line area is adjacent to the GOA signal line area; The data fan-out signal line includes: a first extension line and a first lift line; The angle between the first extension line and the first lifting line is the first included angle.

11. The display panel as claimed in claim 10, wherein, The first included angle is between 20 degrees and 35 degrees.

12. The display panel as claimed in claim 10, wherein, The GOA signal line area includes multiple GOA signal lines; wherein, the GOA signal lines include: a second extension line and a second lifting line; The second extension line is arranged parallel to the first extension line, and the second lifting line is arranged parallel to the first lifting line.

13. The display panel as claimed in claim 10, wherein, The starting end of the data fan-out signal line is located on the lower side of the anti-static unit; the data fan-out signal line includes a first sub-data fan-out signal line and a second sub-data fan-out signal line, wherein the extension direction of the starting end of the first sub-data fan-out signal line has an angle not equal to 90 degrees with the second direction, and / or the extension direction of the starting end of the second sub-data fan-out signal line extends along the first direction.

14. The display panel as claimed in claim 13, wherein, The orthographic projection of the first sub-data fan-out signal line onto the substrate is closer to the display area than the orthographic projection of the second sub-data fan-out signal line onto the substrate.

15. The display panel according to any one of claims 1-8, wherein, Also includes: A gate conductive layer is located on the substrate. A gate insulating layer is located on the side of the gate conductive layer opposite to the substrate. A semiconductor layer is located on the side of the gate insulating layer opposite to the substrate. The semiconductor layer includes multiple active layers; An etching barrier layer is located on the side of the semiconductor layer opposite to the substrate. The source / drain layer, located on the side of the etch barrier layer away from the substrate, includes data lines, data fan-out lines, GOA signal lines, and data conduction signal lines. A first insulating layer is located on the side of the source / drain layer opposite to the substrate. A common electrode layer is located on the side of the first insulating layer away from the substrate. The second insulating layer is located on the side of the common electrode layer that is away from the substrate. The pixel electrode layer is located on the side of the second insulating layer away from the substrate.

16. The display panel as claimed in claim 15, wherein, It also includes: multiple adapter units; each adapter unit includes a first adapter hole and a second adapter hole; wherein the first adapter hole exposes the gate conductive layer, and the second adapter hole exposes the source / drain layer; The pixel electrode layer is connected to the gate conductive layer through the first adapter hole and to the source / drain layer through the second adapter hole.

17. The display panel as claimed in claim 16, wherein, The adapter unit is also used to connect the GOA signal line to the shift register unit, and / or the adapter unit is located within the shift register unit.

18. A display device comprising a display panel as described in any one of claims 1-17.

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