An output current detection method, an electronic device, and a storage medium thereof

Abstract

The embodiment of the application discloses an output current detection method, an electronic device and a storage medium thereof. The method comprises the following steps: acquiring the average current of a switching tube of a switched capacitor converter in N switching periods; and obtaining the output current of the switched capacitor converter based on the duty cycle of the switching tube and the average current. The embodiment of the application is directed to the switched capacitor converter, and the output current is obtained by detecting the switching tube current and the duty cycle of the corresponding switching tube according to the relationship between the switching tube current and the output current, so that the system loss is reduced, the heat dissipation area is reduced, the power density of the switched capacitor converter is improved, and the possibility that the sampling result is affected by the switching noise interference due to the additional sampling resistor in the high-frequency switching loop is avoided.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of switched capacitors, and in particular to an output current detection method, an electronic device and its storage medium. Background Technology

[0002] With the rapid development of artificial intelligence technology, the surge in computing power demand is driving the evolution of hardware systems towards low-voltage, high-current applications. Against this backdrop, DrMOS (Driver-MOSFET integrated module), with its high integration, high efficiency, and optimized thermal management capabilities, has become a core supporting technology for modern power systems. Compared to the high parasitic parameters and slow dynamic response caused by the separation of the driver and MOSFET in traditional discrete solutions, DrMOS integrates both into a single package, significantly reducing the board area (to as much as a quarter of traditional designs), while simultaneously reducing power loss by more than 15% and effectively suppressing high-frequency switching noise.

[0003] DrMOS has achieved a revolutionary breakthrough in current sampling technology. Traditional DCR sampling relies on inductor DC resistors and external RC circuits, which suffer from accuracy issues due to temperature coefficient differences, complex debugging, and the inability to detect inductor saturation in real time. DrMOS, however, employs single-die current mirror technology, directly outputting a mirror current that is strictly proportional to the inductor current through the CS pin, achieving precise cycle-by-cycle monitoring with an error controllable within ±2%. This technology features temperature self-compensation and is independent of on-resistance, duty cycle, and frequency variations, significantly improving the current detection accuracy of each phase. The DrMOS current sensing mechanism can replace the traditional output current sensing network composed of sampling resistors, reducing system losses, minimizing board space, and increasing power density.

[0004] In certain topologies using DrMOS, such as switch-capacitor converters, directly using the current signal generated by DrMOS cannot directly obtain the actual required output current, causing difficulties in output current detection and protection. Existing switch-capacitor converters generally employ an output current detection scheme, that is, a sampling resistor R is connected in series in the inductor and output capacitor circuit. CS The signal is then converted by signal processing circuits such as operational amplifiers, and then converted from analog to digital by the controller's ADC to finally obtain the output current. This method requires an additional sampling resistor, which increases system losses and requires a larger heat dissipation area, significantly reducing the power density of the power supply system. Furthermore, because the sampling resistor is located in a high-frequency switching circuit, it is susceptible to switching noise interference, which affects the final sampling result. Summary of the Invention

[0005] The main technical problem solved by the embodiments of the present invention is to provide an output current detection method, an electronic device and its storage medium, which can solve at least some of the defects of existing switched capacitor converters.

[0006] In a first aspect, embodiments of the present invention provide an output current detection method applied to a switched capacitor converter, comprising: obtaining the average current of the switching transistor of the switched capacitor converter over N switching cycles; and obtaining the output current of the switched capacitor converter based on the duty cycle of the switching transistor and the average current.

[0007] Optionally, the switching transistors include two main switching transistors and two synchronous rectifier transistors. Obtaining the output current of the switched capacitor converter based on the duty cycle of the switching transistors and the average current includes: obtaining the duty cycle of the main switching transistors in the N switching cycles; obtaining the average duty cycle based on the N duty cycles of the main switching transistors; and obtaining the output current based on the average duty cycle and the average current.

[0008] Optionally, obtaining the output current based on the average duty cycle and the average current includes: determining whether the average duty cycle is greater than 0.5; if so, using a preset first calculation formula to obtain the output current based on the average duty cycle and the average current; if not, using a preset second calculation formula to obtain the output current based on the average duty cycle and the average current.

[0009] Optionally, the average current is the sum of the currents of the two main switching transistors and the two synchronous rectifier switching transistors, and is the average value over the N switching cycles.

[0010] The first calculation formula is:

[0011] I OUT =[1 / (1+d)] 2 )]×I Q_all ;

[0012] The second calculation formula is:

[0013] I OUT =[2 / (2+d)]×I Q_all ;

[0014] Among them, I OUT The output current is d, the average duty cycle is I. Q_all The average current value is given.

[0015] Optionally, the average current is the sum of the currents of the two synchronous rectifier switches, and is the average value over the N switching cycles.

[0016] The first calculation formula is:

[0017] I OUT =[1 / (1-d)] 2 )]×I Q_all ;

[0018] The second calculation formula is:

[0019] I OUT =[2 / (2-d)]×I Q_all ;

[0020] Among them, I OUT The output current is d, the average duty cycle is I. Q_all The average current value is given.

[0021] Optionally, obtaining the average current of the switching transistors of the switched capacitor converter over N switching cycles includes: obtaining the current of the two main switching transistors and the two synchronous rectifier transistors over the N switching cycles; summing the currents of the two main switching transistors and the two synchronous rectifier transistors in each switching cycle to obtain the total switching current; converting the total switching current into a voltage signal; sampling the voltage signal over the N switching cycles to obtain an output data stream; and integrating the output data stream to obtain the average current.

[0022] Optionally, obtaining the average current of the switching transistors of the switched capacitor converter over N switching cycles includes: obtaining the current of the two synchronous rectifiers over the N switching cycles; summing the currents of the two synchronous rectifiers in each switching cycle to obtain the total switching current; converting the total switching current into a voltage signal; sampling the voltage signal over the N switching cycles to obtain an output data stream; and integrating the output data stream to obtain the average current.

[0023] Optionally, the step of integrating the output data stream to obtain the average current includes: integrating the output data stream; stopping the integration when the integration time reaches the N switching cycles to obtain the average voltage; and converting the average voltage into the average current.

[0024] Optionally, the two main switching transistors include a first main switching transistor and a second main switching transistor; the first main switching transistor and the second main switching transistor are integrated in a first switching transistor driving integrated module, and the current of the first main switching transistor and the current of the second main switching transistor are obtained through the internal current mirror of the first switching transistor driving integrated module.

[0025] Optionally, the two synchronous rectifiers include a first synchronous rectifier and a second synchronous rectifier; the first synchronous rectifier and the second synchronous rectifier are integrated in a second switch driver integrated module, and the current of the first synchronous rectifier and the current of the second synchronous rectifier are obtained through the internal current mirror of the second switch driver integrated module.

[0026] In a second aspect, embodiments of the present invention provide an electronic device, comprising: at least one processor; at least one network interface communicatively connected to a corresponding processor; and a memory communicatively connected to the at least one processor; wherein the network interface is used to establish a communication connection between the processor and other external devices; the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to perform an output current detection method as described in the first aspect.

[0027] Thirdly, embodiments of the present invention provide a non-volatile computer storage medium storing computer-executable instructions that are executed by one or more processors, causing the one or more processors to perform an output current detection method as described in the first aspect.

[0028] The beneficial effects of the embodiments of the present invention are as follows: Unlike the prior art, the embodiments of the present invention are for switched capacitor converters. Based on the relationship between the switching current and the output current, the output current is obtained by detecting the switching current and the corresponding duty cycle of the switching transistor. This avoids the need to add an additional sampling resistor in the output circuit, thereby reducing system losses, reducing the heat dissipation area and improving the power density of the switched capacitor converter. It also avoids the possibility that adding a sampling resistor in the high-frequency switching circuit will easily affect the sampling results due to switching noise interference. Attached Figure Description

[0029] One or more embodiments are illustrated by way of example with reference to the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Elements having the same reference numerals in the drawings are denoted as similar elements. Unless otherwise stated, the figures in the drawings are not to be limited by scale.

[0030] Figure 1 This is a schematic diagram of the output current detection structure of an existing switched capacitor converter;

[0031] Figure 2 This is the circuit schematic of a switched capacitor converter;

[0032] Figure 3 It is a waveform diagram of the current of each switch when the duty cycle of the main switch is less than or equal to 50%;

[0033] Figure 4 This is a waveform diagram of the current of each switch when the duty cycle of the main switch is greater than 50%.

[0034] Figure 5 This is a schematic flowchart of an output current detection method provided by an embodiment of the present invention;

[0035] Figure 6 This is a schematic diagram of the output current detection structure of the first switched capacitor converter provided in the embodiments of the present invention;

[0036] Figure 7 This is a schematic diagram of the output current detection structure of the second switched capacitor converter provided in the embodiments of the present invention;

[0037] Figure 8 This is a schematic diagram of the output current detection structure of the third switched capacitor converter provided in the embodiments of the present invention;

[0038] Figure 9 This is a schematic diagram of the output current detection structure of the fourth switched capacitor converter provided in the embodiments of the present invention;

[0039] Figure 10 This is a schematic diagram of the structure of an electronic device provided by an embodiment of the present invention. Detailed Implementation

[0040] To facilitate understanding of this application, a more detailed description is provided below with reference to the accompanying drawings and specific embodiments. It should be noted that when an element is described as being "fixed to" another element, it can be directly on the other element, or one or more intermediate elements may exist between them. When an element is described as being "connected" to another element, it can be directly connected to the other element, or one or more intermediate elements may exist between them. The terms "upper," "lower," "inner," "outer," "bottom," etc., used in this specification indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. Furthermore, the terms "first," "second," "third," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0041] Unless otherwise defined, all technical and scientific terms used in this specification have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. The term "and / or" as used in this specification includes any and all combinations of one or more of the associated listed items.

[0042] Furthermore, the technical features involved in the different embodiments of this application described below can be combined with each other as long as they do not conflict with each other.

[0043] The technical solutions in this application will be described below with reference to the accompanying drawings.

[0044] Figure 1 The diagram shown is of a conventional output current sensing structure for a switch-cap converter. This structure is existing technology and not the technical solution proposed in this application.

[0045] Reference Figure 1 Existing switched-capacitor converters mainly consist of a main circuit section and a control and detection section. The main circuit section includes: a power input terminal V... IN Switching transistors Q1, Q5, Q2, Q6, and leap capacitor C FLY Inductor L1, Inductor L2, Output capacitor C O and load resistance R LOAD The control and detection section includes a sampling resistor R connected in series in the output current path. CS The system includes a signal processing module 10 and a control module 20. The control module 20 contains an analog-to-digital conversion unit 210 and a data conversion unit 220.

[0046] The working principle of the existing switched capacitor converter is as follows: power supply voltage V IN Through the high-frequency switching action of switching transistors Q1, Q5, Q2, and Q6, and via the leap capacitor C... FLY Inductors L1 and L2 transfer energy to the output terminal, forming a stable output voltage V. OUT Supply load R LOAD Application. During the operation of the switched capacitor converter, four switching transistors switch according to a specific control strategy to achieve efficient energy transfer.

[0047] For output current detection, the existing technology uses the following method: [The text abruptly shifts to a seemingly unrelated topic about inductors L1 and L2, and output capacitor C.] O A sampling resistor R is connected in series in the circuit. CS When the current I OUT Flow through sampling resistor R CS At this time, a voltage drop proportional to the current will be generated across its terminals. This voltage signal is conditioned and amplified by the signal processing module 10, and then sent to the analog-to-digital conversion unit 210 (such as ADC) inside the control module 20 for analog-to-digital conversion. The converted digital signal is processed by the data conversion unit 220 to finally obtain the output current I. OUT The numerical value.

[0048] The signal processing module 10 in the prior art typically includes signal processing circuits such as operational amplifiers, and mainly performs the following functions: amplification of voltage signals: due to the sampling resistor R CS The resistance value is usually small (milliohm level), and the generated voltage signal is weak, requiring amplification; signal filtering: removes high-frequency switching noise and extracts the real current signal; level conversion: adjusts the signal to the acceptable input range of the ADC of the control module 20; common-mode rejection: reduces common-mode interference through differential structure; the analog-to-digital converter 210 in the control module 20 is responsible for converting the analog voltage signal into a digital signal, while the data conversion unit 220 is responsible for processing the digital signal into the actual output current value according to the preset algorithm.

[0049] Although the above scheme can achieve the detection of output current, it has several technical drawbacks: First, the series sampling resistor R CS This leads to additional power loss, especially in high-current applications. Even with a very small sampling resistor (such as 1mΩ), significant power loss (P=I) can occur under current conditions of tens of amperes. 2 Secondly, the heat generated by the sampling resistor requires additional heat dissipation design, increasing the heat dissipation area requirement; thirdly, additional sampling resistors, signal conditioning circuits, and other components significantly increase the board area occupied, reducing the power density of the power supply system; fourthly, the sampling resistor is located in a high-frequency switching circuit, making it susceptible to switching transients and electromagnetic interference (EMI), reducing sampling accuracy; finally, the temperature coefficient, parasitic inductance, and other parameters of the sampling resistor also affect measurement accuracy, especially in working environments with large temperature variations.

[0050] For modern power systems, especially those powering high-performance computing devices such as AI hardware, power density, efficiency, and accurate current monitoring are becoming increasingly important. With the trend towards low voltage and high current, the shortcomings of traditional sampling resistor solutions are becoming more apparent. For example, in a typical AI accelerator power supply scenario with 12V input and 1V / 100A output, sampling resistor solutions may result in an additional 1-3% efficiency loss, while also increasing the complexity of heat dissipation design by 30-50%.

[0051] Example of power loss calculation introduced by sampling resistor: Assuming a 1mΩ sampling resistor is used, at a current of 100A, the power loss is P = I. 2 R = 100 2 ×0.001 = 10W. The total output power of the power system is P = V × I = 1V × 100A = 100W. Therefore, the loss introduced by the sampling resistor accounts for 10 / 100 = 10%, significantly reducing system efficiency. Furthermore, a heat dissipation scheme needs to be designed for the additional 10W of heat, increasing system size and cost.

[0052] The signal processing flow of existing technical solutions is also relatively complex: first, the current signal must be converted into a voltage signal, then amplified and filtered, then converted into a digital signal by an ADC, and finally processed to obtain the output current value. This multi-stage signal processing not only increases design complexity but may also introduce various errors and delays, affecting the system's dynamic performance and protection response speed.

[0053] Reference Figure 2 The main circuit block diagram of the switched capacitor converter includes: input voltage terminal VIN, first main switch Q1, first synchronous rectifier switch Q5, second main switch Q2, second synchronous rectifier switch Q6, and leap capacitor C. FLY First inductor L1, second inductor L2, output capacitor C O and load resistance R LOAD . Figure 2 The key current paths are also marked, including the first inductor current I1, the second inductor current I2, and the output current I. OUT .

[0054] The switched-capacitor converter operates as follows: the first main switch Q1 and the second main switch Q2 act as the primary control switches, with equal duty cycles within a single switching cycle, and their switching signals are 180 degrees out of phase. The first synchronous rectifier switch Q5 and the first main switch Q1 have complementary conduction states, and the second synchronous rectifier switch Q6 and the second main switch Q2 have complementary conduction states. Through the coordinated operation of these four switches, efficient energy transfer from the input to the output is achieved.

[0055] In a switched-capacitor converter, the leap capacitor C FLY Acting as a charge pump, the switching transistor charges and discharges, forming a specific energy conversion path in conjunction with the two inductors L1 and L2. When the circuit is operating stably, the currents I1 and I2 in the two inductors L1 and L2 are directly related to the output current I. OUT That is, the output current I OUT It is equal to the sum of the currents of the two inductors, I1 and I2.

[0056] It should be noted that inductors L1 and L2 can be two windings of a coupled inductor, or they can be two independent inductors.

[0057] Depending on the duty cycle of the main switching transistor, the operating state of a switched capacitor converter can be divided into two cases: a duty cycle less than or equal to 50% and a duty cycle greater than 50%. (Refer to...) Figure 3 and Figure 4 The two scenarios will be analyzed in detail below.

[0058] like Figure 3As shown, when the duty cycle d of main switch Q1 and main switch Q2 is less than or equal to 50%, in one complete switching cycle T PRD The circuit goes through four different operating stages (I, II, III, IV). Figure 3 The control signals (PWM1, PWM5, PWM2, PWM6) of the four switching transistors and the current waveforms of each channel are shown, including the inductor currents i1(t) and i2(t), as well as the current combination i1(t) of the main switching transistor and the synchronous rectifier switching transistor. M1 (t) and i M2 (t).

[0059] When the duty cycle is less than or equal to 50%, a switching cycle can be divided into the following four stages:

[0060] Stage I (0~d): The first main switch Q1 is turned on, and the second synchronous rectifier switch Q6 is turned on;

[0061] Phase II (d~0.5): The first synchronous rectifier switch Q5 is turned on, and the second synchronous rectifier switch Q6 is turned on;

[0062] Phase III (0.5~0.5+d): The first synchronous rectifier switch Q5 is turned on, and the second main switch Q2 is turned on;

[0063] Phase IV (0.5+d~1): The first synchronous rectifier switch Q5 is turned on, and the second synchronous rectifier switch Q6 is turned on.

[0064] The currents flowing through switching transistors Q1, Q2, Q5, and Q6 during each switching stage are shown in the table below:

[0065]

[0066] Table 1

[0067] Analyze the current flowing through each switch in each stage:

[0068] First main switch Q1: conducts only in stage I, with a current of i1(t); Second main switch Q2: conducts only in stage III, with a current of i2(t); First synchronous rectifier switch Q5: conducts in stages II, III, and IV, with currents of i1(t), i1(t)+i2(t), and i1(t), respectively; Second synchronous rectifier switch Q6: conducts in stages I, II, and IV, with a current of i2(t).

[0069] If i M1 (t) represents the sum of the currents of the first main switch Q1 and the first synchronous rectifier switch Q5, then i M1(t) is i1(t) throughout the entire period, and only includes the i2(t) part in stage III. If i M2 (t) represents the sum of the currents of the second main switch Q2 and the second synchronous rectifier switch Q6, then i M2 (t) is i2(t) throughout the entire period.

[0070] Calculate the total current I flowing through the four switching transistors during one complete switching cycle. Q_all :I Q_all =I1+(1+d)I2, where I1 and I2 are the average values ​​of the two inductor currents i1(t) and i2(t) during the switching cycle, respectively, and d is the duty cycle of the switching cycle. Since the output current I... OUT =I1 + I2, and under steady-state conditions, when the duty cycle is less than or equal to 50%, the two inductor currents are equal: I1 = I2. Therefore, it can be derived that: I OUT =[2 / (2+d)]×I Q_all .

[0071] like Figure 4 As shown, when the duty cycle d of the main switching transistors Q1 and Q2 is greater than 50%, the circuit also experiences four different operating stages, but the duration of each stage is different from before:

[0072] Phase I (0~d-0.5): The first main switch Q1 and the second main switch Q2 are turned on simultaneously;

[0073] Phase II (d-0.5~0.5): The first main switch Q1 and the second synchronous rectifier switch Q6 are turned on;

[0074] Stage III (0.5~d): The first main switch Q1 and the second main switch Q2 are turned on;

[0075] Stage IV (d~1): The first synchronous rectifier switch Q5 and the second main switch Q2 are turned on.

[0076] The currents flowing through switching transistors Q1, Q2, Q5, and Q6 during each switching stage are shown in the table below:

[0077]

[0078] Table 2

[0079] Analyze the current flowing through each switch in each stage:

[0080] The first main switch Q1 is turned on in stages I, II and III, with currents of i1(t)+i2(t), i1(t) and i1(t)+i2(t) respectively;

[0081] The second main switch Q2 is turned on in stages I and III, with currents of i2(t) and i2(t) respectively.

[0082] The first synchronous rectifier switch Q5 is turned on in stage IV, and the current is i1(t) + i2(t);

[0083] The second synchronous rectifier switch Q6 is turned on in stage II, and the current is i2(t);

[0084] The total current I flowing through the four switching transistors Q_all Also: I Q_all =I1 + (1 + d)I2. Under steady-state conditions, when the duty cycle is greater than 50%, the inductor current satisfies the relationship: dI1 = (1 - d)I2, combined with the output current I... OUT =I1+I2, from which we can derive: I OUT =[1 / (1+d)] 2 )]×I Q_all .

[0085] Based on the above analysis, it can be concluded that there is a fixed mathematical relationship between the total average current IQ_all of the four switching transistors during the switching cycle and the output current IOUT in the switched capacitor converter. This relationship is directly related to the duty cycle d.

[0086] When the duty cycle d ≤ 0.5: I OUT =[2 / (2+d)]×I Q_all ;

[0087] When the duty cycle d > 0.5: I OUT =[1 / (1+d)] 2 )]×I Q_all .

[0088] The aforementioned mathematical relationship has significant physical implications. By measuring the total current of the four switching transistors and determining the duty cycle d, the actual output current of the switched capacitor converter can be accurately calculated without inserting an additional sampling resistor in the output circuit.

[0089] It is important to note that the inductor currents i1(t) and i2(t) in actual circuits typically exhibit a triangular wave shape and fluctuate. However, due to the usually high switching frequency (hundreds of kHz to several MHz), the filtering effect of the output filter capacitor CO reduces the output current I... OUT Since it is almost pure DC, the mathematical relationship based on the average value analysis described above has high accuracy in practical applications.

[0090] Similarly, if we only sample the currents of the first synchronous rectifier switch Q5 and the second synchronous rectifier switch Q6, we can obtain the following when the duty cycle is less than or equal to 50%:

[0091] I Q_56 = (1-d)I1+I2;

[0092] When the duty cycle is greater than 50%, then:

[0093] I Q_56 = (1-d)I1+2(1-d)I2.

[0094] Therefore, the output current I of the switched capacitor converter OUT The average switching cycle of the first synchronous rectifier switch Q5 and the second synchronous rectifier switch Q6 can be expressed as:

[0095] When the duty cycle d ≤ 0.5: I OUT =[2 / (2-d)]×I Q_all ;

[0096] When the duty cycle d > 0.5: I OUT =[1 / (1-d)] 2 )]×I Q_all .

[0097] pass Figure 2 , Figure 3 , Figure 4 Analysis reveals that the specific topology and switching timing of the switched-capacitor converter create a deterministic relationship between the switching transistor current and the output current. This embodiment utilizes a method combining switching transistor current information and duty cycle information to achieve accurate measurement of the output current without the need for traditional output current sampling resistors, providing a non-destructive output current detection scheme for switched-capacitor converters.

[0098] Reference Figure 5 This application provides a flowchart of an output current detection method, which is applied to a switched capacitor converter and mainly includes the following two steps:

[0099] Step S100: Obtain the average current of the switching transistor of the switched capacitor converter over N switching cycles;

[0100] Step S100, obtaining the average current of the switching transistor, is fundamental to the entire method. Unlike traditional current detection methods that use a sampling resistor in series in the output circuit, this method directly measures the current flowing through the switching transistor during its conduction period and then calculates its average value over N switching cycles using a specific method. Here, N is an integer greater than or equal to 1, typically taking values ​​such as 1, 2, 4, 8, or 16. Larger values ​​of N improve sampling accuracy and anti-interference capabilities but increase sampling delay. In practical applications, the value of N needs to be chosen by comprehensively considering the balance between accuracy requirements and system response speed.

[0101] There are several ways to obtain the switching current. In a preferred embodiment, the built-in current sensing function of the DrMOS (Driver-MOSFET integrated module) can be utilized. DrMOS, through single-die current mirror technology, can monitor the on-state current of the internal MOSFET in real time and output a signal proportional to the actual current via a dedicated pin. This signal is typically in current form and can be converted to a voltage signal via an external resistor before being sampled by the controller's analog-to-digital converter.

[0102] For sampling the switching transistor current, this method employs a switching cycle averaging sampling technique, which obtains the average value of the switching transistor current over N complete switching cycles. Switching cycle averaging sampling effectively suppresses interference from the switching frequency and its harmonic components, improving measurement accuracy. Specifically, a Σ / Δ analog-to-digital converter can be used to sample the switching transistor current signal at high frequency, followed by averaging in the digital domain.

[0103] If the switched capacitor converter contains multiple switching transistors (such as...) Figure 2 The four switching transistors shown (Q1, Q2, Q5, Q6) can be used to sample the average current of the transistors. The average current can be a specific combination of the currents from multiple transistors. For example, it can be the sum of the currents from all four transistors, or it can be the current from only the synchronous rectifier switching transistors (Q5, Q6). Different sampling methods correspond to different mathematical models, but the core principle remains the same.

[0104] Step S200: Obtain the output current of the switched capacitor converter based on the duty cycle and average current of the switching transistor.

[0105] The calculation of the output current is based on two key parameters: the duty cycle of the switching transistor and the average current obtained in step S100. The duty cycle refers to the proportion of the on-time of the main switching transistor in one switching cycle to the total cycle, usually represented by d, and its value ranges from 0 to 1.

[0106] In a switched-capacitor converter, the controller generates a PWM (Pulse Width Modulation) signal to drive the switching transistors. Therefore, the controller naturally knows the duty cycle value for each switching cycle. For N switching cycles, the average duty cycle d can be calculated and used as an input parameter for the mathematical model.

[0107] Based on the foregoing analysis, there is a deterministic mathematical relationship between the average current of the switching transistor and the output current, and this relationship is directly related to the duty cycle d. The specific relationship is as follows:

[0108] When the average duty cycle d ≤ 0.5: I OUT =[2 / (2+d)]×I Q_all ;

[0109] When the average duty cycle d > 0.5: I OUT =[1 / (1+d)]2 )]×I Q_all .

[0110] Among them, I OUT For the output current, I Q_all The average current of the switching transistor over N switching cycles.

[0111] If only the current of the synchronous rectifier switching transistors (Q5, Q6) is sampled, the mathematical relationship becomes:

[0112] When the average duty cycle d ≤ 0.5: I OUT =[2 / (2-d)]×I Q_all ;

[0113] When the average duty cycle d > 0.5: I OUT =[1 / (1-d)] 2 )]×I Q_all .

[0114] Among them, I Q_all For I Q_56 I Q_56 This represents the average current of the synchronous rectifier switch over N switching cycles.

[0115] The controller can calculate the accurate output current value using an appropriate formula based on the actual sampled switching current and the current average duty cycle d. Since the relationship between the switching current and the output current has been accurately established through a mathematical model, this method eliminates the need for an additional sampling resistor in the output circuit, thus avoiding the power loss problem of traditional solutions.

[0116] In some embodiments of this application, step S100 specifically includes the following steps:

[0117] Step S110: Within N switching cycles, obtain the current of the two main switching transistors and the two synchronous rectifier transistors.

[0118] exist Figure 6 In the diagram, we can see that the four switching transistors Q1, Q5, Q2, and Q6 are marked with current detection points IS1, IS5, IS2, and IS6, respectively. These detection points are used to acquire the current signal flowing through each switching transistor during its conduction period.

[0119] There are several possible implementation methods: for example, a trace can be led out from the source or drain terminal of the switching transistor, and the current can be directly measured by a current sensor (such as a Hall sensor, current transformer, etc.) in the signal processing module 10. Alternatively, the signal processing module can integrate a current detection circuit to separately detect the current of the high-side switching transistors (Q1 / Q2) and the low-side switching transistors (Q5 / Q6).

[0120] In this step, the current signals of the four switching transistors need to be acquired over N consecutive switching cycles. The choice of N affects the measurement accuracy and response speed. A larger N value can improve measurement accuracy but increase detection delay; a smaller N value is beneficial for fast response but may reduce accuracy. Depending on the specific application scenario, N can take values ​​such as 1, 2, 4, 8, 16, etc.

[0121] The current signal acquisition frequency needs to be significantly higher than the switching frequency to ensure that detailed changes in the current waveform can be captured. For example, for a switching frequency of 100 kHz, the current sampling frequency may need to reach 10 MHz or higher to ensure a sufficient number of sampling points within each switching cycle.

[0122] Step S120: In each switching cycle, the currents of the two main switching transistors and the two synchronous rectifier transistors are summed to obtain the total switching current.

[0123] In this step, the current signals from the four switching transistors need to be summed to form the total switching current. From Figure 6 It can be seen that the signals from the four current detection points (IS1, IS5, IS2, IS6) are introduced into the signal processing module 10 for summarization and processing.

[0124] The specific summarization methods may include the following: For example, within the signal processing module 10, the four current signals can be directly added together to form a total current signal through a current mirror or current adder circuit. Alternatively, the current signals of each switching transistor can be converted into voltage signals first, and then summed through an adder circuit composed of operational amplifiers.

[0125] exist Figure 6 In the illustrated embodiment, a hardware aggregation method is used. The current signals of the four switching transistors are introduced into the signal processing module 10, and are directly aggregated into a total current signal through internal circuitry. It is worth noting that due to the timing characteristics of the switching transistor currents (e.g., Figure 3 and Figure 4 As shown in the figure, only some of the switching transistors may be in the conducting state at different times, so the signal processing module 10 needs to have the ability to process discontinuous signals.

[0126] Step S130: Convert the total switching current into a voltage signal.

[0127] from Figure 6 As can be seen, the output of signal processing module 10 is connected to control module 20 through two ports, CS+ and CS-. This indicates that signal processing module 10 converts the summarized current signal into a differential voltage signal for subsequent analog-to-digital conversion processing.

[0128] Current-to-voltage conversion is typically achieved through a precision sampling resistor R. CSImplementation. Unlike traditional solutions, the sampling resistor here is not located in the power loop, but inside the signal processing circuit. Therefore, the power loss on the resistor is minimal and will not significantly affect the system efficiency.

[0129] The conversion circuit may contain the following functional blocks: converting a current signal into a voltage signal, with the conversion ratio determined by the sampling resistor R. CS Decision (V = I × R) CS The system includes a current-to-voltage converter; a differential amplifier that converts single-ended voltage signals into differential signals to improve anti-interference capabilities; a filter circuit that removes high-frequency noise and extracts the effective components of the current signal; and a level adjustment circuit that ensures the output signal is within the input range of the analog-to-digital converter 210, maximizing the utilization of the dynamic range of the analog-to-digital converter 210 and improving measurement accuracy. It should be noted that the current-to-voltage conversion process introduces a certain gain coefficient, which needs to be compensated for in subsequent data processing to ensure the accuracy of the final calculation results.

[0130] Step S140: Sample the voltage signal for N switching cycles to obtain the output data stream.

[0131] This step is completed by the analog-to-digital conversion unit 210 within the control module 20. For example... Figure 6 As shown, the CS+ and CS- differential signals are input to the analog-to-digital converter unit 210, where they are sampled at high speed and converted into digital signal streams.

[0132] Here, a Σ / Δ ADC (Sigma-Delta ADC) is preferred for sampling. Σ / Δ ADCs have the following characteristics: through oversampling and noise shaping techniques, they can achieve a high effective bit depth (e.g., 16-24 bits), meeting the requirements of precise current measurement; compared to other types of ADCs, Σ / Δ ADCs have better linearity, reducing measurement errors; their internal digital filters effectively suppress high-frequency noise, improving the signal-to-noise ratio; and they are particularly suitable for measuring relatively slowly changing signals such as current.

[0133] The working principle of a Σ / Δ ADC is to sample the input signal at a high frequency (far higher than the Nyquist sampling rate), push the quantization noise to the high-frequency region, and then remove the high-frequency noise through a digital filter to finally obtain a high-resolution digital output.

[0134] In this step, the Σ / ΔADC performs high-frequency sampling of the voltage signal and outputs a 1-bit high-speed data stream, where the density of "1"s is proportional to the amplitude of the input signal. This 1-bit data stream will be further processed in the next step.

[0135] It should be noted that the ADC that samples the average current during the switching cycle is not limited to Σ / Δ ADCs; it can also be replaced with other types of ADCs that can achieve the same purpose.

[0136] Step S150: Integrate the output data stream to obtain the average current.

[0137] This step is completed by the data conversion unit 220 within the control module 20. For example... Figure 6 As shown, the output of the analog-to-digital converter 210 is sent to the data conversion unit 220 for processing, and finally outputs a digital value representing the average current.

[0138] The key to integral processing is ensuring that the integration window is strictly aligned with the switching period. The reason is as follows: if a fixed integration time (TAVG) is used, and TAVG is not an integer multiple of the switching period (TSW), the integration result will not accurately represent the average value over an integer number of switching periods. Therefore, the data conversion unit 220 needs to be able to accurately track the switching period and extract the integration result at an integer number of switching periods.

[0139] It should also be noted that, in conjunction with the integrated switching transistor driver module, step S110 can also be implemented in the following ways, see reference. Figure 7 This application illustrates a specific implementation scheme for detecting the output current of a switched capacitor converter using two half-bridge DrMOS modules. Figure 7 The overall system structure is presented in detail, including the DrMOS module with integrated switching transistors, the connection structure, and the control module 20. The following will combine... Figure 7 A detailed explanation of DrMOS's built-in current mirror technology is provided.

[0140] like Figure 7 As shown, the four switching transistors in the switched-capacitor converter are integrated into two half-bridge DrMOS modules: DrMOS1 integrates the first main switch Q1 (D1) and the first synchronous rectifier switch Q5 (S1); DrMOS2 integrates the second main switch Q2 (D2) and the second synchronous rectifier switch Q6 (S2). Each DrMOS module contains the following key pins: PWM: used to receive pulse width modulation control signals; IMON: current monitoring output pin, outputting a mirror current proportional to the internal switch current; IREF: current reference setting pin, used to provide a common-mode voltage for IMON, facilitating the generation of negative current signals; other functional pins: such as GND (ground), power input, etc.

[0141] The DrMOS built-in current mirror technology works as follows: Next to each MOSFET, a mirror MOSFET with a very small area ratio (typically 1:500 to 1:2000) is integrated inside the DrMOS chip. This mirror MOSFET shares the same gate drive signal as the main MOSFET, and therefore has exactly the same switching characteristics.

[0142] Because the area of ​​a mirror MOSFET is much smaller than that of the main MOSFET, but both withstand the same gate-source voltage, the current flowing through the mirror MOSFET is strictly proportional to the current in the main MOSFET. This proportion is equal to the ratio of their areas. For example, if the area of ​​the mirror MOSFET is 1 / 1000 of that of the main MOSFET, then the mirror current is 1 / 1000 of the main current.

[0143] DrMOS integrates the main MOSFET and the mirror MOSFET on the same silicon chip, ensuring that they have the exact same temperature coefficient and process parameters, thereby achieving excellent temperature stability and accuracy.

[0144] In a half-bridge configuration, the high-side MOSFET (main switch) and the low-side MOSFET (synchronous rectifier switch) typically conduct in a complementary manner. The internal circuitry of DrMOS can automatically track which MOSFET is currently conducting and output the corresponding mirrored current to the IMON pin.

[0145] like Figure 7 As shown, the IMON pins of the two DrMOS modules are connected together through a shared sampling resistor R. CS This is converted into a voltage signal. This connection method enables the automatic summarization of the currents of the four switching transistors, forming a comprehensive signal representing the total switching transistor current.

[0146] Specific implementation details include: the mirrored currents output from the IMON pins of the two DrMOS transistors naturally converge and flow through the shared sampling resistor R. CS This generates a voltage signal proportional to the total mirror current. The generated voltage signal is input to the analog-to-digital converter unit 210 of the control module 20 via differential connections (CS+ and CS-). The control module 20 sends control signals to the two DrMOS modules through the PWM1 and PWM2 pins to control the switching states of the four switching transistors. The IREF pin of each DrMOS module is connected to a reference voltage source or resistor network to set the scaling factor of the current mirror, ensuring the accuracy of the measurement results.

[0147] It should also be noted that integrated switching current detection function can be not limited to DrMOS, but can also be other discrete circuits with switching current detection function, switching driver chips with integrated switching current detection function, etc.

[0148] In some other embodiments of this application, step S100 specifically includes the following steps:

[0149] Step S160: Obtain the current of the two synchronous rectifier diodes within N switching cycles.

[0150] like Figure 8 As shown, this embodiment only focuses on the current of the two synchronous rectifier switches Q5 and Q6, with corresponding current detection points IS5 and IS6. This scheme is compared to... Figure 6 The proposed solution has the following advantages: it reduces the number of current detection points and simplifies the complexity of the signal processing circuit; the synchronous rectifier switches Q5 and Q6 are low-side switches (source grounded), and compared with the high-side switches (Q1 and Q2), the low-side current detection technology is more mature and reliable and easier to implement.

[0151] exist Figure 8 In the circuit, the IS5 and IS6 current sensing points can be implemented in several ways: First, by inserting a small resistor at the source of the synchronous rectifier switch or utilizing the PCB trace resistance for current sensing, and then using a dedicated current sensing amplifier to obtain the current signal. Alternatively, a Hall effect sensor can be placed near the current path of the synchronous rectifier switch for non-contact current measurement.

[0152] Similar to the four-switch scheme, this step requires acquiring the current signal of the synchronous rectifier switch over N consecutive switching cycles. The choice of N still requires a trade-off between measurement accuracy and response speed, and values ​​such as 1, 2, 4, 8, and 16 are typically chosen.

[0153] Step S170: In each switching cycle, the current of the two synchronous rectifier diodes is summed to obtain the total switching current.

[0154] In this step, the current signals from the two synchronous rectifier switches Q5 and Q6 need to be combined to form the total switching current. From Figure 8 It can be seen that the signals from the two current detection points (IS5 and IS6) are introduced into the signal processing module 10 for summarization processing.

[0155] Compared to the four-switch scheme, the summing process in this embodiment is simpler, requiring only the processing of two current signals. The summing methods include: directly adding the two current signals to form a total current signal using a current mirror or current adder circuit. Alternatively, since Q5 and Q6 typically do not conduct simultaneously, a time-division multiplexing approach can be used to selectively process the current signal of the currently conducting synchronous rectifier switch according to the switching sequence.

[0156] according to Figure 3 and Figure 4As shown in the switching sequence, synchronous rectifier switches Q5 and Q6 will have different conduction states at different stages. The signal processing module 10 needs to be able to accurately capture these state changes to ensure that the summarized results can correctly reflect the current contribution of the two synchronous rectifier switches throughout the entire switching cycle.

[0157] Furthermore, since only the current of the synchronous rectifier switch is collected, and not the current of the main switch (Q1 and Q2), the subsequent mathematical model needs to be adjusted accordingly to accurately calculate the output current.

[0158] Step S130: Convert the total switching current into a voltage signal.

[0159] like Figure 8 As shown, the signal processing module 10 converts the aggregated current signal into a voltage signal through the two differential ports CS+ and CS-, and outputs it to the control module 20.

[0160] In the embodiment that only samples the current of the synchronous rectifier switch, the current-to-voltage conversion process is basically the same as the four-switch scheme, but the following characteristics may exist: Since only the current of the synchronous rectifier switch is processed, the sampling resistor and amplification circuit can be optimized for the characteristics of this current, improving the dynamic range and measurement accuracy of the signal; the sources of the synchronous rectifier switches Q5 and Q6 are usually grounded, which allows the current detection circuit to adopt a ground-referenced single-ended structure, simplifying the circuit design; although the current detection of the synchronous rectifier switch can theoretically adopt a single-ended structure, Figure 8 Differential signal (CS+ and CS-) output is still used, which helps to suppress common-mode noise and improve measurement accuracy.

[0161] The current-to-voltage conversion process also requires gain calibration and temperature compensation to ensure the accuracy and stability of the measurement results. Furthermore, the signal processing module 10 may also need to include a low-pass filter circuit to remove high-frequency switching noise and extract the effective components of the current signal.

[0162] Step S140: Sample the voltage signal for N switching cycles to obtain the output data stream.

[0163] This step is completed by the analog-to-digital conversion unit 210 within the control module 20. For example... Figure 8 As shown, the CS+ and CS- differential signals are input to the analog-to-digital converter unit 210, where they are sampled at high speed and converted into digital signal streams.

[0164] Similar to the four-switch scheme, this embodiment also preferably uses a Σ / Δ type ADC for sampling. The analog-to-digital converter 210 outputs a 1-bit high-speed data stream, where the density of "1"s is proportional to the amplitude of the input voltage signal. This 1-bit data stream will be further processed in the next step to convert it into a multi-bit resolution digital result.

[0165] It should be noted that since this embodiment only measures the current of the synchronous rectifier switch, its waveform characteristics are different from those of the four-switch scheme. The ADC parameter settings (such as sampling rate, filter bandwidth, etc.) may need to be adjusted accordingly to optimize the measurement results.

[0166] Step S150: Integrate the output data stream to obtain the average current.

[0167] This step is completed by the data conversion unit 220 within the control module 20. For example... Figure 8 As shown, the output of the analog-to-digital converter 210 is sent to the data conversion unit 220 for processing, and the final output is a digital value representing the average current. The integration process is similar to that of the four-switch scheme.

[0168] The key to integral processing is ensuring that the integration window is strictly aligned with the switching period. The reason is as follows: if a fixed integration time (TAVG) is used, and TAVG is not an integer multiple of the switching period (TSW), the integration result will not accurately represent the average value over an integer number of switching periods. Therefore, the data conversion unit 220 needs to be able to accurately track the switching period and extract the integration result at an integer number of switching periods.

[0169] It should also be noted that, in conjunction with the integrated switching transistor driver module, step S160 can also be implemented in the following ways, see reference. Figure 9 This application illustrates a specific implementation scheme for synchronous rectifier switch current detection using two half-bridge DrMOS modules. Figure 7 The embodiments shown are different. Figure 9 The implementation method focuses on the current sensing of the synchronous rectifier switches (Q5 and Q6), and utilizes DrMOS's built-in low-side current mirror technology to achieve high-precision, lossless current sensing.

[0170] like Figure 9 As shown, the switched-capacitor converter is constructed using two half-bridge DrMOS modules: DrMOS1 integrates the first main switch Q1 (D1) and the first synchronous rectifier switch Q5 (S1); DrMOS2 integrates the second main switch Q2 (D2) and the second synchronous rectifier switch Q6 (S2). Key connections and components of the system include: input voltage terminal V... IN Connected to two DrMOS modules, leap capacitor C FLYConnected between the two half-bridges, the first inductor L1 and the second inductor L2 are respectively connected to the output capacitor C. O and load R LOAD The control module 20 sends control signals to the DrMOS module through the PWM1 and PWM2 pins. The IMON pin of the DrMOS outputs a mirrored current, which is connected to the sampling resistor R. CS The CS+ and CS- differential signals are connected to the analog-to-digital conversion unit 210 of the control module 20.

[0171] and Figure 7 The key difference is that, Figure 9 The DrMOS in the configuration is set to output only the current information of the synchronous rectifier switch (low-side MOSFET), excluding the current information of the main switch (high-side MOSFET). The first and second synchronous rectifier switches are integrated into a second switch driver module, and current information is obtained through the module's internal current mirror. Figure 9 In one embodiment, this technique is achieved using a low-side current mirror of DrMOS.

[0172] The DrMOS low-side current mirror works as follows: DrMOS integrates a scaled-down mirror MOSFET within the low-side MOSFET (synchronous rectifier switch) chip. This mirror MOSFET shares the same gate drive signal as the main MOSFET and has identical switching characteristics.

[0173] The area of ​​a mirror MOSFET is typically 1 / 500 to 1 / 2000 of that of the main MOSFET, so the current flowing through the mirror MOSFET is precisely proportional to that of the main MOSFET.

[0174] Because the mirror MOSFET and the main MOSFET are integrated on the same silicon chip, they have the exact same temperature coefficient, ensuring a stable proportional relationship when the temperature changes.

[0175] DrMOS typically allows configuration to select the output current information of the low-side MOSFET, high-side MOSFET, or both. Figure 9 In this embodiment, DrMOS is configured to output only the current information of the low-side MOSFET (synchronous rectifier switch).

[0176] exist Figure 9 In the implementation shown, the IMON pins of the two DrMOS modules are connected together, and the mirrored current of the output flows through a shared sampling resistor R. CS The voltage is converted into differential voltage signals (CS+ and CS-) and input to the control module 20.

[0177] Compared to detecting the current of all four switching transistors, detecting only the current of the synchronous rectifier switch has the following significant advantages: Current sensing technology for the low-side MOSFET is more mature and much easier to implement than for the high-side MOSFET. The high-side MOSFET is at a floating potential, making current sensing more complex. Low-side current mirror technology is more reliable and less affected by factors such as temperature and voltage fluctuations. Almost all DrMOS products support low-side current sensing, while some earlier or lower-cost products may not support high-side current sensing. The low-side MOSFET's source is grounded, resulting in lower common-mode noise in the current sensing signal and generally higher signal quality.

[0178] In some embodiments of this application, step S150 specifically includes the following steps:

[0179] Step S151: Integrate the output data stream.

[0180] In this step, "integration" refers to the accumulation of the data stream output from the analog-to-digital converter 210 (typically a Σ / Δ ADC). The specific details are as follows:

[0181] A Σ / Δ ADC outputs a high-speed 1-bit data stream consisting of "0"s and "1"s. The density of "1"s in this data stream (i.e., the frequency of "1"s) is proportional to the amplitude of the input analog signal. For example, when the input signal amplitude is 80% of full scale, approximately 80% of the bits in the data stream will be "1".

[0182] In the digital domain, "integration" actually refers to counting and accumulating the "1s" in a data stream. This can be achieved using a digital accumulator, which continuously accumulates the input 1-bit data.

[0183] In hardware implementation, a binary counter can be used to record the total number of "1"s in the data stream; in software implementation, a variable can be used to continuously accumulate the value (0 or 1) of each sampling point.

[0184] The bit width of the accumulator needs to be determined based on the expected integration time and target resolution to avoid overflow. For example, for a sampling rate of 20MHz and an integration time of 10ms, the maximum accumulated value can reach 200,000, requiring at least an 18-bit accumulator.

[0185] The integration process itself has low-pass filtering characteristics, which can effectively suppress high-frequency noise. The longer the integration time, the better the filtering effect, but it will increase the system response delay.

[0186] Step S152: When the integration time reaches N switching cycles, stop the integration and obtain the average voltage.

[0187] To avoid errors caused by the mismatch between the integration time and the switching period, the intercept time of the integration result should be an integer multiple of the switching period. This is because the current signal in the switching power supply has significant periodicity, and integration with a non-integer period will lead to inaccurate measurement results.

[0188] The system accurately calculates the number of switching cycles by tracking the PWM signal. The integration process stops when N complete switching cycles are detected. The choice of N needs to balance measurement accuracy and response speed, and is typically 1, 2, 4, or 8.

[0189] To achieve precise synchronization, the controller needs to accurately track the switching cycle boundaries, which can be achieved by: using the cycle overflow flag of the PWM counter; monitoring the rising or falling edge of the PWM signal; or using a dedicated cycle synchronization circuit.

[0190] When the preset N cycles are reached, the system records the current accumulator value, which represents the average voltage over N complete switching cycles.

[0191] Assuming the switching frequency is fsw and the switching period is TSW = 1 / fsw, then the integration time Tint = N × TSW. For example, for a switching frequency of 100kHz and N = 4, the integration time is 40μs.

[0192] Step S153: Convert the average voltage to the average current.

[0193] The average voltage value is converted into the required current value to complete the entire measurement process. Specifically, there is a deterministic conversion relationship between the average voltage and the switching transistor current, mainly determined by the following factors:

[0194] Current sampling resistor R CS Resistance value: V = I × R CS ;

[0195] The scaling factor of the DrMOS internal current mirror is typically 1:500 to 1:2000;

[0196] Gain of signal processing circuits: such as signal amplification or attenuation stages.

[0197] Assuming the current mirror ratio is 1 and the sampling resistor is R CS If the signal processing gain is G, then: I Q_all = (Average voltage / G) / R CS ×K where, I Q_all This represents the actual average current of the switching transistor. For example, if the current mirror ratio is 1:1000, the sampling resistor is 10Ω, the signal processing gain is 2, and the average voltage is 0.8V, then: I Q_all =(0.8V / 2) / 10Ω×1000=40A.

[0198] In some embodiments of this application, step S200 specifically includes the following steps:

[0199] Step S210: Obtain the duty cycle of the main switch transistor in N switching cycles.

[0200] Duty cycle is a key parameter in switching power supply control, defined as the ratio of the on-time of the switching transistor to the switching cycle. This step aims to obtain the real-time duty cycle values ​​of the main switching transistors (Q1 and Q2) over N consecutive switching cycles. The specific details are as follows:

[0201] Duty cycle d = conduction time (ton) / switching period (Tsw), with a value ranging from 0 to 1 (or 0% to 100%). In switched-capacitor converters, the duty cycles of the main switches Q1 and Q2 are usually equal, but they are staggered by 180 degrees in phase. The duty cycle directly determines the proportion of energy transfer and is a key parameter that determines the output voltage and current.

[0202] When the controller generates a PWM signal, the duty cycle value needs to be set. Therefore, the duty cycle value can be read directly from the configuration register of the PWM module; or the duty cycle can be calculated by measuring the ratio of the duration of the PWM high level to the total period; or the duty cycle can be calculated by detecting the rising and falling edges of the PWM signal and calculating the ratio of the time difference between them to the period.

[0203] Step S220: Obtain the average duty cycle based on the N duty cycles of the main switch transistor.

[0204] The most common method is a simple arithmetic mean, which adds up the N duty cycle values ​​and then divides by N. For specific applications, a weighted average can be used, assigning different weights according to the importance of different periods. A moving average can also be used to continuously update the average value, reduce the influence of a single value, and improve stability.

[0205] Step S230: Obtain the output current based on the average duty cycle and average current.

[0206] In some embodiments of this application, step S230 specifically includes the following steps:

[0207] Step S231: Determine whether the average duty cycle is greater than 0.5.

[0208] It is necessary to determine whether the average duty cycle d exceeds the 0.5 (50%) threshold. The result of this determination determines which mathematical formula to use to calculate the output current. The determination must also consider accuracy issues. A comparator with hysteresis can be used to avoid repeated switching around 0.5. If the average duty cycle is greater than 0.5, then proceed to step S232; if the average duty cycle is less than or equal to 0.5, then proceed to step S233.

[0209] Step S232: Using a preset first calculation formula, the output current is obtained based on the average duty cycle and average current.

[0210] When sampling the current of four switching transistors, i.e., the average current is the sum of the currents of the two main switching transistors and the two synchronous rectifier switching transistors, and the average value over N switching cycles, the output current is obtained according to the following formula:

[0211] I OUT =[1 / (1+d)] 2 )]×I Q_all ;

[0212] When sampling the currents of the two synchronous rectifier switches, i.e., when the average current is the sum of the currents of the two synchronous rectifier switches over N switching cycles, the output current is obtained according to the following formula:

[0213] I OUT =[1 / (1-d)] 2 )]×I Q_all ;

[0214] Among them, I OUT Where d is the output current, d is the average duty cycle, and I is the output current. Q_all This represents the average current value.

[0215] Step S233: Using a preset second calculation formula, the output current is obtained based on the average duty cycle and average current.

[0216] When sampling the current of four switching transistors, i.e., the average current is the sum of the currents of the two main switching transistors and the two synchronous rectifier switching transistors, and the average value over N switching cycles, the output current is obtained according to the following formula:

[0217] I OUT =[2 / (2+d)]×I Q_all ;

[0218] When sampling the currents of the two synchronous rectifier switches, i.e., when the average current is the sum of the currents of the two synchronous rectifier switches over N switching cycles, the output current is obtained according to the following formula:

[0219] I OUT =[2 / (2-d)]×I Q_all ;

[0220] Among them, I OUT Where d is the output current, d is the average duty cycle, and I is the output current. Q_all This represents the average current value.

[0221] Unlike existing technologies, the embodiments of the present invention target switched capacitor converters. Based on the relationship between the switching transistor current and the output current, the output current is obtained by detecting the switching transistor current and the corresponding duty cycle of the switching transistor. This avoids the need to add an additional sampling resistor in the output circuit, thereby reducing system losses, reducing the heat dissipation area and increasing the power density of the switched capacitor converter. It also avoids the possibility that adding a sampling resistor in the high-frequency switching circuit will easily affect the sampling results due to switching noise interference.

[0222] The present invention also provides an electronic device based on the above-described output current detection method, the schematic diagram of which is shown below. Figure 10 As shown, the electronic device 700 includes:

[0223] One or more processors 701, a network interface 702, and a memory 703, Figure 10 The example consists of a processor 701, a network interface 702, and a memory 703.

[0224] The network interface 702 is communicatively connected to the corresponding processor 701. The processor 701 and the memory 702 can be connected via a bus or other means. Figure 10 Taking the example of a connection between China and Israel via a bus.

[0225] Network interface 702 is used to establish communication connections between processor 701 and other external devices, including the following types: RJ-45 interface, SC fiber optic interface, AUI interface, FDDI interface and Console interface.

[0226] The memory 703, as a non-volatile computer-readable storage medium, can be used to store non-volatile software programs, non-volatile computer-executable programs, and modules. The processor 701 executes various functional applications and data processing of the electronic device by running the non-volatile software programs, instructions, and units stored in the memory 703, thereby implementing the output current detection method of the above-described method embodiment.

[0227] Memory 103 may include a program storage area and a data storage area. The program storage area may store the operating system and applications required for at least one function; the data storage area may store data created based on the use of the electronic device. Furthermore, memory 703 may include high-speed random access memory and may also include non-volatile memory, such as at least one disk storage device, flash memory device, or other non-volatile solid-state storage device. In some embodiments, memory 703 may optionally include memory remotely located relative to processor 701, and these remote memories can be connected to the electronic device via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.

[0228] The one or more units are stored in the memory 703. When executed by one or more processors 701, they perform the output current detection method in any of the above method embodiments, for example, the method described above. Figure 5 The method steps S100 to S200.

[0229] The aforementioned electronic device can execute the output current detection method provided in the embodiments of the present invention, and has the corresponding program modules and beneficial effects for executing the method. Technical details not described in detail in the embodiments of the electronic device can be found in the output current detection method provided in the embodiments of the present invention.

[0230] This invention also provides a non-volatile computer-readable storage medium, which may be included in the device described in the above embodiments; or it may exist independently and not assembled into the device. The non-volatile computer-readable storage medium carries one or more programs, which, when executed, implement the output current detection method of this disclosure.

[0231] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and not to limit them; under the concept of this application, the technical features of the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations of different aspects of this application as described above. For the sake of brevity, they are not provided in detail; although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or make equivalent substitutions for some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. An output current detection method, applied to a switched capacitor converter, characterized in that, The switched-capacitor converter includes an input voltage terminal, a first main switch, a first synchronous rectifier switch, a second main switch, a second synchronous rectifier switch, a flying capacitor, a first inductor, a second inductor, and an output capacitor. The drain of the first main switch is connected to the positive terminal of the input voltage terminal. The source of the first main switch is connected to the first terminal of the flying capacitor and the drain of the second main switch. The source of the second main switch is connected to the drain of the second synchronous rectifier switch and the first terminal of the second inductor. The second terminal of the flying capacitor is connected to the drain of the first synchronous rectifier switch and the first terminal of the first inductor. The second terminal of the first inductor is connected to the second terminal of the second inductor, the first terminal of the output capacitor, and the first terminal of the load. The sources of the first and second synchronous rectifier switches, the second terminal of the output capacitor, and the negative terminal of the input voltage terminal are connected to a reference ground. The output current of the switched-capacitor converter is equal to the sum of the current of the first inductor and the current of the second inductor. The first main switch and the second main switch have the same duty cycle in one switching cycle and their switching signals are phase-shifted by 180 degrees. The conduction states of the first synchronous rectifier switch and the first main switch are complementary, and the conduction states of the second synchronous rectifier switch and the second main switch are complementary. The method includes: Obtain the average current of the switching transistor of the switched capacitor converter over N switching cycles; Obtain the duty cycle of the main switch transistor during the N switching cycles, and obtain the average duty cycle based on the N duty cycles of the main switch transistor; Determine whether the average duty cycle is greater than 0.5; If so, the preset first calculation formula is used to obtain the output current based on the average duty cycle and the average current; If not, the preset second calculation formula is used to obtain the output current based on the average duty cycle and the average current; When the average current is the sum of the currents of the first main switch, the second main switch, the first synchronous rectifier switch, and the second synchronous rectifier switch over the N switching cycles, The first calculation formula is: I OUT = [1 / (1+d²)] × I Q_all ; The second calculation formula is: I OUT = [2 / (2+d)] × I Q_all ; When the average current is the sum of the currents of the first synchronous rectifier switch and the second synchronous rectifier switch over the N switching cycles, The first calculation formula is: I OUT = [1 / (1-d²)] × I Q_all ; The second calculation formula is: I OUT = [2 / (2-d)] × I Q_all ; Among them, I OUT The output current is d, the average duty cycle is I. Q_all The average current value is given.

2. The method according to claim 1, characterized in that, The step of obtaining the average current of the switching transistor of the switched capacitor converter over N switching cycles includes: During the N switching cycles, the currents of the two main switching transistors and the two synchronous rectifier transistors are obtained; During each switching cycle, the currents of the two main switching transistors and the two synchronous rectifier transistors are summed to obtain the total switching current. The total current of the switch is converted into a voltage signal; The voltage signal of the N switching cycles is sampled to obtain the output data stream; The average current is obtained by integrating the output data stream.

3. The method according to claim 1, characterized in that, The step of obtaining the average current of the switching transistor of the switched capacitor converter over N switching cycles includes: During the N switching cycles, the current of the two synchronous rectifier diodes is obtained; During each switching cycle, the currents of the two synchronous rectifier diodes are summed to obtain the total switching current. The total current of the switch is converted into a voltage signal; The voltage signal of the N switching cycles is sampled to obtain the output data stream; The average current is obtained by integrating the output data stream.

4. The method according to claim 2 or 3, characterized in that, The step of integrating the output data stream to obtain the average current includes: Integrate the output data stream; When the integration time reaches the N switching cycles, integration is stopped, and the average voltage is obtained. The average voltage is converted into the average current.

5. The method according to claim 4, characterized in that, The two main switching transistors include a first main switching transistor and a second main switching transistor; The first main switch and the second main switch are integrated in the first switch driver integrated module. The current of the first main switch and the current of the second main switch are obtained through the internal current mirror of the first switch driver integrated module.

6. The method according to claim 4, characterized in that, The two synchronous rectifier tubes include a first synchronous rectifier tube and a second synchronous rectifier tube; The first synchronous rectifier and the second synchronous rectifier are integrated in the second switch driver integrated module. The current of the first synchronous rectifier and the current of the second synchronous rectifier are obtained through the internal current mirror of the second switch driver integrated module.

7. An electronic device, characterized in that, include: At least one processor; At least one network interface, which is communicatively connected to a corresponding processor; as well as, A memory communicatively connected to the at least one processor; wherein, The network interface is used to establish communication connections between the processor and other external devices; The memory stores instructions that can be executed by the at least one processor to enable the at least one processor to perform an output current detection method as described in any one of claims 1-6.

8. A non-volatile computer storage medium, characterized in that, The computer storage medium stores computer-executable instructions that are executed by one or more processors, causing the one or more processors to perform an output current detection method as described in any one of claims 1-6.

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