An integrated circuit testing method and system

Abstract

This invention relates to the field of circuit testing technology, and more particularly to an integrated circuit testing method and system. The method includes the following steps: acquiring integrated circuit structure data; screening key nodes in the integrated circuit structure data to obtain power supply pins and input pins; setting static bias voltages for the power supply pins and input pins to generate static bias voltage setting data; acquiring bias voltages from the static bias voltage setting data to obtain standard integrated circuit bias voltage acquisition data; superimposing low-amplitude, high-frequency noise sources onto the standard integrated circuit bias voltage acquisition data to obtain voltage acquisition noise data; and simulating power supply interference using the voltage acquisition noise data on the standard integrated circuit bias voltage acquisition data to generate circuit power supply interference simulation data. This invention improves the accuracy of circuit testing through key node screening, parasitic effect assessment, multi-dimensional data analysis, and cloud visualization.

Description

Technical Field

[0001] This invention relates to the field of circuit testing technology, and in particular to an integrated circuit testing method and system. Background Technology

[0002] Early IC testing relied primarily on manual operation and simple functional testers, capable of detecting basic open and short circuits. This approach was suitable for smaller, less complex ICs. However, with the advent of large-scale integrated circuits (LSI) and very large-scale integrated circuits (VLSI), traditional manual testing became insufficient. Automated test equipment (ATE) began to be widely used, automating IC testing and improving efficiency and accuracy. ATE can comprehensively check the chip's functionality, timing, and electrical parameters using pre-written test programs. However, as process nodes continue to shrink, IC design complexity increases significantly, posing new challenges to ATE testing time and cost. In recent years, design-based test (DFT) techniques have matured, such as scan chain testing, built-in self-test (BIST), and logic diagnostics. These techniques reduce testing complexity and cost by embedding test structures during the design phase. However, current conventional IC testing methods struggle to fully simulate power supply noise and interference effects, lack sufficient coverage of real-world operating environments, and fail to accurately assess the impact of parasitic responses on circuit performance, resulting in lower accuracy in circuit testing. Summary of the Invention

[0003] Therefore, it is necessary to provide an integrated circuit testing method and system to solve at least one of the above-mentioned technical problems.

[0004] To achieve the above objectives, an integrated circuit testing method is provided, the method comprising the following steps:

[0005] Step S1: Obtain integrated circuit structure data; perform key node screening on the integrated circuit structure data to obtain power supply pins and input pins; set static bias voltages on the power supply pins and input pins to generate static bias voltage setting data; collect bias voltages from the static bias voltage setting data to obtain standard integrated circuit bias voltage collection data.

[0006] Step S2: Superimpose low-amplitude, high-frequency noise sources onto the standard integrated circuit bias voltage acquisition data to obtain voltage acquisition noise data; simulate power supply interference on the standard integrated circuit bias voltage acquisition data using the voltage acquisition noise data to generate circuit power supply interference simulation data; calculate the circuit parasitic index on the circuit power supply interference simulation data to obtain the actual parasitic data of the integrated circuit.

[0007] Step S3: Perform leakage current testing on the standard integrated circuit bias voltage acquisition data based on the actual parasitic data of the integrated circuit to obtain the integrated circuit leakage current data; perform extreme temperature testing on the integrated circuit using the integrated circuit leakage current data to obtain the integrated circuit extreme temperature test data; mark the integrated circuit batch based on the actual parasitic data of the integrated circuit, the integrated circuit leakage current data, and the circuit extreme temperature test data to generate Class I integrated circuit marking data and Class II integrated circuit marking data.

[0008] Step S4: Upload the Class I and Class II integrated circuit tagging data to the cloud platform for data visualization, generate an integrated circuit test storage report, and execute the complete integrated circuit test job.

[0009] This invention focuses testing on power and input pins through key node screening, avoiding interference from unnecessary nodes and improving testing efficiency and resource utilization. Static bias voltage settings ensure data uniformity and standardization, laying the foundation for the accuracy and comparability of subsequent test results. The generated standard bias voltage data can be used in various test scenarios, such as interference simulation and leakage current testing, enhancing test applicability. By superimposing low-amplitude, high-frequency noise, the operating state of integrated circuits in complex electromagnetic environments is realistically reproduced, improving the comprehensiveness of the test. Power interference simulation data provides a basis for evaluating the impact of power fluctuations on circuit performance, helping to optimize circuit design. Parasitic index calculation quantifies the impact of parasitic effects, providing data support for circuit improvement and defect localization, especially suitable for problem diagnosis in high-density circuit designs. Leakage current and extreme temperature tests based on parasitic data provide in-depth understanding of the performance boundaries and potential risks of integrated circuits. Comprehensive analysis combining parasitic data, leakage current data, and extreme temperature data provides a panoramic view of integrated circuit performance. Intelligent labeling of Class I and Class II products significantly improves the efficiency of product classification and quality control while reducing the error rate of human intervention. Batch tagging data supports traceability in the production chain, providing a basis for subsequent improvements and product grading. Visualization after uploading to the cloud platform facilitates rapid understanding and evaluation of test results, providing an intuitive reference for decision-making. Cloud storage and report generation support cross-departmental collaboration, improving data sharing efficiency and reducing the risk of information silos. The stored reports include multi-dimensional test results and tagging data, providing rich evidence for subsequent design optimization and test process improvement. Cloud visualization of data enhances the transparency of the entire testing process, contributing to quality control and building customer trust. Therefore, this invention improves the accuracy of circuit testing through key node screening, parasitic effect assessment, multi-dimensional data analysis, and cloud visualization.

[0010] Preferably, step S1 includes the following steps:

[0011] Step S11: Obtain integrated circuit structure data;

[0012] Step S12: Perform circuit pin analysis on the integrated circuit structure data to generate integrated circuit pin data; based on the integrated circuit pin data, perform key node screening on the integrated circuit structure data to obtain the key nodes of the integrated circuit, wherein the key nodes of the integrated circuit include power supply pins and input pins;

[0013] Step S13: Set the static bias voltage for the power supply pin and input pin to generate static bias voltage setting data; use a voltage sensor to acquire the bias voltage from the static bias voltage setting data to obtain integrated circuit bias voltage acquisition data;

[0014] Step S14: Perform data preprocessing on the integrated circuit bias voltage acquisition data to generate standard integrated circuit bias voltage acquisition data. The data preprocessing includes data cleaning, data denoising, data missing value filling, and data standardization.

[0015] This invention ensures the accuracy of circuit design by performing detailed circuit pin analysis and key node screening on integrated circuit structure data. Particularly in identifying critical nodes such as power supply and input pins, it effectively aids in subsequent circuit functional analysis and optimization. By setting static bias voltages for power supply and input pins and acquiring voltage data using voltage sensors, it helps ensure that the electrical stability and voltage requirements of the integrated circuit design meet system needs, avoiding circuit instability or failures caused by improper voltage. Data preprocessing (including data cleaning, noise reduction, missing value imputation, and standardization) effectively improves the quality of acquired data, removes noise, corrects missing parts, and ensures the accuracy and reliability of subsequent analysis. This is crucial for further circuit performance evaluation, fault detection, and optimization. By processing and standardizing the integrated circuit bias voltage acquisition data, high-quality foundational data can be provided for subsequent circuit functional evaluation, performance optimization, and fault tolerance analysis, further supporting circuit design verification and improvement.

[0016] Preferably, setting the static bias voltage for the power supply pins and input pins includes:

[0017] Define the operating voltage range for the power supply pins to obtain the operating voltage range of the power supply pins; define the normal logic level range for the input pins to obtain the normal logic level range of the input pins.

[0018] Based on the operating voltage range of the power supply pins and the normal logic level range of the input pins, the bias voltage range of key nodes of the integrated circuit is extended to generate bias voltage range extension data; based on the bias voltage range extension data, the test voltage step setting of key nodes of the integrated circuit is performed to generate a serialized list of test points.

[0019] By setting the static bias voltage of the power supply pin and input pin according to the serialized list of test points based on the preset stabilization time, static bias voltage setting data is generated.

[0020] This invention defines the operating voltage range and normal logic level range for power supply pins and input pins respectively, ensuring that the circuit's voltage requirements match the actual power output and input signal logic requirements, thus guaranteeing the circuit's normal operation. Based on the operating voltage range of the power supply pins and the normal logic level range of the input pins, the bias voltage range of key nodes in the integrated circuit is extended to ensure that the bias voltage covers the possible operating states of the circuit. This extension improves the circuit's adaptability to different operating environments, reduces circuit failures caused by voltage instability, and the generated test voltage step settings and serialization list provide orderly and accurate test steps for subsequent tests, ensuring sufficient voltage verification at different test points. This helps improve the comprehensiveness and systematic nature of the test, reducing omissions and errors. By setting static bias voltages for power supply pins and input pins within a preset stabilization time, the electrical stability of the circuit in a real operating environment can be simulated, ensuring that the circuit will not fail due to voltage instability during long-term use. The static bias voltage setting data provides the basis for subsequent circuit optimization and debugging. Through systematic voltage ranges and test settings, engineers can quickly locate voltage-related problems in the circuit, supporting the improvement of circuit performance.

[0021] Preferably, step S2 includes the following steps:

[0022] Step S21: Superimpose low-amplitude high-frequency noise sources on the standard integrated circuit bias voltage acquisition data to obtain voltage acquisition noise data; simulate power supply interference on the standard integrated circuit bias voltage acquisition data using the voltage acquisition noise data to generate circuit power supply interference simulation data.

[0023] Step S22: Use an oscilloscope to measure the output waveform of the circuit power supply interference simulation data, and perform abnormal output response discrimination on the measured output waveform to obtain an abnormal output response discrimination strategy;

[0024] Step S23: Adjust the signal frequency of the circuit power supply interference simulation data according to the abnormal output response discrimination strategy to generate a circuit power supply interference adjustment signal;

[0025] Step S24: Perform cyclic power supply interference simulation on the standard integrated circuit bias voltage acquisition data through the circuit power supply interference adjustment signal to generate cyclic simulation data of circuit power supply interference; calculate the circuit parasitic index on the cyclic simulation data of circuit power supply interference to obtain the actual parasitic data of the integrated circuit.

[0026] This invention effectively recreates the power interference conditions faced by integrated circuits in real-world operating environments through the superposition of low-amplitude, high-frequency noise sources and power interference simulation. This simulation helps to assess the circuit's anti-interference capability in complex environments in advance, thereby optimizing the design and improving circuit robustness. Measuring the output waveform with an oscilloscope and identifying abnormal output responses allows for rapid identification of abnormal circuit behavior (such as waveform distortion or functional abnormalities) under power interference. The abnormal output response identification strategy provides a clear direction for further circuit optimization and debugging. Signal frequency adjustment, through adaptive optimization of interference characteristics, generates a circuit power interference adjustment signal, which helps enhance the circuit's adaptability to different interference frequencies, thereby improving the circuit's performance stability under various interference scenarios. Cyclic power interference simulation comprehensively tests the circuit's performance under long-term interference environments, ensuring the design has long-term stability and reliability, and avoiding functional failures or malfunctions caused by occasional interference. Circuit parasitic index calculation can quantitatively analyze the actual impact of interference on the circuit, providing intuitive data support. This parasitic data provides a scientific basis for optimizing circuit layout, design, or material selection, thereby reducing the potential risks brought by parasitic effects.

[0027] Preferably, the abnormal output response discrimination of the measured output waveform includes:

[0028] The average value and standard deviation of the measured output waveform are calculated to obtain the average value and standard deviation of the output waveform; based on the average value and standard deviation of the output waveform, the measured output waveform is subjected to waveform amplitude anomaly discrimination to generate waveform amplitude anomaly discrimination data.

[0029] Perform waveform timing analysis on the measured output waveform to generate output waveform timing data; based on the output waveform timing data, perform time delay over-limit judgment on the measured output waveform to generate waveform timing anomaly judgment data;

[0030] The measured output waveform is analyzed to generate output waveform shape data; based on the output waveform shape data, the measured output waveform is subjected to waveform shape distortion discrimination to generate waveform shape anomaly discrimination data.

[0031] Based on waveform amplitude anomaly discrimination data, waveform timing anomaly discrimination data, and waveform morphology anomaly discrimination data, abnormal output response discrimination is performed on the measured output waveform to obtain an abnormal output response discrimination strategy.

[0032] This invention calculates the average value and standard deviation of waveforms to quickly obtain the statistical characteristics of waveform amplitude, accurately determining whether the waveform amplitude is abnormal, providing a reliable data foundation for anomaly identification. Waveform timing analysis and waveform shape analysis cover the characteristics of waveforms in both time and shape dimensions, ensuring that no abnormal factors are overlooked in the discrimination process, further improving the overall accuracy and comprehensiveness of the discrimination. Amplitude statistical characteristics (average value and standard deviation) can quickly detect abnormal situations where voltage amplitude exceeds the normal range. Waveform timing analysis and delay discrimination can identify delay problems in signal transmission, which is particularly critical for high-speed circuits. Analysis based on waveform shape data can effectively detect waveform distortion caused by interference or design defects, ensuring the integrity of the signal shape. Based on the discrimination results of waveform amplitude, timing, and shape, an abnormal output response discrimination strategy is comprehensively generated, providing global guidance. This strategy can help R&D teams quickly locate the root cause of problems and optimize circuit design or operating conditions accordingly. Through multi-dimensional anomaly detection methods, the quality of signal output can be significantly improved, circuit failures caused by signal anomalies can be reduced, and the stability and reliability of circuit operation can be ensured. Especially in complex environments, it can effectively reduce the risk of output anomalies caused by interference or other external factors. Automated anomaly detection and strategy generation significantly shorten the time spent analyzing and resolving output anomalies during the design and debugging process, helping design teams to optimize product performance more efficiently.

[0033] Preferably, the calculation of the circuit parasitic index based on the circuit power supply interference cyclic simulation data includes:

[0034] The integrated circuit structure data is screened for circuit transistor structure to obtain circuit transistor structure data; based on circuit power supply interference cycle simulation data, the circuit transistor structure data is analyzed for transistor threshold voltage variation to generate circuit transistor threshold voltage variation data.

[0035] Based on the threshold voltage variation data of the circuit transistors, the gate length variation of the transistors in the integrated circuit is analyzed to generate transistor gate length variation data; parasitic effect test data of the integrated circuit is generated by using circuit power supply interference cycle simulation data.

[0036] The actual parasitic index of the integrated circuit is calculated from the test data of the parasitic effect of the integrated circuit using the transistor gate length variation data. The formula for calculating the actual parasitic index of the integrated circuit is shown below:

[0037]

[0038] In the formula, P represents the actual parasitic data of the integrated circuit, α represents the influence coefficient of capacitance on circuit performance, β represents the influence coefficient of resistance on circuit performance, K represents the scaling factor, W represents the transistor width, and L... g,act L represents the actual transistor gate length. g R0 represents the design length of the transistor gate, R0 represents the constant drain-source resistance, and B represents the measured value of the parasitic effect of the integrated circuit.

[0039] This invention is based on formula This system quantifies the impact of parasitic effects on circuit performance, providing intuitive and quantifiable actual parasitic index data. This precise calculation helps in a deeper understanding of the characteristics of parasitic effects and their potential threats to circuit functionality. Transistor threshold voltage variation analysis and gate length variation analysis provide fine-grained studies of transistor structures, revealing the dynamic changes of transistors under power supply interference environments. This helps engineers pinpoint specific performance bottlenecks and optimization directions. By combining power supply interference cycle simulation data and parasitic effect test data, a closed-loop analysis from simulation environment to actual testing is achieved, improving the accuracy of parasitic effect calculations and ensuring that the results are more consistent with real-world application scenarios. The influence coefficients α and β in the formulas characterize the different effects of capacitance and resistance on parasitic effects, respectively, enabling the calculation to comprehensively consider the contributions of these two key parameters to circuit performance, providing comprehensive guidance for circuit design. Gate length variation analysis provides a basis for optimizing transistor structure design. By studying the deviation between the actual gate length and the designed length, transistor geometric parameters can be optimized to reduce the impact of parasitic effects on circuit performance. Parasitic effect testing and actual parasitic index calculation help designers better understand and control the impact of parasitic effects on circuits, ensuring high reliability of circuits under high interference environments and reducing the risk of failure.

[0040] Preferably, step S3 includes the following steps:

[0041] Step S31: Perform minimum static power consumption analysis on the standard integrated circuit bias voltage acquisition data based on the actual parasitic data of the integrated circuit to generate minimum static power consumption data of the integrated circuit; perform leakage current test on the minimum static power consumption data of the integrated circuit to obtain leakage current data of the integrated circuit.

[0042] Step S32: Perform extreme temperature tests on the integrated circuit using the integrated circuit leakage current data to obtain the integrated circuit extreme temperature test data; balance the test data based on the actual parasitic data of the integrated circuit, the integrated circuit leakage current data, and the integrated circuit extreme temperature test data to obtain the integrated circuit comprehensive evaluation index;

[0043] Step S33: Compare the integrated circuit comprehensive evaluation index with the preset standard integrated circuit comprehensive evaluation threshold. When the integrated circuit comprehensive evaluation index is greater than or equal to the preset standard integrated circuit comprehensive evaluation threshold, the corresponding integrated circuit is batch-marked to generate a type of integrated circuit marking data.

[0044] Step S34: When the integrated circuit comprehensive evaluation index is less than the preset standard integrated circuit comprehensive evaluation threshold, the corresponding integrated circuit is batch-marked to generate Class II integrated circuit marking data.

[0045] This invention analyzes standard bias voltage data for minimum static power consumption based on actual parasitic data of integrated circuits, quantifying static power consumption levels and ensuring optimal energy consumption under normal operating conditions, providing strong data support for low-power design. Leakage current testing reveals the current leakage of integrated circuits, uncovering potential design flaws or material problems, thus improving circuit durability and reliability. Extreme temperature testing, combined with leakage current data, comprehensively reveals the performance of integrated circuits under extreme thermal environments, providing a reliable basis for application optimization in high-temperature operating environments. Parasitic data, leakage current data, and extreme temperature data are balanced and integrated into a comprehensive integrated circuit evaluation index, forming a unified standard for quantifying performance, providing an efficient tool for batch evaluation and reducing subjective judgment. Based on the comparison of the comprehensive evaluation index with preset thresholds, Class I and Class II integrated circuit data are automatically labeled, ensuring that high-performance circuits are assigned to critical tasks, while circuits requiring improvement are categorized and processed, improving overall product quality. The labeling system, combined with the results of the comprehensive evaluation, facilitates rapid classification and screening in large-scale production, improving efficiency while reducing the risk of defective products circulating in the market. The test data balancing process takes into account multi-dimensional performance data to ensure the stability and scientific validity of the evaluation results, thereby improving the circuit's fault tolerance in complex operating environments. The end-to-end analysis and evaluation guides design optimization, helping to achieve the circuit's goals of low power consumption and high reliability, aligning with the current electronics industry's trend towards green and energy-saving technologies.

[0046] Preferably, the lowest static power consumption analysis of standard integrated circuit bias voltage acquisition data based on actual parasitic data of integrated circuits includes:

[0047] Node capacitance is measured from actual parasitic data of integrated circuits to generate node capacitance value data; distribution network modeling is performed on node capacitance value data to generate parasitic capacitance distribution network data.

[0048] The parasitic capacitance distribution network data is used to identify the current flow path in the standard integrated circuit bias voltage acquisition data, generating current flow path feature data; the current flow path feature data is then used to extract the critical path, generating critical path data.

[0049] Bottleneck analysis is performed on critical path data to generate bottleneck characteristic data; static power consumption calculation is performed on standard integrated circuit bias voltage acquisition data using bottleneck characteristic data to obtain integrated circuit static power consumption data; extreme values ​​are extracted from the integrated circuit static power consumption data to obtain the lowest static power consumption data of the integrated circuit.

[0050] This invention generates accurate node capacitance data through node capacitance measurement, providing fundamental support for subsequent parasitic capacitance network modeling and helping to more comprehensively analyze the impact of capacitance on circuit power consumption. Using node capacitance data for distributed network modeling, the generated parasitic capacitance distribution network data clearly presents the distribution of parasitic capacitance within the circuit, providing an intuitive basis for optimization design. Based on the parasitic capacitance distribution network data, current flow path feature data is generated through current flow path identification, effectively tracking the specific path of current flow through the circuit and identifying key power consumption points. Extracting critical path data allows for focused analysis of the paths with the greatest impact on static power consumption, thus avoiding over-optimization of non-critical paths and improving resource utilization efficiency. Bottleneck analysis of critical paths generates bottleneck feature data, which can intuitively locate power consumption bottleneck areas, providing directional guidance for power reduction. Static power consumption calculation using bottleneck feature data provides designers with comprehensive circuit power consumption evaluation results, supporting more efficient power consumption optimization. Extracting extreme values ​​from the static power consumption data generates the lowest static power consumption data for the integrated circuit, setting a clear performance benchmark for optimization targets and promoting the realization of low-power designs. The end-to-end analysis provided a scientific basis for design optimization, particularly in identifying and improving power consumption bottlenecks, significantly improving the circuit's power efficiency and reliability. By optimizing the lowest static power consumption, not only was the circuit's total energy consumption reduced, but performance fluctuations caused by thermal effects were also minimized, enhancing the circuit's stability and lifespan.

[0051] Preferably, step S4 includes the following steps:

[0052] Step S41: Upload the Class I integrated circuit marking data and Class II integrated circuit marking data to the cloud platform for circuit test data storage, and generate integrated circuit test storage data;

[0053] Step S42: Visualize the integrated circuit test storage data and generate an integrated circuit test storage report to execute the complete integrated circuit test job.

[0054] This invention achieves centralized circuit test data storage by uploading tagged data to a cloud platform, generating integrated circuit test storage data. This ensures the classified management and convenient access to Class I and Class II integrated circuit data, improving data management efficiency. The cloud platform boasts high reliability and redundancy, effectively preventing data loss and ensuring long-term preservation and efficient backup of integrated circuit test storage data, enhancing data security. Cloud-based integrated circuit data storage supports real-time sharing and collaboration among multiple parties, simplifying the flow of circuit test data between R&D teams and promoting efficient collaborative work. Transforming test storage data into test storage reports, through charts, trend analysis, and key indicator displays, enhances data understandability and intuitiveness, facilitating rapid analysis and decision-making. The generation of the test report marks the completion of the entire integrated circuit testing process, providing comprehensive test results and key performance indicators, offering data support for subsequent improvements. The test report visually presents performance comparisons and anomaly analysis of Class I and Class II integrated circuits, helping to quickly locate problem areas and formulate improvement measures, thereby improving integrated circuit performance and quality. Storing test data and reports in the cloud facilitates subsequent analysis by R&D personnel using historical data, providing strong support for product iteration and quality tracking.

[0055] This specification provides an integrated circuit testing system for performing the aforementioned integrated circuit testing method. The integrated circuit testing system includes:

[0056] The bias voltage setting module is used to acquire integrated circuit structure data; filter key nodes in the integrated circuit structure data to obtain power supply pins and input pins; set static bias voltages for the power supply pins and input pins to generate static bias voltage setting data; and acquire bias voltages from the static bias voltage setting data to obtain standard integrated circuit bias voltage acquisition data.

[0057] The power supply interference simulation module is used to superimpose low-amplitude, high-frequency noise sources onto the standard integrated circuit bias voltage acquisition data to obtain voltage acquisition noise data; to simulate power supply interference on the standard integrated circuit bias voltage acquisition data using the voltage acquisition noise data to generate circuit power supply interference simulation data; and to calculate the circuit parasitic index from the circuit power supply interference simulation data to obtain the actual parasitic data of the integrated circuit.

[0058] The layered testing module is used to perform leakage current testing on the bias voltage acquisition data of standard integrated circuits based on the actual parasitic data of integrated circuits, to obtain integrated circuit leakage current data; to perform extreme temperature testing on integrated circuits using the integrated circuit leakage current data, to obtain integrated circuit extreme temperature test data; and to batch mark integrated circuits based on the actual parasitic data of integrated circuits, integrated circuit leakage current data, and circuit extreme temperature test data, to generate Class I integrated circuit marking data and Class II integrated circuit marking data.

[0059] The data visualization module is used to upload Class I and Class II integrated circuit labeling data to the cloud platform for data visualization, generate integrated circuit test storage reports, and execute complete integrated circuit testing jobs.

[0060] The beneficial effects of this invention lie in ensuring that testing focuses on the most critical nodes by screening power supply and input pins of integrated circuit structure data, thereby improving the relevance and effectiveness of the data. It achieves unified setting of static bias voltage, generating high-quality standard bias voltage acquisition data, providing a stable reference benchmark for subsequent testing. By acquiring standardized bias voltage data, the impact of external interference on initial data is reduced, laying the foundation for the reliability of subsequent module test results. By superimposing low-amplitude, high-frequency noise sources, power supply interference in the actual working environment is simulated, enhancing the realism and comprehensiveness of the test. Through parasitic index calculation, the specific impact of parasitic effects on circuit performance is quantitatively analyzed, providing a scientific basis for optimized design and fault diagnosis. The generated circuit power supply interference simulation data helps evaluate the anti-interference capability of integrated circuits to different noise levels, improving product robustness. Combining leakage current testing and extreme temperature testing, the performance boundaries and reliability of integrated circuits under extreme conditions are comprehensively evaluated. Based on the integrated analysis of parasitic data, leakage current data, and temperature test data, circuit defects and potential risks can be deeply explored, improving test coverage. Batch marking of test results enables product classification management, supporting efficient quality control and rapid anomaly traceability. Uploading categorized and labeled data to the cloud platform simplifies the analysis and interpretation of complex test data through visualization, improving user experience. Stored reports support cross-departmental sharing and collaborative work, enhancing efficiency and transparency across the production chain. Data visualization and storage provide crucial data for subsequent product optimization and production process improvement, while also enhancing the traceability and management capabilities of testing work. Therefore, this invention improves the accuracy of circuit testing through key node screening, parasitic effect assessment, multi-dimensional data analysis, and cloud visualization. Attached Figure Description

[0061] Figure 1 This is a flowchart illustrating the steps of an integrated circuit testing method.

[0062] Figure 2 for Figure 1 A detailed flowchart illustrating the implementation steps of step S2.

[0063] Figure 3 for Figure 1 A detailed flowchart illustrating the implementation steps of step S3.

[0064] The realization of the objective, functional features and advantages of the present invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0065] The technical method of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without inventive effort are within the scope of protection of this invention.

[0066] Furthermore, the accompanying drawings are merely illustrative of the invention and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and therefore repeated descriptions of them will be omitted. Some block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities. These functional entities can be implemented in software, in one or more hardware modules or integrated circuits, or in different network and / or processor methods and / or microcontroller methods.

[0067] It should be understood that although the terms "first," "second," etc., may be used herein to describe various units, these units should not be limited by these terms. These terms are used merely to distinguish one unit from another. For example, without departing from the scope of the exemplary embodiments, a first unit may be referred to as a second unit, and similarly, a second unit may be referred to as a first unit. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0068] To achieve the above objectives, please refer to Figures 1 to 3 An integrated circuit testing method, the method comprising the following steps:

[0069] Step S1: Obtain integrated circuit structure data; perform key node screening on the integrated circuit structure data to obtain power supply pins and input pins; set static bias voltages on the power supply pins and input pins to generate static bias voltage setting data; collect bias voltages from the static bias voltage setting data to obtain standard integrated circuit bias voltage collection data.

[0070] Step S2: Superimpose low-amplitude, high-frequency noise sources onto the standard integrated circuit bias voltage acquisition data to obtain voltage acquisition noise data; simulate power supply interference on the standard integrated circuit bias voltage acquisition data using the voltage acquisition noise data to generate circuit power supply interference simulation data; calculate the circuit parasitic index on the circuit power supply interference simulation data to obtain the actual parasitic data of the integrated circuit.

[0071] Step S3: Perform leakage current testing on the standard integrated circuit bias voltage acquisition data based on the actual parasitic data of the integrated circuit to obtain the integrated circuit leakage current data; perform extreme temperature testing on the integrated circuit using the integrated circuit leakage current data to obtain the integrated circuit extreme temperature test data; mark the integrated circuit batch based on the actual parasitic data of the integrated circuit, the integrated circuit leakage current data, and the circuit extreme temperature test data to generate Class I integrated circuit marking data and Class II integrated circuit marking data.

[0072] Step S4: Upload the Class I and Class II integrated circuit tagging data to the cloud platform for data visualization, generate an integrated circuit test storage report, and execute the complete integrated circuit test job.

[0073] This invention focuses testing on power and input pins through key node screening, avoiding interference from unnecessary nodes and improving testing efficiency and resource utilization. Static bias voltage settings ensure data uniformity and standardization, laying the foundation for the accuracy and comparability of subsequent test results. The generated standard bias voltage data can be used in various test scenarios, such as interference simulation and leakage current testing, enhancing test applicability. By superimposing low-amplitude, high-frequency noise, the operating state of integrated circuits in complex electromagnetic environments is realistically reproduced, improving the comprehensiveness of the test. Power interference simulation data provides a basis for evaluating the impact of power fluctuations on circuit performance, helping to optimize circuit design. Parasitic index calculation quantifies the impact of parasitic effects, providing data support for circuit improvement and defect localization, especially suitable for problem diagnosis in high-density circuit designs. Leakage current and extreme temperature tests based on parasitic data provide in-depth understanding of the performance boundaries and potential risks of integrated circuits. Comprehensive analysis combining parasitic data, leakage current data, and extreme temperature data provides a panoramic view of integrated circuit performance. Intelligent labeling of Class I and Class II products significantly improves the efficiency of product classification and quality control while reducing the error rate of human intervention. Batch tagging data supports traceability in the production chain, providing a basis for subsequent improvements and product grading. Visualization after uploading to the cloud platform facilitates rapid understanding and evaluation of test results, providing an intuitive reference for decision-making. Cloud storage and report generation support cross-departmental collaboration, improving data sharing efficiency and reducing the risk of information silos. The stored reports include multi-dimensional test results and tagging data, providing rich evidence for subsequent design optimization and test process improvement. Cloud visualization of data enhances the transparency of the entire testing process, contributing to quality control and building customer trust. Therefore, this invention improves the accuracy of circuit testing through key node screening, parasitic effect assessment, multi-dimensional data analysis, and cloud visualization.

[0074] In this embodiment of the invention, reference is made to Figure 1The above is a flowchart illustrating the steps of an integrated circuit testing method according to the present invention. In this example, the integrated circuit testing method includes the following steps:

[0075] Step S1: Obtain integrated circuit structure data; perform key node screening on the integrated circuit structure data to obtain power supply pins and input pins; set static bias voltages on the power supply pins and input pins to generate static bias voltage setting data; collect bias voltages from the static bias voltage setting data to obtain standard integrated circuit bias voltage collection data.

[0076] In this embodiment of the invention, integrated circuit structure data is imported from design documents or simulation tools. Common formats include SPICE files, Verilog files, or other hardware description language files. The structure data is parsed to extract the following key information: circuit node connection information, logic descriptions of functional modules, and input, output, and power supply pins of each module. If the structure data contains noise or incomplete information, circuit analysis tools (such as HSPICE or Cadence Virtuoso) are used for data cleaning and integrity checks. The integrated circuit's connection network is analyzed, and nodes are filtered: nodes directly connected to the circuit's power rails (VDD / GND) are marked. Nodes connected to external signal sources or other module interfaces are marked. Graph traversal algorithms (such as depth-first search) are used to identify nodes connected to power and inputs. Node types are classified and marked, generating power supply pin data and input pin data. Based on circuit design specifications and actual testing requirements, the following parameters are determined: target voltage values ​​for power supply pins (e.g., 1.8V, 3.3V). The bias voltage range for input pins (e.g., a static value between 0V and a logic high level). Static bias voltages are applied to the pins using test tools (such as automated test instruments ATE). Power pins: Provide a constant voltage via a stabilizing power supply module. Input pins: Set the bias voltage using a precision signal generator, record the bias voltage value for each pin, and generate static bias voltage setting data. Use a high-precision voltage acquisition instrument (such as a digital multimeter or DAQ data acquisition module) to acquire the actual bias voltage of each pin. Check if the acquired voltage value is within the error range (e.g., ±1%). If there is a deviation, adjust the voltage setting until the acquired value matches the target value. Save the acquired voltage data as standard integrated circuit bias voltage acquisition data, including: pin number and type (power / input), actual acquired bias voltage value, and deviation information from the target value (e.g., error range, deviation rate).

[0077] Step S2: Superimpose low-amplitude, high-frequency noise sources onto the standard integrated circuit bias voltage acquisition data to obtain voltage acquisition noise data; simulate power supply interference on the standard integrated circuit bias voltage acquisition data using the voltage acquisition noise data to generate circuit power supply interference simulation data; calculate the circuit parasitic index on the circuit power supply interference simulation data to obtain the actual parasitic data of the integrated circuit.

[0078] In this embodiment of the invention, a low-amplitude, high-frequency noise is generated by selecting an appropriate noise source model (such as Gaussian white noise or pseudo-random signal). The noise amplitude range is set to ±1% of the standard bias voltage. The noise frequency range is set to 1.5 times higher than the circuit operating frequency. The generated noise signal is superimposed on the standard integrated circuit bias voltage acquisition data using the formula: Vnoise(t) = Vbias(t) + N(t); where Vbias(t) is the original bias voltage data and N(t) is the noise signal, generating voltage acquisition noise data containing noise. A power supply interference model is constructed based on the voltage acquisition noise data. Common models include: power supply ripple interference: superimposed with a sinusoidal interference signal; random interference: superimposed with a low-frequency random fluctuation signal. The simulated power supply interference formula is: Vinterference(t) = Vnoise(t) + A·sin(2πft) + R(t), where A is the interference signal amplitude, f is the interference signal frequency, and R(t) is the low-frequency random signal. The power supply interference is dynamically simulated using simulation tools (such as MATLAB or SPICE simulator). Using circuit network analysis tools, parasitic capacitance and inductance are identified. The voltage and current fluctuation characteristics caused by interference are extracted, the amplitude and distribution of parasitic parameters are calculated, and actual parasitic data for integrated circuits are generated.

[0079] Step S3: Perform leakage current testing on the standard integrated circuit bias voltage acquisition data based on the actual parasitic data of the integrated circuit to obtain the integrated circuit leakage current data; perform extreme temperature testing on the integrated circuit using the integrated circuit leakage current data to obtain the integrated circuit extreme temperature test data; mark the integrated circuit batch based on the actual parasitic data of the integrated circuit, the integrated circuit leakage current data, and the circuit extreme temperature test data to generate Class I integrated circuit marking data and Class II integrated circuit marking data.

[0080] In this embodiment of the invention, a static bias voltage is applied using standard test equipment (such as a DC source measurement unit, SMU). The test environment temperature is controlled to room temperature (25°C). Based on the actual parasitic data of the integrated circuit, a static bias voltage is applied to critical nodes (such as power supply pins and input pins). The leakage current value of each node is measured, and the leakage current data is normalized to remove random errors. The leakage current characteristics of each critical node are recorded, including current amplitude and time stability. A hot stage (or environmental test chamber) is used to set the temperature range from -40°C to 125°C (compliant with industry standards). The bias voltage conditions during leakage current testing are applied. The temperature is gradually increased in 10°C steps, and the leakage current value and critical circuit parameters are recorded at each step. The temperature is then reduced from high to low, and the measurement is repeated and the data is recorded. The gradient of leakage current at critical nodes with temperature is calculated, and nodes that fail or experience significant performance degradation at extreme temperatures are marked. The parasitic data, leakage current data, and extreme temperature data are comprehensively analyzed based on the following formula: CI = α·PI + β·ILavg + γ·Tmax; where CI is the comprehensive evaluation index, PI is the parasitic index, ILavg is the average leakage current, Tmax is the extreme temperature point, and α, β, and γ are weighting coefficients, which are adjusted according to testing requirements. When CI ≥ the threshold, the circuit is marked as a high-performance integrated circuit; when CI < the threshold, it is marked as a general-performance integrated circuit. The marked data is stored in a database, and a marking report is generated for each batch of circuits.

[0081] Step S4: Upload the Class I and Class II integrated circuit tagging data to the cloud platform for data visualization, generate an integrated circuit test storage report, and execute the complete integrated circuit test job.

[0082] In this embodiment of the invention, a standard cloud storage interface (such as REST API) is used to connect to the cloud platform. A security authentication mechanism (such as OAuth2 or key authentication) is configured to ensure secure data transmission. Class I and Class II integrated circuit tagging data are uploaded in JSON or CSV format. Each data entry contains the following fields: tag category (e.g., Class I or Class II), test indicators (e.g., leakage current, extreme temperature), timestamp, and batch number. After uploading, data integrity is verified to ensure no data loss or corruption. Professional data visualization tools (such as Tableau, Power BI) or the cloud platform's built-in visualization module are used. Bar charts or pie charts are used to display the quantity distribution of Class I and Class II integrated circuits. A line chart is used to display the leakage current trend with temperature. A scatter plot is used to compare the performance differences between different batches of integrated circuits.

[0083] Preferably, step S1 includes the following steps:

[0084] Step S11: Obtain integrated circuit structure data;

[0085] Step S12: Perform circuit pin analysis on the integrated circuit structure data to generate integrated circuit pin data; based on the integrated circuit pin data, perform key node screening on the integrated circuit structure data to obtain the key nodes of the integrated circuit, wherein the key nodes of the integrated circuit include power supply pins and input pins;

[0086] Step S13: Set the static bias voltage for the power supply pin and input pin to generate static bias voltage setting data; use a voltage sensor to acquire the bias voltage from the static bias voltage setting data to obtain integrated circuit bias voltage acquisition data;

[0087] Step S14: Perform data preprocessing on the integrated circuit bias voltage acquisition data to generate standard integrated circuit bias voltage acquisition data. The data preprocessing includes data cleaning, data denoising, data missing value filling, and data standardization.

[0088] In this embodiment of the invention, circuit structure data is extracted from integrated circuit design files (such as GDSII files or Verilog code). This data can be extracted using EDA tools (such as Cadence or Synopsys). Information such as circuit layout, hierarchy, component distribution, and pin arrangement is obtained. This data includes the geometry, connections, and electrical parameters (such as resistance and capacitance) of all integrated circuit components. Each component of the integrated circuit is analyzed, and pins connecting to the circuit board or other components are identified. This process can be automated using graph processing algorithms or EDA tools. Based on circuit design rules, key nodes such as power supply pins, input pins, output pins, and ground pins are identified. Algorithms (such as graph theory analysis) can be used to filter key nodes in the circuit. Based on the selected key nodes, a pin dataset is created, recording the location, function (power, input, output, etc.), and electrical characteristics of each pin. Static bias voltage values ​​are assigned to each power supply pin and input pin. Typically, these voltage values ​​are set according to the circuit's operating voltage and design specifications. For example, low-voltage logic circuits require a 3.3V or 5V power supply, while analog circuits require more precise voltage values. Create a voltage profile to record the static bias voltage value for each pin. This file can be a spreadsheet, JSON, or database for subsequent analysis and verification. Deploy voltage sensors (e.g., digital oscilloscopes, multimeters, etc.) to measure the voltages of critical nodes in the integrated circuit. The sensors should have high accuracy and low noise characteristics to ensure the reliability of the measurement data. Acquire voltage data from power and input pins, recording the actual voltage value and acquisition timestamp for each node; this data will be used for subsequent bias voltage analysis. Remove invalid data (e.g., outlier data points due to sensor failure). Standard data cleaning techniques such as extreme value removal and filtering can be used. Use appropriate noise filtering methods (e.g., mean filtering, Kalman filtering, etc.) to reduce noise in the acquired data and ensure the accuracy of the voltage data. For missing voltage data, interpolation algorithms (e.g., linear interpolation, Lagrange interpolation, etc.) can be used to fill in the gaps and maintain data continuity. Standardize the voltage data to a uniform range, typically [0,1] or a standard normal distribution (mean 0, standard deviation 1) for subsequent data analysis and modeling.

[0089] Preferably, setting the static bias voltage for the power supply pins and input pins includes:

[0090] Define the operating voltage range for the power supply pins to obtain the operating voltage range of the power supply pins; define the normal logic level range for the input pins to obtain the normal logic level range of the input pins.

[0091] Based on the operating voltage range of the power supply pins and the normal logic level range of the input pins, the bias voltage range of key nodes of the integrated circuit is extended to generate bias voltage range extension data; based on the bias voltage range extension data, the test voltage step setting of key nodes of the integrated circuit is performed to generate a serialized list of test points.

[0092] By setting the static bias voltage of the power supply pin and input pin according to the serialized list of test points based on the preset stabilization time, static bias voltage setting data is generated.

[0093] In this embodiment of the invention, the operating voltage range of the power supply pins is obtained from integrated circuit design documents or specifications. This typically depends on the type of integrated circuit (e.g., digital circuit, analog circuit) and design standards. For example, low-voltage logic circuits typically use power supply voltages such as 3.3V or 5V, while high-performance analog circuits require ±15V or higher voltages. When defining the power supply voltage range, the rated voltage of the power supply pin, the permissible voltage fluctuation range, and the minimum / maximum operating voltage of the power supply should be considered. The operating voltage range of the power supply pins is recorded in tabular or other data structure form, including the minimum voltage, maximum voltage, and recommended operating voltage. The normal logic level of the input pins is defined based on design standards. For example, logic "0" can be 0V, and logic "1" can be 3.3V or 5V, depending on the system operating voltage. Typically, the low logic level (V_Low) range can be 0V to 0.8V, and the high logic level (V_High) range can be 2V to 3.3V. The logic levels of the input pins are standardized according to the datasheet or circuit design document. When defining the logic level range of input pins, it is necessary to ensure that the signal is stable and meets logic requirements (e.g., appropriate threshold voltage) when the circuit operates within that range. Based on the operating voltage range of the power supply pins and the normal logic level range of the input pins, the bias voltage range of critical nodes (such as power supply pins and input pins) of the integrated circuit can be extended. The extended voltage range should include the upper / lower boundaries of the power supply voltage and the logic level range of the input pins, enabling the circuit to operate normally over a larger voltage range, taking into account possible circuit errors or fluctuations. The voltage extension range for each node is generated through programming or algorithms; for example, for power supply pins, the extension range is [minimum power supply voltage, maximum power supply voltage]; for input pins, the extension range is [minimum logic 0 voltage, maximum logic 1 voltage]. This generates a data table or list containing the extended voltage range for each circuit node. The data includes the node name, voltage type (power supply, voltage bias, etc.), and extension range (minimum, maximum value). Based on the bias voltage range extension data, the voltage step size for each test node is defined. The step value is typically determined by the voltage range and the required test accuracy. For example, if the voltage range is large (e.g., 0V to 10V), the step can be 0.1V or 0.2V; if the voltage range is small (e.g., 3.3V to 5V), the step can be 0.05V or less. Based on the minimum and maximum values ​​of the range and the step size, the program calculates the voltage value for each test point. For example, starting from the minimum voltage value, the step value is increased each time until the maximum voltage value is reached. The test voltage points are arranged in order of increasing voltage, forming a list containing the voltage values. Each test point includes information such as the voltage value, the corresponding test node, and the voltage state.If the test point range is [3V, 5V] with a step of 0.1V, then the test point serialization list is: [3.0V, 3.1V, 3.2V, ..., 5.0V]. A settling time is defined for each test point to ensure the circuit operates stably at each voltage point. Typically, the settling time depends on the circuit's response speed, ranging from a few microseconds to a few milliseconds. This parameter can be determined empirically or calculated based on a circuit model. Assume the settling time for each test point is set to 10 milliseconds. Set the static bias voltage at each test point using an automated test system or hardware interface. After each voltage adjustment, the system waits for the preset settling time to ensure the circuit operates stably at that voltage. After setting each voltage point, record the voltage value of that node and its corresponding settling time to form the static bias voltage setting data. For example, the data table records the following information: Node: Power pin 1, Input pin 2, Voltage: 3.0V, 3.1V, 3.2V…, Settling time: 10ms.

[0094] As an example of the present invention, reference is made to... Figure 2 As shown, step S2 in this example includes:

[0095] Step S21: Superimpose low-amplitude high-frequency noise sources on the standard integrated circuit bias voltage acquisition data to obtain voltage acquisition noise data; simulate power supply interference on the standard integrated circuit bias voltage acquisition data using the voltage acquisition noise data to generate circuit power supply interference simulation data.

[0096] Step S22: Use an oscilloscope to measure the output waveform of the circuit power supply interference simulation data, and perform abnormal output response discrimination on the measured output waveform to obtain an abnormal output response discrimination strategy;

[0097] Step S23: Adjust the signal frequency of the circuit power supply interference simulation data according to the abnormal output response discrimination strategy to generate a circuit power supply interference adjustment signal;

[0098] Step S24: Perform cyclic power supply interference simulation on the standard integrated circuit bias voltage acquisition data through the circuit power supply interference adjustment signal to generate cyclic simulation data of circuit power supply interference; calculate the circuit parasitic index on the cyclic simulation data of circuit power supply interference to obtain the actual parasitic data of the integrated circuit.

[0099] In this embodiment of the invention, by defining a noise source, a low-amplitude, high-frequency noise source typically refers to a noise signal with a low amplitude (e.g., 10mV to 100mV) and a high frequency (e.g., tens of MHz to hundreds of MHz). This noise signal can simulate high-frequency noise from interference sources such as power supplies and ground lines. The required noise signal is generated using a signal generator or a digital signal processor (DSP). A random noise signal or a white noise source can be used to simulate the high-frequency noise source. The generated low-amplitude, high-frequency noise signal is superimposed onto the bias voltage acquisition data of a standard integrated circuit. This process can be implemented using hardware (e.g., an oscilloscope) or software simulation. Through a simple superposition operation, the noise signal is added to the voltage data. Through the above superposition operation, the voltage acquisition data with noise is finally obtained, i.e., voltage acquisition noise data, which simulates the power supply interference and noise effects experienced by the integrated circuit during operation. The goal of interference simulation is to simulate noise or power fluctuations occurring in the power supply or circuit, especially interference caused by high-frequency noise, ground line return current, etc. The noise signal output by the signal generator can be used, or a power supply noise interference model can be added through modeling and simulation in computer software. Simulation software (such as Spice and ADS) can be used to model power supply interference or to simulate interference by actually superimposing noise signals on hardware. Interference simulation is performed on the bias voltage data of the integrated circuit by acquiring noise data from voltage acquisition. Specifically, this process can be achieved through time-domain or frequency-domain analysis, applying noise signals to key nodes in the circuit (such as power pins, input pins, etc.) to generate a voltage dataset with interference. The final result is simulated power supply interference data, including the voltage changes and responses of the integrated circuit under power supply interference. An oscilloscope is connected to the output nodes of the integrated circuit (such as output pins, key signal nodes, etc.) to measure the output waveform after power supply interference simulation. The oscilloscope can capture the output signal in real time and display the waveform. Basic parameters of the output waveform are measured, including amplitude, frequency, waveform distortion, rise time, and fall time. Special attention is paid to noise, amplitude fluctuations, and nonlinear responses in the waveform. Analysis of the measured output waveform determines whether the circuit has exhibited abnormal responses. Abnormal responses manifest as waveform distortion, excessive noise, and excessive voltage fluctuations. Thresholding methods (such as setting an allowable noise range) or model-based methods (such as comparing with expected normal waveforms) are used to determine whether a waveform is abnormal. A discrimination strategy can be trained using a machine learning model to identify waveforms that do not conform to normal operation. This ultimately results in an abnormal output response discrimination strategy that defines which waveform characteristics represent abnormal circuit behavior under power supply interference. Based on the discriminated abnormal response strategy, the frequency of the power supply interference signal is adjusted to observe the impact of frequency on circuit performance. The purpose of frequency adjustment is to test the circuit's stability and response capability under power supply interference at different frequencies. The frequency of the power supply interference signal can be dynamically adjusted using a signal generator or software tools, scanning different frequency ranges from low to high frequencies.For example, the frequency range can be adjusted from 1MHz to 100MHz to observe how the output waveform changes. New power supply interference signal data is generated based on the adjusted frequency range. This signal data contains simulated power supply interference information at different frequencies and can be applied to further circuit testing. Power supply interference is periodically simulated at different power supply interference signal frequencies to test the circuit's stability under continuous interference. The impact of continuous power supply disturbances on circuit performance is simulated by applying power supply interference signals of different frequencies to the power supply port and input port. The power supply interference signal is repeatedly applied over multiple cycles to simulate a continuous interference environment. Through multiple interference signal simulations, a circuit simulation data containing cyclic power supply interference at different frequencies is finally obtained. The circuit parasitic index is a quantitative indicator of the circuit parasitic effects caused by factors such as power supply, ground, and capacitance, and is usually related to voltage fluctuations, current anomalies, and impedance changes. The parasitic index is calculated by analyzing the circuit's response under different interference signals using methods such as frequency domain analysis and time domain waveform fitting. Parasitic effects can be modeled using mathematical models (e.g., RC and RL circuit models), and parasitic parameters can be extracted from the simulation data. Based on the calculation results of the circuit parasitic index, the parasitic data of integrated circuits in the actual working environment are obtained. This data can be used to optimize circuit design and improve anti-interference ability.

[0100] Preferably, the abnormal output response discrimination of the measured output waveform includes:

[0101] The average value and standard deviation of the measured output waveform are calculated to obtain the average value and standard deviation of the output waveform; based on the average value and standard deviation of the output waveform, the measured output waveform is subjected to waveform amplitude anomaly discrimination to generate waveform amplitude anomaly discrimination data.

[0102] Perform waveform timing analysis on the measured output waveform to generate output waveform timing data; based on the output waveform timing data, perform time delay over-limit judgment on the measured output waveform to generate waveform timing anomaly judgment data;

[0103] The measured output waveform is analyzed to generate output waveform shape data; based on the output waveform shape data, the measured output waveform is subjected to waveform shape distortion discrimination to generate waveform shape anomaly discrimination data.

[0104] Based on waveform amplitude anomaly discrimination data, waveform timing anomaly discrimination data, and waveform morphology anomaly discrimination data, abnormal output response discrimination is performed on the measured output waveform to obtain an abnormal output response discrimination strategy.

[0105] In this embodiment of the invention, the measured output waveform data is acquired and discretized to obtain a waveform data sequence. Waveform average value calculation: Where μ is the waveform average, N is the total number of data points, and x i For the i-th data point in the waveform data sequence, the waveform standard deviation is calculated as follows: Where σ is the waveform standard deviation and μ is the average value of the output waveform, the average value and standard deviation of the output waveform are obtained and named "output waveform average value" and "output waveform standard deviation" respectively. An amplitude threshold is set based on the output waveform average value and standard deviation. If the waveform amplitude exceeds a predetermined normal range (e.g., exceeding 3 times the standard deviation), the waveform amplitude is considered abnormal. The amplitude anomaly discrimination formula is: A = max(x) - min(x); where A is the waveform amplitude, and max(x) and min(x) are the maximum and minimum values ​​of the waveform data, respectively. If A > k × σ, the waveform amplitude is judged to be abnormal. k is the multiplier factor for amplitude anomaly discrimination (e.g., k = 3), generating "waveform amplitude anomaly discrimination data" to record whether amplitude anomalies have occurred. Time domain analysis is used to calculate the waveform's rise time, fall time, periodicity, and other time-series characteristics. Mathematical models (such as Fourier transform, time-series correlation analysis, etc.) are used to extract time-series data. Periodicity, time delay, and other features are extracted from the waveform. The output waveform timing data can be generated using moving averages across time windows or zero-crossing point-based timing analysis methods. A maximum allowable delay threshold is set, and the delay of the output waveform is judged based on the timing data. If the rise time, fall time, or propagation delay exceeds the predetermined threshold, it is judged as a timing anomaly. The rise time, fall time, and signal delay in the timing data are used to determine whether they exceed the normal range. This includes, but is not limited to, waveform period, delay, rise and fall times, generating "waveform timing anomaly discrimination data" to record whether delay exceeding limits has occurred. The output waveform is fitted and matched, for example, using high-order polynomial fitting or Fourier analysis to obtain the ideal waveform shape. By comparing the error between the actual waveform and the fitted waveform, or by calculating the waveform's peaks, troughs, symmetry, and other characteristics, it is determined whether the shape is distorted. If the waveform's difference from the normal shape exceeds a set threshold (e.g., the fitting error exceeds a certain threshold), the waveform shape is considered distorted, generating "waveform shape anomaly discrimination data" to record whether waveform shape distortion has occurred. The three discrimination results—waveform amplitude anomaly, timing anomaly, and shape anomaly—are comprehensively analyzed. If any judgment result is abnormal, the output response is determined to be abnormal. The comprehensive judgment formula is: Abnormal output response = Amplitude abnormality ∨ Timing abnormality ∨ Morphological abnormality, which yields the "abnormal output response judgment strategy", that is, to comprehensively determine whether there is an abnormal response in the output waveform.

[0106] Preferably, the calculation of the circuit parasitic index based on the circuit power supply interference cyclic simulation data includes:

[0107] The integrated circuit structure data is screened for circuit transistor structure to obtain circuit transistor structure data; based on circuit power supply interference cycle simulation data, the circuit transistor structure data is analyzed for transistor threshold voltage variation to generate circuit transistor threshold voltage variation data.

[0108] Based on the threshold voltage variation data of the circuit transistors, the gate length variation of the transistors in the integrated circuit is analyzed to generate transistor gate length variation data; parasitic effect test data of the integrated circuit is generated by using circuit power supply interference cycle simulation data.

[0109] The actual parasitic index of the integrated circuit is calculated from the test data of the parasitic effect of the integrated circuit using the transistor gate length variation data. The formula for calculating the actual parasitic index of the integrated circuit is shown below:

[0110]

[0111] In the formula, P represents the actual parasitic data of the integrated circuit, α represents the influence coefficient of capacitance on circuit performance, β represents the influence coefficient of resistance on circuit performance, K represents the scaling factor, W represents the transistor width, and L... g,act L represents the actual transistor gate length. g R0 represents the design length of the transistor gate, R0 represents the constant drain-source resistance, and B represents the measured value of the parasitic effect of the integrated circuit.

[0112] In this embodiment of the invention, transistor structure information from integrated circuit design is used, including transistor type, size, gate length, source and drain connections, etc. Based on the integrated circuit design specifications, all transistor nodes are extracted, and transistors affected by power supply interference are screened out. Specifically, netlist data from the design file can be used to filter by transistor type and connection, obtaining a filtered circuit transistor structure dataset, recording the type, size parameters, etc., of each transistor. Power supply interference cyclic simulation data is used to analyze the transistor's operating state under different power supply interference conditions. Voltage changes in the circuit are simulated by applying periodic interference to the power input terminal. Based on the results of the power supply interference simulation, the change in the transistor's threshold voltage under different interference conditions is calculated. The threshold voltage can be extracted by measuring the source and drain voltages and using current-voltage (IV) characteristic curves, generating circuit transistor threshold voltage change data, and recording the threshold voltage change of each transistor under different power supply interference. The change in threshold voltage is closely related to the transistor's gate length. During the threshold voltage change process, the impact of gate length changes on the transistor can be analyzed. By modifying the gate length parameter in the circuit simulation environment, its impact on the threshold voltage is observed. Based on the transistor's threshold voltage change data, the impact of gate length changes is inferred. Device-level simulation tools (such as SPICE) can be used to analyze and calculate the changes in electrical performance under different gate lengths, generating transistor gate length variation data and recording the impact of transistor gate length variations under different power supply interference conditions. By simulating different types of power supply interference (such as voltage noise, current noise, etc.), the impact of power supply interference on circuit parasitic effects can be evaluated. Dynamic simulation (e.g., through time-domain simulation) or frequency-domain simulation can be used to analyze how power supply noise affects the parasitic effects of the circuit. Power supply interference simulation data can be iteratively processed in a simulation environment to perform multiple power supply interference tests on the circuit. Test results, especially changes in current and voltage and noise spectra, can be recorded to generate integrated circuit parasitic effect test data, recording the parasitic effects of power supply interference on the circuit. Based on the transistor gate length variation and the impact of power supply interference on circuit parasitic effects, the actual parasitic index of the integrated circuit can be calculated. The actual parasitic index of the circuit can be calculated using the following formula: In the formula, P represents the actual parasitic data of the integrated circuit, α represents the influence coefficient of capacitance on circuit performance, β represents the influence coefficient of resistance on circuit performance, K represents the scaling factor, W represents the transistor width, and L... g,act L represents the actual transistor gate length. gR0 represents the designed gate length of the transistor, R0 represents the constant drain-source resistance, and B represents the measured value of the parasitic effect of the integrated circuit. Based on the previously obtained transistor gate length variation data and power supply interference simulation data, the parasitic index of each transistor or circuit node is calculated by substituting into the formula, generating actual parasitic data of the integrated circuit, and recording the parasitic effect of the circuit under power supply interference.

[0113] As an example of the present invention, reference is made to... Figure 3 As shown, step S3 in this example includes:

[0114] Step S31: Perform minimum static power consumption analysis on the standard integrated circuit bias voltage acquisition data based on the actual parasitic data of the integrated circuit to generate minimum static power consumption data of the integrated circuit; perform leakage current test on the minimum static power consumption data of the integrated circuit to obtain leakage current data of the integrated circuit.

[0115] Step S32: Perform extreme temperature tests on the integrated circuit using the integrated circuit leakage current data to obtain the integrated circuit extreme temperature test data; balance the test data based on the actual parasitic data of the integrated circuit, the integrated circuit leakage current data, and the integrated circuit extreme temperature test data to obtain the integrated circuit comprehensive evaluation index;

[0116] Step S33: Compare the integrated circuit comprehensive evaluation index with the preset standard integrated circuit comprehensive evaluation threshold. When the integrated circuit comprehensive evaluation index is greater than or equal to the preset standard integrated circuit comprehensive evaluation threshold, the corresponding integrated circuit is batch-marked to generate a type of integrated circuit marking data.

[0117] Step S34: When the integrated circuit comprehensive evaluation index is less than the preset standard integrated circuit comprehensive evaluation threshold, the corresponding integrated circuit is batch-marked to generate Class II integrated circuit marking data.

[0118] In this embodiment of the invention, actual parasitic data of the integrated circuit is used, which comes from the circuit's parasitic resistance, capacitance, and transistor threshold voltage variations. Based on this data, the power consumption of the circuit in its operating state is calculated using a power consumption model (such as a static power consumption model or power consumption estimation formula). Typically, in static power consumption analysis, the circuit's operating state can be defined as the power consumption under the lowest load. The minimum static power consumption is usually the total power consumption related to the transistor source-drain current and leakage current under the power supply voltage. Minimum static power consumption data of the integrated circuit is generated, and the power consumption value under the minimum operating load condition is recorded. Based on the minimum static power consumption data, combined with the leakage current of each transistor in the circuit (leakage current is mainly determined by the power supply voltage, operating temperature, and transistor characteristics), leakage current is measured. A dedicated leakage current testing device (such as a precision current probe) can be used to test the circuit's leakage current. By adjusting the bias voltage and measuring the leakage current of the integrated circuit, its energy efficiency under the minimum load condition is determined, obtaining the integrated circuit leakage current data, i.e., the leakage current value under the lowest power consumption condition. Based on the integrated circuit leakage current data, temperature cycling tests are performed on the integrated circuit at different temperatures. The test temperature range should cover the circuit's operating environment extreme temperatures (e.g., high temperature 150°C, low temperature -40°C). By controlling the temperature changes of the test environment at different temperatures, the changes in leakage current are observed. Temperature changes typically affect the leakage current of transistors, therefore, the variation of leakage current at different temperatures is crucial for evaluating circuit performance. Using environmental temperature control equipment (such as a temperature-controlled chamber or hot plate), extreme operating temperatures are simulated under laboratory conditions. The current changes in the circuit at different temperatures are recorded to obtain integrated circuit extreme temperature test data, recording the changes in leakage current and the stability of circuit performance under different temperature conditions. Data standardization and normalization techniques are used to convert different test data (leakage current, temperature, parasitic effects, etc.) into a unified standard format. The data is balanced based on the following formula: Comprehensive Evaluation Index = w1·Leakage Current Standardized Value + w2·Temperature Influence Standardized Value + w3·Parasitic Effect Standardized Value, where w1, w2, and w3 are the weights of each data point in the comprehensive evaluation, usually adjusted through data analysis or expert experience. This generates the integrated circuit comprehensive evaluation index, which reflects the comprehensive performance of the integrated circuit in multiple aspects (static power consumption, leakage current, temperature influence, etc.). The calculated integrated circuit comprehensive evaluation index is compared with a preset standard integrated circuit comprehensive evaluation threshold. If the comprehensive evaluation index is greater than or equal to the preset standard threshold, the integrated circuit is considered to meet the standard requirements and is suitable for mass production. If the comprehensive evaluation index is less than the preset standard, the integrated circuit is considered to have performance problems, requiring improvement or not suitable for mass production, and Class I integrated circuit labeling data (circuits that meet the standard requirements) or Class II integrated circuit labeling data (circuits that do not meet the standard requirements) is generated. Integrated circuits with a comprehensive evaluation index less than the standard threshold are batch-marked.This batch of integrated circuits will be classified as Class II integrated circuits, which are not suitable for mass production. Class II integrated circuit labeling data will be generated so that relevant teams can conduct performance analysis, improve designs, or modify manufacturing processes.

[0119] Preferably, the lowest static power consumption analysis of standard integrated circuit bias voltage acquisition data based on actual parasitic data of integrated circuits includes:

[0120] Node capacitance is measured from actual parasitic data of integrated circuits to generate node capacitance value data; distribution network modeling is performed on node capacitance value data to generate parasitic capacitance distribution network data.

[0121] The parasitic capacitance distribution network data is used to identify the current flow path in the standard integrated circuit bias voltage acquisition data, generating current flow path feature data; the current flow path feature data is then used to extract the critical path, generating critical path data.

[0122] Bottleneck analysis is performed on critical path data to generate bottleneck characteristic data; static power consumption calculation is performed on standard integrated circuit bias voltage acquisition data using bottleneck characteristic data to obtain integrated circuit static power consumption data; extreme values ​​are extracted from the integrated circuit static power consumption data to obtain the lowest static power consumption data of the integrated circuit.

[0123] In this embodiment of the invention, capacitance measurements are performed on each node of the integrated circuit using capacitance measurement tools (such as a capacitance meter or circuit simulation software). The capacitance of each node in the integrated circuit (such as the source, drain, and gate of a transistor) is directly measured or calculated using simulation tools. The output is capacitance data for each node, including the capacitance value of each node, capacitive coupling between nodes, and other information, resulting in node capacitance data, which is recorded. Based on the node capacitance data, a coupling network model between capacitors in the circuit is established using circuit simulation software (such as SPICE or a custom model). Each capacitor node can be connected to other nodes via capacitive coupling, forming a distributed capacitor network. During the modeling process, parasitic capacitance effects need to be considered; that is, each capacitor node is not only directly coupled to the capacitors of neighboring nodes, but also the mutual influence in the global capacitor network needs to be considered, generating parasitic capacitance distribution network data, including a detailed description of the capacitive coupling relationships between nodes and the capacitor network structure in the circuit. Based on the parasitic capacitance distribution network data, a current flow simulation algorithm is used to identify the paths of current flow in the circuit. These paths reflect the power consumption hotspots and the direction of current flow in the circuit. Current tracing technology is used to track current paths from the power supply to the load and between each capacitor node, identifying the main current flow paths and generating current flow path feature data that describes the main paths, flow direction, and flow intensity of current in the circuit. Based on the current flow path feature data, critical path analysis is used to identify the paths that contribute the most to power consumption. Typically, these paths flow through the power supply, input pins, and main loads. When extracting critical paths, current density analysis can be used to identify paths with high current density, which contribute significantly to static power consumption. Factors such as capacitors, transistor characteristics, and input voltage can also be considered to further determine the most important current paths, generating critical path data that includes the main current flow paths affecting static power consumption. Based on the critical path data, performance bottlenecks are analyzed at which nodes, capacitors, or transistor components in the current flow. Power bottleneck analysis methods are used to assess which current paths exhibit current limitation and excessive power consumption under different operating conditions. Bottlenecks occur in areas of excessively high current density, nonlinear components, excessively high voltage areas, or excessively long current flow paths, generating bottleneck feature data that describes the location and cause of the power bottleneck. Based on bottleneck characteristic data, the power consumption of the circuit in its static state is calculated. At this point, the power consumption is determined by the capacitance of each node, leakage current, and the current density of the current path. Using a power consumption calculation model, the static power consumption of the circuit is obtained by comprehensively calculating factors such as current, power loss, and capacitive coupling in each current path. This yields the static power consumption data of the integrated circuit, i.e., the power consumption of each current path under static conditions.Extreme value extraction is performed on the static power consumption data of integrated circuits to find the lowest power consumption value, which is usually the minimum static power consumption under the conditions of optimal power supply voltage, input voltage, and current path. Data analysis methods (such as minimum value extraction and extreme value search algorithms) are used to extract the minimum value from the power consumption data and confirm the operating state corresponding to this minimum value, thus obtaining the lowest static power consumption data of the integrated circuit, i.e., the static power consumption under optimal conditions.

[0124] Preferably, step S4 includes the following steps:

[0125] Step S41: Upload the Class I integrated circuit marking data and Class II integrated circuit marking data to the cloud platform for circuit test data storage, and generate integrated circuit test storage data;

[0126] Step S42: Visualize the integrated circuit test storage data and generate an integrated circuit test storage report to execute the complete integrated circuit test job.

[0127] In this embodiment of the invention, the Class I and Class II integrated circuit tagging data are organized into a structured format, typically using JSON, XML, or CSV. The data format should include the following: the category of the integrated circuit tag (e.g., Class I, Class II), test parameter data (e.g., leakage current, power consumption, temperature, etc.), test timestamps, test environment, equipment information, etc. The data is preprocessed to ensure no missing values ​​before upload, and necessary cleaning and formatting are performed. A cloud platform that supports large-scale data storage and fast retrieval (e.g., AWS, Azure, Google Cloud) is selected. Data is uploaded using the data upload APIs provided by the cloud platform, such as AWS S3, Google Cloud Storage, and Azure Blob Storage. During the upload process, data security and encryption are ensured to prevent data loss or leakage. During data upload, the cloud platform's metadata storage functions (e.g., creating data tags or indexes) are utilized to quickly retrieve and manage data, generating integrated circuit test storage data, i.e., all Class I and Class II integrated circuit test data uploaded to and stored on the cloud platform. The test storage data is retrieved from storage using the cloud platform's data extraction interface (e.g., AWS Athena, Google BigQuery). Transform the data into a format suitable for visualization. This typically involves using Pandas or SQL to clean, normalize, and impute missing values. Ensure the data includes important metrics such as power consumption, temperature, voltage, and other test parameters, as well as classification labels for each type of integrated circuit. Use data visualization tools (such as Tableau, Power BI, Matplotlib in Python, or Seaborn) to visualize the integrated circuit test data.

[0128] This specification provides an integrated circuit testing system for performing the aforementioned integrated circuit testing method. The integrated circuit testing system includes:

[0129] The bias voltage setting module is used to acquire integrated circuit structure data; filter key nodes in the integrated circuit structure data to obtain power supply pins and input pins; set static bias voltages for the power supply pins and input pins to generate static bias voltage setting data; and acquire bias voltages from the static bias voltage setting data to obtain standard integrated circuit bias voltage acquisition data.

[0130] The power supply interference simulation module is used to superimpose low-amplitude, high-frequency noise sources onto the standard integrated circuit bias voltage acquisition data to obtain voltage acquisition noise data; to simulate power supply interference on the standard integrated circuit bias voltage acquisition data using the voltage acquisition noise data to generate circuit power supply interference simulation data; and to calculate the circuit parasitic index from the circuit power supply interference simulation data to obtain the actual parasitic data of the integrated circuit.

[0131] The layered testing module is used to perform leakage current testing on the bias voltage acquisition data of standard integrated circuits based on the actual parasitic data of integrated circuits, to obtain integrated circuit leakage current data; to perform extreme temperature testing on integrated circuits using the integrated circuit leakage current data, to obtain integrated circuit extreme temperature test data; and to batch mark integrated circuits based on the actual parasitic data of integrated circuits, integrated circuit leakage current data, and circuit extreme temperature test data, to generate Class I integrated circuit marking data and Class II integrated circuit marking data.

[0132] The data visualization module is used to upload Class I and Class II integrated circuit labeling data to the cloud platform for data visualization, generate integrated circuit test storage reports, and execute complete integrated circuit testing jobs.

[0133] The beneficial effects of this invention lie in ensuring that testing focuses on the most critical nodes by screening power supply and input pins of integrated circuit structure data, thereby improving the relevance and effectiveness of the data. It achieves unified setting of static bias voltage, generating high-quality standard bias voltage acquisition data, providing a stable reference benchmark for subsequent testing. By acquiring standardized bias voltage data, the impact of external interference on initial data is reduced, laying the foundation for the reliability of subsequent module test results. By superimposing low-amplitude, high-frequency noise sources, power supply interference in the actual working environment is simulated, enhancing the realism and comprehensiveness of the test. Through parasitic index calculation, the specific impact of parasitic effects on circuit performance is quantitatively analyzed, providing a scientific basis for optimized design and fault diagnosis. The generated circuit power supply interference simulation data helps evaluate the anti-interference capability of integrated circuits to different noise levels, improving product robustness. Combining leakage current testing and extreme temperature testing, the performance boundaries and reliability of integrated circuits under extreme conditions are comprehensively evaluated. Based on the integrated analysis of parasitic data, leakage current data, and temperature test data, circuit defects and potential risks can be deeply explored, improving test coverage. Batch marking of test results enables product classification management, supporting efficient quality control and rapid anomaly traceability. Uploading categorized and labeled data to the cloud platform simplifies the analysis and interpretation of complex test data through visualization, improving user experience. Stored reports support cross-departmental sharing and collaborative work, enhancing efficiency and transparency across the production chain. Data visualization and storage provide crucial data for subsequent product optimization and production process improvement, while also enhancing the traceability and management capabilities of testing work. Therefore, this invention improves the accuracy of circuit testing through key node screening, parasitic effect assessment, multi-dimensional data analysis, and cloud visualization.

[0134] Therefore, the embodiments should be considered as exemplary and non-limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of the equivalents of the application are intended to be included within the invention.

[0135] The above description is merely a specific embodiment of the present invention, enabling those skilled in the art to understand or implement the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the present invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features of the invention herein.

Claims

1. A method for testing integrated circuits, characterized in that, Includes the following steps: Step S1: Obtain integrated circuit structure data; perform key node screening on the integrated circuit structure data to obtain power supply pins and input pins; The power supply pins and input pins are set with static bias voltages to generate static bias voltage setting data; the static bias voltage setting data is then used to acquire bias voltage data to obtain standard integrated circuit bias voltage acquisition data. Step S2: Superimpose low-amplitude high-frequency noise sources onto the standard integrated circuit bias voltage acquisition data to obtain voltage acquisition noise data; simulate power supply interference on the standard integrated circuit bias voltage acquisition data using the voltage acquisition noise data to generate circuit power supply interference simulation data; The circuit parasitic index is calculated from the simulated circuit power supply interference data to obtain the actual parasitic data of the integrated circuit; wherein, step S2 includes the following steps: Step S21: Superimpose low-amplitude high-frequency noise sources on the standard integrated circuit bias voltage acquisition data to obtain voltage acquisition noise data; simulate power supply interference on the standard integrated circuit bias voltage acquisition data using the voltage acquisition noise data to generate circuit power supply interference simulation data. Step S22: Use an oscilloscope to measure the output waveform of the circuit power supply interference simulation data, and perform abnormal output response discrimination on the measured output waveform to obtain an abnormal output response discrimination strategy; Step S23: Adjust the signal frequency of the circuit power supply interference simulation data according to the abnormal output response discrimination strategy to generate a circuit power supply interference adjustment signal; Step S24: Perform cyclic power supply interference simulation on the standard integrated circuit bias voltage acquisition data using the circuit power supply interference adjustment signal to generate cyclic simulation data of circuit power supply interference; calculate the circuit parasitic index on the cyclic simulation data of circuit power supply interference to obtain the actual parasitic data of the integrated circuit; wherein, the calculation of the circuit parasitic index on the cyclic simulation data of circuit power supply interference includes: The integrated circuit structure data is screened for circuit transistor structure to obtain circuit transistor structure data; based on circuit power supply interference cycle simulation data, the circuit transistor structure data is analyzed for transistor threshold voltage variation to generate circuit transistor threshold voltage variation data. Based on the threshold voltage variation data of the circuit transistors, the gate length variation of the transistors in the integrated circuit is analyzed to generate transistor gate length variation data; parasitic effect test data of the integrated circuit is generated by using circuit power supply interference cycle simulation data. The actual parasitic index of the integrated circuit is calculated from the test data of the parasitic effect of the integrated circuit using the transistor gate length variation data. The formula for calculating the actual parasitic index of the integrated circuit is shown below: ； In the formula, Represented as actual parasitic data of integrated circuits, This is expressed as the coefficient representing the impact of capacitance on circuit performance. This is expressed as the coefficient representing the influence of resistance on circuit performance. Represented as a scaling factor, Represented as transistor width, This is expressed as the actual transistor gate length. This is expressed as the design length of the transistor gate. It is expressed as a constant representing the drain-source resistance. Represented as test values ​​for parasitic effects in integrated circuits; Step S3: Perform leakage current testing on the standard integrated circuit bias voltage acquisition data based on the actual parasitic data of the integrated circuit to obtain the integrated circuit leakage current data; perform extreme temperature testing on the integrated circuit using the integrated circuit leakage current data to obtain the integrated circuit extreme temperature test data; mark the integrated circuit batch based on the actual parasitic data of the integrated circuit, the integrated circuit leakage current data, and the circuit extreme temperature test data to generate Class I integrated circuit marking data and Class II integrated circuit marking data. Step S4: Upload the Class I and Class II integrated circuit tagging data to the cloud platform for data visualization, generate an integrated circuit test storage report, and execute the complete integrated circuit test job.

2. The integrated circuit testing method according to claim 1, characterized in that, Step S1 includes the following steps: Step S11: Obtain integrated circuit structure data; Step S12: Perform circuit pin analysis on the integrated circuit structure data to generate integrated circuit pin data; based on the integrated circuit pin data, perform key node screening on the integrated circuit structure data to obtain the key nodes of the integrated circuit, wherein the key nodes of the integrated circuit include power supply pins and input pins; Step S13: Set the static bias voltage for the power supply pin and input pin to generate static bias voltage setting data; use a voltage sensor to acquire the bias voltage from the static bias voltage setting data to obtain integrated circuit bias voltage acquisition data; Step S14: Perform data preprocessing on the integrated circuit bias voltage acquisition data to generate standard integrated circuit bias voltage acquisition data. The data preprocessing includes data cleaning, data denoising, data missing value filling, and data standardization.

3. The integrated circuit testing method according to claim 2, characterized in that, Setting the static bias voltage for power supply and input pins includes: Define the operating voltage range for the power supply pins to obtain the operating voltage range of the power supply pins; define the normal logic level range for the input pins to obtain the normal logic level range of the input pins. Based on the operating voltage range of the power supply pins and the normal logic level range of the input pins, the bias voltage range of key nodes of the integrated circuit is extended to generate bias voltage range extension data; based on the bias voltage range extension data, the test voltage step setting of key nodes of the integrated circuit is performed to generate a serialized list of test points. By setting the static bias voltage of the power supply pin and input pin according to the serialized list of test points based on the preset stabilization time, static bias voltage setting data is generated.

4. The integrated circuit testing method according to claim 1, characterized in that, The abnormal output response discrimination of the measured output waveform includes: The average value and standard deviation of the measured output waveform are calculated to obtain the average value and standard deviation of the output waveform; based on the average value and standard deviation of the output waveform, the measured output waveform is subjected to waveform amplitude anomaly discrimination to generate waveform amplitude anomaly discrimination data. Perform waveform timing analysis on the measured output waveform to generate output waveform timing data; based on the output waveform timing data, perform time delay over-limit judgment on the measured output waveform to generate waveform timing anomaly judgment data; The measured output waveform is analyzed to generate output waveform shape data; based on the output waveform shape data, the measured output waveform is subjected to waveform shape distortion discrimination to generate waveform shape anomaly discrimination data. Based on waveform amplitude anomaly discrimination data, waveform timing anomaly discrimination data, and waveform morphology anomaly discrimination data, abnormal output response discrimination is performed on the measured output waveform to obtain an abnormal output response discrimination strategy.

5. The integrated circuit testing method according to claim 1, characterized in that, Step S3 includes the following steps: Step S31: Perform minimum static power consumption analysis on the standard integrated circuit bias voltage acquisition data based on the actual parasitic data of the integrated circuit to generate minimum static power consumption data of the integrated circuit; perform leakage current test on the minimum static power consumption data of the integrated circuit to obtain leakage current data of the integrated circuit. Step S32: Perform extreme temperature tests on the integrated circuit using the integrated circuit leakage current data to obtain the integrated circuit extreme temperature test data; balance the test data based on the actual parasitic data of the integrated circuit, the integrated circuit leakage current data, and the integrated circuit extreme temperature test data to obtain the integrated circuit comprehensive evaluation index; Step S33: Compare the integrated circuit comprehensive evaluation index with the preset standard integrated circuit comprehensive evaluation threshold. When the integrated circuit comprehensive evaluation index is greater than or equal to the preset standard integrated circuit comprehensive evaluation threshold, the corresponding integrated circuit is batch-marked to generate a type of integrated circuit marking data. Step S34: When the integrated circuit comprehensive evaluation index is less than the preset standard integrated circuit comprehensive evaluation threshold, the corresponding integrated circuit is batch-marked to generate Class II integrated circuit marking data.

6. The integrated circuit testing method according to claim 5, characterized in that, The analysis of minimum static power consumption based on actual parasitic data of integrated circuits and standard integrated circuit bias voltage acquisition data includes: Node capacitance is measured from actual parasitic data of integrated circuits to generate node capacitance value data; distribution network modeling is performed on node capacitance value data to generate parasitic capacitance distribution network data. The parasitic capacitance distribution network data is used to identify the current flow path in the standard integrated circuit bias voltage acquisition data, generating current flow path feature data; the current flow path feature data is then used to extract the critical path, generating critical path data. Bottleneck analysis is performed on critical path data to generate bottleneck characteristic data; static power consumption calculation is performed on standard integrated circuit bias voltage acquisition data using bottleneck characteristic data to obtain integrated circuit static power consumption data; extreme values ​​are extracted from the integrated circuit static power consumption data to obtain the lowest static power consumption data of the integrated circuit.

7. The integrated circuit testing method according to claim 1, characterized in that, Step S4 includes the following steps: Step S41: Upload the Class I integrated circuit marking data and Class II integrated circuit marking data to the cloud platform for circuit test data storage, and generate integrated circuit test storage data; Step S42: Visualize the integrated circuit test storage data and generate an integrated circuit test storage report to execute the complete integrated circuit test job.

8. An integrated circuit testing system, characterized in that, The integrated circuit testing system for performing the integrated circuit testing method as described in claim 1 includes: The bias voltage setting module is used to acquire integrated circuit structure data; filter key nodes in the integrated circuit structure data to obtain power supply pins and input pins; set static bias voltages for the power supply pins and input pins to generate static bias voltage setting data; and acquire bias voltages from the static bias voltage setting data to obtain standard integrated circuit bias voltage acquisition data. The power supply interference simulation module is used to superimpose low-amplitude, high-frequency noise sources onto the standard integrated circuit bias voltage acquisition data to obtain voltage acquisition noise data; to simulate power supply interference on the standard integrated circuit bias voltage acquisition data using the voltage acquisition noise data to generate circuit power supply interference simulation data; and to calculate the circuit parasitic index from the circuit power supply interference simulation data to obtain the actual parasitic data of the integrated circuit. The layered testing module is used to perform leakage current testing on the bias voltage acquisition data of standard integrated circuits based on the actual parasitic data of integrated circuits, to obtain integrated circuit leakage current data; to perform extreme temperature testing on integrated circuits using the integrated circuit leakage current data, to obtain integrated circuit extreme temperature test data; and to batch mark integrated circuits based on the actual parasitic data of integrated circuits, integrated circuit leakage current data, and circuit extreme temperature test data, to generate Class I integrated circuit marking data and Class II integrated circuit marking data. The data visualization module is used to upload Class I and Class II integrated circuit labeling data to the cloud platform for data visualization, generate integrated circuit test storage reports, and execute complete integrated circuit testing jobs.

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