内存控制器发送命令的读写切换方法、装置及内存控制器
By dynamically determining the read/write switching time and optimizing the priority of operation commands, the problem of improper read/write switching timing in LPDDR5 is solved, improving data channel utilization and reducing latency, thus enhancing the performance of the memory controller.
CN120406820BActive Publication Date: 2026-07-17SOPHGO TECH LTD
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SOPHGO TECH LTD
- Filing Date
- 2025-03-07
- Publication Date
- 2026-07-17
AI Technical Summary
Technical Problem
Improper timing of the switching between read and write commands in LPDDR5 leads to reduced DDR data channel utilization and increased command latency.
Method used
By acquiring multiple operation commands and memory status from the preparation queue, the optimal read/write switching time is dynamically determined, the priority and quantity conditions of the operation commands are set, and the operation status of the memory is dynamically adjusted to optimize read/write switching.
Benefits of technology
It improves the utilization of DDR data channels, reduces command latency, and enhances the performance of the memory controller.
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Figure CN120406820B_ABST
Abstract
本申请提供一种内存控制器发送命令的读写切换方法、装置及内存控制器。该方法包括：获取多个命令的准备队列、多个存储块的读写状态、存储器的当前读写状态；动态地对存储器的读写状态进行更改，确定最优的读写切换时刻。本申请的方法可以优化读写命令切换的时机并减少读写命令切换所耗费的时间，从而提高DDR的数据通道利用率，并降低命令的延时。
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