Controller for solid state drive, control method and related device

Abstract

The present disclosure provides a controller, a control method and related devices for a solid state disk. The controller comprises at least one controller channel, each controller channel providing a plurality of data buses and a control bus, a plurality of flash memory particles connected to the control bus, and a plurality of data buses connected to the plurality of flash memory particles. Each controller channel comprises a control bus control unit for generating corresponding control instructions and transmitting the corresponding control instructions to the plurality of flash memory particles via the control bus; a data bus control unit for generating corresponding data instructions; and a data bus selection unit for generating a selection signal based on the host transmission requirements, and for time-divisionally turning on a group of data buses in the plurality of data buses according to the selection signal, and transmitting the corresponding data instructions to the corresponding flash memory particles via the turned-on group of data buses, so as to read and write data to the corresponding flash memory particles, thereby expanding the storage capacity and reducing the production cost.

Description

Technical Field

[0001] This disclosure belongs to the field of memory technology, and specifically relates to a controller, control method and related device for solid-state drives. Background Technology

[0002] Solid-state drives (SSDs) are hard drives made using solid-state electronic storage chips, comprising a controller and storage media. Currently, the most common SSDs use flash memory, such as non-volatile memory using flash memory chips (also known as NAND flash). The controller typically has multiple controller channels, and each controller channel can connect to multiple flash memory chips.

[0003] Figure 1 A schematic diagram of the structure of a solid-state drive (SSD) in related technologies is shown. For example... Figure 1 As shown, the solid-state drive 100 includes a controller 110 and a storage medium 120. The controller 110 includes at least one controller channel (e.g., CH0 to CHn, where n is an integer greater than or equal to 1). The storage medium 120 is, for example, a flash memory chip array. Multiple flash memory chips are mounted under each controller channel. The driving capability of each controller channel is limited, that is, the number of flash memory chips that can be mounted under each controller channel is limited. A common way to expand the storage capacity of an SSD is to increase the number of channels. However, for a large-capacity SSD that has already been designed, due to the bandwidth limitations of other modules (e.g., the host interface), the number of controller channels has reached its limit. In order to support a larger storage capacity, i.e., to control more flash memory chips, continuing to increase the number of channels will not continue to bring performance improvements, but will instead bring some adverse effects. On the one hand, increasing the number of channels will require integrating the control circuits and circuit layout of the corresponding channels inside the controller chip, which will lead to a significant increase in the chip area of ​​the controller and increase production costs. On the other hand, increasing the number of channels will require more wiring, interfaces and related components to support the corresponding channels on the printed circuit board (PCB), which will lead to a significant increase in the overall area of ​​the PCB, reduce production costs, reduce system integration and space utilization, and may bring a series of new challenges to system heat dissipation, electrical performance and other aspects. Summary of the Invention

[0004] In view of the above problems, this disclosure provides a controller, control method and related apparatus for solid-state drives, which aims to support large-capacity storage, reduce production costs and balance performance bandwidth and chip area cost.

[0005] According to a first aspect of this disclosure, a controller for a solid-state drive is provided, the solid-state drive including the controller and a storage medium, comprising:

[0006] At least one controller channel is provided, with multiple sets of flash memory chips in the storage medium connected to each controller channel. Each controller channel provides multiple data buses and one control bus. The multiple sets of flash memory chips are all connected to the one set of control buses, and the multiple sets of flash memory chips are respectively connected to the multiple sets of data buses.

[0007] Each of the controller channels includes:

[0008] A control bus control unit, connected to the set of control buses, is used to generate corresponding control commands and transmit the corresponding control commands to the multiple sets of flash memory chips via the set of control buses.

[0009] The data bus control unit is used to generate corresponding data commands;

[0010] The data bus selection unit, connected to the data bus control unit and the multiple sets of data buses, is used to generate a selection signal based on the host transmission requirements, and to turn on one set of data buses in a time-division multiplexing manner according to the selection signal, so as to transmit the corresponding data instruction to the corresponding flash memory chip via the turned-on set of data buses, so as to facilitate data reading and writing to the corresponding flash memory chip.

[0011] Optionally, if an additional data bus and a set of flash memory chips are added to the controller channel, the data bus selection unit is connected to the added data bus, and the added data bus is connected to the added set of flash memory chips.

[0012] The data bus selection unit is also used to turn on the additional set of data buses in a time-division manner according to the selection signal, and transmit the corresponding data instructions to the corresponding additional flash memory chips via the additional set of data buses, so as to facilitate data reading and writing to the corresponding additional flash memory chips.

[0013] Optionally, if a set of data buses and a set of flash memory chips are added to the controller channel, the set of control buses is connected to the added set of flash memory chips, and the control bus control unit is also used to transmit corresponding control commands to the added set of flash memory chips via the set of control buses.

[0014] Optionally, the bandwidth design of the additional set of data buses added to the controller channel is consistent with the bandwidth design of the multiple sets of data buses already set in the controller channel.

[0015] Optionally, if a set of data buses and a set of flash memory chips are deleted from the controller channel, the data bus selection unit is disconnected from the deleted set of data buses.

[0016] Optionally, if a set of data buses and a set of flash memory chips are deleted from the controller channel, the set of control buses is disconnected from the deleted set of flash memory chips.

[0017] According to a second aspect of this disclosure, a solid-state drive is provided, comprising:

[0018] Storage medium;

[0019] The controller includes at least one controller channel, each controller channel having multiple sets of flash memory chips from the storage medium connected to it. Each controller channel provides multiple data buses and a control bus. The multiple sets of flash memory chips are all connected to the control bus, and the multiple sets of flash memory chips are respectively connected to the multiple data buses.

[0020] Each of the controller channels includes:

[0021] A control bus control unit, connected to the set of control buses, is used to generate corresponding control commands and transmit the corresponding control commands to the multiple sets of flash memory chips via the set of control buses.

[0022] The data bus control unit is used to generate corresponding data commands;

[0023] The data bus selection unit, connected to the data bus control unit and the multiple sets of data buses, is used to generate a selection signal based on the host transmission requirements, and to turn on one set of data buses in a time-division multiplexing manner according to the selection signal, so as to transmit the corresponding data instruction to the corresponding flash memory chip via the turned-on set of data buses, so as to facilitate data reading and writing to the corresponding flash memory chip.

[0024] According to a third aspect of this disclosure, a control method for a controller of a solid-state drive is provided, the solid-state drive including the controller and a storage medium, the controller comprising:

[0025] At least one controller channel, each controller channel having multiple sets of flash memory chips in the storage medium connected thereto, each controller channel providing multiple sets of data buses and a set of control buses, the multiple sets of flash memory chips being connected to the set of control buses, the multiple sets of flash memory chips being connected to the multiple sets of data buses respectively, each controller channel including a control bus control unit connected to the set of control buses, a data bus control unit, and a data bus selection unit connected to the data bus control unit and the multiple sets of data buses;

[0026] The control method includes:

[0027] The control bus control unit generates corresponding control commands and transmits the corresponding control commands to the multiple sets of flash memory chips via the set of control buses.

[0028] The corresponding data instructions are generated by the data bus control unit;

[0029] The data bus selection unit generates a selection signal based on the host's transmission requirements. According to the selection signal, one group of data buses among the multiple groups of data buses is turned on in a time-division manner. The corresponding data instruction is transmitted to the corresponding flash memory chip through the turned-on group of data buses, so as to facilitate data reading and writing to the corresponding flash memory chip.

[0030] According to a fourth aspect of this disclosure, a control device for a controller of a solid-state drive is provided, the solid-state drive including the controller and a storage medium, the controller including:

[0031] At least one controller channel, each controller channel having multiple sets of flash memory chips in the storage medium connected thereto, each controller channel providing multiple sets of data buses and a set of control buses, the multiple sets of flash memory chips being connected to the set of control buses, the multiple sets of flash memory chips being connected to the multiple sets of data buses respectively, each controller channel including a control bus control unit connected to the set of control buses, a data bus control unit, and a data bus selection unit connected to the data bus control unit and the multiple sets of data buses;

[0032] The control device includes:

[0033] A control command transmission unit is used to generate corresponding control commands by the control bus control unit and transmit the corresponding control commands to the multiple sets of flash memory chips via the set of control buses.

[0034] A data instruction generation unit is used to generate corresponding data instructions from the data bus control unit.

[0035] The data instruction transmission unit is used to generate a selection signal based on the host transmission requirements by the data bus selection unit, and to turn on one of the multiple sets of data buses in a time-division manner according to the selection signal, and to transmit the corresponding data instruction to the corresponding flash memory chip through the turned-on set of data buses, so as to facilitate data reading and writing to the corresponding flash memory chip.

[0036] According to a fifth aspect of this disclosure, an electronic device is provided, comprising: a processor, a memory, and a program stored in the memory and executable on the processor, wherein the program, when executed by the processor, implements the steps of the method described above.

[0037] This disclosure brings the following beneficial effects:

[0038] The controller for solid-state drives disclosed herein supports the control of more flash memory chips and expands storage capacity by setting two or more data buses in each controller channel without adding a control bus, similar to increasing the number of controller channels. For already designed high-capacity SSDs, compared to adding controller channels, it reduces the physical layer of the control bus and, by adding a data bus selection unit between the physical layer and the protocol layer, eliminates the need to change the control bus control unit and the data bus control unit, thus reducing design complexity. It eliminates the need to integrate the control circuitry and wiring layout of the corresponding channels within the controller chip, reducing the controller chip area and manufacturing cost, balancing performance bandwidth with chip area cost. It eliminates the need for additional wiring, interfaces, and related components on the PCB to support the corresponding channels, reducing the overall PCB area and manufacturing cost, improving system integration and space utilization, and enhancing system performance in terms of heat dissipation and electrical performance.

[0039] Other features and advantages of this disclosure will be set forth in the following description and will be apparent in part from the description or may be learned by practicing the disclosure. The objects and other advantages of this disclosure are realized and obtained through the structures particularly pointed out in the description and the drawings.

[0040] To make the above-mentioned objects, features and advantages of this disclosure more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0041] The above and other objects, features and advantages of this disclosure will become clearer from the following description of embodiments with reference to the accompanying drawings, in which:

[0042] Figure 1 This diagram illustrates the structure of a solid-state drive (SSD) in the relevant technology.

[0043] Figure 2 This diagram illustrates the structure of a computer system according to an embodiment of the present disclosure;

[0044] Figure 3 This diagram illustrates the structure of a controller channel and a flash memory chip according to an embodiment of the present disclosure.

[0045] Figure 4 This diagram illustrates the structure of a controller channel according to an embodiment of the present disclosure;

[0046] Figure 5 A schematic flowchart of a control method for a solid-state drive according to an embodiment of the present disclosure is shown.

[0047] Figure 6 A schematic diagram of a control device for a solid-state drive according to an embodiment of the present disclosure is shown.

[0048] Figure 7 A schematic diagram of the structure of an electronic device provided according to an embodiment of the present disclosure is shown. Detailed Implementation

[0049] Various embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements are indicated by the same or similar reference numerals. For clarity, the various portions in the drawings are not drawn to scale.

[0050] The following terms are used in this document:

[0051] The controller channel is a set of physical pins in an SSD that connects the SSD's controller and the storage medium, and is responsible for receiving and transmitting data and commands.

[0052] Figure 2 A schematic diagram of the structure of a computer system according to an embodiment of the present disclosure is shown. Figure 2 As shown, the computer system 200 includes a host 210 and a solid-state drive (SSD). The SSD includes a controller 220 and a storage medium 230. The controller 220 is connected to the host 210 and is used to exchange data with the host 210. The controller 220 connects the host 210 and the storage medium 230 and stores the write data of the host 210 into the storage medium 230.

[0053] Controller 220 includes a host interface 221, a processor 222, a cache unit 223, a memory controller 224, and at least one controller channel (e.g., CH0 to CHn, where n is an integer greater than or equal to 1). The host interface 221 of controller 220 is connected to host 210 to transmit data and read / write instructions. Processor 222 is connected to host interface 221, cache unit 223, and memory controller 224. Processor 222 parses read / write instructions and executes read / write operations. Cache unit 223 is, for example, SRAM, used to store a mapping table. Memory controller 224 controls the transmission and storage of write data. Processor 222 also implements the core software layer for memory control, namely FTL (flash translation layer). FTL consists of several programs. Processor 222 executes these programs, enabling it to translate read / write instructions upon receipt, thereby completing access to storage medium 230. Therefore, the file system and operating system of host 210 can access the storage medium as if it were their own memory. This FTL also features bad block management, wear leveling, garbage collection, power-off recovery, and write balancing technologies.

[0054] Storage medium 230 is, for example, a flash memory chip array. To improve data read / write performance, memory controller 224 can read and write to the flash memory chips of storage medium 230 via controller channels. In some embodiments, the controller channel may employ a new flash memory interface protocol (e.g., Separate Command Address, SCA). The SCA protocol separates command / address and data transmission, placing them on two different transmission buses. Control commands (also known as Command and Address commands, CA commands) are transmitted on the control bus (CA bus), while data commands (also known as DATA commands, DQ commands) (i.e., data to be written to or read from the flash memory chips) are transmitted on the data bus (DQ bus). For example, control commands include CE, CLE, ALE, and WEN. For example, data commands include DQ, DBI, DQS, DQSn, REn, and RE. In some embodiments, multiple sets of flash memory chips are connected to each controller channel. Each set of flash memory chips includes multiple flash memory chips. Each controller channel provides multiple sets of data buses and one set of control buses, with each set of flash memory chips connected to that set of control buses. Multiple groups of flash memory chips are connected to multiple data buses. For example, in a high-capacity storage hard drive scenario, if controller 220 includes four controller channels and the storage capacity of a single flash memory chip is 128 GB, then to achieve an 8 TB storage capacity, storage medium 230 would require 16 flash memory chips connected to each controller channel. These 16 flash memory chips can be divided into two groups, each containing four flash memory chips. These 16 flash memory chips can be connected to one control bus, and the two groups of flash memory chips can be connected to their respective data buses. Figure 3 A schematic diagram of the structure of a controller channel and a flash memory chip according to an embodiment of the present disclosure is shown. Figure 3 As shown, controller channel CH0 is connected to four groups of flash memory chips, namely flash memory chip Group0 to flash memory chip Group3. Controller channel CH0 provides four data buses (i.e., DQ BUS 0 to DQ BUS 3) and one control bus (i.e., CA BUS). Flash memory chips Group0 to Group3 are all connected to and share this control bus. Flash memory chips Group0 to Group3 correspond to DQ BUS 0 to DQ BUS 3, with each group of flash memory chips connected to its corresponding data bus. In some embodiments, at the required operating speed of the product, if the maximum number of flash memory chips that a controller channel can drive is A, and the maximum drive capability of a data bus is B, then the number of data bus groups set in a controller channel is the rounded-up result of (A / B).

[0055] Figure 4A schematic diagram of the structure of a controller channel provided according to an embodiment of the present disclosure is shown. Figure 3 As shown, controller channel 300 communicates with host interface 221. Controller channel 300 includes a transport layer 350, a protocol layer 360, and a physical layer 340. Protocol layer 360 includes a control bus management unit 310 and a data bus management unit 320. Physical layer 340 includes multiple sets of data buses (e.g., DQ BUS 0 to DQ BUS 3) and a set of control buses (e.g., CA BUS). In some embodiments, controller channel 300 further includes a data bus selection unit 330. Data bus selection unit 330 is located between protocol layer 360 and physical layer 340.

[0056] In some embodiments, the control bus control unit 310 is connected to the set of control buses and is used to generate corresponding control commands and transmit the corresponding control commands to the multiple sets of flash memory chips via the set of control buses. The data bus control unit 320 generates corresponding data commands. The data bus selection unit 330 is connected to the data bus control unit 310 and the multiple sets of data buses and is used to generate a selection signal based on the host transmission requirements. According to the selection signal, one set of data buses in the multiple sets of data buses is turned on in a time-division multiplexing manner, and the corresponding data command is transmitted to the corresponding flash memory chip via the turned-on data bus (e.g., DQ BUS 0) to facilitate data read and write operations on the corresponding flash memory chip. It can be understood that by setting two or more sets of data buses in each controller channel without adding control buses, it is possible to support the control of more flash memory chips and realize the expansion of storage capacity, just like increasing the number of controller channels. Selecting the corresponding data bus to be turned on according to the selection signal and setting the other data buses to a low-power mode and temporarily not working can reduce power consumption.

[0057] Understandably, for a pre-designed high-capacity SSD, compared to adding controller channels, it reduces the need for a physical layer of the control bus. Furthermore, by adding a data bus selection unit between the physical and protocol layers, there's no need to modify the control bus control unit and data bus control unit, thus reducing design complexity. It eliminates the need to integrate the corresponding channel's control circuitry and wiring layout within the controller chip, reducing chip area and manufacturing costs. This effectively simplifies the complex PCB layout, allowing for a reduction in the number of layers in a PCB design that previously required multiple layers due to dense wiring. This reduces PCB design complexity and overall area, lowering raw material and processing costs in manufacturing, as well as potential debugging costs due to design complexity. It also improves system integration and space utilization, and enhances system performance in areas such as heat dissipation and electrical performance.

[0058] In some embodiments, when an additional data bus and a set of flash memory chips are added to the controller channel, the data bus selection unit 330 is connected to the added data bus, the added data bus is connected to the added set of flash memory chips, and a control bus is connected to the added set of flash memory chips. The data bus selection unit 330 also time-divisionally activates the added data bus according to a selection signal, transmitting corresponding data instructions via the added data bus to the corresponding added flash memory chips to facilitate data read / write operations on the corresponding added flash memory chips. The control bus control unit 310 also transmits corresponding control instructions via a control bus to the added set of flash memory chips. It is understood that because the control bus has a lower I / O rate, it can drive more flash memory chips, and flash memory chips connected to the same controller channel can share the control bus. Understandably, the flash memory chips originally mounted on a single controller channel can be divided into multiple groups, with each data bus connecting one group of flash memory chips. This ensures the data bus transmission rate, reduces the load on the data bus, effectively distributes the load pressure originally concentrated on a single data bus, and significantly reduces the number of flash memory chips connected to each data bus. The reduced load on each data bus creates favorable conditions for increasing the data bus speed, enabling data transmission to operate at higher rates. In some embodiments, the bandwidth design of the additional data bus group for the controller channel is consistent with the bandwidth design of the multiple data buses already set in the controller channel. Understandably, without modifying the physical layer and protocol layer of the controller channel, the storage capacity of the solid-state drive can be expanded by adding a group of data buses and a group of flash memory chips to the controller channel, reducing design complexity. By simply adding a data bus, rather than adding a complete controller channel, only a small number of pins are added, balancing performance bandwidth and chip area cost.

[0059] In some embodiments, when a set of data buses and a set of flash memory chips are removed from the controller channel, the data bus selection unit 330 is disconnected from the removed set of data buses, and a set of control buses is disconnected from the removed set of flash memory chips. It is understood that the storage capacity of the solid-state drive (SSD) can be changed by removing a set of data buses and a set of flash memory chips from the controller channel without modifying the physical and protocol layers of the controller channel, making the storage capacity design of the SSD more flexible.

[0060] Figure 5This diagram illustrates a flow chart of a control method for a solid-state drive (SSD) according to an embodiment of the present disclosure. The SSD includes a controller and a storage medium. The controller includes at least one controller channel, each controller channel having multiple sets of flash memory chips in the storage medium mounted thereon. Each controller channel provides multiple data buses and a control bus. The multiple sets of flash memory chips are all connected to the control bus, and the multiple sets of flash memory chips are respectively connected to the multiple data buses. Each controller channel includes a control bus control unit connected to the control bus, a data bus control unit, and a data bus selection unit connected to the data bus control unit and the multiple data buses. Figure 5 As shown, the control method of this disclosure embodiment may include:

[0061] In step S510, the control bus control unit generates a corresponding control command and transmits the corresponding control command to the multiple sets of flash memory chips via the set of control buses.

[0062] In step S520, the data bus control unit generates corresponding data instructions.

[0063] In step S530, the data bus selection unit generates a selection signal based on the host transmission requirements. According to the selection signal, one group of data buses among the multiple groups of data buses is turned on in a time-division manner, and the corresponding data instruction is transmitted to the corresponding flash memory chip through the turned-on group of data buses, so as to facilitate data reading and writing to the corresponding flash memory chip.

[0064] Since the process of controlling the controller using the control method of this disclosure has been described in detail in the above device embodiments, it will not be repeated here.

[0065] Figure 6 A schematic diagram of a control device for a solid-state drive (SSD) according to an embodiment of the present disclosure is shown. The SSD includes a controller and a storage medium. The controller includes: at least one controller channel, each controller channel having multiple sets of flash memory chips in the storage medium connected thereto. Each controller channel provides multiple data buses and a control bus. The multiple sets of flash memory chips are all connected to the control bus, and the multiple sets of flash memory chips are respectively connected to the multiple data buses. Each controller channel includes a control bus control unit connected to the control bus, a data bus control unit, and a data bus selection unit connected to the data bus control unit and the multiple data buses. Figure 6 As shown, the control device 600 includes:

[0066] The control command transmission unit 610 is used to generate corresponding control commands by the control bus control unit and transmit the corresponding control commands to the multiple sets of flash memory chips via the set of control buses.

[0067] The data instruction generation unit 620 is used to generate corresponding data instructions from the data bus control unit.

[0068] The data instruction transmission unit 630 is used to generate a selection signal based on the host transmission requirements by the data bus selection unit, and to turn on one of the multiple sets of data buses in a time-division manner according to the selection signal, so as to transmit the corresponding data instruction to the corresponding flash memory chip via the turned-on set of data buses, so as to facilitate data reading and writing to the corresponding flash memory chip.

[0069] Since the process of controlling the controller using the control method of this disclosure has been described in detail in the above device embodiments, it will not be repeated here.

[0070] This disclosure also provides an electronic device, such as... Figure 7 As shown, it includes a memory 720, a processor 710, and a program stored in the memory 720 and executable on the processor 710. When the program is executed by the processor 710, it can implement the various processes of the embodiments of the above methods and achieve the same technical effect. To avoid repetition, it will not be described again here.

[0071] Those skilled in the art will understand that all or part of the steps in the various methods of the above embodiments can be implemented by instructions, or by instructions controlling related hardware. These instructions can be stored in a computer-readable storage medium and loaded and executed by a processor. Therefore, this disclosure also provides a storage medium storing a computer program or instructions that, when executed by a processor, can implement the various processes of the embodiments of the above methods.

[0072] Since the instructions stored in the storage medium can execute the steps of the method provided in the embodiments of this disclosure, the beneficial effects achievable by the method provided in the embodiments of this disclosure can be realized, as detailed in the preceding embodiments, and will not be repeated here. Specific implementations of the above operations can be found in the preceding embodiments, and will not be repeated here.

[0073] In summary, the controller for solid-state drives provided in this disclosure, by setting two or more data buses on each controller channel without adding a control bus, can support the control of more flash memory chips and achieve storage capacity expansion, much like increasing the number of controller channels. For already designed high-capacity SSDs, compared to adding controller channels, it reduces the physical layer of the control bus, and by adding a data bus selection unit between the physical layer and the protocol layer, it eliminates the need to change the control bus control unit and the data bus control unit, thus reducing design complexity. It eliminates the need to integrate the control circuitry and wiring layout of the corresponding channels within the controller chip, reducing the controller chip area and manufacturing cost. It eliminates the need for additional wiring, interfaces, and related components on the PCB to support the corresponding channels, reducing the overall PCB area and manufacturing cost, improving system integration and space utilization, and enhancing system performance in terms of heat dissipation and electrical performance.

[0074] Finally, it should be noted that the above embodiments are merely examples for clearly illustrating this disclosure and are not intended to limit the implementation. Those skilled in the art can make other variations or modifications based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of this disclosure.

Claims

1. A controller for a solid-state drive, the solid-state drive including the controller and a storage medium, comprising: At least one controller channel is provided, with multiple sets of flash memory chips in the storage medium connected to each controller channel. Each controller channel provides multiple data buses and one control bus. The multiple sets of flash memory chips are all connected to the one set of control buses, and the multiple sets of flash memory chips are respectively connected to the multiple sets of data buses. Each of the controller channels includes: A control bus control unit, connected to the set of control buses, is used to generate corresponding control commands and transmit the corresponding control commands to the multiple sets of flash memory chips via the set of control buses. The data bus control unit is used to generate corresponding data commands; The data bus selection unit, connected to the data bus control unit and the multiple sets of data buses, is used to generate a selection signal based on the host transmission requirements, and to turn on one set of data buses in a time-division multiplexing manner according to the selection signal, so as to transmit the corresponding data instruction to the corresponding flash memory chip via the turned-on set of data buses, so as to facilitate data reading and writing to the corresponding flash memory chip.

2. The controller according to claim 1, wherein, When an additional data bus and a set of flash memory chips are added to the controller channel, the data bus selection unit is connected to the added data bus, and the added data bus is connected to the added set of flash memory chips. The data bus selection unit is also used to turn on the additional set of data buses in a time-division manner according to the selection signal, and transmit the corresponding data instructions to the corresponding additional flash memory chips via the additional set of data buses, so as to facilitate data reading and writing to the corresponding additional flash memory chips.

3. The controller according to claim 2, wherein, When a set of data buses and a set of flash memory chips are added to the controller channel, the set of control buses is connected to the added set of flash memory chips, and the control bus control unit is also used to transmit corresponding control commands to the added set of flash memory chips via the set of control buses.

4. The controller according to claim 3, wherein, The bandwidth design of the additional data bus added to the controller channel is consistent with the bandwidth design of the multiple data buses already set in the controller channel.

5. The controller according to claim 2, wherein, In the event that a set of data buses and a set of flash memory chips are deleted from the controller channel, the data bus selection unit is disconnected from the deleted set of data buses.

6. The controller according to claim 5, wherein, In the event that a set of data buses and a set of flash memory chips are deleted from the controller channel, the set of control buses will be disconnected from the deleted set of flash memory chips.

7. A solid-state drive, comprising: Storage medium; The controller includes at least one controller channel, each controller channel having multiple sets of flash memory chips from the storage medium connected to it. Each controller channel provides multiple data buses and a control bus. The multiple sets of flash memory chips are all connected to the control bus, and the multiple sets of flash memory chips are respectively connected to the multiple data buses. Each of the controller channels includes: A control bus control unit, connected to the set of control buses, is used to generate corresponding control commands and transmit the corresponding control commands to the multiple sets of flash memory chips via the set of control buses. The data bus control unit is used to generate corresponding data commands; The data bus selection unit, connected to the data bus control unit and the multiple sets of data buses, is used to generate a selection signal based on the host transmission requirements, and to turn on one set of data buses in a time-division multiplexing manner according to the selection signal, so as to transmit the corresponding data instruction to the corresponding flash memory chip via the turned-on set of data buses, so as to facilitate data reading and writing to the corresponding flash memory chip.

8. A control method for a controller of a solid-state drive, the solid-state drive including the controller and a storage medium, the controller comprising: At least one controller channel, each controller channel having multiple sets of flash memory chips in the storage medium connected thereto, each controller channel providing multiple sets of data buses and a set of control buses, the multiple sets of flash memory chips being connected to the set of control buses, the multiple sets of flash memory chips being connected to the multiple sets of data buses respectively, each controller channel including a control bus control unit connected to the set of control buses, a data bus control unit, and a data bus selection unit connected to the data bus control unit and the multiple sets of data buses; The control method includes: The control bus control unit generates corresponding control commands and transmits the corresponding control commands to the multiple sets of flash memory chips via the set of control buses. The corresponding data instructions are generated by the data bus control unit; The data bus selection unit generates a selection signal based on the host's transmission requirements. According to the selection signal, one group of data buses among the multiple groups of data buses is turned on in a time-division manner. The corresponding data instruction is transmitted to the corresponding flash memory chip through the turned-on group of data buses, so as to facilitate data reading and writing to the corresponding flash memory chip.

9. A control device for a controller of a solid-state drive, the solid-state drive including the controller and a storage medium, the controller comprising: At least one controller channel, each controller channel having multiple sets of flash memory chips in the storage medium connected thereto, each controller channel providing multiple sets of data buses and a set of control buses, the multiple sets of flash memory chips being connected to the set of control buses, the multiple sets of flash memory chips being connected to the multiple sets of data buses respectively, each controller channel including a control bus control unit connected to the set of control buses, a data bus control unit, and a data bus selection unit connected to the data bus control unit and the multiple sets of data buses; The control device includes: A control command transmission unit is used to generate corresponding control commands by the control bus control unit and transmit the corresponding control commands to the multiple sets of flash memory chips via the set of control buses. A data instruction generation unit is used to generate corresponding data instructions from the data bus control unit. The data instruction transmission unit is used to generate a selection signal based on the host transmission requirements by the data bus selection unit, and to turn on one of the multiple sets of data buses in a time-division manner according to the selection signal, and to transmit the corresponding data instruction to the corresponding flash memory chip through the turned-on set of data buses, so as to facilitate data reading and writing to the corresponding flash memory chip.

10. An electronic device, comprising: A processor, a memory, and a program stored in the memory and executable on the processor, wherein the program, when executed by the processor, implements the steps of the method as described in claim 8.

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