指令数据预取方法、装置、设备、存储介质及程序产品
By using a block-based instruction prefetcher and table structure, the problems of CPU blocking and low cache utilization caused by instruction cache access failures are solved, achieving more efficient instruction data prefetching and cache utilization.
CN120407021BActive Publication Date: 2026-07-17SOPHGO TECH LTD
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SOPHGO TECH LTD
- Filing Date
- 2025-03-11
- Publication Date
- 2026-07-17
AI Technical Summary
Technical Problem
Existing instruction caching techniques can cause CPU blocking when access fails, and existing prefetching techniques have low accuracy for complex program structures, resulting in reduced cache utilization.
Method used
By obtaining the access address of the instruction, utilizing the block-based instruction prefetcher and table structure, the physical address of the instruction data is determined, and a prefetch request is sent to obtain the instruction data, thereby improving the accuracy of prefetching and cache utilization.
Benefits of technology
It improves the accuracy of instruction data prefetching, reduces access latency, increases cache utilization, and reduces cache miss rate.
✦ Generated by Eureka AI based on patent content.
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Figure CN120407021B_ABST
Abstract
本公开提供一种指令数据预取方法、装置、设备、存储介质及程序产品。该方法包括：获取第一指令的访问地址，其中，第一指令为需要进行数据预取的指令；在访问地址存在对应的第一表项的情况下，根据第一表项，确定第一指令关联的第一指令数据的物理地址，其中，第一指令数据与当前缓存中的数据不同；根据第一指令数据的物理地址，发送预取请求，以获得第一指令数据。如此，根据第一指令的访问地址对应的第一表项获取与第一指令关联的第一指令数据，相对于按照顺序进行数据预取，能够提高预取的数据的准确性，降低访问延迟，提高缓存的利用率。
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