Control device for direct memory access and control method thereof

Abstract

The application provides a direct memory access control device and a control method thereof, and relates to the technical field of data storage. The direct memory access control device comprises a temporary storage for temporarily storing data blocks of data to be transmitted; a counter for counting the data amount of the data blocks stored in the temporary storage and outputting a count value when a preset ending condition is met; a write controller for writing the data blocks stored in the temporary storage into a target storage module according to an initial write address calculated in a previous batch; and a write address updating module for obtaining an initial write address calculated in a current batch according to the initial write address calculated in the previous batch and the count value. According to the technical scheme of the application, the temporary storage is used for data interception, the counter is used for counting, the write controller is used for batch transmission according to the calculated write address, and the write address updating module is used for calculating the write address, so that the data amount is not required to be explicitly determined in advance, the efficiency is high, and the cost is low.

Description

Technical Field

[0001] This invention relates to the field of data storage technology, and more specifically to a control device and control method for direct memory access. Background Technology

[0002] Currently, DMA (Direct Memory Access) is a common feature in chip bus architectures. It allows direct access to memory and peripherals without CPU intervention or with minimal CPU usage, freeing up the CPU to handle other tasks and significantly improving data throughput and system efficiency. To implement DMA functionality, a dedicated DMA controller (DMAC) is typically required. The host (the on-chip CPU or an external control interface such as PCIe) controls the DMAC to transfer data between memory and peripherals.

[0003] For write operations with a known amount of data, the DMAC transfers data between memory or peripherals based on the host's configuration. However, if the amount of data is unknown, the host cannot correctly configure the Write DMA Master because the host itself does not know how much data to write, and consequently, the Write DMA Master cannot generate the correct hardware operation.

[0004] Taking systems with dynamic compression or decompression capabilities as an example, the result of dynamic compression or decompression may be related to the input real-time data. Even if the input data volume is the same, if the data is not completely consistent, the output data volume may be different. This means that the host cannot obtain the amount of data to be output in advance. If DMA is controlled by configuring commands on the host, the host must first perform the same dynamic compression processing on the input real-time data in order to determine the output data volume. Obviously, this will put a lot of additional pressure on the system. The more data there is, the more time and resources the system has to consume for compression processing, and the purpose is only to obtain a value. Obviously, the input-output ratio is very low, resulting in low efficiency and high cost. Summary of the Invention

[0005] Based on this, the present invention provides a control device and control method for direct memory access, which realizes data transmission with high efficiency and low cost.

[0006] According to one aspect of the present invention, a direct memory access control device is provided, comprising: a temporary memory for temporarily storing data blocks of data to be transmitted; a counter for counting the amount of data in the data blocks stored in the temporary memory and outputting a count value when a preset termination condition is met; a write controller for writing the data blocks stored in the temporary memory into a target memory module according to the initial write address calculated in the previous batch; and a write address update module for obtaining the initial write address calculated in the current batch according to the initial write address calculated in the previous batch and the count value.

[0007] According to some embodiments, the temporary memory includes a first temporary memory and a second temporary memory, and the counter includes a first counter and a second counter; wherein, the first counter is used to count the amount of data in the data block stored in the first temporary memory, and outputs the count value of the first counter as a first count value when a preset end condition is met; the second counter is used to count the amount of data in the data block stored in the second temporary memory, and outputs the count value of the second counter as a second count value when a preset end condition is met.

[0008] According to some embodiments, the apparatus further includes: a demultiplexer, configured to: switch the data storage path of a data block when the temporary storage is full; and specify the data storage path of a data block when each temporary storage is empty, wherein the data storage path is a corresponding data storage path in the temporary storage; and a multiplexer, configured to: switch the data source path written to the target storage module when the temporary storage is empty; and specify the data source path of a data block when each temporary storage is full, wherein the data source path is a corresponding data source path in the temporary storage.

[0009] According to some embodiments, the capacity of the temporary memory is the maximum amount of data that can be supported in a single hardware bus operation.

[0010] According to some embodiments, the preset termination condition is that the count value reaches a preset threshold or all data transmission is detected to be complete.

[0011] According to one aspect of the present invention, a direct memory access control method includes: S1: activating a direct memory access control device to acquire data to be transmitted; S2: storing the data to be transmitted byte by byte into a current temporary memory, and counting using a current counter corresponding to the current temporary memory; S3: outputting a count value when the count value of the current counter reaches a preset threshold; S4: when the current batch is 1, writing the data block stored in the current temporary memory into a target storage module according to a pre-configured initial write address, obtaining the initial write address calculated for the current batch according to the pre-configured initial write address and the count value, and determining whether all data has been transmitted. If yes, proceed to S6; otherwise, proceed to the next step; S5: when the current batch is greater than 1, writing the data block stored in the current temporary memory into the target storage module according to the initial write address calculated for the previous batch, and obtaining the initial write address calculated for the current batch according to the initial write address calculated for the previous batch and the count value; S6: repeating steps S2-S5 until all data transmission is completed.

[0012] According to some embodiments, before step S2, the method further includes: determining the current data storage path using a demultiplexer; and using the temporary storage corresponding to the current data storage path as the current temporary storage.

[0013] According to some embodiments, before step S6, the method further includes: using a demultiplexer to determine the current data source path; and using the temporary storage corresponding to the current data source path as the current temporary storage.

[0014] According to one aspect of the present invention, an electronic device is provided, comprising: one or more processors; a storage device for storing one or more programs; and, when the one or more programs are executed by the one or more processors, causing the one or more processors to implement the method described above.

[0015] According to one aspect of the invention, a computer-readable medium is provided having a computer program stored thereon, which, when executed by a processor, implements the method described above.

[0016] Through the embodiments provided by this invention, temporary memory is used to store data blocks of data to be transmitted, a counter is used to count the amount of data transmitted in each batch, and the temporary memory is used to count the amount of data while intercepting data; the write controller is used to complete the write operation based on the initial write address calculated in the previous batch, and the initial write address of the current batch is obtained from the previous batch, which can realize uninterrupted batch transmission; the write address update module is used to calculate the initial write address of the current batch based on the initial write address calculated in the previous batch and the count value, and the address configuration information is dynamically generated in real time based on the dynamic temporary memory. This invention realizes data transmission without needing to know the amount of data in advance, which is highly efficient and low-cost. Attached Figure Description

[0017] It should be understood that the above general description and the following detailed description are merely exemplary and do not limit the invention.

[0018] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without exceeding the scope of protection claimed by the present invention.

[0019] Figure 1 One of the block diagrams of a control device for direct memory access provided in an embodiment of the present invention;

[0020] Figure 2 The diagram below shows the read and write operations of direct memory access in the background technology.

[0021] Figure 3 A second block diagram of a control device for direct memory access provided in an embodiment of the present invention;

[0022] Figure 4 A schematic diagram of the first batch of data transmission provided for an embodiment of the present invention;

[0023] Figure 5 A schematic diagram of the second batch of data transmission provided in an embodiment of the present invention;

[0024] Figure 6 A schematic diagram of the third batch of data transmission provided in an embodiment of the present invention;

[0025] Figure 7 This is a schematic diagram of the storage area distribution after a write operation is completed, provided in an embodiment of the present invention.

[0026] Figure 8 A flowchart illustrating the direct memory access control method provided in this embodiment of the invention;

[0027] Figure 9 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present invention.

[0028] Figure label:

[0029] 110: Temporary memory; 111: First temporary memory; 112: Second temporary memory; 120: Counter; 121: First counter; 122: Second counter; 130: Write controller; 140: Write address update module; 150: Demultiplexer; 160: Multiplexer. Detailed Implementation

[0030] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0031] Furthermore, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Numerous specific details are provided in the following description to give a full understanding of embodiments of the invention. However, those skilled in the art will recognize that the technical solutions of the invention can be practiced without one or more of the specific details, or other methods, components, apparatuses, steps, etc., can be employed. In other instances, well-known methods, apparatuses, implementations, or operations are not shown or described in detail to avoid obscuring various aspects of the invention.

[0032] The block diagrams shown in the accompanying drawings are merely functional entities and do not necessarily correspond to physically independent entities. That is, these functional entities can be implemented in software, in one or more hardware modules or integrated circuits, or in different network and / or processor devices and / or microcontroller devices.

[0033] The flowcharts shown in the accompanying drawings are merely illustrative and do not necessarily include all content and operations / steps, nor do they necessarily have to be performed in the described order. For example, some operations / steps can be broken down, while others can be combined or partially combined; therefore, the actual execution order may change depending on the specific circumstances.

[0034] It should be understood that although the terms first, second, third, etc., may be used herein to describe various components, these components should not be limited by these terms. These terms are used to distinguish one component from another. Therefore, the first component discussed below may be referred to as the second component without departing from the teachings of the present invention. As used herein, the term "and / or" includes all combinations of any one and more of the associated listed items.

[0035] First, let's explain the background technology. A DMAC (Direct Memory Access Controller) implements data reading and writing, typically divided into independent read and write functions, as illustrated in the simplified diagram below. Figure 2 As shown.

[0036] Figure 2The chip internally includes a CPU (Central Processing Unit), an IP (Intellectual Property Core), a DDR IP (Double Data Rate Intellectual Property Core), and an on-chip bus. Path 1 represents the configuration path, path 2 represents the data path, and DDR refers to DDR (Double Data Rate SDRAM) peripheral chips. The DMAC in the diagram stands for DMA Master. The master signifies the ability to actively initiate data communication, typically responsible for translating software commands into hardware bus operations. Correspondingly, there exists a DMA Slave, located opposite the master. The slave passively receives hardware bus operations from the master and accesses data from the DDR or peripherals based on these operations. For example, a DMA Slave exists within the DDR IP in the diagram above.

[0037] If IP A needs to read data from the DDR chip, the Host (the CPU on the chip) can first control the DMAC to transfer data between memory and peripherals. Configuring IP A's DMAC using path 1 can also be considered as simply configuring the Read DMA Master. Under this configuration, the DMAC uses path 2 through the on-chip bus and the DDR IP to finally retrieve the data from the DDR chip; this is one DMA read data process.

[0038] If IP A needs to write data to the DDR chip, the Host (the CPU on the chip) can first configure IP A's DMAC using path 1. Alternatively, it can be considered that only Write DMA Master needs to be configured at this time. Under the control of this configuration, DMAC uses path 2 through the on-chip bus and DDR IP to finally write the data to the DDR chip. This is a DMA write data process.

[0039] In other words, to write data to DDR or other peripherals, at least two things must be clear: the amount of data to be written and the address of the region to be written, i.e., the memory address. During the actual writing process, the host typically configures the data amount, memory address, and other relevant information to the Write DMA Master via software commands. Based on these configurations and other relevant information (such as the address change method, determined by the specific hardware bus protocol), the Write DMA Master translates the write command into a hardware bus operation, such as the AXI protocol's write operation. That is, the Write DMA Master encapsulates the raw data in the hardware bus interface and writes it out.

[0040] If the amount of data is unknown, the Host cannot properly configure the Write DMA Master, and consequently, the Write DMA Master cannot generate the correct hardware operations.

[0041] Based on this, the present invention proposes a control device and control method for direct memory access.

[0042] For specific implementation details, please refer to the following examples.

[0043] Figure 1 A block diagram of a direct memory access control device provided in an embodiment of the present invention. Figure 1 As shown, the device includes a temporary memory 110, a counter 120, a write controller 130, and a write address update module 140.

[0044] Temporary memory 110 is used to temporarily store data blocks of data to be transmitted.

[0045] The temporary storage 110 can be any storage device that facilitates data storage and retrieval. According to an example embodiment, the temporary storage 110 can be RAM (Random Access Memory).

[0046] Furthermore, the number of temporary memories 110 can be one or more. When a temporary memory 110 is set up, all data is sequentially input / output to this memory. To maintain the continuity of the overall transmission and improve transmission efficiency, two or more temporary memories 110 can be set up.

[0047] The data to be transmitted is data that needs to be written to DDR or other peripherals. It can be the original data transmitted from the previous system, or the original data transmitted from the previous system, which is then processed by the system's required data processing module (e.g., dynamic compression or decompression) to obtain new data. This invention does not limit this.

[0048] The data to be transmitted is transmitted byte by byte to the temporary storage 110. Due to the limited capacity of the temporary storage 110, multiple data blocks are formed. Each data block is a portion of the data to be transmitted stored in the temporary storage 110 in each transmission batch.

[0049] Counter 120 is used to count the amount of data in the data block stored in temporary memory 110, and outputs the count value when the preset termination condition is met.

[0050] In order to obtain the amount of data in the temporary memory 110, a corresponding counter 120 must be added to the temporary memory 110 to count the inputs to the temporary memory 110.

[0051] It should be noted that the initial count of counter 120 is 0. Each time a byte of data enters the temporary memory 110, counter 120 is incremented by 1 until the preset end condition is met, at which point it is reset to zero.

[0052] The write controller 130 is used to write the data block stored in the temporary memory 110 to the target memory module according to the initial write address calculated in the previous batch.

[0053] The main configuration for the write controller 130 to perform hardware write operations comes from the initial write address calculated in the previous batch, and the write data comes from the temporary memory 110.

[0054] If the current batch is 1, since there is no previous batch, the initial write address calculated by the previous batch is fixed as the initial write address configured by the Host. If the current batch is greater than 1, the initial write address calculated by the previous batch is used as the address for the current write operation.

[0055] Furthermore, the initial write address calculated in the previous batch is obtained based on the count value of counter 120 in the previous batch (t-1 batch) and the initial write address calculated in the batch before that (t-2 batch).

[0056] According to the example embodiment, the write controller 130 is a Write DMA Master.

[0057] The write address update module 140 is used to obtain the initial write address calculated for the current batch based on the initial write address and count value calculated in the previous batch.

[0058] As the temporary memory 110 outputs data to be written in turn, the count value is also synchronously output to the write address update module 140. The write address update module 140 updates the storage address of the DMA write operation based on the initial address configured by the host and the amount of data in the temporary memory 110 each time (i.e., the count value). The updated address is used for the next write operation. It should be emphasized that the initial write address of the current batch of write operations in this invention is calculated from the previous batch, thereby achieving uninterrupted batch transmission.

[0059] According to the example implementation, the initial write address calculated in the previous batch is X, the counter 120 starts from 0 and ends at 4KB-1, then the initial write address calculated in the current batch is X+4096.

[0060] This invention stores data blocks of data to be transmitted in a temporary memory, uses a counter to count the amount of data transmitted in each batch, and simultaneously counts the amount of data while the temporary memory is used for data truncation. A write controller completes the write operation based on the initial write address calculated for the previous batch; the initial write address for the current batch is obtained from the previous batch, enabling uninterrupted batch transmission. A write address update module calculates the initial write address for the current batch based on the initial write address calculated for the previous batch and the count value. Address configuration information is dynamically generated in real-time using dynamic temporary storage. This invention achieves data transmission without needing to predetermine the data volume, resulting in high efficiency and low cost.

[0061] According to some embodiments, the temporary memory 110 includes a first temporary memory 111 and a second temporary memory 112, and the counter 120 includes a first counter 121 and a second counter 122;

[0062] The first counter 121 is used to count the amount of data in the data block stored in the first temporary memory 111, and outputs the count value of the first counter 121 as the first count value when the preset end condition is met. The second counter 122 is used to count the amount of data in the data block stored in the second temporary memory 112, and outputs the count value of the second counter 122 as the second count value when the preset end condition is met.

[0063] Specifically, when setting up two temporary storage devices 110, one of the temporary storage devices is named the first temporary storage device 111, and the other temporary storage device is named the second temporary storage device 112.

[0064] According to the example embodiment, the two temporary memories take turns receiving / outputting new data in a ping-pong operation.

[0065] Correspondingly, a corresponding counter is set for each temporary memory to count the amount of data. That is, the first counter 121 is set to count the first temporary memory 111, and the second counter 122 is set to count the second temporary memory 112.

[0066] Accordingly, if multiple temporary storage devices are set up, the same configuration can be used as described in this embodiment, and the present invention will not elaborate on this further.

[0067] In this embodiment of the invention, multiple temporary memories and corresponding counters are set up to maintain the continuity of the overall transmission and improve the transmission efficiency.

[0068] According to some embodiments, the apparatus further includes:

[0069] Demultiplexer 150 is used for:

[0070] If temporary storage 110 is full, switch the data storage path of the data block;

[0071] as well as

[0072] When each temporary storage 110 is empty, specify the data storage path for the data block, where the data storage path is a corresponding data storage path in the temporary storage 110.

[0073] When two or more temporary storage units 110 are set up, in order to switch the path of data storage in temporary storage units 110, a demultiplexer 150 is required to coordinate which temporary storage unit 110 the data is stored in.

[0074] According to the example embodiment, for example, when the current batch is 1, each temporary storage 110 is empty. At this time, the data storage path of the data block is specified by the demultiplexer 150, for example, the storage path corresponding to the second temporary storage 112.

[0075] According to an example embodiment, for instance, when the current batch is a middle batch, if a temporary storage device (e.g., the second temporary storage device 112) is full, the data storage path of the data block is switched to another temporary storage device (e.g., the first temporary storage device 111) via the demultiplexer 150. That is, the demultiplexer 150 controls the two temporary storage devices to take turns receiving data in a ping-pong operation. The multiplexer 160 is used for:

[0076] When temporary storage 110 is empty, switch the data source path written to the target storage module; and

[0077] When each temporary storage 110 is full, the data source path of the data block is specified, wherein the data source path is a corresponding data source path in the temporary storage 110.

[0078] When two or more temporary storage units 110 are set up, a multiplexer needs to be added on the output side of the temporary storage units 110 to coordinate which temporary storage unit 110 the data is output from.

[0079] According to the example embodiment, for example, when the current batch is a certain batch in the middle, if a certain temporary storage (e.g., the second temporary storage 112) is empty, the data source path of the target storage module is switched to another temporary storage (e.g., the first temporary storage 111). That is, the multiplexer 160 controls the two temporary storages to output data in a ping-pong operation.

[0080] According to the example embodiment, for example, when the current batch is a certain batch in the middle, each temporary storage 110 is full. At this time, the data source path of the target storage module is specified by the multiplexer 160, for example, the data source path corresponding to the second temporary storage 112.

[0081] In this embodiment of the invention, a demultiplexer and a multiplexer are set up to coordinate the data storage path and the data output path, making the write operation more orderly and improving the efficiency of the write operation.

[0082] According to some embodiments, in the temporary memory 110, the capacity of the temporary memory 110 is the maximum amount of data that can be supported in a single hardware bus operation.

[0083] To ensure maximum utilization of computing resources, regardless of how many temporary storage units 110 are set up, the capacity of each temporary storage unit 110 is equal to the maximum amount of data that can be supported by one hardware bus operation.

[0084] According to the example embodiment, taking the commonly used AXI protocol as an example, the maximum amount of data that can be supported in a single hardware transmission is 4KB, so the capacity of the temporary memory 110 is set to 4KB.

[0085] According to some embodiments, in counter 120, the preset end condition is that the count value reaches a preset threshold or all data transmission is detected to be complete.

[0086] Specifically, the preset threshold is the upper limit of the capacity of the temporary storage 110, such as 4KB as specified in the above embodiment.

[0087] Understandably, when multiple temporary storage units 110 are set, the preset threshold can be set to the same value or different values.

[0088] When the preset threshold values ​​of the preset termination conditions of multiple temporary storage devices 110 are set to different values, the counting will end and the value will be returned to zero when the corresponding preset termination condition is met.

[0089] When determining whether all data transmission has been completed, it is understood that during data transmission, the last data will be accompanied by a valid ending indicator signal. By detecting this indicator signal, it can be determined whether all data transmission has been completed.

[0090] To provide a more detailed description of the present invention, a specific embodiment is given, such as... Figure 3 As shown in the figure, RAM is used as temporary storage in this embodiment. In the figure, cnt1 represents the first counter 121, cnt2 represents the second counter 122, ram1 represents the first temporary memory 111, and ram2 represents the second temporary memory 112.

[0091] This embodiment uses the INCR burst type of the AXI protocol, which means that the write address increases naturally as data enters, and the host only needs to configure the starting address corresponding to the first piece of data.

[0092] Assuming the original data passes through the data processing module, it will output 10KB of new data. The last data in this new data will be accompanied by an ending valid indication signal, indicating that the 10KB of data has ended.

[0093] During the transmission process, after power-on or a complete DMA write operation, the values ​​of cnt1 and cnt2 are both set to 0. The demultiplexer and multiplexer select ram1 as the data path (obviously, neither ram1 nor ram2 stores any data at this time). This means that the first data is stored in ram1 by default, and the first batch of write operations are output from ram1 by default. Since the total data size is 10KB and ram1 has a capacity of 4KB, ram1 stores the first 4KB of data, while the cnt1 count reaches 4KB-1 (because counting starts from 0).

[0094] The write address update module uses the count value of cnt1 and the initial write address X configured by the host to obtain the initial write address X+4096 for the second write operation. The Write DMA Master executes the first hardware write operation, in which the main configuration of the first hardware operation of the Write DMA Master includes 4KB of data statistics from cnt1 and the initial write address X configured by the host. The multiplexer configures the write data to come from ram1.

[0095] At this point, 6KB of the 10KB new data remains to be transmitted. The demultiplexer is configured to store the remaining data in RAM2. Since the total data volume is 6KB and the capacity of RAM2 is 4KB, RAM2 stores the second batch of 4KB data. At the same time, the CNT2 counter reaches 4KB-1.

[0096] The write address update module uses the count value of cnt2 and the initial write address of the second write operation to obtain the write address of the third write operation, X+4096+4096=X+8192. The Write DMAMaster executes the second hardware write operation. The main configuration of the Write DMAMaster's second hardware operation includes 4KB of data statistics from cnt2 and the initial write address of the second write operation, X+4096. The multiplexer configures the write data to come from ram2.

[0097] At this point, 2KB of the 10KB new data remains to be transmitted. The demultiplexer is configured to store the remaining data in RAM1. Since the total data size is 2KB and RAM1 has a capacity of 4KB, RAM1 stores the third batch of 2KB data. Simultaneously, the cnt1 counter reaches 2KB-1. The last data in the third batch will be accompanied by a valid ending indication signal. Therefore, the main configuration of the third hardware operation of Write DMAMaster includes the 2KB data statistics from cnt1 and the initial write address X+8192 for the third write operation. The multiplexer is configured to send the write data from RAM1.

[0098] As can be seen from the perspective of Write DMAMaster, 10KB of data is transmitted almost without interruption, which means that this invention can maximize transmission efficiency.

[0099] More specifically, the first batch of data transmissions, such as Figure 4 As shown, the first hardware bus write operation of Write DMAMaster writes 4KB of data from ram1. The data amount is obtained from cnt1, i.e., 4095+1=4096. The initial write address is the initial write address X configured by the Host.

[0100] The second batch of data transmission is as follows Figure 5 As shown, the second hardware bus write operation of Write DMAMaster writes 4KB of data from ram2. The data size is obtained from cnt2, i.e., 4095 + 1 = 4096. The initial write address is the address calculated by the write address update module at a previous moment, i.e., X + 4096.

[0101] The third batch of data transmission, such as Figure 6 As shown, the third hardware bus write operation of Write DMAMaster writes 2KB of data from ram1. The data amount is obtained from cnt1, i.e., 2047+1=2048. The initial write address is the address calculated by the write address update module at a previous moment, i.e., X+8192.

[0102] After all 10KB of data is written to DDR or a peripheral device, the memory area is distributed as follows: Figure 7 As shown.

[0103] As can be seen, after the data arrives at the terminal, it is stored for 10KB starting from address X according to the host configuration, although the host is unaware of the exact amount of data to be stored. Following a standard DMA write design, the host needs to send a 10KB data configuration to the DMAC. The final storage area distribution is as follows... Figure 1 To.

[0104] The following describes method embodiments of the present invention, which can control direct memory access using the apparatus embodiments of the present invention. For details not disclosed in the method embodiments of the present invention, please refer to the apparatus embodiments of the present invention.

[0105] Figure 8 A flowchart illustrating the direct memory access control method provided in an embodiment of the present invention is shown. Figure 8 As shown, the method includes steps S1-S8.

[0106] In step S1, the direct memory access control device is activated to acquire the data to be transmitted.

[0107] Before step S1, the method further includes: setting the temporary memory capacity according to the hardware bus protocol, for example, equal to the maximum amount of data that can be supported in a single write transfer.

[0108] Before step S1, the method also includes: configuring the initial write address for the Host, which is the initial write address used for the first write transfer after the control device for direct memory access is started.

[0109] In step S2, the data to be transmitted is stored byte by byte into the current temporary memory, and the current counter corresponding to the current temporary memory is used for counting.

[0110] When only one temporary storage is set up, the data to be transmitted is stored byte by byte into the current temporary storage, and the corresponding counter counts the amount of data synchronously when storing it into the temporary storage.

[0111] When two or more temporary storage devices are set up, the data to be transmitted is stored into each temporary storage device in a ping-pong operation using a demultiplexer. When storing data into a temporary storage device, the corresponding counter synchronously counts the amount of data.

[0112] In step S3, when the current counter value reaches the preset threshold, the count value is output, and it is determined whether all data has been transmitted. If yes, proceed to S6; otherwise, proceed to the next step.

[0113] The preset threshold is the upper limit of the temporary memory capacity. In other words, step S3 determines whether the temporary memory is full. If it is full, it checks whether all data has been transferred. If yes, it jumps to S6 to end the loop; otherwise, it executes the subsequent steps. The subsequent steps output the current data in the temporary memory, provide the amount of data, and generate the initial write address for the next write operation.

[0114] In step S4, when the current batch is 1, the data block stored in the current temporary memory is written to the target storage module according to the pre-configured initial write address, and the initial write address calculated for the current batch is obtained according to the pre-configured initial write address and the count value.

[0115] This step determines whether this is the first output from temporary storage after the control device for initiating direct memory access. If so, the initial write address for the current batch is calculated using the pre-configured initial write address and count value.

[0116] In addition, the first hardware write operation needs to be performed using the pre-configured initial write address, and the source of the write data is the current temporary memory.

[0117] It should be noted that hardware write operations and updating the initial write address can be performed simultaneously or sequentially; this invention does not impose any restrictions on this.

[0118] In step S5, if the current batch is greater than 1, the data block stored in the current temporary memory is written to the target storage module according to the initial write address calculated in the previous batch, and the initial write address calculated in the current batch is obtained according to the initial write address and count value calculated in the previous batch.

[0119] If this is not the first output from temporary storage after the controller initiates direct memory access, the initial write address for the current batch is obtained using the initial write address and count value calculated in the previous batch.

[0120] In addition, the data blocks stored in the current temporary storage need to be written to the target storage module based on the initial write address calculated in the previous batch.

[0121] If this is not the first time the controller has output from temporary memory after initiating direct memory access, the hardware write operation is performed using the initial write address calculated in the previous batch, and the source of the write data is the current temporary memory.

[0122] When only one temporary storage is set up, the source of written data is the current temporary storage.

[0123] When two or more temporary storages are set up, the current temporary storage is determined by a multiplexer, and data is output from each temporary storage in a ping-pong operation.

[0124] It should be noted that hardware write operations and updating the initial write address can be performed simultaneously or sequentially; this invention does not impose any restrictions on this.

[0125] In step S6, steps S2-S5 are repeated until all data transmission is complete.

[0126] If a valid data termination indication signal is detected, all data transmission is complete and the process ends.

[0127] According to some embodiments, before step S2, the method further includes:

[0128] The current data storage path is determined using a demultiplexer;

[0129] Use the temporary storage corresponding to the current data storage path as the current temporary storage.

[0130] When setting up two or more temporary storage devices, a demultiplexer is required to switch the path of data storage in temporary storage device 110 in order to coordinate which temporary storage device the data is stored in.

[0131] According to the example embodiment, for example, when the current batch is 1, each temporary storage is empty. At this time, the current data storage path of the data block is specified by the demultiplexer, for example, the storage path corresponding to the second temporary storage, and then the second temporary storage is used as the current temporary storage.

[0132] According to the example embodiment, for example, when the current batch is a certain batch in the middle, if a certain temporary storage (e.g., the second temporary storage) is full, the data storage path of the data block is switched to another temporary storage (e.g., the first temporary storage) by the demultiplexer. The first temporary storage is used as the current temporary storage. That is, the two temporary storages are controlled by the demultiplexer to take turns receiving data in a ping-pong operation.

[0133] According to some embodiments, before step S6, the method further includes:

[0134] Use a demultiplexer to determine the current data source path;

[0135] Use the temporary storage corresponding to the current data source path as the current temporary storage.

[0136] When setting up two or more temporary storage devices, a multiplexer needs to be added on the output side of the temporary storage devices to coordinate which temporary storage device the data is output from.

[0137] According to the example embodiment, for example, when the current batch is a certain batch in the middle, if a certain temporary storage (e.g., the second temporary storage) is empty, the data source path of the target storage module is switched to another temporary storage (e.g., the first temporary storage), and the first temporary storage is used as the current temporary storage. That is, the two temporary storages are controlled by the multiplexer to output data in turn in a ping-pong operation.

[0138] According to the example embodiment, for example, when the current batch is a certain batch in the middle, each temporary storage is full. At this time, the data source path of the target storage module is specified by the multiplexer, for example, the data source path corresponding to the second temporary storage, and then the second temporary storage is used as the current temporary storage.

[0139] The method performs similar functions to the apparatus provided above; other steps are described in the preceding description and will not be repeated here.

[0140] Figure 9 An electronic device according to an exemplary embodiment of the present invention is shown below. Figure 9 To describe an electronic device 900 according to this embodiment of the present invention. Figure 9 The electronic device 900 shown is merely an example and should not impose any limitations on the functionality and scope of use of the embodiments of the present invention.

[0141] like Figure 9 As shown, the electronic device 900 is presented in the form of a general-purpose computing device. The components of the electronic device 900 may include, but are not limited to: at least one processing unit 910, at least one storage unit 920, a bus 930 connecting different system components (including storage unit 920 and processing unit 910), a display unit 940, etc.

[0142] The storage unit stores program code, which can be executed by the processing unit 910 to perform the methods described in this specification according to various exemplary embodiments of the present invention. For example, the processing unit 910 can perform the methods described above.

[0143] Storage unit 920 may include readable media in the form of volatile storage units, such as random access memory (RAM) 9201 and / or cache memory 9202, and may further include read-only memory (ROM) 9203.

[0144] Storage unit 920 may also include a program / utility 9204 having a set (at least one) program module 9205, such program module 9205 including but not limited to: operating system, one or more application programs, other program modules and program data, each or some combination of these examples may include an implementation of a network environment.

[0145] Bus 930 can represent one or more of several types of bus structures, including a memory cell bus or memory cell controller, a peripheral bus, a graphics acceleration port, a processing unit, or a local bus using any of the various bus structures.

[0146] Electronic device 900 can also communicate with one or more external devices 300 (e.g., keyboard, pointing device, Bluetooth device, etc.), and with one or more devices that enable a user to interact with electronic device 900, and / or with any device that enables electronic device 900 to communicate with one or more other computing devices (e.g., router, modem, etc.). This communication can be performed via input / output (I / O) interface 950. Furthermore, electronic device 900 can also communicate with one or more networks (e.g., local area network (LAN), wide area network (WAN), and / or public networks, such as the Internet) via network adapter 960. Network adapter 960 can communicate with other modules of electronic device 900 via bus 930. It should be understood that, although not shown in the figures, other hardware and / or software modules can be used in conjunction with electronic device 900, including but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data backup storage systems.

[0147] Through the above description of the embodiments, those skilled in the art will readily understand that the exemplary embodiments described herein can be implemented by software or by combining software with necessary hardware. The technical solutions of the embodiments of the present invention can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (such as a CD-ROM, USB flash drive, portable hard drive, etc.) or on a network, including several instructions to cause a computing device (such as a personal computer, server, or network device, etc.) to execute the methods described above according to the embodiments of the present invention.

[0148] Software products may employ any combination of one or more readable media. A readable medium may be a readable signal medium or a readable storage medium. A readable storage medium may be, for example,, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of readable storage media (a non-exhaustive list) include: electrical connections having one or more wires, portable disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof.

[0149] Computer-readable storage media may include data signals propagated in baseband or as part of a carrier wave, carrying readable program code. Such propagated data signals may take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. A readable storage medium may also be any readable medium other than a readable storage medium that can transmit, propagate, or transfer a program for use by or in connection with an instruction execution system, apparatus, or device. The program code contained on the readable storage medium may be transmitted using any suitable medium, including but not limited to wireless, wired, optical fiber, RF, etc., or any suitable combination thereof.

[0150] Program code for performing the operations of this invention can be written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Java and C++, and conventional procedural programming languages ​​such as C or similar languages. The program code can execute entirely on the user's computing device, partially on the user's device, as a standalone software package, partially on the user's computing device and partially on a remote computing device, or entirely on a remote computing device or server. In cases involving remote computing devices, the remote computing device can be connected to the user's computing device via any type of network, including a local area network (LAN) or a wide area network (WAN), or it can be connected to an external computing device (e.g., via the Internet using an Internet service provider).

[0151] The aforementioned computer-readable medium carries one or more programs, which, when executed by a device, cause the computer-readable medium to perform the aforementioned functions.

[0152] Those skilled in the art will understand that the above modules can be distributed in the device as described in the embodiments, or they can be modified accordingly and placed in one or more devices that are unique to this embodiment. The modules in the above embodiments can be combined into one module, or they can be further divided into multiple sub-modules.

[0153] Through the description of the above embodiments, those skilled in the art will readily understand that the exemplary embodiments described herein can be implemented by software or by combining software with necessary hardware. Therefore, the technical solutions of the embodiments of the present invention can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (such as a CD-ROM, USB flash drive, portable hard drive, etc.) or on a network, including several instructions to cause a computing device (such as a personal computer, server, mobile terminal, or network device, etc.) to execute the methods according to the embodiments of the present invention.

[0154] Exemplary embodiments of the present invention have been specifically shown and described above. It should be understood that the present invention is not limited to the detailed structures, arrangements, or implementations described herein; rather, the present invention is intended to cover various modifications and equivalent arrangements contained within the spirit and scope of the appended claims.

Claims

1. A direct memory access control device, characterized in that, include: A demultiplexer is used to switch the data storage path of data blocks when the temporary storage is full. And when each of the temporary storages is empty, specify the data storage path of the data block, wherein the data storage path is a corresponding data storage path in the temporary storage; A multiplexer is used to switch the data source path to the target storage module when the temporary storage is empty; and to specify the data source path of the data block when each of the temporary storages is full, wherein the data source path is a corresponding data source path in the temporary storage; The temporary storage includes a first temporary storage and a second temporary storage, which is used to temporarily store data blocks of the current batch of data to be transmitted in turn to the first temporary storage or the second temporary storage according to the data storage path specified or switched by the demultiplexer in a ping-pong operation. The counter, including a first counter and a second counter, is used to count the amount of data in the data block stored in the temporary memory in the current batch, and outputs the count value when a preset end condition is met. The first counter is used to count the amount of data stored in the first temporary memory, and the second counter is used to count the amount of data stored in the second temporary memory. The write controller is used to write the data blocks stored in the first temporary memory or the second temporary memory of the current batch into the target storage module in turn according to the initial write address calculated in the previous batch, based on the data source path specified or switched by the multiplexer. The write address update module is used to obtain the initial write address calculated for the current batch based on the initial write address calculated for the previous batch and the count value.

2. The apparatus of claim 1, wherein, The first counter is used to count the amount of data stored in the first temporary memory, and when a preset end condition is met, the count value of the first counter is output as a first count value. The second counter is used to count the amount of data stored in the second temporary memory, and when a preset end condition is met, the count value of the second counter is output as a second count value.

3. The apparatus of claim 1, wherein, The capacity of the temporary memory is the maximum amount of data that can be supported in a single hardware bus operation.

4. The apparatus according to claim 1 or 2, characterized in that, The preset termination condition is when the count value reaches a preset threshold or when all data transmission is detected to be complete.

5. A method of controlling a direct memory access using the control device of any one of claims 1 to 4, characterized by include: S1: Start the direct memory access control device to acquire the data to be transmitted; S2: Store the data to be transmitted byte by byte into the current temporary memory, and count using the current counter corresponding to the current temporary memory; S3: When the count value of the current counter reaches the preset threshold, output the count value and determine whether all data has been transmitted. If yes, end the loop; otherwise, proceed to the next step. S4: When the current batch is 1, write the data block stored in the current temporary memory to the target storage module according to the pre-configured initial write address, and obtain the initial write address of the current batch according to the pre-configured initial write address and the count value. S5: If the current batch is greater than 1, write the data block stored in the current temporary memory into the target storage module according to the initial write address calculated in the previous batch, and obtain the initial write address calculated in the current batch according to the initial write address calculated in the previous batch and the count value. S6: Repeat steps S2-S5 until all data transmission is complete.

6. The method of claim 5, wherein, Before step S2, the following is also included: The current data storage path is determined using a demultiplexer; The temporary storage corresponding to the current data storage path is used as the current temporary storage.

7. The method of claim 5, wherein, Before step S4, the following is also included: Use a demultiplexer to determine the current data source path; The temporary storage corresponding to the current data source path is used as the current temporary storage.

8. An electronic device, comprising: include: One or more processors; Storage device for storing one or more programs; When the one or more programs are executed by the one or more processors, the one or more processors implement the method as described in any one of claims 5-7.

9. A computer-readable storage medium having a computer program or instructions stored thereon, characterized in that, When the computer program or instructions are executed by a processor, they implement the method as described in any one of claims 5-7.

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