A chip initial layout method, device and terminal equipment

Abstract

The application discloses a chip initial layout method, device and terminal equipment, the method comprises traversing the specified parent module of the chip hierarchy structure and the sub-modules included in the specified parent module, and expanding the layout area; the sub-modules are hierarchically clustered to generate corresponding cluster modules; the pins of each sub-module in each cluster module are traversed, and the pins of each sub-module are mapped to the center position of the cluster module; according to the network connected by the pins of the sub-modules, the line network connection relationship between the cluster modules is established; based on the line network connection weight between the cluster modules and the module overlapping repulsion, a quadratic programming model is constructed, and a two-dimensional layout area is iteratively optimized to generate. The application enables cross-layer modules to be quickly divided and laid out in a more reasonable manner, reduces unnecessary cross-layer wiring, and provides a more stable initial solution for the subsequent 3D-EFS layout optimization process.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit layout technology, and more specifically to a chip initial layout method, apparatus and terminal equipment. Background Technology

[0002] With the continuous expansion of integrated circuit (IC) design scale, 3D integrated circuits (3D-ICs) have gradually become an important development direction in the chip industry due to their higher integration density, shorter interconnect length, and lower power consumption. Currently, mainstream 3D-IC design research focuses on the hybrid layout of macrocells and standard cells. In actual layout, a common practice is to rationally allocate macrocells and standard cells to the top die and bottom die, taking into account the net length and the number of vias (such as vertical interconnect channels). To this end, various 3D layout algorithms have been proposed in existing technologies, such as temperature-sensing layout methods, genetics-based optimization methods, and physical models based on electric fields. These methods mostly aim at the hybrid layout of macrocells and standard cells, improving the performance and integration density of 3D-ICs through various optimization strategies.

[0003] Existing 3D layout planning methods have certain limitations in 3D-EFS (3D Early Floorplan Synthesis) scenarios. First, 3D-EFS requires hierarchical clustering and packaging of modules, and then rationally dividing these packaged modules into different chip layers to further shorten the net length between modules, accelerate data transmission speed, and improve overall chip performance.

[0004] Existing layout algorithms fail to effectively address the specific requirements of this "modular packaged layout," and cannot quickly output a high-quality initial layout suitable for this scenario. Secondly, in the 2D layout stage, traditional secondary layout algorithms require repeated calculations of net attraction and cell overlap repulsion, generating a layout solution through multiple iterations. In the complex net structure of 3D-EFS, directly applying these algorithms is not only inefficient but also leads to layout results that fail to meet the requirements of 3D-EFS due to unnecessary attention to all cell connections and overlaps.

[0005] Therefore, a new technological solution is needed. Summary of the Invention

[0006] In view of this, embodiments of the present invention provide a chip initial layout method, apparatus and terminal device to at least solve the problems existing in the existing three-dimensional layout planning methods.

[0007] The embodiments of the present invention provide the following technical solutions:

[0008] This invention provides a chip initial layout method, including:

[0009] Traverse the specified parent module and its child modules in the chip hierarchy, and expand the layout area.

[0010] The sub-modules are hierarchically clustered to generate corresponding clustering modules. Each clustering module inherits the total area, network connection relationship and pin information of the corresponding sub-module.

[0011] Iterate through the pins of each sub-module in each clustering module and map the pins of each sub-module to the center position of the clustering module;

[0012] Based on the network connected to the pins of the submodules, a wire mesh connection relationship is established between the clustering modules, wherein repeated network connections between the submodules can increase the wire mesh connection weight between the corresponding clustering modules;

[0013] Based on the wire connection weights and module overlap repulsion forces between the clustering modules, a quadratic programming model is constructed and iteratively optimized to generate a two-dimensional layout region.

[0014] The clustering modules within the two-dimensional layout area are divided into top-level chips and bottom-level chips;

[0015] The area of ​​the layout region is reduced, and a three-dimensional initial layout is generated iteratively in the top-level chip and the bottom-level chip based on the net connection weights between the clustering modules and the module overlap repulsion force.

[0016] Furthermore, the step of dividing the clustering modules within the two-dimensional layout area into top-level chips and bottom-level chips includes:

[0017] The two-dimensional layout area is divided into N*N panes, and the clustering module is assigned to the top-level chip and the bottom-level chip based on the position of the pane where the center point of the clustering module is located, as well as the area utilization rate of the top-level chip and the bottom-level chip.

[0018] Furthermore, when assigning the clustering module to the top-level chip and the bottom-level chip, if the area utilization rate of the top-level chip or the bottom-level chip exceeds a preset threshold, the clustering module will be preferentially assigned to the chip with the smaller area utilization rate.

[0019] Furthermore, the shrinking of the layout area includes:

[0020] The area of ​​the layout region is reduced according to a preset ratio;

[0021] In the top-level chip and the bottom-level chip, the positions of the respective clustering modules are iteratively optimized based on the net connection weights and the module overlap repulsion forces to generate a three-dimensional initial layout.

[0022] Furthermore, the clustering module includes a specified clustering module and a non-specified clustering module;

[0023] The specified clustering module includes the specified sub-modules in the specified parent module, and the non-specified clustering module includes the non-specified sub-modules in the specified parent module.

[0024] Furthermore, the clustering modules are spaced apart on the expanded layout area.

[0025] Furthermore, establishing the net connection relationship between the clustering modules based on the network connected to the pins of the submodules includes:

[0026] Obtain the network information of the pin connections of each submodule, and determine all the clustering modules connected to the pins in the network information;

[0027] Traverse all network information and record the wire connection relationships between interconnected clustering modules in the netlist.

[0028] Furthermore, the step of constructing a quadratic programming model based on the network connection weights and module overlap repulsion between the clustering modules, and iteratively optimizing the generation of a two-dimensional layout region, includes:

[0029] Based on the clustering module and the preset mesh model, mesh modeling is performed, mesh connection relationships between the clustering modules are established, and mesh connection weights are obtained.

[0030] Based on the network connection weights and module overlap repulsion between the clustering modules, the coefficient matrix and target vector required for solving the quadratic programming problem are constructed, and the two-dimensional layout region is generated iteratively using the quadratic programming algorithm.

[0031] The present invention also provides a chip initial layout apparatus, comprising:

[0032] The traversal module is used to traverse a specified parent module and the sub-modules included in the specified parent module of the chip hierarchy, expand the layout area, and traverse the pins of the sub-modules.

[0033] A clustering module is used to perform hierarchical clustering of the sub-modules to generate corresponding clustering modules. Each clustering module inherits the total area, network connection relationship and pin information of the corresponding sub-module.

[0034] A mapping module is used to map the pins of the submodule to the center position of the clustering module;

[0035] A building module is established, which is used to establish the wire mesh connection relationship between the clustering modules based on the network of the pin connection of the sub-module. The repeated network connection between the sub-modules can increase the wire mesh connection weight between the corresponding clustering modules.

[0036] An iterative generation module is used to construct a quadratic programming model based on the net connection weights and module overlap repulsion forces between the clustering modules, and iteratively optimize and generate a two-dimensional layout region. The clustering modules within the two-dimensional layout region are divided into top-level chips and bottom-level chips. The area of ​​the layout region is reduced, and a three-dimensional initial layout is iteratively generated in the top-level chips and the bottom-level chips according to the net connection weights and module overlap repulsion forces between the clustering modules.

[0037] This invention also provides a terminal device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the steps of the chip initial layout method as described in any of the preceding embodiments.

[0038] Compared with the prior art, the beneficial effects that the at least one technical solution adopted in the embodiments of the present invention can achieve include at least:

[0039] This invention provides a chip initial layout method that, through a complete process from hierarchical structure analysis and clustering to two-dimensional optimization and three-dimensional layered legalization, can quickly obtain a reasonable initial layout of a three-dimensional chip. Furthermore, this invention fully considers the hierarchical relationships of modules and can utilize user-specified hierarchical structures to guide clustering, enabling cross-layer modules to be divided and laid out more quickly and in a more reasonable manner. Moreover, by maintaining the logical integrity of clustering modules during the layout stage, unnecessary cross-layer connections are reduced, providing a more stable initial solution for subsequent 3D-EFS layout optimization. Attached Figure Description

[0040] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0041] Figure 1 This is a flowchart of a chip initial layout method according to an embodiment of the present invention;

[0042] Figure 2 A schematic diagram of a user-specified hierarchical module in an embodiment of the present invention;

[0043] Figure 3 This is an overall flowchart illustrating the implementation of a chip initial layout method according to an embodiment of the present invention;

[0044] Figure 4 This is a flowchart illustrating a chip initial layout method according to an embodiment of the present invention;

[0045] Figure 5 This is a window partitioning diagram of a chip initial layout method according to an embodiment of the present invention. Detailed Implementation

[0046] The embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0047] The following specific examples illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. This application can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this application. It should be noted that, in the absence of conflict, the following embodiments and features in the embodiments can be combined with each other. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0048] It should be noted that various aspects of embodiments within the scope of the appended claims are described below. It will be apparent that the aspects described herein can be embodied in a wide variety of forms, and any particular structure and / or function described herein is merely illustrative. Based on this application, those skilled in the art will understand that one aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number and aspects set forth herein can be used to implement the device and / or practice the method. Additionally, this device and / or method can be implemented using structures and / or functionalities other than one or more of the aspects set forth herein.

[0049] It should also be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of this application. The drawings only show the components related to this application and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0050] Additionally, specific details are provided in the following description to facilitate a thorough understanding of the examples. However, those skilled in the art will understand that practice can be carried out without these specific details.

[0051] Based on the shortcomings of existing 3D layout methods, the inventors conducted in-depth research and improvement on hierarchical clustering and window partitioning, and discovered that: by clustering modules below the user-specified level, and using a quadratic programming layout algorithm to generate a 2D initial layout based on the clustered modules formed by this clustering method, and finally using a window-based partitioning method to iterate the 2D initial layout into a 3D chip initial layout, a high-quality initial solution that meets the requirements of composite 3D-EFS scene is obtained.

[0052] Based on this, the embodiments of this specification propose a processing solution: such as Figures 1-5 As shown, the present invention provides a three-dimensional chip initial layout method based on hierarchical clustering and window partitioning. By performing hierarchical clustering on specified modules and inheriting the area, utilization rate and network information of sub-modules, an improved quadratic planning layout algorithm is used to place the clustered modules in two-dimensional positions. Finally, a window-based partitioning method is used to obtain a three-dimensional legal layout, thereby providing an efficient and stable initial solution for subsequent three-dimensional integrated circuit layout.

[0053] Specifically, this invention expands the layout area, clusters hierarchical modules according to user settings, and generates a two-dimensional layout solution based on the attractive forces generated by the nets between clustered modules and the repulsive forces generated by module overlap. Then, it uses a window partitioning method, such as dividing the two-dimensional layout solution into 4*4 panes, and divides the clustered modules into two chips according to the position of the clustered modules in the panes and the area occupancy rate in the chip. Finally, it shrinks the position coordinates of the clustered modules and iterates in the two layers of chips based on the attractive forces generated by the nets and the repulsive forces generated by module overlap to obtain the final three-dimensional initial layout.

[0054] More specifically, by specifying parent modules and their child modules in the chip hierarchy, these child modules are clustered and uniformly inherit area, network connectivity, and pin information. Subsequently, by center-mapping the pins of the child modules in each cluster and establishing inter-module net weights based on network relationships, the complex unit-level network connections in the original design are effectively simplified, significantly reducing the scale and complexity of the local optimization objective. This solves the problem that existing algorithms struggle to handle large-scale "module-packed layout" scenarios, providing a feasible and efficient initial layout strategy for novel 3D integrated circuits such as 3D-EFS.

[0055] Furthermore, in the two-dimensional layout stage, a quadratic programming model is constructed by focusing only on the net connection weights and module overlap repulsion forces between clustering modules, significantly reducing the number of objects requiring iterative calculation. Combined with pane partitioning and area utilization balancing mechanisms, clustering modules are rationally allocated to the top and bottom layers of the chip. Simultaneously, after shrinking the layout area, layered optimization continues, ultimately efficiently outputting a three-dimensional initial layout that meets the specific requirements of 3D-EFS. Compared to traditional quadratic layout algorithms that directly apply to all units, this invention effectively avoids inefficient and irrelevant iterations, significantly improving layout efficiency and quality, and better adapting to the practical application needs of complex net structures in three-dimensional chips.

[0056] The technical solutions provided by the various embodiments of this application are described below with reference to the accompanying drawings.

[0057] like Figures 1-5 As shown, a chip initial layout method of the present invention includes:

[0058] Step S102: Traverse the specified parent module and the sub-modules included in the specified parent module of the chip hierarchy, and expand the layout area.

[0059] The process involves traversing the specified parent module of the chip hierarchy, which includes traversing all parent modules at the user-specified level, and then traversing all child modules contained within those parent modules. By analyzing and traversing the user-specified parent modules and all their child modules in the chip design, the orderly filtering and information collection of layout objects are achieved.

[0060] In this regard, the area of ​​the layout region is expanded to reserve physical space for subsequent clustering and optimization stages, and to prevent initial crowding and overlap from affecting the optimization effect.

[0061] The area of ​​the layout region can be expanded proportionally or appropriately according to the number of modules. The purpose is to enable subsequent clustering modules to be distributed in the layout region without overlap.

[0062] Step S102 is used to lay the data foundation for the module packaging layout, so that the whole process can focus on the structural units of the designer and provide a good initial distribution environment for large-scale modules, thereby improving the feasibility of the initial solution.

[0063] Step S104: Perform hierarchical clustering on the sub-modules to generate corresponding clustering modules. Each clustering module inherits the total area, network connection relationship and pin information of the corresponding sub-module.

[0064] The clustering module includes a specified clustering module and a non-specified clustering module; the specified clustering module includes a specified sub-module in the specified parent module, and the non-specified clustering module includes a non-specified sub-module in the specified parent module.

[0065] Among them, the specified clustering module is the clustering module formed by the sub-modules specified by the user; the unspecified clustering module is the clustering module automatically formed by the sub-modules not specified by the user.

[0066] By dividing the clustering modules into specified and unspecified categories, the layout process can be handled separately as needed, achieving precise control over key modules and overcoming the problem that existing methods cannot flexibly cope with diverse needs. Furthermore, the unspecified clustering modules, as ordinary background structures, participate in automated packaging and optimization, which also effectively reduces the overall complexity.

[0067] The total area of ​​the clustering module can be obtained based on the total area of ​​the sub-modules and the specified area utilization rate. For example, the total area of ​​the sub-modules can be divided by the specified area utilization rate to obtain the total area of ​​the clustering module. Thus, the clustering modules are distributed on the expanded layout area based on the total area.

[0068] For example, such as Figure 2 As shown in the diagram, all modules are hierarchical. The top module contains three modules: A, B, and C. A contains three modules: D, E, and F. B contains two modules: G and H. The user specifies that modules A and G should be clustered separately. The results are three clustering modules: I, J, and K (K is automatically formed by clustering unspecified sub-modules). Module I contains all modules from module A, namely modules D, E, and F; module J contains only module G; and module K contains modules C and H from module B.

[0069] Furthermore, the clustering modules are spaced apart on the expanded layout area so that when the clustering modules are initially placed, they are evenly distributed in the expanded layout space without significant accumulation. This avoids the clustering modules being concentrated in local areas in the initial stage, which would lead to serious overlap and density. This provides a good starting point for secondary planning optimization and improves the convergence speed of the optimization algorithm and the final layout quality.

[0070] Step S104 uses a hierarchical clustering method to merge the user-specified sub-modules into a single clustering module and fully inherit the key attributes, thereby eliminating redundant connection operations in the original net label and shifting the focus of optimization from numerous small units to a more representative set of modules.

[0071] Step S104 can greatly reduce the amount of computation and the complexity of network relationships, provide a concise but complete input for subsequent secondary layout optimization, and preserve the functional boundaries of each module, thus solving the problem that existing algorithms are difficult to adapt to module-level layout.

[0072] Step S106: Traverse the pins of each sub-module in each clustering module and map the pins of each sub-module to the center position of the clustering module.

[0073] In step S106, by physically converging the pins of sub-modules of the same clustering module to the center of the clustering module, the reference coordinates for subsequent mesh modeling are unified, thereby avoiding the virtual height or error of the wire mesh length caused by the spatial distribution of factor modules and ensuring the accuracy of network modeling.

[0074] For example, after the user specifies the modules to be clustered, all clustering modules will inherit the net information of the sub-modules, build the network connection relationship between the clustering modules, and place the pins at the center of the clustering module.

[0075] Step S106 provides a precise physical basis for establishing network relationships, making the layout optimization objective function more intuitive and reasonable, thereby further reducing the complexity of subsequent connection length estimation and improving the overall layout quality.

[0076] Step S108: Based on the network connected to the pins of the sub-modules, establish the wire mesh connection relationship between the clustering modules, wherein repeated network connections between the sub-modules can increase the wire mesh connection weight between the corresponding clustering modules.

[0077] In step S108, a weighted inter-module network relationship diagram is established by counting the number of all interconnected networks between clustering modules. The weight settings also reflect the strength of the actual electrical connection between different clustering modules (i.e., the attraction between clustering modules), which is helpful for correctly measuring the driving force of moving closer or further apart during the optimization process.

[0078] The greater the weight between clustering modules, the stronger the attraction between them.

[0079] Specifically, step S108 includes:

[0080] Step S108a: Obtain the network information of the pin connections of each sub-module, and determine all the clustering modules connected to the pins in the network information;

[0081] Step S108b: Traverse all network information and record the wire connection relationships between interconnected clustering modules in the netlist.

[0082] Steps S108a and S108b systematically obtain the actual network connection status of each submodule pin and trace the corresponding cluster module through mapping relationship. Then, they traverse all network information, aggregate the cluster modules involved in each network, abstract these interconnected cluster modules into an effective edge in the network graph, and clearly record them in the netlist. Furthermore, they automatically accumulate weights for recurring networks to reflect the actual signal interaction strength between modules.

[0083] Steps S108a and S108b greatly simplify the scale of network modeling, providing highly relevant and non-redundant inputs for subsequent layout objective function modeling and physical implementation. This effectively solves the problem of relying solely on network information at the original sub-module level, which leads to a huge and redundant network model and increases useless computation. In complex wire mesh scenarios such as 3D-EFS, this improves efficiency.

[0084] Step S108 can reveal the actual path signal requirements after the clustering module is packaged, which avoids unnecessary consideration of all unit-level connections and ensures that key paths are optimized, thereby fundamentally improving the efficiency and controllability of layout search.

[0085] Step S110: Based on the network connection weights and module overlap repulsion between the clustering modules, construct a quadratic programming model and iteratively optimize to generate a two-dimensional layout region.

[0086] In step S110, by transforming the attraction (network) and repulsion (overlap) factors between clustering modules into quadratic programming modules, the optimal two-dimensional placement of modules can be achieved through a finite number of iterations.

[0087] By optimizing only the clustering module instead of all units, the solution size is significantly reduced.

[0088] In the process of iteratively optimizing and generating the two-dimensional layout region, the total area of ​​the clustering modules must also be considered. Based on the total area of ​​the clustering modules, the wire connection weight, and the module overlap repulsion force, the optimal two-dimensional layout region is obtained, that is, the optimal placement position of the clustering modules on the two-dimensional level is obtained.

[0089] Step S110 includes:

[0090] Step S110a: Based on the clustering module and the preset mesh model, perform mesh modeling, establish mesh connection relationships between the clustering modules, and obtain the mesh connection weights;

[0091] Step S110b: Based on the wire connection weights and module overlap repulsion between the clustering modules, construct the coefficient matrix and target vector required for solving the quadratic programming problem, and use the quadratic programming algorithm to iteratively generate a two-dimensional layout region.

[0092] Among them, the net weights between clustering modules are obtained based on clustering modules and preset net models, thereby eliminating irrelevant fine-grained units. Furthermore, based on net connection weights and overlapping repulsion between modules, a secondary optimization objective is constructed, and a coefficient matrix and objective vector are generated, which can also achieve the goal of "bringing together strongly related modules and avoiding overlap".

[0093] Steps S110a and S110b can significantly reduce the number of computational objects and redundant edges, improve optimization speed, and solve the problem that traditional methods are difficult to apply efficiently to large-scale complex 3D-EFS design. For example, they solve the problem that traditional quadratic programming algorithms directly take all elements as objects, which requires repeated calculation of massive attraction / repulsion terms. In 3D-EFS scenarios, the computational workload increases dramatically due to the complexity of the wire mesh structure, making convergence difficult.

[0094] Step S110 can overcome the inefficiency of traditional algorithms in large-scale 3D scenarios, significantly accelerate the generation speed of layout results, and the optimization target is highly consistent with engineering practice, providing a high-quality initial solution for subsequent 3D layering and legalization.

[0095] Step S112: Divide the clustering modules in the two-dimensional layout area into top-level chips and bottom-level chips.

[0096] Specifically, by dividing the space into panes and evaluating area utilization, clustering modules in two-dimensional space are automatically assigned to different chip layers. This not only reflects the layered characteristics of three-dimensional integrated circuits but also facilitates balancing the utilization of resources across different layers.

[0097] Step S112 can effectively connect two-dimensional optimization and three-dimensional layering, realize the automated deployment of layering strategies in scenarios such as 3D-EFS, and solve problems such as cumbersome manual intervention and uncontrollable layering effects.

[0098] Step S114: Shrink the area of ​​the layout region, and generate a three-dimensional initial layout in the top-level chip and the bottom-level chip according to the net connection weights and module overlap repulsion between the clustering modules.

[0099] In this process, by shrinking the layout area according to the actual chip size and running optimization algorithms again within each chip layer to refine the module placement, the final solution is guaranteed to meet both manufacturing size constraints and optimize netting and space resources to the greatest extent.

[0100] Step S114 enables a smooth transition from theoretical optimization to a manufacturing-ready layout, bypassing the failures and contradictions caused by large-scale global optimization in traditional algorithms in 3D scenes, and outputting a high-quality 3D initial layout that can be directly applied in industry.

[0101] Further, step S114 includes dividing the two-dimensional layout area into N*N panes, and dividing the clustering module into the top-level chip and the bottom-level chip according to the position of the pane where the center point of the clustering module is located, and the area utilization rate of the top-level chip and the bottom-level chip.

[0102] Furthermore, when assigning the clustering module to the top-level chip and the bottom-level chip, if the area utilization rate of the top-level chip or the bottom-level chip exceeds a preset threshold, the clustering module will be preferentially assigned to the chip with the smaller area utilization rate.

[0103] Among them, the pane mechanism and area utilization detection can make the module layering more scientific and avoid overloading of any chip layer area, so as to ensure optimal utilization of layout resources, avoid hot spots and bottlenecks in 3D-EFS scenarios, and improve the stability and robustness of the entire design process.

[0104] Furthermore, shrinking the layout area includes: shrinking the area of ​​the layout area according to a preset ratio; in the top-level chip and the bottom-level chip, based on the net connection weight and the module overlap repulsion force, iteratively optimizing the position of the respective clustering modules to generate a three-dimensional initial layout.

[0105] In this process, after shrinking the layout area according to a preset ratio, and generating a three-dimensional initial layout based on the net connection weights and module overlap repulsion, the total area of ​​the clustering modules must also be considered, and the three-dimensional initial layout is iteratively optimized based on its total area.

[0106] like Figure 3 As shown, this invention involves inputting the hierarchical structure, size, and netting relationships of the input modules; the user specifying the modules to be clustered; merging un-clustered modules into an independent clustering module; the clustering module inheriting the network information of its sub-modules, constructing equivalent netting connections, and placing pins at the center of the clustering module; iteratively generating a two-dimensional optimal layout based on the attractive forces of netting connections between clustering modules and the repulsive forces generated by module overlap; using windows to divide the modules to the top and bottom layers of the chip, and performing validation on both layers to obtain a three-dimensional initial solution; and outputting the size, position, netting information, and information of the sub-modules contained in the clustering module. Ultimately, from data collection, clustering reduction, network modeling, optimization algorithms, hierarchical strategies to result validation, this invention comprehensively addresses the shortcomings of existing methods, providing a practical and high-quality initial layout scheme for complex three-dimensional integrated circuit design.

[0107] The following is a specific embodiment of the present invention:

[0108] like Figure 4 As shown, first iterate through all modules at the user-specified level, then iterate through the modules... i All submodules contained therein are added to the cluster module corresponding to the module. iIn the process, the pins of each submodule are traversed, and the pin position is set to the center of the clustering module. The corresponding network (net) is obtained, and the other modules connected to that pin in the network are traversed to obtain their respective clustering modules. Finally, the cluster is added to the netlist. i with cluster x The connection relationships are such that repeated network connections strengthen the connection weights between each other, which will affect the attraction and repulsion of each module in the subsequent layout, thus completing the network connection relationships between the clustering modules. Finally, the cluster is obtained by dividing the total area of ​​the sub-modules by the user-specified utilization rate. i The total area.

[0109] After obtaining all clustering modules according to the above process, wire mesh modeling is performed based on a specific connection model to construct the matrix and vector of the secondary layout. Only the connection attraction between the wire meshes of the clustering modules and the repulsion generated by the overlap of the modules are considered to iteratively generate the optimal 2D layout.

[0110] Finally, according to... Figure 5 The method shown uses a 4×4 pane to divide the upper and lower layers of modules in 2D. Considering the position of the pane where the center point of the module is located, the modules in the pane are divided into the top and bottom layers of the chip. When dividing, it is also necessary to consider that the area utilization of the two layers of chips should be kept as consistent as possible. If one exceeds a threshold (the chip density before division is the default), the module is preferentially assigned to the chip with the smaller area utilization to balance the area utilization of the two chips.

[0111] Finally, after the partitioning is completed, the chip layout area is reduced (default is 2 times), and the optimal 3D initial solution is generated iteratively in the two layers of chips based on the net attraction and repulsion generated by the overlap between the modules. In other words, the clustering modules are finally placed on the top and bottom layers of chips in the optimal way.

[0112] This invention fully considers the hierarchical relationship of modules and can use the user-specified hierarchical structure to guide clustering, enabling cross-layer modules to be divided and laid out more quickly and in a more reasonable manner. By maintaining the logical integrity of clustering modules during the layout phase, unnecessary cross-layer connections are reduced, providing a more stable initial solution for subsequent 3D-EFS layout optimization.

[0113] This invention also provides a chip initial layout apparatus, including a traversal module, a clustering module, a mapping module, a building module, and an iterative generation module. The traversal module is used to traverse a specified parent module and its sub-modules within the chip hierarchy, expand the layout area, and traverse the pins of the sub-modules. The clustering module is used to hierarchically cluster the sub-modules to generate corresponding clustering modules, each of which inherits the total area, network connection relationships, and pin information of the corresponding sub-module. The mapping module is used to map the pins of the sub-modules to the center position of the clustering modules. The construction module is used to establish the wire-net connection relationships between the clustering modules based on the network of the pin connections of the sub-modules, wherein repeated network connections between the sub-modules can increase the wire-net connection weights between the corresponding clustering modules. The iterative generation module is used to construct a quadratic programming model based on the wire-net connection weights and module overlap repulsion forces between the clustering modules, and iteratively optimize and generate a two-dimensional layout area, dividing the clustering modules within the two-dimensional layout area into top-level chips and bottom-level chips. The layout area is shrunk, and a three-dimensional initial layout is iteratively generated in the top-level chips and bottom-level chips based on the wire-net connection weights and module overlap repulsion forces between the clustering modules.

[0114] The iterative generation module is also used to divide the two-dimensional layout area into N*N panes, and according to the position of the pane where the center point of the clustering module is located, as well as the area utilization rate of the top chip and the bottom chip, divide the clustering module into the top chip and the bottom chip.

[0115] The iterative generation module is also used to allocate the clustering module to the chip with a smaller area utilization rate when dividing the clustering module to the top-level chip and the bottom-level chip, if the area utilization rate of the top-level chip or the bottom-level chip exceeds a preset threshold.

[0116] The iterative generation module is also used to shrink the area of ​​the layout region according to a preset ratio; in the top-level chip and the bottom-level chip, the position of the respective clustering module is iteratively optimized based on the net connection weight and the module overlap repulsion force, thereby generating the three-dimensional initial layout.

[0117] The iterative generation module is also used to perform wire mesh modeling based on the clustering module and the preset wire mesh model, establish the wire mesh connection relationship between the clustering modules, and obtain the wire mesh connection weight; based on the wire mesh connection weight between the clustering modules and the module overlap repulsion force, construct the coefficient matrix and target vector required for solving the quadratic programming problem, and use the quadratic programming algorithm to iteratively generate a two-dimensional layout region.

[0118] The module is further configured to obtain network information of the pin connections of each sub-module, and determine all clustering modules connected to the pins in the network information; traverse all network information, and record the wire connection relationships between interconnected clustering modules in the netlist.

[0119] As can be seen from the above, the chip initial layout device provided in this application provides an orderly screening and hierarchical clustering method by specifying a parent module and its child modules, inheriting and reducing relevant area, network and pin information, and combining pin center mapping and weighted net relationship modeling to effectively simplify the original layout objects and network scale; then, by using a quadratic programming method based on net connection weights and module overlap repulsion, a highly efficient iterative optimization of the two-dimensional initial layout is achieved; and by using a reasonable partitioning and layering strategy, the clustering modules are scientifically divided into top-level and bottom-level chips, and finally, after size legalization, a high-quality three-dimensional initial layout scheme that can meet the requirements of complex integrated circuits such as 3D-EFS is generated.

[0120] It should be noted that the information interaction and execution process between the above-mentioned devices / units are based on the same concept as the method embodiments of this application. For details on their specific functions and technical effects, please refer to the method embodiments section, and they will not be repeated here.

[0121] The present invention also provides a terminal device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that the processor executes the computer program to implement the steps of the chip initial layout method as described in any of the preceding claims.

[0122] The terminal device may include, but is not limited to, processors and memory, and may also include input / output devices, network access devices, etc.

[0123] The processor referred to can be a Central Processing Unit (CPU), but it can also be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor can be a microprocessor or any conventional processor.

[0124] In some embodiments, the memory may be an internal storage unit of the terminal device, such as the terminal device's RAM. In other embodiments, the memory may be an external storage device of the terminal device, such as a plug-in hard drive, Smart Media Card (SMC), Secure Digital Card (SD), or Flash Card. Furthermore, the memory may include both internal and external storage units of the terminal device. The memory is used to store the operating system, applications, bootloader, data, and other programs, such as the program code of the computer program. The memory can also be used to temporarily store data that has been output or will be output.

[0125] In this specification, the same or similar parts between the various embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, for the product embodiments described later, since they correspond to the methods, the descriptions are relatively simple, and the relevant parts can be referred to the descriptions in the system embodiments.

[0126] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A chip initial layout method, characterized in that, include: Traverse the specified parent module and its child modules in the chip hierarchy, and expand the layout area. The sub-modules are hierarchically clustered to generate corresponding clustering modules. Each clustering module inherits the total area, network connection relationship and pin information of the corresponding sub-module. Iterate through the pins of each sub-module in each clustering module and map the pins of each sub-module to the center position of the clustering module; Based on the network connected to the pins of the submodules, a wire mesh connection relationship is established between the clustering modules, wherein repeated network connections between the submodules can increase the wire mesh connection weight between the corresponding clustering modules; Based on the wire connection weights and module overlap repulsion forces between the clustering modules, a quadratic programming model is constructed and iteratively optimized to generate a two-dimensional layout region. The two-dimensional layout area is divided into N*N panes. Based on the position of the pane where the center point of the clustering module is located, and the area utilization rate of the top chip and the bottom chip, the clustering module is assigned to the top chip and the bottom chip. If the area utilization rate of the top chip or the bottom chip exceeds a preset threshold, the clustering module is preferentially assigned to the chip with a smaller area utilization rate. The area of ​​the layout region is reduced, and a three-dimensional initial layout is generated iteratively in the top-level chip and the bottom-level chip based on the net connection weights between the clustering modules and the module overlap repulsion force.

2. The chip initial layout method according to claim 1, characterized in that, The shrinking of the layout area includes: The area of ​​the layout region is reduced according to a preset ratio; In the top-level chip and the bottom-level chip, the positions of the respective clustering modules are iteratively optimized based on the net connection weights and the module overlap repulsion forces to generate a three-dimensional initial layout.

3. The chip initial layout method according to claim 1, characterized in that, The clustering module includes a specified clustering module and an unspecified clustering module; The specified clustering module includes the specified sub-modules in the specified parent module, and the non-specified clustering module includes the non-specified sub-modules in the specified parent module.

4. The chip initial layout method according to claim 1, characterized in that, The clustering modules are spaced apart on the expanded layout area.

5. The chip initial layout method according to claim 1, characterized in that, The step of establishing the wire connection relationship between the clustering modules based on the network connected to the pins of the submodules includes: Obtain the network information of the pin connections of each submodule, and determine all the clustering modules connected to the pins in the network information; Traverse all network information and record the wire connection relationships between interconnected clustering modules in the netlist.

6. The chip initial layout method according to claim 1, characterized in that, The process of constructing a quadratic programming model based on the network connection weights and module overlap repulsion between the clustering modules, and iteratively optimizing and generating a two-dimensional layout region, includes: Based on the clustering module and the preset mesh model, mesh modeling is performed, mesh connection relationships between the clustering modules are established, and mesh connection weights are obtained. Based on the network connection weights and module overlap repulsion between the clustering modules, the coefficient matrix and target vector required for solving the quadratic programming problem are constructed, and the two-dimensional layout region is generated iteratively using the quadratic programming algorithm.

7. A chip initial layout apparatus, characterized in that, include: The traversal module is used to traverse a specified parent module and the sub-modules included in the specified parent module of the chip hierarchy, expand the layout area, and traverse the pins of the sub-modules. A clustering module is used to perform hierarchical clustering of the sub-modules to generate corresponding clustering modules. Each clustering module inherits the total area, network connection relationship and pin information of the corresponding sub-module. A mapping module is used to map the pins of the submodule to the center position of the clustering module; A network connection module is established based on the network connected to the pins of the sub-modules to establish the wire connection relationship between the clustering modules. The repeated network connections between the sub-modules can increase the wire connection weight between the corresponding clustering modules. An iterative generation module is used to construct a quadratic programming model based on the net connection weights and module overlap repulsion forces between the clustering modules, and iteratively optimize and generate a two-dimensional layout region. The two-dimensional layout region is divided into N*N panes, and the clustering modules are assigned to the top-level chip and the bottom-level chip based on the pane position of the center point of each clustering module and the area utilization rate of the top-level chip and the bottom-level chip. If the area utilization rate of the top-level chip or the bottom-level chip exceeds a preset threshold, the clustering module is preferentially assigned to a chip with a smaller area utilization rate. The layout region area is then reduced, and a three-dimensional initial layout is iteratively generated within the top-level chip and the bottom-level chip based on the net connection weights and module overlap repulsion forces between the clustering modules.

8. A terminal device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the steps of the chip initial layout method as described in any one of claims 1 to 6.

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