Data processing method, device and computer storage medium

Abstract

This application proposes a data processing method, device, and computer storage medium. The data processing method includes: obtaining a threshold voltage distribution corresponding to a target flash memory particle based on a first flash memory technology, wherein the threshold voltage distribution is used to represent the voltage distribution probability corresponding to different data states in the target flash memory particle; determining a target multiplexing relationship between different types of storage pages based on the threshold voltage distribution; and simulating a second flash memory technology on the target flash memory particle to perform data processing based on the target multiplexing relationship. The above-described data processing method improves the reliability of data reading when simulating low-data-bit flash memory technology on flash memory particles based on multi-data-bit flash memory technology.

Description

Technical Field

[0001] The present application relates to the field of data storage, and in particular to a data processing method, device, and computer storage medium. Background Art

[0002] Flash memory storage technology can be divided into the following categories based on the number of binary bits stored in each storage cell (floating-gate transistor): QLC (Quad-Level Cell), TLC (Triple-Level Cell), MLC (Multi-Level Cell), and SLC (Single-Level Cell). Compared to low-data-bit storage technology, high-data-bit flash memory technology stores more data bits in each storage cell, significantly increasing storage capacity and reducing costs in the same physical space. However, its storage performance, such as read and write speeds, is slightly inferior.

[0003] In scenarios where there are certain requirements for storage performance but the desire to control costs is high, low-data-bit flash memory technology is simulated on flash memory particles based on multi-data-bit flash memory technology to balance performance and cost. A common method is to simulate MLC on flash memory particles based on TLC. In the related art, when simulating low-data-bit flash memory technology (with n data bits) on flash memory particles based on multi-data-bit flash memory technology (with m data bits), after limiting the storage bits of each storage unit from m bits to n bits, the remaining data bits are uniformly set to a fixed value. In the related art, the data with fixed data bits will cause the corresponding voltage threshold to deviate to the high potential or low potential area for a long time. Temperature / voltage fluctuations can easily lead to state misjudgment. Therefore, fixing the remaining bits to a fixed value will make data reading less reliable.

[0004] Therefore, the related art has the problem of low data reading reliability when simulating low data bit flash memory technology on flash memory particles based on multi-data bit flash memory technology. Summary of the Invention

[0005] To solve the above technical problems, the present application proposes a data processing method, device and computer storage medium.

[0006] To solve the above technical problems, the present application proposes a data processing method, which includes:

[0007] Obtaining a threshold voltage distribution corresponding to a target flash memory particle based on a first flash memory technology, wherein the threshold voltage distribution is used to represent voltage distribution probabilities corresponding to different data states in the target flash memory particle;

[0008] determining a target multiplexing relationship between different types of memory pages based on the threshold voltage distribution;

[0009] Based on the target reuse relationship, a second flash memory technology is simulated on the target flash memory particle to perform data processing.

[0010] The determining of the target multiplexing relationship between storage pages based on the threshold voltage distribution includes:

[0011] Traversing each multiplexing relationship in the multiplexing relationship set, and determining the minimum spacing between threshold voltage peaks corresponding to each multiplexing relationship;

[0012] The target multiplexing relationship is determined in the multiplexing relationship set according to the minimum distance between threshold voltage peaks.

[0013] The step of simulating a second flash memory technology on the target flash memory particles to perform data processing based on the target reuse relationship includes:

[0014] Obtaining a write command instructing to write data to be processed;

[0015] In response to the write command, determining a target write position corresponding to each sub-data in the data to be processed;

[0016] Simulating the second flash memory technology to store the data to be processed in a corresponding cache space according to the target write position and the target multiplexing relationship;

[0017] The data to be processed is written from the cache space into the target flash memory particle.

[0018] Wherein, the target multiplexing relationship represents the multiplexing of data of the first storage page and data of the second storage page;

[0019] The cache space includes a first cache area and a second cache area;

[0020] Storing the to-be-processed data in a corresponding cache space according to the target write position and the target multiplexing relationship includes:

[0021] storing the first sub-data whose target write location is the first storage page in the first buffer area, and copying the first sub-data to the second buffer area;

[0022] The second sub-data whose target writing location is the third storage page is stored in the first buffer area.

[0023] The data processing method further includes:

[0024] After the first sub-data is stored in the first channel of the first cache area, sending a first write request to the flash memory controller, wherein the first write request is used to instruct the flash memory controller to write the data of the first channel into the target flash memory particle;

[0025] After the first sub-data is stored in the second channel of the first cache area, a second write request is sent to the flash memory controller, wherein the second write request is used to instruct the flash memory controller to write the data in the second channel and at least part of the data in the second cache area into the target flash memory particles in sequence.

[0026] The data processing method further includes:

[0027] Reading valid data in a to-be-processed flash memory block in the target flash memory particle, and placing the read valid data in a preset cache area, wherein the amount of valid data read each time is less than or equal to a first preset data amount;

[0028] The valid data is written into a target flash memory block in the target flash memory particle according to the data amount of the valid data and the target multiplexing relationship.

[0029] Wherein, the target multiplexing relationship represents the multiplexing of data of the first storage page and data of the second storage page;

[0030] The step of writing the valid data into a target flash memory block in the target flash memory particle according to the data amount of the valid data and the target multiplexing relationship includes:

[0031] When the amount of the valid data is equal to the first preset data amount, first valid data among the valid data is written to the first storage page in the target flash memory block; the first valid data is reused to write the first valid data to the second storage page in the target flash memory block; and the remaining valid data among the valid data is written to the third storage page of the target flash memory block;

[0032] When the amount of the valid data is less than the first preset data amount and greater than the second preset data amount, first valid data in the valid data is written to the first storage page; the first valid data is reused and written to the second storage page; remaining valid data in the valid data is padded and written to the third storage page;

[0033] When the amount of the valid data is less than or equal to the second preset data amount, the valid data is filled; the second valid data obtained after filling is written to the first storage page of the target flash memory block; the second valid data is reused and written to the second storage page; and the filled data is written to the third storage page.

[0034] The data processing method further includes:

[0035] When an error occurs in reading data of the target storage page, reading data of a multiplexing storage page multiplexed with the target storage page;

[0036] When reading the data of the reused storage page successfully, determining that an exception occurs when writing the data from the cache space to the target flash memory particle;

[0037] In the case where an error occurs in reading data from the reused storage page, it is determined that an abnormality occurs when storing the data in the cache space.

[0038] To solve the above technical problems, the present application also proposes a data processing device, which includes a memory and a processor coupled to the memory; wherein the memory is used to store program data, and the processor is used to execute the program data to implement the data processing method as described above.

[0039] In order to solve the above technical problems, the present application also proposes a computer storage medium, which is used to store program data. When the program data is executed by a computer, it is used to implement the above data processing method.

[0040] Compared with the prior art, the beneficial effects of the present application are: when simulating the second flash memory technology on the target flash memory particles of the first flash memory technology, the target multiplexing relationship is determined according to the threshold voltage distribution, and at least two storage pages in the first flash memory technology are multiplexed according to the target multiplexing relationship to realize the simulation of low-data-bit flash memory technology on flash memory particles of multi-data-bit flash memory technology. Through the multiplexing of storage pages, the data of all data bits are not fixed values, and the corresponding voltage threshold will not be biased towards the high potential or low potential area for a long time, which reduces the state misjudgment when reading data and improves the reliability of data reading when simulating low-data-bit flash memory technology on flash memory particles based on multi-data-bit flash memory technology. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for describing the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without inventive efforts. Among them:

[0042] Figure 1 This is a flow chart of an embodiment of a data processing method provided by the present application;

[0043] Figure 2 is a schematic diagram of the threshold voltage distribution in an embodiment provided by the present application;

[0044] Figure 3 This is a schematic diagram of the threshold voltage distribution after the most significant data bit is fixed to 1, provided by the present application;

[0045] Figure 4 Schematic diagram of the threshold voltage distribution after LP and MP multiplexing in one embodiment provided by the present application;

[0046] Figure 5 Schematic diagram of the threshold voltage distribution after UP and MP are multiplexed in one embodiment provided by the present application;

[0047] Figure 6 This is a schematic diagram of the threshold voltage distribution after UP and LP are multiplexed in one embodiment provided by the present application;

[0048] Figure 7 is a schematic diagram of a cache space in an embodiment provided by the present application;

[0049] Figure 8 This is a schematic diagram of word line alignment writing in TLC in another embodiment provided by the present application;

[0050] Figure 9 is a schematic diagram of a cache space in another embodiment provided by the present application;

[0051] Figure 10 This is a schematic diagram of the state change of the cache space when the data to be processed is written into the cache space provided by the present application;

[0052] Figure 11 This is a flowchart of the write command processing provided by this application;

[0053] Figure 12 This is a schematic diagram of data writing in GC mode in the first embodiment provided by this application;

[0054] Figure 13 This is a schematic diagram of data writing in GC mode in the second embodiment provided by this application;

[0055] Figure 14 This is a schematic diagram of data writing in GC mode in the third embodiment provided by this application;

[0056] Figure 15 It is a structural diagram of an embodiment of a data processing device provided by the present application;

[0057] Figure 16 It is a structural diagram of an embodiment of a data processing device provided by the present application;

[0058] Figure 17 It is a structural diagram of an embodiment of a computer storage medium provided by this application. DETAILED DESCRIPTION

[0059] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0060] The terms "first," "second," "third," "fourth," and the like (if any) in the specification and claims of this application and in the accompanying drawings are used to distinguish similar objects and are not necessarily used to describe a particular order or precedence. It should be understood that the terms used in this manner are interchangeable where appropriate, so that the embodiments of the application described herein can, for example, be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having," and any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or apparatus comprising a series of steps or elements is not necessarily limited to those steps or elements explicitly listed, but may include other steps or elements not explicitly listed or inherent to such process, method, product, or apparatus.

[0061] To facilitate understanding of the embodiments of the present application, the technical terms appearing in the embodiments are explained below:

[0062] SLC: Single-Level Cell, a single-layer cell. Its core technology is that each storage cell can store 1 bit of data.

[0063] MLC: Multi-Level Cell, a double-layer cell. Its core technology is that each storage cell can store 2 bits of data. Its advantages are longer erase and write life and relatively fast read and write speeds, but it is more expensive and has lower capacity density.

[0064] TLC: Triple-Level Cell, a three-layer cell. Its core technology is that each storage cell can store 3 bits of data. The advantages are low production cost and high capacity density, but the disadvantages are short erase and write life and relatively slow read and write speed.

[0065] QLC: Quad-Level Cell, a four-layer cell. Its core technology is that each storage cell can store 4 bits of data. It has higher capacity density and lower cost. It is suitable for large-capacity storage products. The read and write speed is slower than TLC and MLC.

[0066] pMLC: pseudo Multi-Level Cell, a technology that simulates the performance of TLC or QLC-based flash memory particles to MLC through firmware and controller optimization.

[0067] Gray code distribution: A technology that maps binary data to the charge state of flash memory cells. Gray code is a cyclic binary encoding in which only one bit changes between adjacent values. The Gray code corresponding to two-bit data is 00→01→11→10→00, and the Gray code corresponding to three-bit data is 111→101→100→000→001→011→010→110→111.

[0068] A page (memory page) is the basic write / read unit of a flash memory chip. A page consists of multiple memory cells on the same word line. In MLC flash memory, one word line corresponds to three pages: Lower Page and Upper Page; in TLC flash memory, one word line corresponds to three pages: Lower Page, Middle Page, and Upper Page; in QLC flash memory, one word line corresponds to four pages: Lower Page, Middle Page 1, Middle Page 2, and Upper Page.

[0069] Lower Page (LP): used to store the least significant bit of data. It is the first memory page written during programming. For example, in a 3-bit TLC data, the least significant bit is the rightmost data bit (such as the 1 in 001).

[0070] Middle Page (MP): used to store the middle significant bit data. For example, in the 3-bit data of TLC, the middle significant bit is the middle data bit (such as 1 in 010).

[0071] Upper Page (UP): Used to store the most significant bit of data. It is the last memory page written. For example, in the 3-bit data of TLC, the middle significant bit is the leftmost data bit (such as 1 in 100).

[0072] Die: A bare die is the smallest functional unit of a chip. In flash memory technology, each die contains an independent memory array that can independently execute commands and return status. Multiple dies can be packaged into a single chip to create greater storage capacity.

[0073] Plane: An independent storage partition within a die, containing independent page buffers and control circuitry, supports on-chip parallel operations. A die typically has 2 to 8 planes (for example, TLC flash memory often has two planes per die). Multi-plane technology allows multiple planes within a die to be read and written simultaneously.

[0074] NVML: Non-volatile Memory Location, a non-volatile memory location used to describe the data size or address that can be programmed once on a die.

[0075] Word line: A signal line that controls the selection of a row of memory cells. When a word line is activated, the corresponding row of memory cells will be selected for read and write operations.

[0076] Bit line: A vertical data line used to transmit specific binary data.

[0077] The data processing method of the present application is applied to a data processing device, wherein the data processing device of the present application can be a server, a terminal device, or a system comprising a server and a terminal device in cooperation with each other. Accordingly, the various components of the data processing device, such as the various units, subunits, modules, and submodules, can be all provided in the server, all provided in the terminal device, or separately provided in the server and the terminal device.

[0078] Furthermore, the server described above may be either hardware or software. When the server is hardware, it may be implemented as a distributed server cluster consisting of multiple servers, or as a single server. When the server is software, it may be implemented as multiple software programs or software modules, such as software or software modules for providing a distributed server, or as a single software program or software module, without further limitation.

[0079] Please refer to the following for details: Figure 1 , Figure 1 This is a flow chart of an embodiment of the data processing method provided by this application. Figure 1 As shown, the specific steps are as follows:

[0080] Step S11: obtaining a threshold voltage distribution corresponding to a target flash memory particle based on a first flash memory technology, wherein the threshold voltage distribution is used to represent voltage distribution probabilities corresponding to different data states in the target flash memory particle.

[0081] Step S12: determining a target multiplexing relationship between different types of memory pages based on the threshold voltage distribution.

[0082] In an embodiment of the present application, the first flash memory technology and the second flash memory technology are different flash memory technologies, and the number of data bits that can be stored in each storage unit corresponding to the first flash memory technology is greater than the number of data bits that can be stored in each storage unit corresponding to the second flash memory technology.

[0083] The first flash memory technology is a multi-data bit flash memory technology, specifically one of QLC, TLC, and MLC, or other flash memory technologies, wherein the number of data bits that can be stored in each storage unit is greater than 1.

[0084] The second flash memory technology is a low data bit flash memory technology, specifically, the number of data bits that can be stored in each storage unit is less than any flash memory technology of the first flash memory technology. For example, when the first flash memory technology is QLC, the second flash memory technology can be TLC or MLC or SLC. When the first flash memory technology is TLC, the second flash memory technology can be MLC or SLC.

[0085] In this embodiment, data multiplexing is used to simulate the second flash memory technology on the target flash memory particles based on the first flash memory technology. This data multiplexing refers to always writing the same data in at least two reused storage pages to map the corresponding m voltage states or data states in the first flash memory technology to n voltage states or data states in the second flash memory technology, where m and n are both integers greater than or equal to 1, and m is greater than n.

[0086] Taking the simulation of MLC on a target flash memory particle based on TLC as an example, each storage cell of TLC stores 3 bits of data, corresponding to 8 data states (000 to 111), and each storage cell of MLC stores 2 bits of data, corresponding to 4 data states (00 to 11). Simulating MLC on a target flash memory particle based on TLC means mapping the 8 data states in TLC to the 4 data states in MLC.

[0087] TLC is managed through three independent memory pages (LP, MP, and UP). Two of these pages are reused, for example, LP and MP. This means that two of the three bits of data stored in each TLC cell are reused (the two reused bits remain consistent). Each TLC cell originally stores three bits of data: Q2, Q1, and Q0. Q2 is stored in UP, Q1 in MP, and Q0 in LP. If Q2 is forced to equal Q1, meaning UP and MP are reused, the valid data states become four (000, 001, 110, and 111), which can be mapped to the four data states corresponding to MLC.

[0088] When simulating TLC on a QLC-based target flash memory particle, two storage pages can be selected from the four storage pages corresponding to QLC for multiplexing to map the 16 data states in QLC to the 8 data states in TLC. When simulating MLC on a QLC-based target flash memory particle, three storage pages can be selected from the four storage pages corresponding to QLC for multiplexing or the four storage pages can be multiplexed in pairs to map the 16 data states in QLC to the 4 data states in MLC.

[0089] The data state of the first flash memory technology can be mapped to the data state of the second flash memory technology through storage page reuse. However, when simulating the second flash memory technology based on the target flash memory particles of the first flash memory technology, it is necessary to further determine which storage pages in the first flash memory technology are reused. Taking the simulation of MLC on the target flash memory particles based on TLC as an example, it is necessary to select two storage pages from the three storage pages in the TLC for reuse. Which two storage pages need to be selected for reuse, that is, to determine the target reuse relationship.

[0090] When determining the target reuse relationship, the target reuse relationship is determined based on the threshold voltage distribution corresponding to the target flash memory particles. The threshold voltage distribution includes the voltage distribution corresponding to the storage unit in different data states. Figure 2 , Figure 2 is a schematic diagram of the threshold voltage distribution in an embodiment provided in this application, Figure 2 The data states stored in the memory cell are shown in the figure. The horizontal axis represents the voltage of the memory cell. Figure 2 The data states corresponding to the corresponding TLCs follow a Gray code distribution, that is, the data states corresponding to adjacent threshold voltage intervals differ by only one bit.

[0091] Through 7 threshold voltages ( Figure 2 The voltage values ​​corresponding to the 7 vertical dotted lines are voltage value 0, voltage value 1, voltage value 2, voltage value 3, voltage value 4, voltage value 5, and voltage value 6, respectively. The voltage axis is divided into 8 threshold voltage intervals, and each threshold voltage interval corresponds to a data state, that is, when the voltage of the storage cell is less than voltage value 0, the data state is 111, when the voltage of the storage cell is greater than voltage value 0 and less than voltage value 1, the data state is 011, when the voltage of the storage cell is greater than voltage value 1 and less than voltage value 2, the data state is 001, when the voltage of the storage cell is greater than voltage value 2 and less than voltage value 3, the data state is 000, when the voltage of the storage cell is greater than voltage value 3 and less than voltage value 4, the data state is 010, when the voltage of the storage cell is greater than voltage value 4 and less than voltage value 5, the data state is 110, when the voltage of the storage cell is greater than voltage value 5 and less than voltage value 6, the data state is 100, and when the voltage of the storage cell is greater than voltage value 6, the data state is 101.

[0092] The third storage page Upper Page corresponds to the highest data bit, and its corresponding threshold voltages are: voltage value 0 and voltage value 4; the second storage page Middle Page corresponds to the middle data bit, and its corresponding threshold voltages are: voltage value 1, voltage value 3, and voltage value 5; the first storage page Lower Page corresponds to the lowest data bit, and its corresponding threshold voltages are: voltage value 2 and voltage value 6.

[0093] Figure 2 The eight threshold voltage peaks (ER peak, A~G peaks) represent the probability that the storage cell is at each voltage value under the corresponding data state. The ER peak corresponds to the erased state, and the corresponding data state is 111. The data state corresponding to the A peak is 011. The data state corresponding to the B peak is 001. The data state corresponding to the C peak is 000. The data state corresponding to the D peak is 010. The data state corresponding to the E peak is 110. The data state corresponding to the F peak is 100. The data state corresponding to the G peak is 101.

[0094] In the related art, when simulating MLC on TLC-based flash memory particles, the three data bits of TLC are limited to two, and the remaining one is set to a fixed value. For example, the most significant data bit is fixed to 1. Figure 3 , Figure 3 is a schematic diagram of the threshold voltage distribution after the most significant data bit (ie, the data bit corresponding to the Upper Page) is fixed to 1, as provided in this application. Figure 3 As shown, a single memory cell corresponds to four data states, namely 111, 110, 100, and 101. The probability of the memory cell being at each voltage value in the four data states corresponds to Figure 3 The ER peak, A peak, B peak, and C peak in the image are shown. Among them, the distances between adjacent threshold voltage peaks in peaks A, B, and C are relatively close, which easily leads to overlapping threshold voltage intervals of adjacent states, resulting in misjudgment during reading (such as 110 being misread as 100), and reducing data reading reliability.

[0095] The target multiplexing relationship is determined based on the threshold voltage distribution to ensure that after the two storage pages are multiplexed, the spacing between multiple threshold voltage peaks corresponding to different data states of the target flash memory particles is large.

[0096] In an optional embodiment, determining the target multiplexing relationship between storage pages based on the threshold voltage distribution includes: traversing each multiplexing relationship in the multiplexing relationship set, and determining the corresponding minimum spacing of threshold voltage peaks under each multiplexing relationship; and determining the target multiplexing relationship in the multiplexing relationship set according to the minimum spacing of threshold voltage peaks.

[0097] Taking the simulation of MLC on a TLC-based target flash memory particle as an example, it is necessary to select two storage pages in the TLC for multiplexing. The multiplexing relationship set includes three selectable multiplexing relationships: UP and MP multiplexing, MP and LP multiplexing, and LP and MP multiplexing.

[0098] See also Figure 4 , Figure 4 FIG. 1 is a schematic diagram of the threshold voltage distribution after LP and MP are multiplexed in one embodiment provided by the present application. Figure 4 As shown, LP and MP are multiplexed, that is, the first storage page Lower Page and the second storage page Middle Page are multiplexed, that is, the lowest data bit and the middle data bit are written with the same data. At this time, a single storage cell corresponds to four data states, namely 111, 011, 000, and 100. The probability of the storage cell being at each voltage value in the four data states corresponds to Figure 4 ER peak, A peak, B peak, and C peak.

[0099] See also Figure 5 , Figure 5 FIG. 1 is a schematic diagram of the threshold voltage distribution after UP and MP are multiplexed in one embodiment provided by the present application. Figure 5 As shown, UP and MP are multiplexed, that is, the third storage page Upper Page and the second storage page Middle Page are multiplexed, that is, the middle data bit and the highest data bit are written with the same data. At this time, a single storage cell corresponds to four data states, namely 111, 001, 000, and 110. The probability of the storage cell being at each voltage value in the four data states corresponds to Figure 5 ER peak, A peak, B peak, and C peak.

[0100] See also Figure 6 , Figure 6 FIG. 1 is a schematic diagram of the threshold voltage distribution after UP and LP are multiplexed in one embodiment provided by the present application. Figure 6 As shown, UP and LP are multiplexed, that is, the third storage page Upper Page and the first storage page Lower Page are multiplexed, that is, the lowest data bit and the highest data bit are written with the same data. At this time, a single storage cell corresponds to four data states, namely 111, 000, 010, and 101. The probability of the storage cell being at each voltage value in the four data states corresponds to Figure 6 ER peak, A peak, B peak, and C peak.

[0101] Determine the minimum spacing of the threshold voltage peaks corresponding to each multiplexing relationship respectively. Specifically, determine the spacing between any two adjacent threshold voltage peaks. Each multiplexing relationship corresponds to four threshold voltage peaks, and each multiplexing relationship corresponds to four spacings. The minimum value of the four spacings is determined as the minimum spacing of the threshold voltage peaks.

[0102] The target multiplexing relationship is determined according to the minimum spacing of the threshold voltage peaks corresponding to each multiplexing relationship, that is, the multiplexing relationship corresponding to the maximum value among the three minimum spacings of the threshold voltages corresponding to the three multiplexing relationships is determined as the target multiplexing relationship.

[0103] Optionally, since the distance between the threshold voltage peak corresponding to the erased state (ER peak) and its adjacent threshold voltage peak is much larger than the distance between any other two threshold voltage peaks, the distance between the erased state and other threshold voltage peaks can be ignored when determining the threshold voltage peak corresponding to each multiplexing relationship, and only the multiple threshold voltage peaks corresponding to the non-erased state (such as Figures 4 to 6 The distance between any two adjacent threshold voltage peaks (peak A, peak B, peak C in ).

[0104] Figure 4 The minimum spacing between the threshold voltage peaks is the spacing between peaks A and B, assuming it is 2. Figure 5 The minimum spacing between the threshold voltage peaks is the spacing between peaks A and B, assuming it is 1. Figure 6 The minimum spacing between the middle threshold voltage peaks is also the spacing between peaks A and B, and is assumed to be 1. It can be seen that the maximum value among the three minimum spacings of the threshold voltages corresponding to the three multiplexing relationships is 2, and the corresponding multiplexing relationship is LP and MP multiplexing. Therefore, the target multiplexing relationship determined in this embodiment is LP and MP multiplexing.

[0105] Step S13: simulating a second flash memory technology on the target flash memory particles to perform data processing based on the target reuse relationship.

[0106] In an embodiment of the present application, a controller of a target flash memory particle executes the aforementioned data processing method, and the controller includes a flash memory controller and a flash memory translation layer. After determining the target multiplexing relationship, the controller simulates a second flash memory technology on the target flash memory particle based on the target multiplexing relationship to perform data processing. The data processing includes, but is not limited to, storing only two valid bits of data in each storage cell in the target flash memory particle and reading only the two valid bits of data from each storage cell when reading data.

[0107] In the present application, when simulating the second flash memory technology on the target flash memory particles of the first flash memory technology, the target multiplexing relationship is determined according to the threshold voltage distribution, and at least two storage pages in the first flash memory technology are multiplexed according to the target multiplexing relationship to realize the simulation of the low-data-bit flash memory technology on the flash memory particles of the multi-data-bit flash memory technology. Through the multiplexing of the storage pages, the data of all data bits are not fixed values, and the corresponding voltage threshold will not be biased towards the high potential or low potential area for a long time, which reduces the state misjudgment when reading data and improves the reliability of data reading when simulating the low-data-bit flash memory technology on the flash memory particles based on the multi-data-bit flash memory technology.

[0108] In addition, the minimum spacing of threshold voltage peaks under each multiplexing relationship is determined based on the threshold voltage distribution, and the best multiplexing relationship, that is, the target multiplexing relationship, is selected from multiple multiplexing relationships based on the minimum spacing of threshold voltage peaks, so that the spacing of the voltage threshold interval is looser, that is, the threshold voltage distribution is more dispersed, reducing misreading caused by temperature / voltage fluctuations, and further improving the reliability of data reading when simulating low data bit flash memory technology on flash memory particles based on multi-data bit flash memory technology.

[0109] When simulating the second flash memory technology to perform data processing on the target flash memory particle based on the target multiplexing relationship, the data processing includes writing the data to be processed.

[0110] When writing data on the target flash memory particle, the following process must be followed: the host sends the pending data to the controller through a write command. The flash memory conversion layer in the controller stores the sent pending data in the cache area to temporarily store the pending data to be written, and sends a write request to the flash memory controller to forward the pending data from the cache space to the target flash memory particle through the flash memory controller.

[0111] In an optional embodiment, a write command indicating writing of the data to be processed is obtained; in response to the write command, a target write position corresponding to each sub-data in the data to be processed is determined; according to the target write position and the target multiplexing relationship, the second flash memory technology is simulated to store the data to be processed in the corresponding cache space; and the data to be processed is written from the cache space to the target flash memory particle.

[0112] In an embodiment of the present application, when writing data to the target flash memory particle, the data is written in a word line aligned manner. When the controller receives the data to be processed, it splits the data to be processed into multiple sub-data according to the paging structure of the word line in the target flash memory particle using NVML (Non-volatile Memory Location), and determines the target write position of each sub-data. The target write position refers to the physical address where the sub-data is about to be written in the target flash memory particle, that is, the specific storage page corresponding to the specific word line of the target flash memory particle is written. The sub-data is first cached in different locations in the cache space according to the target write position and the target multiplexing relationship.

[0113] Since the second flash memory technology is simulated in this embodiment, when dividing data, the write location of the sub-data should include only the storage pages corresponding to the second flash memory technology. Taking the first flash memory technology as TLC, the second flash memory technology as MLC, and the MP multiplexing the LP data as an example, the target write locations of the sub-data after the data to be processed is LP and UP. When simulating MLC on TLC, the MP data still needs to be configured. In this embodiment, the LP data is copied to the MP.

[0114] In an optional embodiment, the target multiplexing relationship represents the multiplexing of data of the first storage page and data of the second storage page; the cache space includes a first cache area and a second cache area; the data to be processed is stored in the corresponding cache space according to the target write position and the target multiplexing relationship, including: storing the first sub-data of the first storage page whose target write position is stored in the first cache area, and copying the first sub-data to the second cache area; storing the second sub-data of the third storage page whose target write position is stored in the first cache area.

[0115] In this embodiment, the first flash memory technology is TLC, the second flash memory technology is MLC, and the storage pages controlled by each word line in TLC include 3 storage pages (the first storage page, the second storage page, and the third storage page). The first storage page is LP, the second storage page is MP, and the third storage page is UP. The target multiplexing relationship is LP and MP multiplexing, that is, the data of the first storage page is multiplexed with the data of the second storage page.

[0116] When writing data, it is written in the form of word line alignment. Taking the word line range of 192KB as an example, the storage page controlled by a word line in the target flash memory particle includes 3 storage pages (the first storage page LP, the second storage page MP and the third storage page UP). The storage pages are written in the following order: LP, MP, UP. The size of each storage page is 64KB.

[0117] After receiving the data to be written, the write data will be divided according to the paging structure of the word line. The TLC will split the data into three parts according to the structure of the three storage pages in the TLC. Among them, the multiple sub-data in the first part of the data are programmed by LP in different word lines and stored in the target flash memory particles, the multiple sub-data in the second part of the data are programmed by MP in different word lines and stored in the target flash memory particles, and the multiple sub-data in the third part of the data are programmed by UP in different word lines and stored in the target flash memory particles.

[0118] In this embodiment, because MLC is simulated on a TLC-based target flash memory cell, upon receiving data to be written (data to be processed), it is split into two parts. The multiple sub-data in the first part are programmed into the target flash memory cell using the LPs in different word lines, while the multiple sub-data in the second part are programmed into the target flash memory cell using the UPs in different word lines. To enable word-line-aligned writing, the data corresponding to the LP is copied to the MP.

[0119] in, Figures 2 to 6 The first storage page corresponds to the Lower Page, the second storage page corresponds to the Middle Page, and the third storage page corresponds to the Upper Page.

[0120] See also Figure 7 , Figure 7 This is a schematic diagram of the cache space in an embodiment provided by this application, please refer to Figure 7 The cache space is divided into a first cache area and a second cache area, wherein the first cache area is used to cache data of the first storage page and the third storage page, and the data of the first storage page is copied and cached in the second cache area, that is, the second cache area caches the copied data, and the cache space is used cyclically.

[0121] In this embodiment, a storage page controlled by a word line in the target flash memory particle includes three storage pages (a first storage page LP, a second storage page MP, and a third storage page UP). The first storage page and the second storage page are multiplexed, that is, the data to be processed will be written into the first storage page and the third storage page, and the data of the second storage page is set to be the same as the data of the first storage page.

[0122] The data to be processed is divided into multiple first sub-data corresponding to LP and multiple second sub-data corresponding to UP according to their corresponding target write positions. The data to be processed (multiple first sub-data and multiple second sub-data) are stored in the first cache area in sequence. After the first sub-data is stored in the first cache area, the first sub-data is copied and stored in the second cache area.

[0123] For example, see Figure 8 and Figure 9 , Figure 8 This is a schematic diagram of word line alignment writing in TLC in another embodiment provided by the present application. Figure 9 This is a schematic diagram of the cache space in another embodiment provided by the present application. In this embodiment, each Die has two Planes (Channel0 and Channel1), which can operate on the storage pages of different Planes at the same time. When writing data, it is split according to the storage page type, specifically split into LP, MP, and UP. The data of each storage page is further split, and the split data corresponds to Figure 8 LP0, LP1, MP0, MP1, UP0 and UP1 in the system are written in parallel using multi-plane technology. Figure 8 The data write order of the flash memory shown is: LP0, LP1, MP0, MP1, UP0, UP1. LP0, LP1, MP0, MP1, UP0, and UP1 each occupy 32KB, corresponding to the size of one NVML data page. A memory page occupies 64KB, and the size of a word line is 192KB. LP0 and LP1 are the first and second channels of the first memory page, respectively. MP0 and MP1 are the first and second channels of the second memory page, respectively. UP0 and UP1 are the first and second channels of the third memory page, respectively.

[0124] based on Figure 8 Word line alignment write, the cache space is divided into Figure 9 The first cache area and the second cache area shown in the figure, the first cache area caches user data, i.e., data to be processed, and the second cache area caches copied data. The first cache area and the second cache area are both divided into four unit spaces (slot0~slot7), and the size of each unit space is 32KB. When a write command is received, each sub-data is temporarily stored in the unit space of the first cache area in sequence, and the first sub-data is copied and temporarily stored in the unit space of the second cache area. The status of each unit space is updated in real time, and the status of each unit space is divided into an idle state and a used state. Slot0 and slot1 in the first cache area are used to cache the first sub-data to be written to LP0 and LP1, and slot2 and slot3 in the first cache area are used to cache the second sub-data to be written to UP0 and UP1.

[0125] See also Figure 10 , Figure 10 This is a schematic diagram of the state change of the cache space when the data to be processed is written into the cache space provided by this application, such as Figure 10 As shown:

[0126] S1001, during initialization, the states of all unit spaces are initialized to an idle state;

[0127] S1002: After initialization, the sub-data in the data to be processed are sequentially stored in the first buffer area. First, two first sub-data are stored in slots 0 and 1 of the first buffer area. Slots 0 and 1 are put into use. Slots 4 and 5 are requested to cache copies of the two first sub-data. Slots 4 and 5 are put into use.

[0128] S1003, two second sub-data are stored in slot 2 and slot 3 in the first buffer area, and slot 2 and slot 3 become in use;

[0129] S1004: After the data stored in slot 0 and slot 1 in the first cache area are written into the target flash memory particle, the corresponding cache space is released, and slot 0 and slot 1 become idle;

[0130] S1005: After the two first sub-data are stored in slot 0 and slot 1 in the first buffer area, slot 0 and slot 1 are changed from the idle state to the used state again; slot 6 and slot 7 are requested to cache the copies of the two first sub-data, and slot 6 and slot 7 are changed to the used state;

[0131] S1006: Slot 4 and slot 5 in the second cache area write the stored data into the target flash memory particle, releasing the corresponding cache space, and slot 4 and slot 5 become idle;

[0132] S1007: The data stored in slot 2 and slot 3 in the first cache area are written into the target flash memory chip, releasing the corresponding cache space, and slot 2 and slot 3 become idle;

[0133] S1008, after storing two second sub-data in slot 2 and slot 3 in the first buffer area, slot 2 and slot 3 are changed from the idle state to the used state again;

[0134] S1009: The data stored in slot 0 and slot 1 in the first cache area are written into the target flash memory chip, releasing the corresponding cache space, and slot 0 and slot 1 become idle again;

[0135] S1010: The two first sub-data are stored in slots 0 and 1 in the first buffer again, and slots 0 and 1 are changed from the idle state to the used state again; slots 4 and 5 are requested to cache the copies of the two first sub-data, and slots 4 and 5 are changed to the used state;

[0136] S1011, the data stored in slots 6 and 7 in the second cache area is written into the target flash memory particle, the corresponding cache space is released, and slots 6 and 7 become idle;

[0137] S1012: The data stored in slot 2 and slot 3 in the first cache area are written into the target flash memory chip, releasing the corresponding cache space, and slot 2 and slot 3 become idle.

[0138] S1013, after the two second sub-data are stored in slot 2 and slot 3 of the first cache area again, slot 2 and slot 3 are changed from the idle state to the used state again... The above rules are cyclically executed to manage the cache space.

[0139] In an optional embodiment, after the first sub-data is stored in the first channel of the first cache area, a first write request is sent to a flash memory controller, wherein the first write request is used to instruct the flash memory controller to write the data of the first channel into the target flash memory particle;

[0140] After the first sub-data is stored in the second channel in the first cache area, a second write request is sent to the flash memory controller, wherein the second write request is used to instruct the flash memory controller to write the data in the second channel and at least part of the data in the second cache area into the target flash memory particles in sequence.

[0141] In this embodiment, when processing a write command to write data to be processed, a write request is generated after each sub-data is stored in the cache space. The write request is sent to the flash memory controller, and the flash memory controller processes the write request to write the corresponding data from the cache space to the target flash memory particle.

[0142] According to the different locations of the sub-data stored in the cache space, the write request sent is different. Specifically, the target write location of the first sub-data is the first storage page. Further, if the target write location is the first channel of the first storage page, that is, corresponding to Figure 8 LP0 in the first buffer, that is, the first sub-data is stored in the first channel of the first buffer (corresponding to Figure 9 At the same time, the first sub-data will be copied to the second buffer area (corresponding to slot 0 in Figure 9 Slot4 in the first buffer), at this time, the first write request is issued. The first write request is just the flash memory controller writing the data in slot0 (the data in the first channel in the first cache area) into the target flash memory particle. Specifically, it is written into the target flash memory particle through word line encoding. The data stored in slot4 needs to wait for the first sub-data after the second channel to be written before it is written into the target flash memory particle.

[0143] After the first sub-data is stored in the first channel of the first buffer, the next first sub-data is stored in the second channel of the first buffer (corresponding to Figure 9 At the same time, the first sub-data is copied to the second buffer area (corresponding to slot 1 in Figure 9 Slot5 in the second channel), a second write request is issued at this time. The second write request is just the flash memory controller writing the following data in sequence: the data in the second channel (corresponding to Figure 9 data in slot 1 in the second buffer area), at least part of the data in the second buffer area (corresponding to Figure 9 slot4 and slot5 data in ).

[0144] The second sub-data will then be stored in the first cache area. After each second sub-data is stored, a third write request is directly generated to instruct the flash memory controller to write the second sub-data just placed into the target flash memory particle.

[0145] See also Figure 11 , Figure 11 This is a flowchart of the write command processing provided by this application, such as Figure 11As shown, when a write command is received to write the data to be processed into the target flash memory particle, the process of processing the write command includes:

[0146] S1101, dividing the data to be processed into multiple sub-data according to the NVML size, so as to process each sub-data separately;

[0147] S1102: Process each sub-data separately to find the target write location in the target flash memory particle where the sub-data is to be written. The specific location can be determined based on a pointer variable. The pointer variable stores a physical address in the flash memory that points to the target write location where the data is to be written.

[0148] S1103, determines whether the target write location of the sub-data is the first storage page (LP0 or LP1); if the target write location is LP0 or LP1, execute step S1104; if it is not one of LP0 or LP1, the target write location is UP1 or UP0, execute step S1109;

[0149] S1104 , further determining whether the target write location is the first channel ( LP0 ) of the first storage page; if it is LP0 , executing step S1105 ; if it is not LP0 , that is, the target write location is LP1 , executing step S1107 .

[0150] S1105, storing the sub-data in the first channel of the first buffer area, and copying the sub-data to the second buffer area;

[0151] S1106, sending a first write request;

[0152] S1107, storing the sub-data in the second channel of the first buffer area, and copying the sub-data to the second buffer area;

[0153] S1108, sending a second write request;

[0154] S1109, storing the sub-data in the first buffer area and sending a third write request;

[0155] S1110 , after sending a write request (a first write request, a second write request, or a third write request), updating a pointer variable;

[0156] The above steps are repeated until all sub-data are stored in the cache space.

[0157] In an optional embodiment, based on the target reuse relationship, a second flash memory technology is simulated on the target flash memory particle to perform data processing, and the data in the target flash memory particle is further subjected to GC (Garbage Collection) processing, that is, valid data on a flash memory block is read out and rewritten, and then the flash memory block is erased to obtain a new available flash memory block.

[0158] The specific GC processing process includes: reading valid data in the flash memory block to be processed in the target flash memory particle, and placing the read valid data in a preset cache area, wherein the amount of valid data read each time is less than or equal to a first preset data amount;

[0159] The valid data is written into a target flash memory block in the target flash memory particle according to the data amount of the valid data and the target multiplexing relationship.

[0160] In this embodiment, the flash memory block to be processed and the target flash memory block are two different flash memory blocks in the same flash memory particle. The valid data of the flash memory block to be processed is read out and written into the new target flash memory block. After the valid data is read, the data of the flash memory block to be processed is erased. The preset cache area is used to temporarily store the valid data read from the flash memory block to be processed.

[0161] In this embodiment, MLC is simulated on a TLC-based flash memory particle. The TLC corresponds to three storage pages (a first storage page, a second storage page, and a third storage page). The first storage page and the second storage page are multiplexed.

[0162] When reading data, it is read multiple times. Since the first storage page and the second storage page are multiplexed, only data of two storage pages need to be read each time, for example, data of the first storage page and data of the third storage page (or data of the second storage page and data of the third storage page) are read.

[0163] When writing the read data into the target flash memory block, the data of the second storage page only needs to reuse the data of the first storage page.

[0164] Each time valid data is read, the reading is performed with the first preset data amount as the target. When the valid data of the flash memory block to be processed is less than the first preset data amount, the amount of valid data read last in sequence is less than the first preset data amount. Therefore, the amount of valid data read each time is less than or equal to the first preset data amount.

[0165] The valid data is written into the target flash memory block according to the data amount of the read valid data and the target multiplexing relationship.

[0166] In an optional embodiment, writing the valid data into the target flash memory block in the target flash memory particle according to the data amount of the valid data and the target multiplexing relationship includes:

[0167] When the amount of the valid data is equal to the first preset data amount, first valid data among the valid data is written to the first storage page in the target flash memory block; the first valid data is reused to write the first valid data to the second storage page in the target flash memory block; and the remaining valid data among the valid data is written to the third storage page of the target flash memory block;

[0168] When the amount of the valid data is less than the first preset data amount and greater than the second preset data amount, first valid data in the valid data is written to the first storage page; the first valid data is reused and written to the second storage page; remaining valid data in the valid data is padded and written to the third storage page;

[0169] When the amount of the valid data is less than or equal to the second preset data amount, the valid data is filled; the second valid data obtained after filling is written to the first storage page of the target flash memory block; the second valid data is reused and written to the second storage page; and the filled data is written to the third storage page.

[0170] In this embodiment, the amount of data is represented by the number of AUs. Taking the example of 16 AUs written to each storage page at a time, the first preset data amount is 32 AUs, and the second preset data amount is 16 AUs. The amount of valid data read at one time is equal to or less than 32 valid data. The first preset data amount is 32 AUs, and the second preset data amount is 16 AUs.

[0171] See also Figure 12 , Figure 12 This is a schematic diagram of data writing in GC mode in the first embodiment provided by this application, such as Figure 12 As shown, the amount of valid data read at one time is 32 AUs (the amount of valid data is equal to the first preset data amount), the data of the first 16 AUs in the preset cache space (corresponding to the first valid data) are written to the first storage page (corresponding to LP), the data of the 16 AUs written to the first storage page are reused and written to the second storage page (corresponding to MP), and the data of the remaining 16 AUs in the preset cache space (corresponding to the second valid data) are written to the third storage page (corresponding to UP).

[0172] See also Figure 13 , Figure 13This is a schematic diagram of data writing in GC mode in the second embodiment provided by this application, such as Figure 13 As shown, the amount of valid data read at one time is 24 AUs (the amount of valid data is less than the first preset data amount and greater than the second preset data amount), the data of the first 16 AUs in the preset cache space (corresponding to the first valid data) are written to the first storage page (corresponding to the LP), the data of the 16 AUs written to the first storage page are reused and written to the second storage page (corresponding to the MP), and the data of the remaining 8 AUs in the preset cache space are filled to 16 AUs. The remaining valid data after filling is obtained and written to the third storage page (corresponding to the UP).

[0173] See also Figure 14 , Figure 14 This is a schematic diagram of data writing in GC mode in the third embodiment provided by this application, such as Figure 14 As shown, the amount of valid data read at one time is 10 AUs (the amount of valid data is less than or equal to the second preset data amount), the data of the 10 AUs (valid data) are padded with valid data until 16 AUs are obtained to obtain second valid data, and the second valid data is written to the first storage page (corresponding to LP). The second valid data of the 16 AUs written into the first storage page are multiplexed and written into the second storage page (corresponding to MP), and the padded data is written into the third storage page. The padded data is preset data for padding, and its data amount is 16 AUs.

[0174] In an optional embodiment, the data processing method further includes: when there is an error in reading the data of the target storage page, reading the data of the multiplexed storage page multiplexed with the target storage page; when reading the data of the multiplexed storage page successfully, determining that an abnormality occurs when writing the data from the cache space to the target flash memory particle; when there is an error in reading the data of the multiplexed storage page, determining that an abnormality occurs when storing the data in the cache space.

[0175] In this embodiment, in the process of simulating the second flash memory technology to store data, the data of the target storage page and the data stored in the corresponding reused storage page are the same. When reading data, only the data of some storage pages in all storage pages are read. For example, MLC is simulated on a target flash memory particle based on TLC, including a first storage page, a second storage page, and a third storage page. The first storage page and the second storage page are reused. When reading data, generally, the data of the first storage page and the third storage page can be successfully read. At this time, the target storage page is the first storage page, and the reused storage page is the second storage page. In the process of reading data, if an error occurs when reading the data of the first storage page (target storage page), the data of the second storage page (reuse storage page) can be further read. If an error still occurs when reading the data of the second storage page, it is determined that an exception occurs in the process of storing the data received by the master control in the cache space when writing data. Conversely, if the data of the second storage page is read successfully, it is determined that an exception occurs in the process of writing data from the cache space to the target flash memory particle when writing data.

[0176] By using the data processing method for memory page reuse in this embodiment, the same data is written into two memory pages, which is conducive to quickly locating the step where the abnormality occurs when an error occurs in reading data, thereby improving the efficiency of resolving the abnormality.

[0177] Those skilled in the art will understand that in the above-mentioned method of the specific implementation method, the writing order of each step does not mean a strict execution order and does not constitute any limitation on the implementation process. The specific execution order of each step should be determined by its function and possible internal logic.

[0178] In order to implement the above data processing method, this application also proposes a data processing device, please refer to Figure 15 , Figure 15 It is a structural diagram of an embodiment of a data processing device provided by this application.

[0179] The data processing device 500 of this embodiment includes:

[0180] An acquisition module 51 is configured to acquire a threshold voltage distribution corresponding to a target flash memory particle based on a first flash memory technology, wherein the threshold voltage distribution is used to represent voltage distribution probabilities corresponding to different data states in the target flash memory particle;

[0181] a determination module 52, configured to determine a target multiplexing relationship between different types of storage pages based on the threshold voltage distribution;

[0182] The processing module 53 is configured to simulate a second flash memory technology on the target flash memory particle to perform data processing based on the target reuse relationship.

[0183] In order to implement the above data processing method, this application also proposes a data processing device, please refer to Figure 16 , Figure 16 It is a structural diagram of an embodiment of a data processing device provided by this application.

[0184] The data processing device 400 of this embodiment includes a processor 41 , a memory 42 , an input / output device 43 , and a bus 44 .

[0185] The processor 41 , memory 42 , and input / output device 43 are respectively connected to a bus 44 . The memory 42 stores program data, and the processor 41 is used to execute the program data to implement the data processing method described in the above embodiment.

[0186] In the embodiments of the present application, the processor 41 may also be referred to as a CPU (Central Processing Unit). The processor 41 may be an integrated circuit chip with signal processing capabilities. The processor 41 may also be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic device, discrete gate or transistor logic device, or discrete hardware component. A general-purpose processor may be a microprocessor, or the processor 41 may be any conventional processor.

[0187] This application also provides a computer storage medium, please continue to refer to Figure 17 , Figure 17 6 is a schematic structural diagram of an embodiment of a computer storage medium provided in the present application. The computer storage medium 600 stores a computer program 61. When the computer program 61 is executed by a processor, it is used to implement the data processing method of the above embodiment.

[0188] When the embodiments of the present application are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) or a processor to execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes various media that can store program code, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

[0189] The above description is only an implementation method of the present application and does not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the description and drawings of this application, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A data processing method, characterized in that: The data processing method includes: Obtaining a threshold voltage distribution corresponding to a target flash memory particle based on a first flash memory technology, wherein the threshold voltage distribution is used to represent voltage distribution probabilities corresponding to different data states in the target flash memory particle; Determining a target multiplexing relationship between different types of storage pages in the target flash memory particles based on the threshold voltage distribution; Based on the target multiplexing relationship, a second flash memory technology is simulated on the target flash memory particle to perform data processing, wherein the number of data bits that can be stored in each storage unit corresponding to the first flash memory technology is greater than the number of data bits that can be stored in each storage unit corresponding to the second flash memory technology.

2. The data processing method according to claim 1, wherein: The determining of a target multiplexing relationship between storage pages based on the threshold voltage distribution includes: Traversing each multiplexing relationship in the multiplexing relationship set, and determining the minimum spacing between threshold voltage peaks corresponding to each multiplexing relationship; The target multiplexing relationship is determined in the multiplexing relationship set according to the minimum distance between threshold voltage peaks.

3. The data processing method according to claim 1, wherein: Simulating a second flash memory technology on the target flash memory particle to perform data processing based on the target multiplexing relationship includes: Obtaining a write command instructing to write data to be processed; In response to the write command, determining a target write position corresponding to each sub-data in the data to be processed; Simulating the second flash memory technology to store the data to be processed in a corresponding cache space according to the target write position and the target multiplexing relationship; The data to be processed is written from the cache space into the target flash memory particle.

4. The data processing method according to claim 3, characterized in that: The target multiplexing relationship indicates that data of the first storage page and data of the second storage page are multiplexed; The cache space includes a first cache area and a second cache area; Storing the to-be-processed data in a corresponding cache space according to the target write position and the target multiplexing relationship includes: storing the first sub-data whose target write location is the first storage page in the first buffer area, and copying the first sub-data to the second buffer area; storing the second sub-data whose target write location is the third storage page in the first buffer area, The first storage page, the second storage page, and the third storage page are different types of storage pages in the target flash memory particle.

5. The data processing method according to claim 4, characterized in that: The method further comprises: After the first sub-data is stored in the first channel of the first cache area, sending a first write request to the flash memory controller, wherein the first write request is used to instruct the flash memory controller to write the data of the first channel into the target flash memory particle; After the first sub-data is stored in the second channel in the first cache area, a second write request is sent to the flash memory controller, wherein the second write request is used to instruct the flash memory controller to write the data in the second channel and at least part of the data in the second cache area into the target flash memory particles in sequence.

6. The data processing method according to claim 1, wherein: The data processing method further includes: Reading valid data in a to-be-processed flash memory block in the target flash memory particle, and placing the read valid data in a preset cache area, wherein the amount of valid data read each time is less than or equal to a first preset data amount; The valid data is written into a target flash memory block in the target flash memory particle according to the data amount of the valid data and the target multiplexing relationship.

7. The data processing method according to claim 6, characterized in that: The target multiplexing relationship indicates that data of the first storage page and data of the second storage page are multiplexed; The step of writing the valid data into a target flash memory block in the target flash memory particle according to the data amount of the valid data and the target multiplexing relationship includes: When the amount of the valid data is equal to the first preset data amount, first valid data among the valid data is written to the first storage page in the target flash memory block; the first valid data is reused to write the first valid data to the second storage page in the target flash memory block; and the remaining valid data among the valid data is written to the third storage page of the target flash memory block; When the amount of the valid data is less than the first preset data amount and greater than the second preset data amount, first valid data in the valid data is written to the first storage page; the first valid data is reused and written to the second storage page; remaining valid data in the valid data is padded and written to the third storage page; When the amount of the valid data is less than or equal to the second preset data amount, the valid data is filled; the second valid data obtained after filling is written to the first storage page of the target flash memory block; the second valid data is reused and written to the second storage page; the filled data is written to the third storage page, wherein the first storage page, the second storage page and the third storage page are different types of storage pages in the target flash memory particles.

8. The data processing method according to claim 1, wherein: The data processing method further includes: When an error occurs in reading data of the target storage page, reading data of a multiplexing storage page multiplexed with the target storage page; When reading the data of the reused storage page successfully, determining that an exception occurs when writing the data from the cache space to the target flash memory particle; In the case where an error occurs in reading data from the reused storage page, it is determined that an abnormality occurs when storing the data in the cache space.

9. A data processing device, characterized in that: The data processing device includes a memory and a processor coupled to the memory; The memory is used to store program data, and the processor is used to execute the program data to implement the data processing method according to any one of claims 1 to 8.

10. A computer storage medium, characterized in that The computer storage medium is used to store program data, and when the program data is executed by a computer, it is used to implement the data processing method according to any one of claims 1 to 8.

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