In-cell cryptographic engine for memory controller

Abstract

Various embodiments include a method for in-cell cryptographic core management implemented in an in-cell cryptographic module of a system on chip (SoC). Embodiments may include receiving a cryptographic core configuration request for a data stream of a multi-data stream memory controller, and dynamically configuring at least one cryptographic core for the data stream. Embodiments may include: the request is an allocation request for the data stream; enabling an available cryptographic core, the available cryptographic core being the at least one cryptographic core; and assigning the at least one cryptographic core to the data stream. Embodiments may include: the request is a deallocation request for the data stream; scanning a plurality of cryptographic cores assigned to the data stream to obtain an indication of an idle state of the at least one cryptographic core; deactivating the at least one cryptographic core; and deallocating the at least one cryptographic core from the data stream.

Description

[0001] Related Applications

[0002] This application claims the benefit of priority of U.S. Non - Provisional Application No. 18 / 151,445, filed on January 8, 2023; the entire content of which is incorporated herein by reference. Background Art

[0003] A memory controller configured with multiple data streams for memory read and write transactions can use a dedicated Advanced Encryption Standard (AES) core to implement AES encryption of the data streams. The design of such a memory controller (including the number of AES cores for each data stream) depends on the memory throughput requirements. By statically allocating AES cores to the corresponding data streams, the number of AES cores is provided in the memory controller to meet the throughput requirements. Summary of the Invention

[0004] Various aspects include apparatuses and methods for implementing an embedded cryptographic module for an on - chip system (SoC) for embedded cryptographic core management. Aspects can include receiving a cryptographic core configuration request for a data stream of a multi - data - stream memory controller and dynamically configuring at least one cryptographic core for the data stream.

[0005] In some aspects, the cryptographic core configuration request can be a cryptographic core allocation request for a data stream. Some aspects can also include enabling available cryptographic cores, where the available cryptographic cores can be at least one cryptographic core, and allocating the at least one cryptographic core to the data stream.

[0006] In some aspects, enabling available cryptographic cores can include setting an enable value of a data structure for at least one cryptographic core to indicate the active state of the at least one cryptographic core to the multi - data - stream memory controller.

[0007] In some aspects, allocating at least one cryptographic core to a data stream can include setting a reference value of a data structure for at least one cryptographic core to indicate a link to another cryptographic core allocated to the data stream to the multi - data - stream memory controller.

[0008] Some aspects can also include aligning another cryptographic core allocated to the data stream. In some aspects, aligning another cryptographic core allocated to the data stream can include setting a reference value of a data structure for the another cryptographic core to indicate a link to the at least one cryptographic core to the multi - data - stream memory controller.

[0009] In some aspects, the cryptographic core configuration request can be a cryptographic core deallocation request for a data stream. Some aspects may also include: scanning a plurality of cryptographic cores assigned to the data stream to obtain an indication of the idle state of at least one cryptographic core; deactivating the at least one cryptographic core; and deallocating the at least one cryptographic core from the data stream.

[0010] In some aspects, deactivating at least one cryptographic core may include: setting an enable value of a data structure for the at least one cryptographic core to indicate to the multi-data stream memory controller the inactive state of the at least one cryptographic core.

[0011] In some aspects, deallocating at least one cryptographic core from the data stream may include: setting a reference value of a data structure for the at least one cryptographic core to indicate to the multi-data stream memory controller a link to no other cryptographic core.

[0012] Some aspects may also include aligning a first cryptographic core assigned to the data stream. In some aspects, aligning a first cryptographic core assigned to the data stream may include: updating a reference value of a data structure for the first cryptographic core configured to indicate to the multi-data stream memory controller a link to at least one cryptographic core to a reference value configured to indicate to the multi-data stream memory controller a link to a second cryptographic core assigned to the data stream.

[0013] Other aspects include a computing device including an embedded cryptographic device configured to perform the operations of any of the methods outlined above. Additional aspects include computing devices having components for performing any of the functions of the methods outlined above. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The drawings incorporated herein and constituting a part of this specification illustrate example embodiments in various implementations and, together with the general description given above and the detailed description given below, serve to explain the features of the claims.

[0015] Figure 1 is a block diagram of components of an example computing device suitable for implementing various implementations.

[0016] Figure 2 is a block diagram of components of an example embedded cryptographic multi-data stream memory system suitable for implementing various implementations.

[0017] Figures 3A to 3D is a block diagram of components of an example of embedded cryptographic core management for a multi-data stream memory controller suitable for implementing various implementations.

[0018] Figure 4A and Figure 4BIt is a component block diagram illustrating an example of the allocation of an embedded cryptographic core for a multi-data stream memory controller for implementing various embodiments.

[0019] Figure 5A and Figure 5B It is a component block diagram illustrating an example of the deallocation of an embedded cryptographic core for a multi-data stream memory controller for implementing various embodiments.

[0020] Figure 6 It is a process flow diagram illustrating a method for the management of an embedded cryptographic core for a multi-data stream memory controller according to some embodiments.

[0021] Figure 7A and Figure 7B It is a process flow diagram illustrating a method for the management of an embedded cryptographic core for a multi-data stream memory controller according to some embodiments.

[0022] Figure 8 It is a component block diagram illustrating an example mobile computing device suitable for implementing various embodiments.

[0023] Figure 9 It is a component block diagram illustrating an example mobile computing device suitable for implementing various embodiments.

[0024] Figure 10 It is a component block diagram illustrating an example server suitable for implementing various embodiments. Detailed Description

[0025] Various embodiments will be described in detail with reference to the accompanying drawings. Wherever possible, the same reference numerals will be used throughout the drawings to refer to the same or like components. References to specific examples and specific implementations are for illustrative purposes and are not intended to limit the scope of protection of the claims.

[0026] Various embodiments include methods for implementing an embedded cryptographic module for a system-on-chip (SoC) for cryptographic core management and computing devices that implement such methods. In some embodiments, the embedded cryptographic module may be configured with a process and / or circuitry for dynamically configuring cryptographic cores for multiple data streams of a multi-data stream memory controller. Dynamic configuration of the cryptographic cores may include allocating and / or deallocating one or more cryptographic cores to one or more data streams of the multi-data stream memory controller. Dynamic configuration of the cryptographic cores may include allocating a cryptographic core to a data stream by enabling an available or inactive cryptographic core and associating the cryptographic core with the data stream and / or at least one other cryptographic core associated with the data stream. Dynamic configuration of the cryptographic cores may include deallocating a cryptographic core from a data stream by disabling an idle (or about to become idle) cryptographic core associated with the stream and disassociating the cryptographic core from the data stream and / or at least one other cryptographic core associated with the data stream. Dynamic configuration of the cryptographic cores may include aligning any other cryptographic cores associated with the stream by updating the association of at least one such cryptographic core relative to at least one other such cryptographic core.

[0027] The terms "computing device" and "mobile device" are used interchangeably herein to refer to any one or all of the following: cellular phone, smartphone, personal or mobile multimedia player, personal data assistant (PDA), laptop computer, tablet computer, convertible laptop / tablet computer (2-in-1 computer), smartbook, ultrabook, netbook, palmtop computer, wireless email receiver, Internet-enabled multimedia cellular phone, mobile game console, wireless game controller, and similar personal electronic devices that include a memory and a programmable processor. The term "computing device" may further refer to a stationary computing device, including a personal computer, desktop computer, monolithic computer, workstation, supercomputer, mainframe computer, embedded computer, server, home theater computer, and game console.

[0028] A memory controller configured with multiple data streams for memory read and write transactions may implement AES encryption of the data streams using dedicated Advanced Encryption Standard (AES) cores. The design of such a memory controller (including the number of AES cores per data stream) depends on the memory throughput requirements. By statically allocating AES cores to the corresponding data streams, the number of AES cores provided in the memory controller meets the throughput requirements.

[0029] The AES core occupies the area of the memory controller circuit. For example, a cryptographic engine including the AES core can consume approximately 50% to approximately 60% of the integrated circuit area of the memory controller. Memory technology is advancing, increasing memory throughput, which requires increasing the number of statically allocated AES cores and increasing the area of the memory controller. However, in applications with limited physical space, the size of the memory controller may be restricted, making it unsustainable to increase the memory controller area to keep up with the development of memory throughput.

[0030] After the final design, including the design of the memory controller, the increased memory throughput of the SoC is limited by the number of statically allocated AES cores of the memory controller. Such limitations have a negative impact on the performance benchmarks of the SoC.

[0031] The statically allocated AES cores of the memory controller result in inefficient use of resources. For example, during the operation of the memory controller using a specific data stream, not all statically allocated AES cores are required, leaving some AES cores for the data stream idle. In a more extreme example, all statically allocated AES cores can be idle for an unused data stream. This inefficiency of idle AES cores can be realized across multiple data streams, exacerbating the inefficiency of the use of statically allocated AES cores.

[0032] Various embodiments address and overcome the foregoing problems of statically allocating AES cores to specific data streams of a memory controller by implementing dynamic allocation of cryptographic cores, such as AES cores, to multiple data streams of a multi-data stream memory controller. The dynamic allocation of cryptographic cores enables the use of fewer cryptographic cores than the statically allocated AES cores of the memory controller to achieve the same and / or higher throughput of the multi-data stream memory controller. Using fewer dynamically allocated cryptographic cores than statically allocated AES cores reduces the area of the multi-data stream memory controller required to achieve the same and / or higher throughput. The dynamic allocation of cryptographic cores enables support for increased memory throughput of the SoC after the final design, thereby enabling a benchmark performance gain. By allowing different data streams to use available cryptographic cores to meet throughput requirements, the dynamic allocation of cryptographic cores makes the use of cryptographic cores more efficient than statically allocated AES cores. The dynamic allocation of available cryptographic cores to different streams reduces the number of idle cryptographic cores compared to statically allocated AES cores for the same or similar workloads.

[0033] A multi-data stream memory controller may be provided with multiple cryptographic cores, which can be dynamically configured by a cryptographic core configuration module for multiple data streams, including allocation and / or deallocation. The dynamic configuration of the multiple cryptographic cores by the cryptographic core configuration module may be based on throughput requirements of the workload of the data stream at runtime. Allocation and deallocation can be implemented from an available cryptographic core pool of available or unallocated cryptographic cores, and allocation and deallocation can also be implemented to the available cryptographic core pool of available or unallocated cryptographic cores. For example, allocating a cryptographic core to a stream may include allocating an available cryptographic core from the available cryptographic core pool. As another example, deallocating an available cryptographic core from a stream may include making the cryptographic core available in the available cryptographic core pool.

[0034] The dynamic configuration of multiple cryptographic cores by the cryptographic core configuration module may include associating for a stream to effect allocation of a cryptographic core and / or dissociating to effect deallocation. For example, a cryptographic core allocated to a stream may be associated with other cryptographic cores allocated to that stream. As another example, a cryptographic core deallocated from a stream may be dissociated from other cryptographic cores allocated to that stream.

[0035] Figure 1 Illustrated is a system including a computing device 10 suitable for use with various embodiments. The computing device 10 may include a system-on-chip (SoC) 12 having a processor 14, a memory 16, a memory interface 34, an embedded cryptographic module 38, a communication interface 18, a storage memory interface 20, a clock controller 30, and an interconnect 32. The computing device 10 may also include a communication component 22 (such as a wired or wireless modem), a storage memory 24, an antenna 26 for establishing a wireless communication link, a power manager 28, and a memory 36. The processor 14 may include any one of a variety of processing devices (such as multiple processor cores).

[0036] The term "system on a chip" (SoC) is used herein to refer to a collection of interconnected electronic circuits, typically but not exclusively including processing devices, memory, and communication interfaces. The processing devices can include a variety of different types of processors 14 and processor cores, such as general-purpose processors, central processing units (CPUs), digital signal processors (DSPs), graphics processing units (GPUs), accelerated processing units (APUs), security processing units (SPUs), neural network processing units (NPUs), subsystem processors for specific components of a computing device (such as an image processor for a camera subsystem or a display processor for a display), auxiliary processors, single-core processors, multi-core processors, controllers, and microcontrollers. The processing devices can further embody other hardware and hardware combinations, such as field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), other programmable logic devices, discrete gate logic, transistor logic, performance monitoring hardware, watchdog hardware, and time references. The integrated circuit can be configured such that the components of the integrated circuit reside on a single piece of semiconductor material (such as silicon).

[0037] The SoC 12 can include one or more processors 14. The computing device 10 can include more than one SoC 12, thereby increasing the number of processors 14 and processor cores. The computing device 10 can also include processors 14 that are not associated with the SoC 12. Each of the processors 14 can be configured for a specific purpose that can be the same as or different from other processors 14 of the computing device 10. One or more of the processors 14 and processor cores with the same or different configurations can be grouped together. A group of processors 14 or processor cores can be referred to as a multiprocessor cluster.

[0038] The computing device 10 can include any number and combination of memories, such as the memory 16 integral with the SoC 12 and the memory 36 separate from the SoC 12. Any of the memories 16, 36 can be a volatile or non-volatile memory configured to store data and processor-executable code accessible by the processors 14. The computing device 10 and / or the SoC 12 can include one or more memories 16, 36 configured for various purposes. The one or more memories 16, 36 can include volatile memories, such as random access memory (RAM) or main memory, including static RAM (SRAM) (such as the memory 16), dynamic RAM (DRAM) (such as the memory 36), or cache memory.

[0039] The memories 16, 36 can be configured to temporarily store a limited amount of data. For example, data can be received from a data sensor or subsystem. As another example, the data can be data requested from the non-volatile memories 16, 24, 36 and / or processor-executable code instructions that are loaded from the non-volatile memories 16, 24, 36 into the memories 16, 36 upon anticipated future access based on various factors. As another example, the data can be intermediate processing data and / or processor-executable code instructions generated by the processor 14 and are temporarily stored for future quick access without being stored in the non-volatile memories 16, 24, 36.

[0040] The memory interface 34 can work in concert with the memory 36 to enable the computing device 10 to store data and processor-executable code on the memory 36 and retrieve data and processor-executable code from that memory. The memory interface 34 can control access to the memory 36 storing the memory 36 and allow the processor 14 to read data from and write data to the memory 36.

[0041] The storage memory interface 20 and the storage memory 24 can work in concert to allow the computing device 10 to store data and processor-executable code on a non-volatile storage medium (such as, a non-volatile storage device). The storage memory 24 can be configured very similarly to the implementation of the memory 16, where the storage memory 24 can store data or processor-executable code for access by one or more of the processors 14. The non-volatile storage memory 24 can retain information after the computing device 10 has been powered off. When powered on again and the computing device 10 restarts, the information stored on the storage memory 24 can be used by the computing device 10. The storage memory interface 20 can control access to the storage memory 24 and allow the processor 14 to read data from and write data to the storage memory 24.

[0042] The embedded cryptographic module 38 can be configured to implement cryptographic functions for data of transactions of the memory storage device 24, such as encryption and decryption. Data transmitted between the memory 36 and the storage memory 24 can be encrypted and decrypted by the embedded cryptographic module 38 to protect the stored data and the memory storage device 24 by encrypting the data, and to make the encrypted data retrieved from the memory storage device 24 usable by the SoC by decrypting the data. The embedded cryptographic module 38 can be configured with multiple cryptographic cores (not shown), and the embedded cryptographic module 38 can be dynamically configured for multiple data streams of a multi-data stream memory controller (not shown). In some specific implementations, the embedded cryptographic module 38 can be an independent component of the SoC 12. In some specific implementations, the embedded cryptographic module 38 can be integrated with another component of the SoC 12, such as the memory interface 34, the storage memory interface 20, the processor 14, the multi-data stream memory controller, etc.

[0043] The power manager 28 can be configured to control the power state of one or more power rails (not shown) for power delivery to components of the SoC 12. In some embodiments, the power manager 28 can be configured to control the amount of power supplied to components of the SoC 12. For example, the power manager 28 can be configured to control the connection between components of the SoC 12 and the power rails. As another example, the power manager 28 can be configured to control the amount of power on the power rails connected to components of the SoC 12. The power manager 28 can be configured as a power management integrated circuit (power management IC or PMIC).

[0044] The clock controller 30 can be configured to control clock signals sent to components of the SoC 12. For example, the clock controller 30 can gate components of the SoC 12 by disconnecting the components of the SoC 12 from the clock signals, and can ungate components of the SoC 12 by connecting the components of the SoC 12 to the clock signals.

[0045] The interconnect 32 can be a communication structure configured to communicatively connect components of the SoC 12, such as a communication bus. The interconnect 32 can send signals between components of the SoC 12. In some embodiments, the interconnect 32 can be configured to control signals between components of the SoC 12 by controlling the timing and / or the transmission path of the signals.

[0046] Some or all of the components of the computing device 10 and / or the SoC 12 can be arranged and / or combined differently and still provide the functions of the various embodiments. The computing device 10 is not limited to one component of each component, and multiple instances of each component can be included in various configurations of the computing device 10.

[0047] Figure 2 Illustrates an example of an embedded cryptographic multi-data stream memory system 200 suitable for implementing various embodiments. Refer to Figure 1 and Figure 2 , the embedded cryptographic multi-data stream memory system 200 may include a multi-data stream memory controller 202 and an embedded cryptographic module 206 (e.g., Figure 1 's embedded cryptographic module 38). In some embodiments, the multi-data stream memory controller 202 and the embedded cryptographic module 206 may be separate components of an SoC (e.g., Figure 1 's SoC 12), which may be independent components of the SoC and / or integrated with other components of the SoC. In some embodiments, the embedded cryptographic module 206 may be an integral component of the multi-data stream memory controller 202, which may be an independent component of the SoC and / or integrated with another component of the SoC. Other components of the SoC may include a memory interface (e.g., Figure 1 's memory interface 34), a storage memory interface 20 (e.g., Figure 1 's storage memory interface 20), a processor (e.g., Figure 1 's processor 14), etc. In some embodiments, the embedded cryptographic multi-data stream memory system 200 may be included in a computing device (e.g., Figure 1 's computing device 10).

[0048] The multi-data stream memory controller 202 may implement multiple data streams 204a, 204b, such as up to N data streams, where N is an integer greater than 1 (e.g., stream 1 204a, stream N 204b). The multi-data stream memory controller 202 may implement multiple data streams 204a, 204b for read and / or write transactions between a storage memory (e.g., Figure 1 's storage memory 24) and components of the SoC and / or components of the computing device. For example, the multi-data stream memory controller 202 may implement multiple data streams 204a, 204b to read data from the storage memory into components of the SoC, such as a memory (e.g., Figure 1 's memory 16), a processor, etc. and / or a memory of a computing device independent of the SoC (e.g., Figure 1 's memory 36). As another example, the multi-data stream memory controller 202 may implement multiple data streams 204a, 204b to write data from components of the SoC (such as a memory, a processor, etc.) and / or a memory of a computing device to the storage memory.

[0049] The multi-data stream memory controller 202 can implement read and / or write transactions for workloads with various data throughput requirements using data streams 204a, 204b. For example, the multi-data stream memory controller 202 can implement read and / or write transactions for a workload with a data throughput requirement using data stream 204a, which is higher than the data throughput requirement of the workload for which read and / or write transactions are implemented using data stream 204b.

[0050] The embedded cryptographic module 206 can include a cryptographic core configuration module 208 and multiple cryptographic cores 212 (e.g., Figure 1 processor 14 in ). The cryptographic core 212 can be configured to implement cryptographic functions for reading and / or writing data for data streams 204a, 204b, such as encryption and / or decryption. For example, the cryptographic core 212 can encrypt the data to be written from the components of the SoC and / or the memory of the computing device, thereby generating encrypted data for writing to the storage memory. As another example, the cryptographic core 212 can decrypt the data read from the storage memory, thereby generating decrypted data for the components of the SoC and / or the memory of the computing device. The cryptographic core 212 can be configured to implement cryptographic functions based on any known, proprietary, or future cryptographic algorithms and / or standards. For example, in some embodiments, the cryptographic core 212 can be configured to implement cryptographic functions based on the Advanced Encryption Standard (AES).

[0051] The cryptographic cores 212 can be logically grouped in the available cryptographic core pool 210 and / or assigned to data streams 204a, 204b by the cryptographic core configuration module 208 (e.g., cryptographic core 214a assigned to stream 1, cryptographic core 214b assigned to stream N). In Figure 2 the illustrated example, the physical cryptographic cores 212 are illustrated using solid lines, and for the assigned cryptographic cores 214a, 214b, the logical assignment of the cryptographic cores 212 is illustrated using dashed lines. The cryptographic cores 212 in the available cryptographic core pool 210 are available for assignment to data streams 204a, 204b. In other words, the cryptographic cores 212 in the available cryptographic core pool 210 can be de-assigned to data streams 204a, 204b and / or can be idle. The cryptographic core 214a assigned to stream 1 and the cryptographic core 214b assigned to stream N can be assigned to the corresponding data streams 204a, 204b to implement cryptographic functions for reading and / or writing data for the corresponding data streams 204a, 204b. In Figure 2In the illustrated example, arrows 218a, 218b illustrate the transmission of encrypted read data and / or unencrypted write data from data streams 204a, 204b to the allocated cryptographic cores 214a, 214b, and the transmission of decrypted read data and / or encrypted write data from the allocated cryptographic cores 214a, 214b to data streams 204a, 204b.

[0052] A cryptographic core configuration module 208, which can be implemented as a hardware component of the embedded cryptographic module 206, can include circuitry for configuring the cryptographic core 212, including circuitry for allocating the cryptographic core 212 to the data streams 204a, 204b and deallocating the cryptographic core from the data streams. Alternatively, the cryptographic core configuration module 208 can be a software component of the embedded cryptographic module 206, which can include computer code instructions for configuring the cryptographic core 212. In Figure 2 the illustrated example, arrows 216a, 216b illustrate the hardware and / or software operations of the cryptographic core configuration module 208 for allocating and deallocating the cryptographic core 212 between the data streams 204a, 204b and the pool of available cryptographic cores 210.

[0053] The configuration of the cryptographic core 212 for the data streams 204a, 204b can be implemented as allocating the cryptographic core 212 to the data streams 204a, 204b. The cryptographic core configuration module 208 can identify the cryptographic core 212 in the pool of available cryptographic cores 210 and allocate the cryptographic core 212 to the data streams 204a, 204b. The cryptographic core configuration module 208 can determine when to allocate and how many cryptographic cores 212 to allocate to the data streams 204a, 204b based on the throughput requirements of the workload for the data streams 204a, 204b.

[0054] The assignment of the cryptographic core 212 to the data streams 204a, 204b can be achieved by logically associating the cryptographic core 212, which is the assigned cryptographic core 214a, 214b, with the data streams 204a, 204b. In a specific implementation with a single cryptographic core or only one cryptographic core for the data stream, for one assigned cryptographic core 214a, 214b for the data streams 204a, 204b, the association with the data streams 204a, 204b can be achieved by the association of the cryptographic core 212 with itself. In a specific implementation with multiple cryptographic cores in the data structure of the data stream, the association with the data streams 204a, 204b can be achieved by the first cryptographic core 212 and the association with at least one other assigned cryptographic core 214a, 214b for the data streams 204a, 204b. In some embodiments, the assigned cryptographic cores 214a, 214b can be associated by a data structure that provides a reference to itself from the assigned cryptographic cores 214a, 214b for the data streams 204a, 204b, these assigned cryptographic cores being the first and / or only assigned cryptographic cores 214a, 214b for the data streams 204a, 204b and / or at least one other assigned cryptographic core 214a, 214b for the same data streams 204a, 204b. In some embodiments, the reference can be stored in a memory (e.g., Figure 1 the memory 16 in) (not shown), such as registers at each cryptographic core 212, at the cryptographic core configuration module 208, and / or at the multi-data stream memory controller 202.

[0055] The assignment of the cryptographic core 212 to the data streams 204a, 204b can also be achieved by logically disassociating the cryptographic core 212 from the pool of available cryptographic cores 210. For example, the cryptographic core 212 can be disassociated from the pool of available cryptographic cores 210 by using a data structure to assign the cryptographic core 212, which is the assigned cryptographic core 214a, 214b, for the data streams 204a, 204b. As another example, the cryptographic core 212 can be disassociated from the pool of available cryptographic cores 210 by providing a data structure of the enabled state of the cryptographic core 212 to the cryptographic core configuration module 208. Indicating to the cryptographic core configuration module 208 that the cryptographic core 212 is in an active enabled state can disassociate the cryptographic core 212 from the pool of available cryptographic cores 210. In some embodiments, the enabled state can be stored in a memory, such as registers at each cryptographic core 212, at the cryptographic core configuration module 208, and / or at the multi-data stream memory controller 202.

[0056] A non-limiting example of such a data structure is a linked list, where any entry of the linked list for the allocated cryptographic cores 214a, 214b can include a reference value to the allocated cryptographic core itself, which is the first and / or only allocated cryptographic core 214a, 214b for the data streams 204a, 204b and / or at least one other allocated cryptographic core 214a, 214b for the same data streams 204a, 204b. The reference value can be the cryptographic core identifier (ID) of the cryptographic core itself, which is the first and / or only allocated cryptographic core 214a, 214b for the data streams 204a, 204b and / or at least one other allocated cryptographic core 214a, 214b for the same data streams 204a, 204b. An entry of the linked list can also include an enable value, which can indicate to the cryptographic core configuration module 208 that the cryptographic core 212 (i.e., the allocated cryptographic cores 214a, 214b) is active.

[0057] The configuration of the cryptographic core 212 for the data streams 204a, 204b can be implemented as deallocating the cryptographic core 212 from the data streams 204a, 204b. The cryptographic core configuration module 208 can identify the allocated cryptographic cores 214a, 214b of the data streams 204a, 204b that are idle and / or will become idle next, and deallocate the allocated cryptographic cores 214a, 214b from the data streams 204a, 204b. The cryptographic core configuration module 208 can determine when to allocate and how many allocated cryptographic cores 214a, 214b to deallocate from the data streams 204a, 204b based on the throughput requirements of the workload for the data streams 204a, 204b and the active state of the allocated cryptographic cores 214a, 214b.

[0058] Deallocating the cryptographic core 212 from the data streams 204a, 204b can be achieved by logically decoupling the cryptographic core 212, which is the allocated cryptographic core 214a, 214b, from the data streams 204a, 204b. The decoupling from the data streams 204a, 204b can be achieved by decoupling the cryptographic core 212 from itself, which is the last and / or only allocated cryptographic core 214a, 214b for the data streams 204a, 204b and / or at least one other allocated cryptographic core 214a, 214b for the data streams 204a, 204b. For example, the allocated cryptographic core 214a, 214b can be decoupled by a data structure by removing the reference to itself from the allocated cryptographic core 214a, 214b for the data streams 204a, 204b, which are the last and / or only allocated cryptographic core 214a, 214b for the data streams 204a, 204b and / or at least one other allocated cryptographic core 214a, 214b for the same data streams 204a, 204b.

[0059] Deallocating the cryptographic core 212 from the data streams 204a, 204b can also be achieved by logically associating the cryptographic core 212 with the pool 210 of available cryptographic cores. For example, the cryptographic core 212 can be associated with the pool 210 of available cryptographic cores by deallocating, using a data structure, the cryptographic core 212 for the data streams 204a, 204b that is the allocated cryptographic core 214a, 214b. As another example, the cryptographic core 212 can be associated with the pool 210 of available cryptographic cores by providing a data structure with the enabled state of the cryptographic core 212, which indicates to the cryptographic core configuration module 208 that the cryptographic core 212 is in an inactive state.

[0060] A non-limiting example of such a data structure is a linked list, where any entry of the linked list for the cryptographic core 212 can include a reference value to no other allocated cryptographic core 214a, 214b. The entry of the linked list can also include an enabled value, which can indicate to the cryptographic core configuration module 208 that the cryptographic core 212 is in an inactive state.

[0061] Figure 2The examples illustrated therein show two data streams 204a, 204b and eight cryptographic cores 212 evenly distributed to the data streams 204a, 204b, which is for clarity and ease of explanation and is not intended to limit the scope of the claims and the specification to the number of data streams, the number of cryptographic cores and the distribution of cryptographic cores as shown in the figure. Any number of data streams greater than one, any number of cryptographic cores greater than one, and different distributions of cryptographic cores (including distributions where not all cryptographic cores are distributed and / or non-uniform distributions of cryptographic cores) can be implemented by the embedded cryptographic multi-data stream memory system 200.

[0062] Reference Figures 1 to 5B , in Figures 3A to 5B an example of the cryptographic core configuration performed by the cryptographic core configuration module 208 is illustrated. Figures 3A to 3D An example of two data streams 300a, 300b ( Figures 3A to 3D stream 1 300a and stream 2 300b in Figure 2 ), the data streams 204a, 204b in Figure 2 ), M cryptographic cores (e.g., Figure 2 the cryptographic cores 212 in

[0063] where M is an integer greater than 1), and the available cryptographic core pool 302 (e.g., Figure 3A the available cryptographic core pool 210 in Figures 3A to 5B ), the reference value ( Figure 2 the link value or LV in Figure 2 ), which is configured to indicate to the multi-data stream memory controller (e.g., Figures 3A to 5Bin the link activity or LA), the enable value is configured to indicate to the multi-data stream memory controller and the cryptographic core configuration module whether the cryptographic core is in an active state or an inactive state. For example, each cryptographic core may have a reference value (e.g., LV = 0) that does not reference any other cryptographic core and indicates no link to another cryptographic core and / or an enable value (e.g., LA = 0) that indicates an inactive state.

[0064] In Figure 3B at least some of the cryptographic cores in the cryptographic core are assigned to data streams 300a, 300b. The sequence of the assigned cryptographic cores may be dynamically managed by the cryptographic core configuration module 208 at runtime according to the throughput requirements of the workloads for each of the data streams 300a, 300b. In Figure 3B a non-limiting example of, cryptographic cores 1 to 7 are de-associated from the pool 302 of available cryptographic cores, and the cryptographic cores are assigned to the corresponding data streams 300a, 300b. Cryptographic cores 1, 3, 5, and 7 are assigned to data stream 300a, and cryptographic cores 2, 4, and 6 are assigned to data stream 300b.

[0065] Based on the respective reference values and enable values of each of cryptographic cores 1, 3, 5, and 7, cryptographic cores 1, 3, 5, and 7 are assigned to data stream 300a. For example, cryptographic core 1 has a reference value (e.g., LV = 3) that references cryptographic core 3 and an enable value (e.g., LA = 1) that indicates that cryptographic core 1 is active. Similarly, cryptographic core 3 has a reference value (e.g., LV = 5) that references cryptographic core 5, cryptographic core 5 has a reference value (e.g., LV = 7) that references cryptographic core 7, and cryptographic core 7 has a reference value (e.g., LV = 1) that references cryptographic core 1. Each of cryptographic cores 3, 5, and 7 has an enable value (e.g., LA = 1) that indicates that the corresponding cryptographic core is active. In addition, based on the respective reference values and enable values of each of cryptographic cores 2, 4, and 6, cryptographic cores 2, 4, and 6 are assigned to data stream 300b. For example, cryptographic core 2 has a reference value (e.g., LV = 4) that references cryptographic core 4, cryptographic core 4 has a reference value (e.g., LV = 6) that references cryptographic core 6, and cryptographic core 6 has a reference value (e.g., LV = 2) that references cryptographic core 2. Each of cryptographic cores 2, 4, and 6 has an enable value (e.g., LA = 1) that indicates that the corresponding cryptographic core is active.

[0066] In Figure 3CAmong them, at least some of the allocated cryptographic cores in the allocated cryptographic cores are still allocated to data streams 300a and 300b, while the cryptographic core is deallocated from data stream 300a. The sequence of the deallocated cryptographic cores can be dynamically managed at runtime by the cryptographic core configuration module 208 according to the throughput requirements of the workloads for each of the data streams 300a and 300b and the active state of the cryptographic cores. In Figure 3C In a non-limiting example, cryptographic core 5 is deallocated from data stream 300a and associated with the pool 302 of available cryptographic cores. The cryptographic core configuration module 208 can determine that one less core is needed to achieve the throughput of the workload of data stream 300a, and that cryptographic core 5 is idle and / or will become idle next among the cryptographic cores allocated to data stream 300a. The cryptographic core configuration module 208 can update the associations of the remaining cryptographic cores 1, 3, and 7 allocated to data stream 300a.

[0067] Based on the corresponding reference value and enable value of cryptographic core 5, cryptographic core 5 is deallocated from data stream 300a. For example, cryptographic core 5 has a reference value that does not refer to other cryptographic cores (e.g., LV = 0) and an enable value indicating that cryptographic core 5 is inactive (e.g., LA = 0). The deallocation of cryptographic core 5 logically associates cryptographic core 5 with the pool 302 of available cryptographic cores. To compensate for the deallocation of cryptographic core 5 from data stream 300a, the reference value of cryptographic core 3 that previously referred to cryptographic core 5 (e.g., Figure 3B in which LV = 5) is updated to the reference cryptographic core 7 that was previously referred to by cryptographic core 5 (e.g., LV = 7).

[0068] In Figure 3D Among them, at least some of the cryptographic cores are allocated to data streams 300a and 300b. The sequence of the allocated cryptographic cores can be dynamically managed at runtime by the cryptographic core configuration module 208 according to the throughput requirements of the workloads for each of the data streams 300a and 300b. In Figure 3D In a non-limiting example, cryptographic core 5 is deassociated from the pool 302 of available cryptographic cores and allocated to data stream 300b. The cryptographic core configuration module 208 can update the associations of the other cryptographic cores 2, 4, and 6 allocated to data stream 300b.

[0069] Based on the corresponding reference value and enable value of cryptographic core 5, cryptographic core 5 is allocated to data stream 300b. For example, cryptographic core 5 has a reference value that refers to cryptographic core 4 (e.g., LV = 4) and an enable value indicating that cryptographic core 1 is active (e.g., LA = 1). To compensate for the allocation of cryptographic core 5 to data stream 300b, the previous reference to cryptographic core 4 (e.g., Figure 3CThe reference value of the cryptographic core 2 in (where LV = 4) is updated to reference the cryptographic core 5 (e.g., LV = 5).

[0070] Figures 4A to 5B Illustrative non - limiting examples of the allocation and de - allocation of cryptographic cores are also included, which also include using stream pointers (e.g., Figures 4A to 5B the current stream pointer and the next stream pointer in ). The current stream pointer and the next stream pointer can be pointers associated with data streams 400, 500 (e.g., Figures 2 to 3D the data streams 204a, 204b, 300a, 300b in ). The current stream pointer and the next stream pointer can point to entries in a data structure that associates cryptographic cores (e.g., Figures 4A to 5B cores 1, 2, 3, 4 in ) with each other and with the data streams 400, 500 to which the cryptographic cores are allocated. The current stream pointer and the next stream pointer can be used to direct the data for processing to the cryptographic core of the entry they point to. Any new incoming data block can be assigned to the cryptographic core associated with the entry pointed to by the current stream pointer. The cryptographic core associated with the entry pointed to by the next stream pointer can be the next cryptographic core in the sequence to which data is to be assigned. The cryptographic core associated with the entry pointed to by the next stream pointer can also be the core that is expected to be idle after the cryptographic core associated with the entry pointed to by the current stream pointer.

[0071] For the allocation of a cryptographic core to data stream 400, the cryptographic core configuration module 208 can allocate the cryptographic core to data stream 400 by placing the cryptographic core at the location pointed to by the next stream pointer in the data structure. In this way, the newly allocated cryptographic core can be the next cryptographic core in the sequence to which data is to be assigned. In Figure 4A and Figure 4B in the example of cryptographic core allocation, the cryptographic core may have been previously allocated to data stream 400, where in Figure 4A the current stream pointer points to the entry for core 2 and the next stream pointer points to the entry for core 3. In Figure 4B core 4 can be allocated to data stream 400 by inserting an entry for core 4 at the next stream pointer location in the data structure and updating the entry for core 2 at the current stream pointer location in the data structure. The entry for core 4 can be configured to reference the entry previously pointed to by the next stream pointer in the data structure, which in this example is the entry for core 3.

[0072] For deallocating a cryptographic core from the data stream 500, the cryptographic core configuration module 208 may deallocate the cryptographic core from the data stream 500 by removing the cryptographic core from the position pointed to by the next pointer flowing from the data structure. To deallocate the cryptographic core, the cryptographic core configuration module 208 may wait until the cryptographic core has completed its processing task. In Figure 5A and Figure 5B In the example of cryptographic core deallocation, the cryptographic core may have been previously allocated to the data stream 500, where in Figure 5A , the current stream pointer points to the entry for core 2, and the next pointer flowing points to the entry for core 4. In Figure 5B , core 4 may be deallocated from the data stream 500 by removing the entry for core 4 from the data structure at the position of the next pointer flowing, updating the next pointer flowing, and updating the entry for core 2 at the current stream pointer position in the data structure. The next pointer flowing may be updated to point to the entry previously referenced by the entry for the deallocated core 4 in the data structure. In Figure 5A and Figure 5B In the example, the entry for the deallocated core 4 previously referenced the entry for core 3, and the next pointer flowing may be updated to point to the entry for core 3. The entry for core 2 may be configured to reference the entry pointed to by the next pointer flowing in the data structure, which in this example is the entry for core 3.

[0073] Figure 6 Illustrates a method for in - line cryptographic core management for a multi - data - stream memory controller according to some embodiments. Referring to Figures 1 to 6 , method 600 may be implemented in a computing device (e.g., the computing device 10 in Figure 1 ), in software executed in a processor (e.g., the in - line cryptographic module 38 in processor 14, Figure 1 ), the multi - data - stream memory controller 202, the in - line cryptographic module 206, Figure 2 the cryptographic core configuration module 208 in Figure 1 ), in general - purpose hardware, in dedicated hardware (e.g., the in - line cryptographic module 38 in Figure 2 ), the multi - data - stream memory controller 202, the in - line cryptographic module 206, Figure 2 the cryptographic core configuration module 208 in ), or in a combination of a software - configured processor and dedicated hardware (such as a processor executing software within an in - line cryptographic multi - data - stream memory system (e.g., the in - line cryptographic multi - data - stream memory system 200 in Figure 2 ), and various memory / cache controllers). To cover alternative configurations implemented in various embodiments, the hardware implementing method 600 is referred to herein as an "in - line cryptographic device".

[0074] In block 602, an embedded cryptographic device may receive a cryptographic core configuration request for a data stream (e.g., data streams 204a, 204b, 300a, 300b, 400, 500 in Figures 2 to 5B ). The cryptographic core configuration request may be used to allocate a cryptographic core (e.g., cryptographic core 212 in Figure 2 ) to the data stream, which is further described with reference to block 702 of method 700a in Figure 7A . The cryptographic core configuration request may be used to deallocate a cryptographic core from the data stream, which is further described with reference to block 720 of method 700b in Figure 7B . In some embodiments, the cryptographic core configuration request may include the throughput requirements of the workload that received the cryptographic core configuration request and / or be associated with the throughput requirements. In some embodiments, the embedded cryptographic device that receives the cryptographic core configuration request for the data stream in block 602 may be a processor (e.g., processor 14 in Figure 1 ), an embedded cryptographic module (e.g., embedded cryptographic modules 38, 206 in Figure 1 and Figure 2 ), a multi-data stream memory controller (e.g., multi-data stream memory controller 202 in Figure 2 ), and / or a cryptographic core configuration module (e.g., cryptographic core configuration module 208 in Figure 2 ).

[0075] In block 604, the embedded cryptographic device may dynamically configure at least one cryptographic core for the data stream. In some embodiments, the embedded cryptographic device may allocate at least one cryptographic core to a data stream that has no other allocated cryptographic cores. In some embodiments, the embedded cryptographic device may allocate at least one cryptographic core to a data stream that has at least one other allocated cryptographic core. The allocation of at least one cryptographic core to a data stream is further described with reference to blocks 704 through 712 of the illustrated method 700a in Figure 7A . In some embodiments, the embedded cryptographic device may deallocate at least one cryptographic core from a data stream that has no other allocated cryptographic cores. In some embodiments, the embedded cryptographic device may deallocate at least one cryptographic core from a data stream that has at least one other allocated cryptographic core. The deallocation of at least one cryptographic core from the data stream is further described with reference to blocks 722 through 732 of the illustrated method 700b in Figure 7B . In some embodiments, the embedded cryptographic device that dynamically configures at least one cryptographic core for the data stream in block 604 may be a processor, an embedded cryptographic module, a multi-data stream memory controller, and / or a cryptographic core configuration module.

[0076] Figure 7A and Figure 7B A method for embedded cryptographic core management for a multi-stream memory controller according to some embodiments is illustrated. Figures 1 to 7B , methods 700a, 700b may be performed on a computing device (e.g., Figure 1 In the computing device 10), in the processor (eg, processor 14, Figure 1 The embedded cryptographic module 38, the multi-stream memory controller 202, the embedded cryptographic module 206, Figure 2 In software executed in the cryptographic core configuration module 208 in the , in general-purpose hardware, in dedicated hardware (e.g., Figure 1 The embedded cryptographic module 38, the multi-stream memory controller 202, the embedded cryptographic module 206, Figure 2 In the cryptographic core configuration module 208 in the embodiment of the present invention, or in a software configured processor and dedicated hardware (such as, in an embedded cryptographic multi-stream memory system including other separate components (e.g., Figure 2 The method 700a and 700b are implemented in a combination of a processor executing software within an embedded cryptographic multi-stream memory system 200 and various memory / cache controllers. To encompass alternative configurations implemented in various embodiments, the hardware implementing methods 700a and 700b is referred to herein as an "embedded cryptographic device."

[0077] refer to Figure 7A , for method 700a, in block 702, the embedded cryptographic device may receive a request for a data stream (eg, Figures 2 to 5B 204a, 204b, 300a, 300b, 400, 500) in the data stream. A cryptographic core allocation request may be received from a processor (e.g., Figure 1 The processor 14 in the embodiment receives a cryptographic core allocation request for a cryptographic core allocation request for a storage memory (eg, Figure 1 storage memory 24) and SoC components (e.g., Figure 1 12) and / or a workload configured to execute read transactions and / or write transactions between components of the computing device and / or the SoC 12) and / or the computing device. Figure 2 Components of the SoC may include memory (e.g., Figure 1 16), memory interfaces (e.g., Figure 1 34), storage memory interface 20 (e.g., Figure 1 storage memory interface 20 in the processor (e.g., Figure 1 14 in the SoC), etc. Components of the computing device may include memory that may be independent of the SoC (e.g.,Figure 1 The memory 36) therein. The cryptographic core allocation request may include and / or be associated with achieving the throughput requirements of the workload. The embedded cryptographic device may determine how many cryptographic cores to allocate to the data stream based on the throughput requirements. In some embodiments, the embedded cryptographic device that receives the cryptographic core allocation request for the data stream at block 702 may be a processor (e.g., Figure 1 the processor 14) therein, an embedded cryptographic module (e.g., Figure 1 and Figure 2 the embedded cryptographic modules 38, 206) therein, a multi-data stream memory controller (e.g., Figure 2 the multi-data stream memory controller 202) therein, and / or a cryptographic core configuration module (e.g., Figure 2 the cryptographic core configuration module 208) therein.

[0078] At block 704, the embedded cryptographic device may enable the available cryptographic cores. The embedded cryptographic device may select to enable the cryptographic cores logically associated with a pool of available cryptographic cores (e.g., Figure 2 the pool of available cryptographic cores 210) therein. For example, the embedded cryptographic device may select the cryptographic cores associated with an enable value stored in a memory (e.g., Figure 1 the memory 16) therein (such as a register), where the enable value is set to indicate to the embedded cryptographic device that the cryptographic core is inactive or available. The embedded cryptographic device may enable the selected cryptographic cores by setting the enable value to a value that is set to indicate to the embedded cryptographic device that the cryptographic core is active. In some embodiments, the embedded cryptographic device that enables the available cryptographic cores at block 704 may be a processor, an embedded cryptographic module, a multi-data stream memory controller, and / or a cryptographic core configuration module.

[0079] At block 706, the embedded cryptographic device may turn on the clock of the cryptographic core. The embedded cryptographic device may signal a clock controller for the cryptographic core to provide a clock signal to the cryptographic core. In some embodiments, the embedded cryptographic device that turns on the clock for the cryptographic core at block 706 may be a processor, an embedded cryptographic module, a multi-data stream memory controller, and / or a cryptographic core configuration module.

[0080] At block 708, the embedded cryptographic device may allocate the cryptographic cores to the data stream. To allocate the cryptographic cores to the data stream, the embedded cryptographic device may include an entry for the cryptographic core in the data structure of the data stream, where the data structure may be configured to associate any number of cryptographic cores allocated to the data stream with each other. For example, the embedded cryptographic device may set what is stored in a memory (e.g., Figure 1a reference value in a memory 16) (such as, a register), the reference value being set to indicate to the embedded cryptographic device an entry reference for the cryptographic core for its own entry, the cryptographic core being the first and / or only cryptographic core of the data structure of the data stream and / or another cryptographic core of the data structure of the data stream. The reference value may be a cryptographic core ID of the first cryptographic core and / or another cryptographic core. In some embodiments, the embedded cryptographic device that assigns the cryptographic core to the data stream in block 708 may be a processor, an embedded cryptographic module, a multi-data stream memory controller, and / or a cryptographic core configuration module.

[0081] In optional block 710, the embedded cryptographic device may align at least one other cryptographic core assigned to the data stream. Optional block 710 may be implemented for the case where there are multiple cryptographic cores in the data structure of the data stream. An entry of at least one other cryptographic core in the data structure of the data stream may be updated to set the reference value of the entry for the at least one other cryptographic core to reference the entry for the assigned cryptographic core in block 708. For example, at least one other cryptographic core may have an entry in the data structure of the data stream that references the entry for the cryptographic core that the entry for the assigned cryptographic core in block 708 now references. The reference value of the entry for the at least one other cryptographic core may be updated to now reference the entry for the assigned cryptographic core in block 708. In some embodiments, the embedded cryptographic device that aligns at least one other cryptographic core assigned to the data stream in optional block 710 may be a processor, an embedded cryptographic module, a multi-data stream memory controller, and / or a cryptographic core configuration module.

[0082] In determination block 712, the embedded cryptographic device can determine whether the cryptographic core allocation for the data stream is complete. The embedded cryptographic device can determine how many cryptographic cores to allocate to the data stream based on the throughput requirements of the workload for which the cryptographic core allocation request for the data stream was received in block 702. The embedded cryptographic device can track the cryptographic cores allocated to the data stream, such as based on the data structure of the data stream. Using the information of the cryptographic cores allocated to the data stream, the embedded cryptographic device can determine whether sufficient cryptographic cores have been allocated to the data stream to meet the throughput requirements. For example, the embedded cryptographic device can compare the number and / or capabilities of the cryptographic cores allocated to the data stream with the number and / or capabilities of the cryptographic cores required to meet the throughput requirements. For the number and / or capabilities of the cryptographic cores allocated to the data stream that can meet the throughput requirements, the embedded cryptographic device can determine that the cryptographic core allocation for the data stream is complete. For the number and / or capabilities of the cryptographic cores allocated to the data stream that cannot meet the throughput requirements, the embedded cryptographic device can determine that the cryptographic core allocation for the data stream is not complete. In some embodiments, the embedded cryptographic device that determines whether the cryptographic core allocation for the data stream is complete in determination block 712 can be a processor, an embedded cryptographic module, a multi-data stream memory controller, and / or a cryptographic core configuration module.

[0083] In response to determining that the cryptographic core allocation for the data stream is not complete (i.e., determination block 712 = "no"), the embedded cryptographic device can enable available cryptographic cores in block 704. In some embodiments, the embedded cryptographic device that enables available cryptographic cores in block 704 can be a processor, an embedded cryptographic module, a multi-data stream memory controller, and / or a cryptographic core configuration module.

[0084] In response to determining that the cryptographic core allocation for the data stream is complete (i.e., determination block 712 = "yes"), the embedded cryptographic device can receive a cryptographic core allocation request for the data stream in block 702. In some embodiments, the embedded cryptographic device that receives a cryptographic core allocation request for the data stream in block 702 can be a processor, an embedded cryptographic module, a multi-data stream memory controller, and / or a cryptographic core configuration module.

[0085] Reference Figure 7B , in method 700b, the embedded cryptographic device can receive a cryptographic core deallocation request for a data stream (e.g., Figures 2 to 5B data streams 204a, 204b, 300a, 300b, 400, 500 in Figure 1 . The cryptographic core deallocation request can be received from a processor (e.g., Figure 1the storage memory 24) and components of the SoC (e.g., Figure 1 at least one cryptographic core (e.g., Figure 2 the cryptographic core 212) in the SoC 12) and / or components of the computing device for the execution of the data flow of read transactions and / or write transactions between components of the SoC 12) and / or components of the computing device. Components of the SoC may include a memory (e.g., Figure 1 the memory 16), a memory interface (e.g., Figure 1 the memory interface 34), a storage memory interface 20 (e.g., Figure 1 the storage memory interface 20), a processor (e.g., Figure 1 the processor 14), etc. Components of the computing device may include a memory (e.g., Figure 1 the memory 36) that may be independent of the SoC. A cryptographic core deallocation request may include for meeting the throughput requirements of the workload and / or associated with the throughput requirements. The embedded cryptographic device may determine how many cryptographic cores to deallocate from the data flow based on the throughput requirements. In some embodiments, the embedded cryptographic device that receives a cryptographic core deallocation request for the data flow at block 720 may be a processor (e.g., Figure 1 the processor 14), an embedded cryptographic module (e.g., Figure 1 and Figure 2 the embedded cryptographic modules 38, 206), a multi-data flow memory controller (e.g., Figure 2 the multi-data flow memory controller 202), and / or a cryptographic core configuration module (e.g., Figure 2 the cryptographic core configuration module 208).

[0086] At block 722, the embedded cryptographic device may scan for cryptographic cores that are idle and / or will become idle for the data flow. In some embodiments, the embedded cryptographic device may analyze the tasks scheduled and / or executed by the cryptographic cores allocated to the data flow to determine which cryptographic cores are idle (e.g., have no tasks) and / or which cryptographic cores will become idle (e.g., have the fewest number of tasks). In some embodiments, the embedded cryptographic device may assume that a cryptographic core will become idle based on the relationship of the cryptographic cores allocated to the data flow in a data structure with respect to the cryptographic cores receiving and / or executing tasks. For example, it may be assumed that the cryptographic core referenced by the cryptographic core receiving and / or executing tasks will be the next to be idle. In some embodiments, the embedded cryptographic device that scans for cryptographic cores that are idle and / or will become idle for the data flow at block 722 may be a processor, an embedded cryptographic module, a multi-data flow memory controller, and / or a cryptographic core configuration module.

[0087] In block 724, the embedded cryptographic device may deactivate a cryptographic core. The embedded cryptographic device may optionally deactivate idle and / or cryptographic cores that will become idle. In some embodiments, a cryptographic core may be associated with an enable value stored in a memory (e.g., Figure 1 memory 16 in) (such as, a register), the enable value being set to indicate to the embedded cryptographic device that the cryptographic core is active or active. The embedded cryptographic device may deactivate the cryptographic core by setting the enable value to a value that is set to indicate to the embedded cryptographic device that the cryptographic core is inactive. In some embodiments, the embedded cryptographic device that deactivates the cryptographic core in block 724 may be a processor, an embedded cryptographic module, a multi-data stream memory controller, and / or a cryptographic core configuration module.

[0088] In block 726, the embedded cryptographic device may turn off the clock of the cryptographic core. The embedded cryptographic device may signal a clock controller for the cryptographic core to stop providing a clock signal to the cryptographic core. In some embodiments, the embedded cryptographic device that turns off the clock for the cryptographic core in block 726 may be a processor, an embedded cryptographic module, a multi-data stream memory controller, and / or a cryptographic core configuration module.

[0089] In block 728, the embedded cryptographic device may deallocate a cryptographic core from a data stream. To deallocate a cryptographic core from a data stream, the embedded cryptographic device may remove an entry for the cryptographic core from a data structure of the data stream, where the data structure may be configured to associate any number of cryptographic cores allocated to the data stream with each other. For example, the embedded cryptographic device may set a reference value stored in a memory (e.g., Figure 1 memory 16 in) (such as, a register), the reference value being set to indicate to the embedded cryptographic device that the entry for the cryptographic core does not reference other entries of another cryptographic core of the data structure of the data stream. The reference value may be a value of a cryptographic core ID that is not used as any other cryptographic core. In some embodiments, the embedded cryptographic device that deallocates the cryptographic core from the data stream in block 728 may be a processor, an embedded cryptographic module, a multi-data stream memory controller, and / or a cryptographic core configuration module.

[0090] In optional box 730, the embedded cryptographic device may align at least one other cryptographic core assigned to the data stream. Optional box 730 may be implemented for a case where there are multiple cryptographic cores in the data structure of the data stream. An entry of at least one other cryptographic core in the data structure of the data stream may be updated to set a reference value for the entry of at least one other cryptographic core to reference the entry of the cryptographic core that was previously referenced by the entry of the deallocated cryptographic core. For example, at least one other cryptographic core may have an entry in the data structure of the data stream that references the previous entry of the deallocated cryptographic core. The reference value of the entry for at least one other cryptographic core may be updated to now reference the entry of the cryptographic core that was previously referenced by the entry of the deallocated cryptographic core. In some embodiments, the embedded cryptographic device that aligns at least one other cryptographic core assigned to the data stream in optional box 730 may be a processor, an embedded cryptographic module, a multi-data stream memory controller, and / or a cryptographic core configuration module.

[0091] In decision box 732, the embedded cryptographic device may determine whether deallocation of the cryptographic core for the data stream is complete. The embedded cryptographic device may determine how many cryptographic cores are to be deallocated from the data stream based on the throughput requirement of the workload that received the request to deallocate the cryptographic core for the data stream in box 720. The embedded cryptographic device may track the cryptographic cores assigned to the data stream, such as based on the data structure of the data stream. Using the information of the cryptographic cores assigned to the data stream, the embedded cryptographic device may determine whether there are enough cryptographic cores to be deallocated from the data stream to meet the throughput requirement. For example, the embedded cryptographic device may compare the number and / or capabilities of the cryptographic cores assigned to the data stream with the number and / or capabilities of the cryptographic cores for meeting the throughput requirement. For the number and / or capabilities of the cryptographic cores assigned to the data stream that can exceed the throughput requirement, the embedded cryptographic device may determine that the deallocation of the cryptographic core for the data stream is not complete.

[0092] In some embodiments, exceeding the throughput requirement may include exceeding the throughput requirement by more than a specified margin. For the number and / or capabilities of the cryptographic cores assigned to the data stream that can meet the throughput requirement, the embedded cryptographic device may determine that the allocation of the cryptographic core for the data stream is complete. In some embodiments, meeting the throughput requirement may include exceeding the throughput requirement by less than a specified margin. In some embodiments, the embedded cryptographic device that determines whether deallocation of the cryptographic core for the data stream is complete in decision box 732 may be a processor, an embedded cryptographic module, a multi-data stream memory controller, and / or a cryptographic core configuration module.

[0093] In response to determining that the cryptographic core deallocation for the data stream is not complete (i.e., determining that box 732 = "No"), the embedded cryptographic device can scan for cryptographic cores that are idle and / or will become idle for the data stream in box 722. In some embodiments, the embedded cryptographic device that scans for cryptographic cores that are idle and / or will become idle for the data stream in box 722 can be a processor, an embedded cryptographic module, a multi-data stream memory controller, and / or a cryptographic core configuration module.

[0094] In response to determining that the cryptographic core deallocation for the data stream is complete (i.e., determining that box 732 = "Yes"), the embedded cryptographic device can receive a cryptographic core deallocation request for the data stream in box 720. In some embodiments, the embedded cryptographic device that receives a cryptographic core deallocation request for the data stream in box 720 can be a processor, an embedded cryptographic module, a multi-data stream memory controller, and / or a cryptographic core configuration module.

[0095] Various embodiments (including but not limited to the embodiments described above with reference to Figures 1 to 7B can be implemented in a wide variety of computing systems including mobile computing devices, examples of which are illustrated in Figure 8 Mobile computing device 800 may include a processor 802, which is coupled to a touch screen controller 804 and an internal memory 806. Processor 802 can be one or more multi-core integrated circuits designated for general or specific processing tasks. Internal memory 806 can be volatile or non-volatile memory, and can also be secure and / or encrypted memory, or insecure and / or non-encrypted memory, or any combination thereof. Examples of memory types that can be utilized include but are not limited to DDR, LPDDR, GDDR, WIDEIO, RAM, SRAM, DRAM, P-RAM, R-RAM, M-RAM, STT-RAM, embedded DRAM, non-volatile flash memory, UFS, SDCC, etc. Touch screen controller 804 and processor 802 can also be coupled to a touch screen panel 812, such as a resistive sensing touch screen, a capacitive sensing touch screen, an infrared sensing touch screen, etc. Additionally, the display of mobile computing device 800 does not need to have touch screen capabilities.

[0096] The mobile computing device 800 may have one or more radio signal transceivers 808 (e.g., Peanut, Bluetooth, ZigBee, Wi-Fi, RF radio) and antennas 810 that are coupled to each other and / or coupled to the processor 802 for transmitting and receiving communications. The transceivers 808 and antennas 810 may be used with the circuitry mentioned above to implement various wireless transmission protocol stacks and interfaces. The mobile computing device 800 may include a cellular network wireless modem chip 816 that enables communication via a cellular network and is coupled to the processor 802.

[0097] The mobile computing device 800 may include a peripheral device connection interface 818 coupled to the processor 802. The peripheral device connection interface 818 may be individually configured to accept one type of connection, or may be configured to accept various types of physical and communication connections, such as Universal Serial Bus (USB), FireWire, Thunderbolt, or PCIe. The peripheral device connection interface 818 may also be coupled to a similarly configured peripheral device connection port (not shown).

[0098] The mobile computing device 800 may also include a speaker 814 for providing audio output. The mobile computing device 800 may also include a housing 820 for housing all or some of the components described herein, the housing being constructed of plastic, metal, or a combination of materials. The mobile computing device 800 may include a power supply 822 coupled to the processor 802, such as a disposable or rechargeable battery. The rechargeable battery may also be coupled to the peripheral device connection port to receive a charging current from a source external to the mobile computing device 800. The mobile computing device 800 may also include physical buttons 824 for receiving user input. The mobile computing device 800 may also include a power button 826 for turning on and off the power of the mobile computing device 800.

[0099] Various embodiments (including but not limited to the embodiments referenced above Figures 1 to 7B described) may be implemented in a wide variety of computing systems including a laptop computer 900, an example of which is shown in Figure 9is shown. Many laptop computers include a touchpad touch surface 917 that serves as a pointing device for the computer and can thus receive drag, scroll, and tap gestures similar to those implemented on a computing device equipped with a touchscreen display and as described above. Laptop computer 900 will typically include a processor 902 coupled to volatile memory 912 and a mass non-volatile memory such as a disk drive 913 of flash memory. Additionally, computer 900 may have one or more antennas 908 for transmitting and receiving electromagnetic radiation, connectable to a wireless data link, and / or a cellular phone transceiver 916 coupled to processor 902. Computer 900 may also include a floppy disk drive 914 and a compact disk (CD) drive 915 coupled to processor 902. In a notebook configuration, the computer enclosure includes a touchpad 917, a keyboard 918, and a display 919, all coupled to processor 902. Other configurations of the computing device may include a computer mouse or trackball, as is well known, coupled to processor 902 (e.g., via a USB input), which may also be used in conjunction with various embodiments.

[0100] Various embodiments, including but not limited to the embodiments described above with reference to Figures 1 to 7B can also be implemented in a fixed computing system such as any of a variety of commercially available servers. Figure 10 An example server 1000 is illustrated therein. Such a server 1000 typically includes one or more multi-core processor assemblies 1001 coupled to volatile memory 1002 and a mass non-volatile memory such as a disk drive 1004. As Figure 10 shown, a multi-core processor assembly 1001 can be added to server 1000 by inserting it into a rack of the assembly. Server 1000 may also include a floppy disk drive, a compact disk (CD) or digital versatile disk (DVD) drive 1006 coupled to processor 1001. Server 1000 may also include a network access port 1003 that is coupled to the multi-core processor component 1001 for establishing a network interface connection with a network 1005 such as a local area network, the Internet, a public switched telephone network, and / or a cellular data network (e.g., CDMA, TDMA, GSM, PCS, 3G, 4G, 5G, LTE, or any other type of cellular data network) coupled to other broadcast system computers and servers.

[0101] Computer program code, or "program code," for use in performing the operations of the various embodiments when executed on a programmable processor, may be written in a high-level programming language, such as C, C++, C#, Smalltalk, Java, JavaScript, Visual Basic, Structured Query Language (e.g., Transact-SQL), Perl, or in various other programming languages. Program code or programs stored on a computer-readable storage medium as used in this application may refer to machine language code (such as, object code) in a format understandable by a processor.

[0102] Specific implementation examples are described in the following paragraphs. Although some of the specific implementation examples in the following are described in accordance with example systems, devices, or methods, additional example specific implementations may include: example systems or devices implemented as methods for performing the operations of the example systems or devices discussed in the following paragraphs; example systems, devices, or methods implemented by an embedded cryptographic device configured to perform the operations of the example systems, devices, or methods discussed in the following paragraphs; example systems, devices, or methods implemented by a computing device that includes a processing device configured with processing device-executable instructions to perform the operations of the example systems, devices, or methods; a computing device including components for performing the functions of the example systems, devices, or methods; and example systems, devices, or methods implemented as a non-transitory processor-readable storage medium storing processor-executable instructions thereon, the processor-executable instructions being configured to cause a processor of the computing device to perform the operations of the example systems, devices, or methods.

[0103] Example 1. A method for embedded cryptographic core management implemented in an embedded cryptographic module of a system-on-chip (SoC), the method comprising: receiving a cryptographic core configuration request for a data stream of a multi-data stream memory controller; and dynamically configuring at least one cryptographic core for the data stream.

[0104] Example 2. The method according to Example 1, wherein the cryptographic core configuration request is a cryptographic core allocation request for the data stream, the method further comprising: enabling available cryptographic cores, wherein the available cryptographic cores are the at least one cryptographic core; and allocating the at least one cryptographic core to the data stream.

[0105] Example 3. The method according to Example 2, wherein enabling the available cryptographic cores includes: setting an enable value of a data structure for the at least one cryptographic core to indicate an active state of the at least one cryptographic core to the multi-data stream memory controller.

[0106] Example 4. The method according to any one of Example 2 or Example 3, wherein allocating the at least one cryptographic core to the data stream includes: setting a reference value of a data structure for the at least one cryptographic core to indicate to the multi-data stream memory controller a link to another cryptographic core allocated to the data stream.

[0107] Example 5. The method according to any one of Example 2 to Example 4, the method further includes aligning another cryptographic core allocated to the data stream.

[0108] Example 6. The method according to Example 5, wherein aligning another cryptographic core allocated to the data stream includes: setting a reference value of a data structure for another cryptographic core to indicate to the multi-data stream memory controller a link to the at least one cryptographic core.

[0109] Example 7. The method according to any one of Example 1 to Example 5, wherein the cryptographic core configuration request is a cryptographic core deallocation request for the data stream, the method further includes: scanning a plurality of cryptographic cores assigned to the data stream to obtain an indication of the idle state of the at least one cryptographic core; deactivating the at least one cryptographic core; and deallocating the at least one cryptographic core from the data stream.

[0110] Example 8. The method according to Example 7, wherein deactivating the at least one cryptographic core includes: setting an enable value of a data structure for the at least one cryptographic core to indicate to the multi-data stream memory controller the inactive state of the at least one cryptographic core.

[0111] Example 9. The method according to any one of Example 7 or Example 8, wherein deallocating the at least one cryptographic core from the data stream includes: setting a reference value of a data structure for the at least one cryptographic core to indicate to the multi-data stream memory controller no link to other cryptographic cores.

[0112] Example 10. The method according to any one of Example 7 to Example 9, the method further includes: aligning a first cryptographic core allocated to the data stream.

[0113] Example 11. The method according to Example 10, wherein aligning the first cryptographic core allocated to the data stream includes: updating a reference value of a data structure for the first cryptographic core configured to indicate to the multi-data stream memory controller a link to the at least one cryptographic core to a reference value configured to indicate to the multi-data stream memory controller a link to a second cryptographic core allocated to the data stream.

[0114] The foregoing method descriptions and process flow diagrams are provided only as illustrative examples and are not intended to require or imply that the operations of the various embodiments must be performed in the order presented. The order of operations in the foregoing embodiments may be performed in any order. Words such as “thereafter,” “then,” “next,” etc. are not intended to limit the order of operations; these words are only used to guide the reader through the description of the method. Additionally, any reference to an element of a claim in the singular (e.g., a reference using the articles “a,” “an,” or “the”) should not be construed as limiting that element to the singular.

[0115] The various illustrative logical blocks, modules, circuits, and algorithmic operations described in connection with the various embodiments can be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, the various illustrative components, blocks, modules, circuits, and operations have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system. While a person skilled in the art may implement the described functionality in different ways for each particular application, such specific implementation decisions should not be interpreted as causing a departure from the scope of the claims.

[0116] The hardware for implementing the various illustrative logics, logical blocks, modules, and circuits described in connection with the embodiments disclosed herein can be implemented or performed with a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. While a general purpose processor may be a microprocessor, in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration. Alternatively, some operations or methods may be performed by circuitry specific to a given function.

[0117] In one or more embodiments, the described functionality may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored as one or more instructions or code on a non-transitory computer-readable medium or a non-transitory processor-readable medium. Operations of the methods or algorithms disclosed herein may be implemented in a processor-executable software module that may reside on a non-transitory computer-readable or processor-readable storage medium. A non-transitory computer-readable or processor-readable storage medium may be any storage medium that can be accessed by a computer or a processor. By way of example, and not limitation, such non-transitory computer-readable or processor-readable media may include RAM, ROM, EEPROM, flash memory, CD-ROM or other optical disk storage, disk storage or other magnetic storage devices, or any other medium that can be used to store the desired program code in the form of instructions or data structures and that can be accessed by a computer. As used herein, disk and optical disks include compact disk (CD), laser disk, optical disk, digital versatile disk (DVD), floppy disk, and Blu-ray disk, where disks typically reproduce data magnetically, while optical disks reproduce data optically with lasers. Combinations of the above are also included within the scope of non-transitory computer-readable and processor-readable media. Additionally, operations of a method or algorithm may reside as one code and / or instruction or any combination or collection of codes and / or instructions on a non-transitory processor-readable medium and / or a computer-readable medium that may be incorporated into a computer program product.

[0118] The foregoing description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the claims. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments and implementations without departing from the scope of the claims. Thus, the present disclosure is not intended to be limited to the embodiments and implementations described herein, but is to be accorded the broadest scope consistent with the claims and the principles and novel features disclosed herein.

Claims

1. A method for in - chip cryptographic core management implemented in an embedded cryptographic module of a system - on - a - chip (SoC), the method comprising: Receiving a cryptographic core configuration request for a data stream of a multi - data - stream memory controller; And Dynamically configuring at least one cryptographic core for the data stream.

2. The method according to claim 1, wherein the cryptographic core configuration request is a cryptographic core allocation request for the data stream, The method further comprising: Enabling available cryptographic cores, wherein the available cryptographic cores are the at least one cryptographic core; And Allocating the at least one cryptographic core to the data stream.

3. The method according to claim 2, wherein enabling the available cryptographic core comprises: Setting an enable value of a data structure for the at least one cryptographic core to indicate an active state of the at least one cryptographic core to the multi - data - stream memory controller.

4. The method according to claim 2, wherein allocating the at least one cryptographic core to the data stream comprises: Setting a reference value of a data structure for the at least one cryptographic core to indicate a link to another cryptographic core allocated to the data stream to the multi - data - stream memory controller.

5. The method according to claim 2, the method further comprising: Aligning another cryptographic core allocated to the data stream.

6. The method according to claim 5, wherein aligning another cryptographic core assigned to the data stream comprises: Setting a reference value of a data structure for another cryptographic core to indicate a link to the at least one cryptographic core to the multi - data - stream memory controller.

7. The method according to claim 1, wherein the cryptographic core configuration request is a cryptographic core de - allocation request for the data stream, The method further comprising: Scanning a plurality of cryptographic cores assigned to the data stream to obtain an indication of an idle state of the at least one cryptographic core; De - activating the at least one cryptographic core; And De - allocating the at least one cryptographic core from the data stream.

8. The method according to claim 7, wherein deactivating the at least one cryptographic core comprises: Setting an enable value of a data structure for the at least one cryptographic core to indicate an inactive state of the at least one cryptographic core to the multi - data - stream memory controller.

9. The method according to claim 7, wherein deallocating the at least one cryptographic core from the data stream comprises: Setting a reference value of a data structure for the at least one cryptographic core to indicate no link to other cryptographic cores to the multi - data - stream memory controller.

10. The method according to claim 7, the method further comprising: Aligning a first cryptographic core allocated to the data stream.

11. The method according to claim 10, wherein aligning the first cryptographic core assigned to the data stream comprises: Updating a reference value of a data structure for the first cryptographic core, which is configured to indicate a link to the at least one cryptographic core to the multi - data - stream memory controller, to be configured to indicate a link to a second cryptographic core allocated to the data stream to the multi - data - stream memory controller.

12. An embedded cryptographic device, the embedded cryptographic device being configured to: Receive a cryptographic core configuration request for a data stream of a multi - data - stream memory controller; and Dynamically configure at least one cryptographic core for the data stream.

13. The embedded cryptographic device according to claim 12, wherein: The cryptographic core configuration request is a cryptographic core allocation request for the data stream; and The embedded cryptographic device is further configured to: Enable available cryptographic cores, wherein the available cryptographic cores are the at least one cryptographic core; and Allocate the at least one cryptographic core to the data stream.

14. The embedded cryptographic device according to claim 12, wherein the embedded cryptographic device is further configured to: set an enable value of a data structure for the at least one cryptographic core to indicate an active state of the at least one cryptographic core to the multi-data stream memory controller.

15. The embedded cryptographic device according to claim 12, wherein the embedded cryptographic device is further configured to: set a reference value of a data structure for the at least one cryptographic core to indicate a link to another cryptographic core assigned to the data stream to the multi-data stream memory controller.

16. The embedded cryptographic device according to claim 12, wherein the embedded cryptographic device is further configured to: align another cryptographic core assigned to the data stream.

17. The embedded cryptographic device according to claim 12, wherein the embedded cryptographic device is further configured to: set a reference value of a data structure for another cryptographic core to indicate a link to the at least one cryptographic core to the multi-data stream memory controller.

18. The embedded cryptographic device according to claim 12, wherein: the cryptographic core configuration request is a cryptographic core deallocation request for the data stream, the embedded cryptographic device is further configured to: scan a plurality of cryptographic cores assigned to the data stream to obtain an indication of an idle state of the at least one cryptographic core; deactivate the at least one cryptographic core; and deallocate the at least one cryptographic core from the data stream.

19. The embedded cryptographic device according to claim 12, wherein the embedded cryptographic device is further configured to: set an enable value of a data structure for the at least one cryptographic core to indicate an inactive state of the at least one cryptographic core to the multi-data stream memory controller.

20. The embedded cryptographic device according to claim 12, wherein the embedded cryptographic device is further configured to: set a reference value of a data structure for the at least one cryptographic core to indicate no link to other cryptographic cores to the multi-data stream memory controller.

21. The embedded cryptographic device according to claim 12, wherein the embedded cryptographic device is further configured to: align a first cryptographic core assigned to the data stream.

22. The embedded cryptographic device according to claim 12, wherein the embedded cryptographic device is further configured to: update a reference value of a data structure for a first cryptographic core, which is configured to indicate a link to the at least one cryptographic core to the multi-data stream memory controller, to a reference value configured to indicate a link to a second cryptographic core assigned to the data stream.

23. A computing device, the computing device comprising: means for receiving a cryptographic core configuration request for a data stream of a multi-data stream memory controller; and means for dynamically configuring at least one cryptographic core for the data stream.

24. The computing device according to claim 23, wherein the cryptographic core configuration request is a cryptographic core allocation request for the data stream, The computing device further includes: A component for enabling available cryptographic cores, where the available cryptographic cores are the at least one cryptographic core; And A component for allocating the at least one cryptographic core to the data stream.

25. The computing device according to claim 24, wherein: The component for enabling the available cryptographic cores includes a component for setting an enabling value of a data structure for the at least one cryptographic core to indicate an active state of the at least one cryptographic core to the multi-data stream memory controller; And The component for allocating the at least one cryptographic core to the data stream includes a component for setting a reference value of the data structure for the at least one cryptographic core to indicate a link to another cryptographic core allocated to the data stream to the multi-data stream memory controller.

26. The computing device according to claim 23, the computing device further includes a component for setting a reference value of a data structure for another cryptographic core to indicate a link to the at least one cryptographic core to the multi-data stream memory controller.

27. The computing device according to claim 23, wherein the cryptographic core configuration request is a cryptographic core deallocation request for the data stream, The computing device further includes: A component for scanning a plurality of cryptographic cores assigned to the data stream to obtain an indication of an idle state of the at least one cryptographic core; A component for deactivating the at least one cryptographic core; And A component for deallocating the at least one cryptographic core from the data stream.

28. The computing device according to claim 27, wherein: The component for deactivating the at least one cryptographic core includes a component for setting an enabling value of a data structure for the at least one cryptographic core to indicate an inactive state of the at least one cryptographic core to the multi-data stream memory controller; And The component for deallocating the at least one cryptographic core from the data stream includes a component for setting a reference value of the data structure for the at least one cryptographic core to indicate no link to other cryptographic cores to the multi-data stream memory controller.

29. The computing device according to claim 23, the computing device further includes a component for updating a reference value of a data structure for a first cryptographic core configured to indicate a link to the at least one cryptographic core to a reference value configured to indicate a link to a second cryptographic core allocated to the data stream to the multi-data stream memory controller.

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