Array substrate and display panel

Abstract

The application relates to an array substrate and a display panel. The array substrate has a display area and a non-display area located at the periphery of the display area. The non-display area comprises a virtual pixel area arranged adjacent to the display area. The array substrate comprises a substrate layer, a first transparent electrode layer and a first metal layer. The first transparent electrode layer comprises a first pixel electrode located in the virtual pixel area and a second pixel electrode located in the display area. The first metal layer is located on the side of the first transparent electrode layer away from the substrate layer and at least partially contacts the first transparent electrode layer. The first metal layer comprises a first common electrode located in the non-display area and the display area, and the first common electrode is arranged close to the first pixel electrode and the second pixel electrode. At least one side of the first pixel electrode extends to overlap and at least partially contact the adjacent first common electrode, and any side of the second pixel electrode is arranged to be spaced apart from the adjacent first common electrode. The application can effectively improve the display effect of the display panel.

Description

Technical Field

[0001] This application relates to the field of display technology, and more particularly to an array substrate and a display panel. Background Technology

[0002] To improve the etching uniformity of the display area and reduce etching load, dummy pixels are typically designed around the periphery of the display area, with the shape of the dummy pixels being basically consistent with the shape of the pixels in the display area. To ensure that the area where the dummy pixels are located is not displayed, for example, to keep the area where the dummy pixels are located in a constantly black state, the gate, data lines, and pixel electrodes in the dummy pixels are usually designed to be in a floating state.

[0003] However, in fringe field switching (FFS) and in-plane switching (IPS) type liquid crystal display panels, the pixel electrodes are usually a single piece of metal structure. Therefore, the pixel electrodes in the virtual pixels are also a single piece of metal structure. Charge tends to accumulate on large floating metal structures, which creates a voltage difference between the pixel electrodes and the common electrode in the virtual pixel. This causes the liquid crystal in the area where the virtual pixel is located to rotate irregularly, preventing the area where the virtual pixel is located from remaining normally black. Consequently, the edges of the liquid crystal panel become bright, reducing the display effect. Summary of the Invention

[0004] This application provides an array substrate and a display panel. By using a simpler film structure, a simpler manufacturing process, and lower cost, the pixel electrodes in the virtual pixel area are electrically connected to the common electrode, thereby keeping the virtual pixel area in a normally black state, which can effectively improve the display effect of the display panel.

[0005] To achieve the above objectives, according to a first aspect of this application, an array substrate is provided, the array substrate having a display area and a non-display area located around the display area, the non-display area including a virtual pixel area disposed adjacent to the display area; the array substrate includes:

[0006] Substrate layer;

[0007] The first transparent electrode layer includes at least one first pixel electrode located in the virtual pixel area and at least one second pixel electrode located in the display area;

[0008] A first metal layer is located on the side of the first transparent electrode layer opposite to the substrate layer and is at least partially in contact with the first transparent electrode layer; the first metal layer includes a first common electrode located in the non-display area and the display area, the first common electrode being disposed close to the first pixel electrode and the second pixel electrode;

[0009] Wherein, at least one side of the first pixel electrode extends to overlap with and at least partially contact the adjacent first common electrode, and any side of the second pixel electrode is spaced apart from the adjacent first common electrode.

[0010] Optionally, the first metal layer and the first transparent electrode layer are at least partially overlapped in a direction perpendicular to the substrate layer; the first metal layer further includes a first gate located in the virtual pixel area and a second gate located in the display area; the first transparent electrode layer further includes a first electrode block located between the first gate and the substrate layer, and a second electrode block located between the second gate and the substrate layer; the first electrode block matches the shape and size of the first gate, and the second electrode block matches the shape and size of the second gate;

[0011] In the display area, the first transparent electrode layer further includes a third electrode block located between the first common electrode and the substrate layer, the shape of the third electrode block matching the shape and size of the corresponding first common electrode.

[0012] Optionally, the first pixel electrode extends to connect with the adjacent first electrode block.

[0013] Optionally, the first gate is connected to the adjacent first common electrode.

[0014] Optionally, the array substrate further includes a second metal layer, which is located on the side of the first metal layer opposite to the substrate layer;

[0015] The second metal layer includes a first data line located in the virtual pixel area, the first data line extending to overlap with and be electrically connected to the first common electrode.

[0016] Optionally, the array substrate further includes an insulating layer located between the first metal layer and the second metal layer, and the first data line is electrically connected to the first common electrode located in the non-display area through a first via penetrating the insulating layer.

[0017] Optionally, the array substrate further includes:

[0018] An insulating layer is located on the side of the first metal layer opposite to the substrate layer;

[0019] An active layer is located on the side of the insulating layer opposite to the first metal layer; the active layer includes a first semiconductor pattern aligned with the first gate and a second semiconductor pattern aligned with the second gate; and

[0020] The second metal layer is located on the side of the active layer away from the insulating layer; the second metal layer includes a first source electrically connected to the first semiconductor pattern, a first drain insulated from the first semiconductor pattern, and a second source and a second drain electrically connected to the second semiconductor pattern.

[0021] Optionally, the array substrate further includes:

[0022] A passivation layer is located on the side of the second metal layer opposite to the active layer; and

[0023] The second transparent electrode layer is located on the side of the passivation layer that is opposite to the second metal layer;

[0024] The second transparent electrode layer includes a first connection electrode located in the virtual pixel area and a second connection electrode located in the display area; the first connection electrode is electrically connected to the first drain and the first pixel electrode through a second via penetrating the insulating layer and the passivation layer; the second connection electrode is electrically connected to the second drain and the second pixel electrode through a third via penetrating the insulating layer and the passivation layer.

[0025] Optionally, the second transparent electrode layer further includes a second common electrode located around the first pixel electrode and the second pixel electrode, the second common electrode overlapping the first common electrode and being electrically connected.

[0026] According to a second aspect of this application, a display panel is provided, the display panel including an opposing substrate, a liquid crystal layer and an array substrate as described above; the opposing substrate and the array substrate are disposed opposite to each other, and the liquid crystal layer is sandwiched between the opposing substrate and the array substrate.

[0027] In the array substrate and display panel of this application embodiment, the first pixel electrode in the virtual pixel area is located on the first metal layer and is directly electrically connected to the first common electrode. This allows the first pixel electrode and the first common electrode to receive the same COM signal, thereby avoiding a voltage difference between the first pixel electrode and the first common electrode, preventing the liquid crystal in the virtual pixel area from rotating irregularly, and keeping the virtual pixel area in a normally black state, which is beneficial to improving the display effect of the display panel. Furthermore, no insulating layer is required between the first metal layer and the first transparent electrode layer, allowing the first pixel electrode to directly contact and electrically connect with the adjacent first common electrode, avoiding the connection between the two through vias. This simplifies the manufacturing process, reduces manufacturing costs, and improves the stability of the electrical connection between the first pixel electrode and the first common electrode. Therefore, this application embodiment can achieve electrical connection between the first pixel electrode and the first common electrode in the virtual pixel area through a simpler film structure, a simpler process, and lower cost, thereby keeping the virtual pixel area in a normally black state, which can effectively improve the display effect of the display panel using this array substrate, especially beneficial to improving the display effect of FFS / IPS type liquid crystal display panels.

[0028] Other features and advantages of this application will be described in detail in the following detailed description section. Attached Figure Description

[0029] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0030] To gain a more complete understanding of this application and its beneficial effects, the following description will be provided in conjunction with the accompanying drawings, wherein the same reference numerals in the following description denote the same parts.

[0031] Figure 1 This is a schematic diagram illustrating an exemplary region division of an array substrate provided in an embodiment of this application;

[0032] Figure 2 yes Figure 1 Enlarged view of region A in the middle;

[0033] Figure 3 This is a schematic diagram of the region division of an array substrate provided in an embodiment of this application;

[0034] Figure 4 yes Figure 3 Enlarged view of region B in the middle;

[0035] Figure 5 yes Figure 4 Enlarged view of region C in the middle;

[0036] Figure 6 yes Figure 5 A schematic diagram of the cross-sectional structure at position D-D';

[0037] Figure 7 yes Figure 3 A magnified view of a portion of the central display area;

[0038] Figure 8 yes Figure 7 A schematic diagram of the cross-sectional structure at position E-E';

[0039] Figure 9 This is a schematic diagram of the cross-sectional structure of a display panel provided in an embodiment of this application.

[0040] Explanation of reference numerals in the attached figures:

[0041] 1 (1') Array substrate; 2 (2') Display area; 3 (3') Non-display area; 4 (4') Virtual pixel area; 5 (5') Driving circuit area; 6. Data signal pad; 7. Substrate layer; 8. First transparent electrode layer; 9. First metal layer; 10 (10') First pixel electrode; 11. Second pixel electrode; 12. First common electrode; 12'. Common electrode; 13 (13') First gate; 14. Second gate; 15. First electrode block; 16. Second electrode block; 17. Third electrode block; 18. Second metal layer; 19 (19') First data line; 20. Insulating layer; 21. First via; 22. Active layer; 23. First semiconductor pattern Case; 24, second semiconductor pattern; 25 (25'), first source electrode; 26, first drain electrode; 27, second source electrode; 28, second drain electrode; 29, passivation layer; 30, second transparent electrode layer; 31, first connecting electrode; 32, second connecting electrode; 33, second via; 34, third via; 35, second common electrode; 36, first pixel unit; 37, first thin film transistor; 38 (38'), second data line; 39, first scan line; 40 (40'), second pixel unit; 41, second thin film transistor; 42 (42'), second scan line; 43, display panel; 44, opposing substrate; 45, liquid crystal layer; X, second direction; Y, first direction. Detailed Implementation

[0042] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the protection scope of this application.

[0043] like Figure 1 and Figure 2 As shown, an exemplary array substrate 1' has a non-display area 3' surrounding a display area 2', and the non-display area 3' includes a virtual pixel area 4' surrounding the display area 2' and a driving circuit area 5' located on the side of the virtual pixel area 4' away from the display area 2'. The display area 2' has a plurality of first pixel units arranged in an array, and the virtual pixel area 4' has a plurality of second pixel units 40' arranged along the extending direction of the edge of the display area 2'. The second pixel units 40' and the first pixel units are fabricated in the same process, and the shape of the second pixel units 40' is substantially consistent with the shape of the first pixel units in the display area 2'. This design can improve the etching uniformity of the display area 2' of the array substrate 1' and reduce the etching load.

[0044] To ensure that the virtual pixel area 4' is not displayed, the first gate 13', the first source 25' (or the first data line 19'), and the first pixel electrode 10' in the second pixel unit 40' are typically designed to be in a floating state, so that the virtual pixel area 4' remains normally black. It should be noted that the floating state described in this application refers to the state where no electrical signal is applied.

[0045] like Figure 2 As shown, the first data line 19' located in the virtual pixel area 4' and the second data line 38' located in the display area 2' both extend into the driving circuit area 5'. The driving circuit area 5' has a data signal pad 6 that corresponds only to the second data line 38'. The second data line 38' is electrically connected to the corresponding data signal pad 6 to receive data signals, while the first data line 19' is in a floating state. Furthermore, as... Figure 2 As shown, the first gate 13', the second scan line 42' and the first pixel electrode 10' in the virtual pixel area 4' are also in a floating state, and the first gate 13', the second scan line 42' and the first pixel electrode 10' are all spaced apart (insulated) from the common (COM) electrode 12'.

[0046] Since the pixel electrodes in edge field switching (FFS) and planar switching (IPS) type liquid crystal display panels are usually solid metal structures, the first pixel electrode 10' is also a solid metal structure. Charge tends to accumulate on large floating metal structures, which causes a voltage difference between the first pixel electrode 10' and the common electrode 12'. This causes the liquid crystal in the virtual pixel area 4' to rotate irregularly, preventing the virtual pixel area 4' from remaining in a normally black state. Consequently, the edges of the liquid crystal panel become bright, reducing the display effect.

[0047] against Figure 2To address the problems with the array substrate shown, this application employs a differentiated design for the pixel electrodes in the virtual pixel area and the display area. Furthermore, through improvements to the film layer structure, the pixel electrodes in the virtual pixel area and the common electrode can be fabricated using the same mask in the same process, and the fabricated pixel electrodes in the virtual pixel area are directly electrically connected to the common electrode. Therefore, this application can simplify the process and reduce manufacturing costs while ensuring that the pixel electrodes in the virtual pixel area and the common electrode always maintain the same electrical signal. This avoids voltage differences between the pixel electrodes and the common electrode, prevents irregular rotation of the liquid crystal in the virtual pixel area, and keeps the virtual pixel area in a constantly black state, thus improving the display effect of the display panel. Please refer to the following description of the embodiments for details.

[0048] like Figures 3 to 8 As shown, this application embodiment provides an array substrate 1, which has a display area 2 and a non-display area 3 located around the display area 2. The non-display area 3 includes a virtual pixel area 4 disposed adjacent to the display area 2.

[0049] It should be noted that the display area 2 and non-display area 3 described in this application embodiment are divided according to the effective display area 2 and the border area of ​​the display panel on which the array substrate 1 is applied. That is, the display area 2 of the array substrate 1 is aligned with the effective display area 2 of the display panel on which the array substrate 1 is applied, and the non-display area 3 of the array substrate 1 is aligned with the border area of ​​the display panel on which the array substrate 1 is applied.

[0050] In some embodiments, such as Figure 3 As shown, the virtual pixel area 4 is arranged around the display area 2, but it is not limited to this. This application embodiment is described with the virtual pixel area 4 surrounding the display area 2 as an example, that is, the virtual pixel area 4 is provided on all four sides of the display area 2.

[0051] In some embodiments, such as Figure 6 and Figure 8 As shown, the array substrate 1 includes a substrate layer 7, a first transparent electrode layer 8, and a first metal layer 9. The first transparent electrode layer 8 includes at least one first pixel electrode 10 located in the virtual pixel region 4 and at least one second pixel electrode 11 located in the display region 2. The first metal layer 9 is located on the side of the first transparent electrode layer 8 facing away from the substrate layer 7 and is at least partially in contact with the first transparent electrode layer 8. The first metal layer 9 includes a first common electrode 12 located in the non-display region 3 and the display region 2, and the first common electrode 12 is disposed close to the first pixel electrode 10 and the second pixel electrode 11. At least one side of the first pixel electrode 10 extends to overlap with and at least partially contact the adjacent first common electrode 12, and any side of the second pixel electrode 11 is spaced apart from the adjacent first common electrode 12.

[0052] Understandably, when the array substrate 1 is working, the first common electrode 12 is connected to a common voltage signal (i.e., a COM signal).

[0053] In this embodiment, the second pixel electrode 11 in the display area 2 is spaced apart from the adjacent first common electrode 12 on either side, allowing the second pixel electrode 11 and the first common electrode 12 to be connected to different electrical signals to generate an electric field, thereby driving the liquid crystal in the display area 2 to rotate regularly to achieve a normal display effect. The first pixel electrode 10 in the virtual pixel area 4 is electrically connected to the adjacent first common electrode 12, allowing the first pixel electrode 10 and the first common electrode 12 to be connected to the same COM signal. This avoids a voltage difference between the first pixel electrode 10 and the first common electrode 12, thus preventing the liquid crystal in the virtual pixel area 4 from rotating irregularly and keeping the virtual pixel area 4 in a normally black state, which is beneficial for improving the display effect of the display panel. Furthermore, an insulating layer 20 is not required between the first metal layer 9 and the first transparent electrode layer 8, allowing the first pixel electrode 10 to directly contact and electrically connect with the adjacent first common electrode 12, avoiding connection through vias. This simplifies the fabrication process of the array substrate 1, reduces its manufacturing cost, and improves the connection stability between the first pixel electrode 10 and the first common electrode 12.

[0054] In some embodiments, the substrate layer 7 can be a flexible substrate or a rigid substrate, and the embodiments of this application are not limited thereto. For example, the material of the substrate layer 7 includes polyimide or glass, but is not limited thereto.

[0055] In some embodiments, the material of the first transparent electrode layer 8 is selected from transparent metal oxides, such as indium tin oxide (ITO), but is not limited thereto.

[0056] In some embodiments, the first metal layer 9 and the first transparent electrode layer 8 are disposed at least partially overlapping in a direction perpendicular to the substrate layer 7.

[0057] In one specific embodiment, the orthographic projection of the first metal layer 9 onto the substrate layer 7 is located in the orthographic projection of the first transparent electrode layer 8 onto the substrate layer 7. That is, the first metal layer 9 and the first transparent electrode layer 8 are completely overlapped in the direction perpendicular to the substrate layer 7.

[0058] When the first metal layer 9 and the first transparent electrode layer 8 are completely overlapped in a direction perpendicular to the substrate layer 7, the first metal layer 9 and the first transparent electrode layer 8 can be fabricated using a halftone mask (HTM) in the same process, so that the first transparent electrode layer 8 is located at the bottom of the first metal layer 9. This design can save a photomask process, thereby further simplifying the fabrication process of the array substrate 1 and saving the manufacturing cost of the array substrate 1.

[0059] In some embodiments, the edge of the portion of the first pixel electrode 10 that overlaps with the first common electrode 12 may extend in a direction away from the first common electrode 12, or it may be aligned with the edge of the first common electrode 12. This application does not limit this aspect.

[0060] In some embodiments, such as Figure 5 and Figure 7 As shown, the first pixel electrode 10 and the second pixel electrode 11 are arranged in a block shape, but this is not the only possibility. For example, in other embodiments, the first pixel electrode 10 and the second pixel electrode 11 may also have a hollow structure formed on them according to display requirements.

[0061] In some embodiments, such as Figure 6 and Figure 8 As shown, the first metal layer 9 also includes a first gate 13 located in the virtual pixel area 4 and a second gate 14 located in the display area 2. The first transparent electrode layer 8 also includes a first electrode block 15 located between the first gate 13 and the substrate layer 7, and a second electrode block 16 located between the second gate 14 and the substrate layer 7. The first electrode block 15 matches the shape and size of the first gate 13, and the second electrode block 16 matches the shape and size of the second gate 14. In the display area 2, the first transparent electrode layer 8 also includes a third electrode block 17 located between the first common electrode 12 and the substrate layer 7, and the shape of the third electrode block 17 matches the shape and size of the corresponding first common electrode 12.

[0062] It is understandable that the first electrode block 15, the second electrode block 16 and the third electrode block 17 are fabricated in the same photomask process as the corresponding first gate 13, second gate 14 and the first common electrode 12 in the display area 2.

[0063] In some embodiments, the first pixel electrode 10 extends to connect with the adjacent first electrode block 15, so that the first pixel electrode 10 is electrically connected to the first gate 13, thereby making the first gate 13 electrically connected to the first common electrode 12. This design allows the first gate 13 in the virtual pixel area 4 to also receive the COM signal, which helps to enhance the stability of the first common electrode 12, that is, to enhance the stability of the COM signal on the array substrate 1, thereby improving the display effect.

[0064] In some embodiments, such as Figure 4 and Figure 5 As shown, the first gate 13 is directly connected to the adjacent first common electrode 12, making the first gate 13 and the first common electrode 12 directly electrically connected. This design allows the first gate 13 in the virtual pixel area 4 to also receive the COM signal, which helps to enhance the stability of the first common electrode 12, that is, to enhance the stability of the COM signal on the array substrate 1, thereby improving the display effect.

[0065] Since the distance between the first common electrode 12 and the first gate electrode 13 in the non-display area 3 is small, and the first gate electrode 13 and the first common electrode 12 are arranged in the same layer, it is relatively easy to directly connect the first gate electrode 13 and the adjacent first common electrode 12 without increasing the manufacturing process difficulty.

[0066] In some embodiments, such as Figures 4 to 6 As shown, the array substrate 1 further includes a second metal layer 18, which is located on the side of the first metal layer 9 facing away from the substrate layer 7. The second metal layer 18 includes a first data line 19 located in the virtual pixel area 4, which extends to overlap with and is electrically connected to the first common electrode 12. This design allows the first data line 19 in the virtual pixel area 4 to also receive the COM signal, which helps to further enhance the stability of the first common electrode 12, that is, to further enhance the stability of the COM signal on the array substrate 1, thereby further improving the display effect.

[0067] In some embodiments, such as Figure 4 and Figure 6 As shown, the array substrate 1 also includes an insulating layer 20 located between the first metal layer 9 and the second metal layer 18, and a first via 21 penetrating the insulating layer 20. The first via 21 is located in the non-display area 3. The first data line 19 is electrically connected to the first common electrode 12 located in the non-display area 3 through the first via 21 penetrating the insulating layer 20.

[0068] Understandably, it is easier to make an electrical connection between the first data line 19 and the first common electrode 12 in the non-display area 3 than in the display area 2, and it will not affect the aperture ratio of the display area 2.

[0069] In some embodiments, the insulating layer 20 is located on the side of the first metal layer 9 away from the substrate layer 7, and the insulating layer 20 is a gate insulating layer 20, that is, the insulating layer 20 covers at least the first gate 13 and the second gate 14.

[0070] In some embodiments, the insulating layer 20 also covers the first pixel electrode 10, the second pixel electrode 11, and the first common electrode 12, but is not limited thereto.

[0071] In some embodiments, such as Figure 6 and Figure 8 As shown, the array substrate 1 further includes an active layer 22, which is located on the side of the insulating layer 20 away from the first metal layer 9. The active layer 22 includes a first semiconductor pattern 23 aligned with the first gate 13 and a second semiconductor pattern 24 aligned with the second gate 14. A second metal layer 18 is located on the side of the active layer 22 away from the insulating layer 20. The second metal layer 18 includes a first source 25 electrically connected to the first semiconductor pattern 23, a first drain 26 insulated from the first semiconductor pattern 23, and a second source 27 and a second drain 28 electrically connected to the second semiconductor pattern 24.

[0072] In some embodiments, the orthographic projection of the first source 25 on the substrate 7 coincides with the orthographic projection of the first semiconductor pattern 23 on the substrate 7, the orthographic projection of the first drain 26 on the substrate 7 is spaced apart from the orthographic projection of the first semiconductor pattern 23 on the substrate 7, and the orthographic projections of the second source 27 and the second drain 28 on the substrate 7 coincide with the orthographic projection of the second semiconductor pattern 24 on the substrate 7.

[0073] In some embodiments, the edge of the first semiconductor pattern 23 is aligned with the edge of the first source 25, and the edge of the second semiconductor pattern 24 is aligned with the edges of the second source 27 and the second drain 28.

[0074] It should be noted that the source and drain in the embodiments of this application can be interchanged.

[0075] Understandably, the second metal layer 18 and the active layer 22 can also be formed in the same process. For example, the second metal layer 18 and the active layer 22 can be fabricated using a halftone mask (HTM), which helps to further save one photomask process. In this case, the active layer 22 is provided below the second metal layer 18.

[0076] Of course, in other embodiments, the second metal layer 18 and the active layer 22 can also be fabricated using two different photomask processes. In this case, it is not required that an active layer 22 be provided under all the second metal layers 18.

[0077] In some embodiments, such as Figure 6 and Figure 8 As shown, the array substrate 1 further includes a passivation layer 29 and a second transparent electrode layer 30. The passivation layer 29 is located on the side of the second metal layer 18 opposite to the active layer 22; the second transparent electrode layer 30 is located on the side of the passivation layer 29 opposite to the second metal layer 18. The second transparent electrode layer 30 includes a first connection electrode 31 located in the virtual pixel area 4 and a second connection electrode 32 located in the display area 2.

[0078] In some embodiments, such as Figure 6 and Figure 8 As shown, the array substrate 1 also includes a second via 33 and a third via 34 penetrating the insulating layer 20 and the passivation layer 29. The first connection electrode 31 is electrically connected to the first drain electrode 26 and the first pixel electrode 10 through the second via 33. The second connection electrode 32 is electrically connected to the second drain electrode 28 and the second pixel electrode 11 through the third via 34.

[0079] In some embodiments, such as Figures 4 to 8 As shown, the second transparent electrode layer 30 also includes a second common electrode 35 located around the first pixel electrode 10 and the second pixel electrode 11. The second common electrode 35 overlaps with and is electrically connected to the first common electrode 12. It is understood that the second common electrode 35 and the first common electrode 12 are connected to the same COM signal.

[0080] In some embodiments, the second common electrode 35 is distributed in multiple blocks. The distribution position of the second common electrode 35 is not limited in the embodiments of this application.

[0081] In some embodiments, the first transparent electrode layer 8 and the second transparent electrode layer 30 are made of the same material, but are not limited thereto.

[0082] It is understood that the array substrate 1 provided in this application embodiment can be fabricated using either a 4-mask process or a 5-mask process. In the 4-mask process, the first mask process is used to form the first metal layer 9 and the first transparent electrode layer 8, the second mask process is used to form the active layer 22 and the second metal layer 18, the third mask process is used to form the passivation layer 29 and the vias on the insulating layer 20, and the fourth mask process is used to form the second transparent electrode layer 30. The difference between the 5-mask process and the 4-mask process is that the active layer 22 and the second metal layer 18 in the 5-mask process are fabricated using two different masks.

[0083] In some embodiments, such as Figure 4 and Figure 7 As shown, the array substrate 1 includes a plurality of first pixel units 36 located in the display area 2 and arranged in an array. Each first pixel unit 36 ​​includes a second pixel electrode 11, at least one first thin film transistor 37 disposed adjacent to and electrically connected to the second pixel electrode 11, a second data line 38 and a first scan line 39 electrically connected to the at least one first thin film transistor 37.

[0084] Understandably, the first thin-film transistor 37 is composed of a second gate 14, a second semiconductor pattern 24, a second source 27, and a second drain 28. The second data line 38 is electrically connected to the second source 27, and the first scan line 39 is electrically connected to the second gate 14. Furthermore, the first scan line 39 and the second gate 14 are disposed on the same layer and are both located on the first metal layer 9; the second data line 38, the second source 27, and the second drain 28 are disposed on the same layer and are both located on the second metal layer 18.

[0085] In one embodiment, the second data line 38 and the first scan line 39 intersect each other and are insulated from each other. The second data line 38 extends along a first direction (e.g., vertical direction) Y, and the first scan line 39 extends along a second direction (e.g., horizontal direction) X. The second pixel electrode 11 is located in the area defined by two adjacent second data lines 38 and two adjacent first scan lines 39.

[0086] In some embodiments, such as Figure 4 and Figure 5 As shown, the array substrate 1 includes a plurality of second pixel units 40 located in the virtual pixel area 4. Each second pixel unit 40 includes a first pixel electrode 10 and at least one second thin-film transistor 41 disposed adjacent to and electrically connected to the first pixel electrode 10. The plurality of second pixel units 40 are arranged sequentially along the extending direction of the edge of the display area 2.

[0087] Understandably, the second thin-film transistor 41 is composed of a first gate 13, a first semiconductor pattern 23, a first source 25 and a first drain 26. Since the first drain 26 is insulated from the first semiconductor pattern 23, the second thin-film transistor 41 cannot perform the normal function of a transistor.

[0088] For example, when the first direction Y is vertical and the second direction X is horizontal, a portion of the second pixel units 40 are located on the upper and lower sides of the display area 2 and arranged sequentially along the second direction X, while another portion of the second pixel units 40 are located on the left and right sides of the display area 2 and arranged sequentially along the first direction Y. Furthermore, the second pixel units 40 located on the upper and lower sides of the display area 2 can be arranged in a single row or in multiple rows; similarly, the second pixel units 40 located on the left and right sides of the display area 2 can be arranged in a single column or in multiple columns. In this embodiment, the example given is that the second pixel units 40 located on the upper and lower sides of the display area 2 are arranged in a single row and the second pixel units 40 located on the left and right sides of the display area 2 are arranged in a single column.

[0089] In some embodiments, a plurality of second pixel units 40 located on any side of the display area 2 are aligned one-to-one with a plurality of adjacent first pixel units 36 in the display area 2. This design ensures that the structure of the pixel units in the display area 2 and the virtual pixel area 4 is consistent, which is beneficial for simplifying the manufacturing process, improving the etching uniformity of the display area 2, and reducing the etching load.

[0090] In some embodiments, the second data line 38 in the display area 2 extends into the virtual pixel area 4 along the first direction Y, and among the plurality of second pixel units 40 arranged along the second direction X, a second data line 38 is provided between any two adjacent first pixel electrodes 10. The first scan line 39 in the display area 2 extends into the virtual pixel area 4 along the second direction X, and among the plurality of second pixel units 40 arranged along the first direction Y, a first scan line 39 is provided between any two adjacent first pixel electrodes 10.

[0091] In some embodiments, the second data line 38 located in the virtual pixel area 4 is connected to the adjacent first source 25, and the first scan line 39 located in the virtual pixel area 4 is connected to the adjacent first gate 13. This design makes the connection between the second data line 38 and the first source 25, and the first scan line 39 and the first gate 13 in the virtual pixel area 4 the same as the connection between the second data line 38 and the second source 27, and the first scan line 39 and the second gate 14 in the display area 2, which is beneficial to improving the etching uniformity of the display area 2 and can reduce the etching load.

[0092] Understandably, although the second data line 38 and the first scan line 39 are electrically connected to the first source 25 and the first gate 13 respectively in the virtual pixel area 4, the first drain 26 in the second thin film transistor 41 is not electrically connected to the first semiconductor pattern 23. Therefore, the electrical connection between the second thin film transistor 41 and the first scan line 39 or the second data line 38 will not affect the normally black state of the virtual pixel area 4.

[0093] In some embodiments, a first data line 19 extending along the first direction Y is provided on the side of any row of first pixel electrodes 10 arranged along the first direction Y, away from or near the display area 2. The first data line 19 is connected to the first source 25 of at least one second thin-film transistor 41 in an adjacent second pixel unit 40. A second scan line 42 extending along the second direction X is provided on the side of any row of first pixel electrodes 10 arranged along the second direction X, away from or near the display area 2. The second scan line 42 is connected to the first gate 13 of at least one second thin-film transistor 41 in an adjacent second pixel unit 40.

[0094] Understandably, when the first gate 13 is electrically connected to the adjacent first common electrode 12, the second scan line 42 is also electrically connected to the first common electrode 12. Either the first gate 13 can be directly connected to the first common electrode 12, or the second scan line 42 can be directly connected to the first common electrode 12.

[0095] It should be noted that the above description of the structure and arrangement of the second pixel unit 40 in the virtual pixel area 4 is only an exemplary illustration, and this application does not limit the arrangement of the second pixel unit 40.

[0096] In some embodiments, the non-display area 3 further includes a driving circuit area 5 located on the side of the virtual pixel area 4 away from the display area 2. The first data line 19 located in the virtual pixel area 4 and the second data line 38 located in the display area 2 both extend into the driving circuit area 5. The driving circuit area 5 is provided with a data signal pad corresponding only to the second data line 38, and the second data line 38 is electrically connected to the corresponding data signal pad to receive data signals.

[0097] In some embodiments, the array substrate 1 provided in this application can be applied to edge field switch (FFS) type and planar switching (IPS) type liquid crystal display panels, but is not limited thereto.

[0098] In this embodiment, the first pixel electrode 10 in the virtual pixel area 4 is located on the first metal layer 9 and is directly electrically connected to the first common electrode 12. This allows the first pixel electrode 10 and the first common electrode 12 to receive the same COM signal, thereby avoiding a voltage difference between them and preventing the liquid crystal in the virtual pixel area 4 from rotating erratically. This keeps the virtual pixel area 4 in a normally black state, which is beneficial for improving the display effect of the display panel. Furthermore, an insulating layer 20 is not required between the first metal layer 9 and the first transparent electrode layer 8, allowing the first pixel electrode 10 to directly contact and electrically connect with the adjacent first common electrode 12, avoiding the need for a via connection. This simplifies the manufacturing process, reduces manufacturing costs, and improves the stability of the electrical connection between the first pixel electrode 10 and the first common electrode 12. Therefore, the embodiments of this application can achieve electrical connection between the first pixel electrode 10 and the first common electrode 12 through a simpler film structure, a simpler process, and a lower cost, thereby making the virtual pixel area 4 in a normally black state, which can effectively improve the display effect of the display panel using the array substrate 1, especially beneficial to improving the display effect of FFS / IPS type liquid crystal display panels.

[0099] In addition, the first gate 13 in the virtual pixel area 4 can be connected to the adjacent first common electrode 12, making the first gate 13 electrically connected to the first common electrode 12. This allows the first gate 13 in the virtual pixel area 4 to also receive the COM signal, which helps to enhance the stability of the first common electrode 12, that is, enhance the stability of the COM signal on the array substrate 1, and thus improve the display effect of the display panel using the array substrate 1. Furthermore, the second scan line 42 in the virtual pixel area 4 can be electrically connected to the first common electrode 12, making the first data line 19 in the virtual pixel area 4 also receive the COM signal. This further enhances the stability of the first common electrode 12, that is, further enhances the stability of the COM signal on the array substrate 1, and thus further improves the display effect of the display panel using the array substrate 1.

[0100] like Figure 9 As shown, this application embodiment also provides a display panel 43, which includes an opposing substrate 44, a liquid crystal layer 45, and an array substrate 1 as described in the foregoing embodiments. The opposing substrate 44 is disposed opposite to the array substrate 1, and the liquid crystal layer 45 is sandwiched between the opposing substrate 44 and the array substrate 1.

[0101] In some embodiments, the display panel 43 includes either an edge field switch (FFS) type liquid crystal display panel 43 or an in-plane switching (IPS) type liquid crystal display panel 43, but is not limited thereto.

[0102] In this embodiment, the first pixel electrode 10 in the virtual pixel area 4 is directly electrically connected to the first common electrode 12, so that the virtual pixel area 4 is in a normally black state, which can effectively improve the display effect of the display panel 43, especially the display effect of the FFS / IPS type liquid crystal display panel 43. In addition, the first gate 13 in the virtual pixel area 4 can be connected to the adjacent first common electrode 12, so that the first gate 13 in the virtual pixel area 4 also receives the COM signal, which helps to enhance the stability of the first common electrode 12, that is, enhance the stability of the COM signal on the array substrate 1, and thus improve the display effect of the display panel 43. Furthermore, the second scan line 42 in the virtual pixel area 4 can be electrically connected to the first common electrode 12, so that the first data line 19 in the virtual pixel area 4 also receives the COM signal, which further enhances the stability of the first common electrode 12, that is, further enhances the stability of the COM signal on the array substrate 1, and thus further improves the display effect of the display panel 43.

[0103] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0104] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0105] The embodiments, implementation methods, and related technical features of this application can be combined and substituted for each other without conflict.

[0106] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.

Claims

1. An array substrate, characterized in that, The array substrate has a display area and a non-display area located around the display area, the non-display area including a virtual pixel area disposed adjacent to the display area; the array substrate includes: Substrate layer; The first transparent electrode layer includes at least one first pixel electrode located in the virtual pixel area and at least one second pixel electrode located in the display area; A first metal layer is located on the side of the first transparent electrode layer opposite to the substrate layer and is at least partially in contact with the first transparent electrode layer; the first metal layer includes a first common electrode located in the non-display area and the display area, the first common electrode being disposed close to the first pixel electrode and the second pixel electrode; Wherein, at least one side of the first pixel electrode extends to overlap with and at least partially contact the adjacent first common electrode, and either side of the second pixel electrode is spaced apart from the adjacent first common electrode. The first metal layer and the first transparent electrode layer are at least partially overlapped in a direction perpendicular to the substrate layer; the first metal layer further includes a first gate located in the virtual pixel area and a second gate located in the display area; the first transparent electrode layer further includes a first electrode block located between the first gate and the substrate layer and a second electrode block located between the second gate and the substrate layer; the first electrode block matches the shape and size of the first gate, and the second electrode block matches the shape and size of the second gate; In the display area, the first transparent electrode layer further includes a third electrode block located between the first common electrode and the substrate layer, the shape of the third electrode block matching the shape and size of the corresponding first common electrode.

2. The array substrate according to claim 1, characterized in that, The first pixel electrode extends to connect with the adjacent first electrode block.

3. The array substrate according to claim 1, characterized in that, The first gate is connected to the adjacent first common electrode.

4. The array substrate according to any one of claims 1 to 3, characterized in that, The array substrate further includes a second metal layer, which is located on the side of the first metal layer away from the substrate layer. The second metal layer includes a first data line located in the virtual pixel area, the first data line extending to overlap with and be electrically connected to the first common electrode.

5. The array substrate according to claim 4, characterized in that, The array substrate further includes an insulating layer located between the first metal layer and the second metal layer, and the first data line is electrically connected to the first common electrode located in the non-display area through a first via penetrating the insulating layer.

6. The array substrate according to any one of claims 1 to 3, characterized in that, The array substrate further includes: An insulating layer is located on the side of the first metal layer opposite to the substrate layer; An active layer is located on the side of the insulating layer opposite to the first metal layer; the active layer includes a first semiconductor pattern aligned with the first gate and a second semiconductor pattern aligned with the second gate; and The second metal layer is located on the side of the active layer away from the insulating layer; the second metal layer includes a first source electrically connected to the first semiconductor pattern, a first drain electrically insulated from the first semiconductor pattern, and a second source and a second drain electrically connected to the second semiconductor pattern.

7. The array substrate according to claim 6, characterized in that, The array substrate further includes: A passivation layer is located on the side of the second metal layer opposite to the active layer; and The second transparent electrode layer is located on the side of the passivation layer that is opposite to the second metal layer; The second transparent electrode layer includes a first connection electrode located in the virtual pixel area and a second connection electrode located in the display area; the first connection electrode is electrically connected to the first drain and the first pixel electrode through a second via penetrating the insulating layer and the passivation layer; the second connection electrode is electrically connected to the second drain and the second pixel electrode through a third via penetrating the insulating layer and the passivation layer.

8. The array substrate according to claim 7, characterized in that, The second transparent electrode layer also includes a second common electrode located around the first pixel electrode and the second pixel electrode, the second common electrode being overlapped with and electrically connected to the first common electrode.

9. A display panel, characterized in that, It includes a counter substrate, a liquid crystal layer, and an array substrate as described in any one of claims 1-8; the counter substrate and the array substrate are disposed opposite to each other, and the liquid crystal layer is sandwiched between the counter substrate and the array substrate.

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