A true random number generation circuit and chip

Abstract

The application relates to a true random number generation circuit and a chip, the true random number generation circuit comprising a clock signal generation module and a sampling module, an output end of the clock signal generation module being connected with an input end of the sampling module, the clock signal generation module being used for randomly switching input current or voltage of the clock signal generation module according to a random signal, thereby generating a jitter clock signal, the sampling module being used for sampling a target clock signal according to the jitter clock signal to generate a true random number, in the application, the switching action of switching the input current or voltage can introduce jitter, and the input current or voltage is randomly switched through the random signal, so that the input time of the input current or voltage is random, the jitter degree of the generated jitter clock signal can be effectively increased, the randomness of the generated true random number can be effectively enhanced, and the quality of the true random number can be effectively improved.

Description

Technical Field

[0001] This application relates to the field of electronic technology, and in particular to a true random number generation circuit and chip. Background Technology

[0002] In today's era of rapid information technology development, information security is receiving increasing attention from countries and industries. Information security is mostly based on keys and implemented through different encryption and decryption algorithms, while the generation of keys depends on random number generators.

[0003] Random number generation circuits are divided into true random number generation circuits and pseudo random number generation circuits. Generating random numbers based on the jitter of an oscillating ring is one of the common implementation methods of true random number generation circuits. It uses the small jitter of the clock signal as an entropy source. However, because the jitter of the clock signal is small, the randomness of the true random numbers is not strong, and the quality of the true random numbers is not good. Summary of the Invention

[0004] To address the aforementioned technical problems, the purpose of this application is to provide a true random number generation circuit and chip that can effectively increase the jitter level of the generated jitter clock signal, thereby effectively enhancing the randomness of the generated true random numbers and improving the quality of the true random numbers.

[0005] The technical solution provided in this application is as follows: A true random number generation circuit includes a clock signal generation module and a sampling module, wherein the output terminal of the clock signal generation module is connected to an input terminal of the sampling module; The clock signal generation module is used to randomly switch the input current or voltage of the clock signal generation module according to a random signal, thereby generating a jitter clock signal; The sampling module is used to sample the target clock signal based on the jittered clock signal to generate true random numbers.

[0006] Optionally, the control terminal of the clock signal generation module is connected to the output terminal of the sampling module, and the random signal is associated with the true random number.

[0007] Optionally, the clock signal generation module includes a dynamic matching module and an oscillation module; The output of the dynamic matching module is connected to one input of the oscillation module, and the output of the oscillation module is connected to one input of the sampling module. The dynamic matching module is used to randomly switch the input current or voltage according to the random signal and output a first jitter voltage. The oscillation module is used to generate the jitter clock signal based on the first jitter voltage.

[0008] Optionally, the clock signal generation circuit further includes a bias module, and each output terminal of the bias module is connected to the input terminal of the dynamic matching module; The bias module is used to output the input current or voltage.

[0009] Optionally, the oscillation module includes an oscillation unit and a first trigger; One input terminal of the oscillation unit is connected to the output terminal of the dynamic matching module, and the output terminal of the oscillation unit is connected to one input terminal of the first trigger. The oscillation unit is used to output a jitter signal according to the first jitter voltage; The first trigger is used to generate the jitter clock signal based on the jitter signal.

[0010] Optionally, the oscillation unit includes a comparator, a control unit, and a capacitor; The first terminal of the capacitor, the first terminal of the control unit, and the first input terminal of the comparator are connected, and the common terminal of the three connections is connected to the output terminal of the dynamic matching module. The output terminal of the comparator is connected to the second terminal of the control unit, and the common terminal of the two connections is connected to the first input terminal of the first trigger. The control unit is used to control the voltage at the first input terminal of the comparator to fluctuate within a preset voltage range after the capacitor has discharged.

[0011] Optionally, the control unit includes a first MOSFET; The first MOSFET is used to control the voltage at the first input terminal of the comparator to fluctuate within a preset voltage range after the capacitor has discharged; wherein the preset voltage value is greater than 0V.

[0012] Optionally, the sampling module includes a second flip-flop, the other input of which is used to input the target clock signal; The second trigger is used to sample the target clock signal based on the jittered clock signal to generate the true random number.

[0013] Optionally, the input current or voltage includes multiple values, and each two adjacent switching operations can yield a different value of the input current or voltage.

[0014] This application also provides a chip including the true random number generation circuit described in any of the above claims.

[0015] Compared with the prior art, this application provides a true random number generation circuit and chip. The true random number generation circuit includes a clock signal generation module and a sampling module. The output terminal of the clock signal generation module is connected to an input terminal of the sampling module. The clock signal generation module is used to randomly switch the input current or voltage of the clock signal generation module according to a random signal, thereby generating a jittered clock signal. The sampling module is used to sample the target clock signal according to the jittered clock signal to generate true random numbers. In this application, since the switching action of switching the input current or voltage will introduce jitter, and the input current or voltage is randomly switched by a random signal, the input current or voltage input time is random, which can effectively increase the jitter degree of the generated jittered clock signal, thereby effectively enhancing the randomness of the generated true random numbers and effectively improving the quality of the true random numbers. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a circuit diagram of a true random number generation circuit provided in an embodiment of this application; Figure 2 This is a circuit diagram of another true random number generation circuit provided in the embodiments of this application; Figure 3 This is a circuit diagram of yet another true random number generation circuit provided in the embodiments of this application; Figure 4 This is a circuit diagram of the dynamic matching module provided in the embodiments of this application; Figure reference numerals: 100 - Clock signal generation module; 200 - Sampling module; 110 - Dynamic matching module; 120 - Oscillation module; 130 - Bias module; 121 - Oscillator; CMP - Comparator; C - Capacitor; 1211 - Control Unit; FF1 - First Flip-Flop; 1212 - First inverter unit; INV1 - First inverter; 1213 - Second inverter unit; INV2 - Second inverter; INV3 - Third inverter; 1214 - Third inverter unit; INV4 - Fourth inverter; INV5 - Fifth inverter; MOS1 - First MOSFET; FF2 - Second flip-flop; 131 - Bias unit; MOS2 - Second MOS transistor; FF3 - Third flip-flop; MOS3 - Third MOS transistor; 111 - NOR gate. Detailed Implementation

[0018] To enable those skilled in the art to better understand the technical solutions in this application, the technical solutions in the embodiments of this application will be clearly and completely described below. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0019] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly set on the other component; when a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to the other component.

[0020] It should be understood that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0021] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "a plurality of" or "several" means two or more, unless otherwise explicitly specified.

[0022] It should be noted that the structures, proportions, sizes, etc., shown in the accompanying drawings of this specification are only for the purpose of assisting those skilled in the art in understanding and reading the content disclosed in the specification, and are not intended to limit the conditions under which this application can be implemented. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in the proportions, or adjustments to the size should still fall within the scope of the technical content disclosed in this application, provided that they do not affect the effects and purposes that this application can produce.

[0023] like Figure 1As shown, this application embodiment provides a true random number generation circuit, including a clock signal generation module 100 and a sampling module 200. The output terminal of the clock signal generation module 100 is connected to an input terminal of the sampling module 200. The clock signal generation module 100 is used to randomly switch the input current or voltage of the clock signal generation module 100 according to the random signal CLK_TRNG, thereby generating a jittered clock signal CLK_L. The sampling module 200 is used to sample the target clock signal CLK_H according to the jittered clock signal CLK_L to generate true random numbers.

[0024] In this embodiment, the random signal CLK_TRNG can be a signal associated with a true random number or an external random signal CLK_TRNG; another input terminal of the sampling module 200 is used to receive the target clock signal CLK_H, the jitter clock signal CLK_L can be a low-frequency clock signal or a high-frequency clock signal, preferably the jitter clock signal CLK_L is a low-frequency clock signal, and the target clock signal CLK_H can be a low-frequency clock signal or a high-frequency clock signal, preferably the target clock signal CLK_H is a high-frequency clock signal.

[0025] In this embodiment, the clock signal generation module 100 randomly switches its input current or input voltage using the received random signal CLK_TRNG, and generates a jittered clock signal CLK_L which is output to the sampling module 200. The sampling module 200 samples the received target clock signal CLK_H based on the received jittered clock signal CLK_L to generate a true random number. The random switching of the input current or input voltage using the random signal CLK_TRNG introduces jitter, and the random switching of the input current or input voltage using the random signal CLK_TRNG makes the input time of the input current or input voltage random. This effectively increases the jitter of the jittered clock signal CLK_L generated by randomly switching the input current or input voltage of the clock signal generation module 100 based on the random signal CLK_TRNG, thereby effectively enhancing the randomness of the true random number generated by sampling the target clock signal CLK_H based on the jittered clock signal CLK_L and effectively improving the quality of the true random number.

[0026] Compared with the prior art, this application provides a true random number generation circuit and chip. The true random number generation circuit includes a clock signal generation module 100 and a sampling module 200. The output terminal of the clock signal generation module 100 is connected to an input terminal of the sampling module 200. The clock signal generation module 100 is used to randomly switch the input current or voltage of the clock signal generation module 100 according to the random signal CLK_TRNG, thereby generating a jittered clock signal CLK_L. The sampling module 200 is used to sample the target clock signal CLK_H according to the jittered clock signal CLK_L to generate true random numbers. In this application, since the switching action of switching the input current or voltage will introduce jitter, and the random switching of the input current or voltage through the random signal CLK_TRNG makes the input time of the input current or voltage random, it can effectively increase the jitter degree of the generated jittered clock signal CLK_L, thereby effectively enhancing the randomness of the generated true random numbers and effectively improving the quality of the true random numbers.

[0027] like Figure 2 As shown, in one embodiment of this application, the control terminal of the clock signal generation module 100 is connected to the output terminal of the sampling module 200, and the random signal CLK_TRNG is associated with a true random number.

[0028] In this embodiment, the association of the random signal CLK_TRNG with the true random number can mean that the random signal CLK_TRNG is the true random number, or it can mean that the random signal CLK_TRNG is generated based on the true random number.

[0029] In this embodiment, the input terminal of the clock signal generation module 100 receives N sets of input current or input voltage, where N is a positive integer greater than 1. Specifically, the clock signal generation module 100 is used to switch the input current or input voltage according to the random signal CLK_TRNG received by the control terminal to generate a jitter clock signal CLK_L. By feeding back the random signal CLK_TRNG associated with the true random number to the control terminal of the clock signal generation module 100, and then switching the input current or input voltage according to the random signal CLK_TRNG received by the control terminal, the timing of each set of input current or input voltage input is random, which can effectively increase the jitter of the generated jitter clock signal CLK_L, thereby effectively enhancing the randomness of the generated true random number and effectively improving the quality of the true random number.

[0030] like Figure 2As shown, in one embodiment of this application, the clock signal generation module 100 includes a dynamic matching module 110 and an oscillation module 120; the output terminal of the dynamic matching module 110 is connected to an input terminal of the oscillation module 120, and the output terminal of the oscillation module 120 is connected to an input terminal of the sampling module 200; the dynamic matching module 110 is used to randomly switch the input current or voltage according to the random signal CLK_TRNG and output a first jitter voltage; the oscillation module 120 is used to generate a jitter clock signal CLK_L according to the first jitter voltage.

[0031] In this embodiment, the input terminal of the dynamic matching module serves as the input terminal of the clock signal generation module 100 and receives N sets of input currents or input voltages. The control terminal of the dynamic matching module 110 serves as the control terminal of the clock signal generation circuit and is connected to the output terminal of the sampling module 200. The output terminal of the oscillation module 120 serves as the output terminal of the clock signal generation module 100 and is connected to one input terminal of the sampling module 200.

[0032] In this embodiment, the switching action of switching the input current or input voltage itself increases the jitter of the output first jitter voltage. Furthermore, switching the input current or input voltage according to the random signal CLK_TRNG makes the input time of each group of input current or input voltage random, causing the voltage value of the output first jitter voltage to change randomly according to the random signal CLK_TRNG. Since the values ​​of each group in the N groups of input current or input voltage can be all the same, all different, or some values ​​can be the same while others are different, if the values ​​of each group in the N groups of input current or input voltage are all different, or some values ​​are the same while others are different, it will further increase the jitter of the output first jitter voltage, making the jitter degree of the first jitter voltage related to the input current or input voltage. The larger the jitter of the first jitter voltage, the larger the jitter of the jitter clock signal CLK_L generated based on the first jitter voltage. The jitter degree of the jitter clock signal CLK_L is positively correlated with the jitter degree of the first jitter voltage.

[0033] In this embodiment, the dynamic matching module 110 randomly switches the input current or input voltage according to the random signal CLK_TRNG and outputs a first jitter voltage, which can effectively increase the jitter of the first jitter voltage. Furthermore, the dynamic matching module is provided with N input terminals for receiving N sets of current or voltage. Each current or voltage is input to the corresponding input terminal of the dynamic matching module through a corresponding switch. The input terminals of the dynamic matching module are connected one-to-one with the output terminals of the switch. The switch is turned on or off according to the control signal received at its control terminal to control the switching output of the corresponding current or voltage. The control signal includes a random signal. When the control signal is a random signal, the current or voltage received by the input terminal of the dynamic matching module is random each time, and the time of receiving the current or voltage is random. The control signal includes a cyclic control signal. When the control signal is a cyclic control signal, N sets of current or voltage are sequentially input to the corresponding input terminal of the dynamic matching module in a preset order. Each time, at least one set of current or voltage is input to the corresponding input terminal of the dynamic matching module. In this way, the switching transistor is turned on or off according to the control signal to control the switching of the corresponding input current, thereby increasing the jitter of the first jitter voltage output by the dynamic matching module. Since the oscillation module 120 can enhance the signal jitter, it can further increase the jitter of the jitter clock signal CLK_L generated based on the first jitter voltage, thereby further enhancing the randomness of the true random number generated by sampling the target clock signal CLK_H based on the jitter clock signal CLK_L, and further improving the quality of the true random number.

[0034] like Figure 2 As shown, in one embodiment of this application, the clock signal generation circuit further includes a bias module 130, and each output terminal of the bias module 130 is connected to the input terminal of the dynamic matching module 110; the bias module 130 is used to output input current or voltage.

[0035] In this embodiment, the input terminal of the bias module is connected to the power supply VDD, and the bias module is provided with N output terminals. The dynamic matching module is provided with N input terminals. Each output terminal of the bias module 130 is connected to each input terminal of the dynamic matching module 110 in a one-to-one correspondence. The bias module 130 is used to output M sets of different values ​​of input current or input voltage; where M is a natural number not greater than N.

[0036] In this embodiment, the dynamic matching module 110 is specifically used to, when the true random number received by the control terminal is not less than a preset value, sequentially switch the input current or input voltage according to a preset order, and output a first jitter voltage based on the input current or input voltage. The jitter degree of the first jitter voltage is positively correlated with the number of groups of input currents or input voltages with different current or voltage values. The preset value is a pre-set value, and the preset order is a pre-set sequence. The more groups of input currents or input voltages with different current or voltage values, the greater the jitter degree of the first jitter voltage. This allows each... The input current value or input voltage value of the group are set to be different to enhance the jitter of the first jitter voltage. Since the random signal CLK_TRNG received by the control terminal is not less than (i.e. greater than or equal to) a preset value for a random time, the jitter of the first jitter voltage output by the dynamic matching module 110 can be further enhanced. The dynamic matching module can also be used to connect the bias current output by the first bias unit when the random signal received by the control terminal flips to an effective level for the first time, and to switch to the bias current output by the next bias control unit when the random signal flips to an effective level for the second time.

[0037] like Figure 2 As shown, in one embodiment of this application, the oscillation module 120 includes an oscillation unit 121 and a first flip-flop FF1; one input terminal of the oscillation unit 121 is connected to the output terminal of the dynamic matching module 110, and the output terminal of the oscillation unit 121 is connected to one input terminal of the first flip-flop FF1; the oscillation unit 121 is used to output a jitter signal according to the first jitter voltage; the first flip-flop FF1 is used to generate a jitter clock signal CLK_L according to the jitter signal.

[0038] In this embodiment, the first flip-flop FF1 can be a D flip-flop. The output terminal of the first flip-flop FF1 is connected to an input terminal of the sampling module 200 as the output terminal of the clock signal generation circuit. The inverted output terminal of the first flip-flop FF1 is connected to an input terminal. Since the oscillation unit 121 can enhance signal jitter, it can increase the jitter of the jitter signal output according to the first jitter voltage, thereby increasing the jitter of the jitter clock signal CLK_L generated according to the jitter signal. This can further enhance the randomness of the true random number generated by sampling the target clock signal CLK_H based on the jitter clock signal CLK_L, and further improve the quality of the true random number.

[0039] like Figure 2As shown, in one embodiment of this application, the oscillation unit 121 includes a comparator CMP, a control unit 1211, and a capacitor C; the first terminal of the capacitor C, the first terminal of the control unit 1211, and the first input terminal of the comparator CMP are connected, and the common terminal of the three connections is connected to the output terminal of the dynamic matching module 110; the output terminal of the comparator CMP is connected to the second terminal of the control unit 1211, and the common terminal of the two connections is connected to an input terminal of the first trigger FF1; the control unit 1211 is used to control the voltage VFB of the first input terminal of the comparator CMP to jitter within a preset voltage value range after the capacitor C has discharged.

[0040] In this embodiment, the output terminal of comparator CMP is connected to the second terminal of control unit 1211, and the common terminal of the two connections is connected to one input terminal of the first flip-flop FF1 as the output terminal of oscillation unit 121. The second terminal of capacitor C is connected to the third terminal of control unit 1211, and the common terminal of the two connections is grounded. The preset voltage value range can be a pre-set voltage value range. The other input terminal of comparator CMP is used to input the reference voltage Vref. The output terminal of dynamic matching module 110 outputs a first jitter voltage to the common terminal of the first terminal of capacitor C, the first terminal of control unit 1211, and the first input terminal of comparator CMP. When the voltage VFB at the first input terminal of comparator CMP is greater than or less than the reference voltage Vref, the output signal of comparator CMP flips, causing control unit 1211 to be turned on or off. The discharge or charging of capacitor C and the operating state of capacitor C and control unit 1211 change with the jitter of the first jitter voltage. Since the jitter of the first jitter voltage is random, the oscillation loop formed by comparator CMP, control unit 1211 and capacitor C cannot reach balance and is always in the process of seeking balance. This can effectively increase the jitter of the jitter signal output from the common terminal of the output of comparator CMP and the second terminal of control unit 1211. After capacitor C is discharged, the voltage VFB at the first input terminal of comparator CMP is controlled by control unit 1211 to jitter within a preset voltage range. Since VFB jitters within the preset voltage range, the charging and discharging time of capacitor C changes each time, which can further increase the jitter of the jitter signal output from the common terminal of the output of comparator CMP and the second terminal of control unit 1211.

[0041] like Figure 3 As shown, in one embodiment of this application, the control unit 1211 includes a first MOS transistor MOS1; the first MOS transistor MOS1 is used to control the voltage VFB at the first input terminal of the comparator CMP to jitter within a preset voltage value range after the capacitor C has discharged; wherein, the preset voltage value is greater than 0V.

[0042] In this embodiment, the preset voltage value can be 50mV. By setting the on-resistance of the first MOS transistor MOS1 to the preset impedance value, the voltage VFB at the first input terminal of the comparator CMP will fluctuate within the preset voltage range (or near the preset voltage value) corresponding to the preset impedance value after the capacitor C has discharged. Since the preset voltage value still has room to decrease, the lower limit of the voltage VFB at the first input terminal of the comparator CMP is a floating value, so that the charging and discharging time of the capacitor C changes each time, which can further increase the jitter of the jitter signal output from the common terminal of the output terminal of the comparator CMP and the second terminal of the first MOS transistor MOS1.

[0043] like Figure 3 As shown, in this embodiment, the first MOS transistor MOS1 is an NMOS transistor. The oscillation unit 121 also includes a first inverting unit 1212. One input terminal of the comparator CMP is an inverting input terminal, and the other input terminal of the comparator CMP is a non-inverting input terminal. The output terminal of the comparator CMP is connected to the input terminal of the first inverting unit 1212, and the common terminal of the two connections is connected as the output terminal of the oscillation unit 121 and connected to one input terminal of the first flip-flop FF1. The output terminal of the first inverting unit 1212 is connected to the control terminal of the first MOS transistor MOS1. When the reference voltage Vref is just input to the second input terminal of the comparator CMP, the voltage VFB at the first input terminal of the comparator CMP is 0. The dynamic matching module 110 outputs the first jitter voltage to the first terminal of the capacitor C to charge the capacitor C, so that the comparator C... When the voltage VFB at the first input terminal of the comparator CMP rises, and the voltage VFB at the first input terminal of the comparator CMP is greater than the reference voltage Vref, the output signal at the output terminal of the comparator CMP flips (from 1 to 0). After the output signal is inverted by the first inverting unit 1212, the first MOSFET MOS1 is turned on, the capacitor C is discharged, and the voltage at the first input terminal drops. When the voltage at the first input terminal is less than the reference voltage Vref, the output signal at the output terminal of the comparator CMP flips again (from 0 to 1). After the output signal is inverted by the first inverting unit 1212, the first MOSFET MOS1 is turned off, and the capacitor C is charged. The operating states of the capacitor C and the first MOSFET MOS1 will change with the jitter of the first jitter voltage. Specifically, the first inverting unit 1212 includes the first inverter INV1.

[0044] like Figure 3As shown, in this embodiment, the oscillation unit 121 further includes a second inverting unit 1213. The output terminal of the comparator CMP is connected to the input terminal of the second inverting unit 1213, and the output terminal of the second inverting unit 1213 is connected to the input terminal of the first inverting unit 1212. The common terminal connecting the two is used as the output terminal of the oscillation unit 121 and connected to one input terminal of the first flip-flop FF1. The output terminal of the first inverting unit 1212 is connected to the control terminal of the first MOS transistor MOS1. The second inverting unit 1213 is used to shape the waveform of the output signal output by the comparator CMP, improve the waveform quality, and enhance the driving force of the output signal, so that the output signal... It can effectively transmit to the first flip-flop FF1 and the first inverter unit 1212. Specifically, the second inverter unit 1213 includes a second inverter INV2 and a third inverter INV3. The output terminal of the comparator CMP is connected to the input terminal of the second inverter INV2, the output terminal of the second inverter INV2 is connected to the input terminal of the third inverter INV3, the output terminal of the third inverter INV3 is connected to the input terminal of the first inverter INV1, and the common terminal of the two connections is connected as the output terminal of the oscillation unit 121 and connected to one input terminal of the first flip-flop FF1. The output terminal of the first inverter INV1 is connected to the control terminal of the first MOS transistor MOS1.

[0045] like Figure 3 As shown, in this embodiment, the oscillation unit 121 further includes a third inverter unit 1214. The output terminal of the first inverter INV1 is connected to the input terminal of the third inverter unit 1214, and the output terminal of the third inverter unit 1214 is connected to the control terminal of the first MOS transistor MOS1. The third inverter unit 1214 is used to shape the waveform of the signal output by the first inverter INV1, improve the waveform quality, and enhance the driving force of the signal so that the signal can be effectively transmitted to the first MOS transistor MOS1. Specifically, the third inverter unit 1214 includes a fourth inverter INV4 and a fifth inverter INV5. The output terminal of the first inverter INV1 is connected to the input terminal of the fourth inverter INV4, the output terminal of the fourth inverter INV4 is connected to the input terminal of the fifth inverter INV5, and the output terminal of the fifth inverter INV5 is connected to the control terminal of the first MOS transistor MOS1.

[0046] like Figure 3 As shown, in one embodiment of this application, the sampling module 200 includes a second flip-flop FF2, the other input of which is used to input the target clock signal CLK_H; the second flip-flop FF2 is used to sample the target clock signal CLK_H according to the jitter clock signal CLK_L to generate a true random number.

[0047] In this embodiment, the second flip-flop FF2 can be a D flip-flop. The data output terminal of the first flip-flop FF1 is connected to one input terminal of the second flip-flop FF2 as the output terminal of the clock signal generation circuit. One input terminal of the second flip-flop FF2 can be the clock input terminal of the second flip-flop FF2, and the other input terminal of the second flip-flop FF2 can be the data input terminal of the second flip-flop FF2. Specifically, the second flip-flop FF2 is used to sample the target clock signal CLK_H input from the data input terminal based on the jittered clock signal CLK_L input from the clock input terminal to generate a true random number and output it.

[0048] In one implementation method, the input current or voltage in this application embodiment includes multiple values, and different values ​​of input current or voltage can be obtained for each two adjacent switching operations.

[0049] like Figure 3 As shown, in this embodiment, the bias module 130 includes N bias units 131, each of which... The input terminal of bias unit 131 is connected to power supply VDD. The output terminal of each bias unit 131 is connected one-to-one with the input terminal of dynamic matching module 110. There can be N bias units 131 mirror images of each other, with different aspect ratios, resulting in different values ​​for the input current or voltage output by each bias unit 131. Alternatively, the input terminals of each bias unit 131 can be connected to different power supplies VDD with different values, also resulting in different values ​​for the input current or voltage output by each bias unit 131. Preferably, there are N bias units 131 mirror images of each other with different aspect ratios. Specifically, when the random signal CLK_TRNG received by the control terminal first flips to an effective level, the dynamic matching module 110 connects to the corresponding input current or voltage output by the first bias unit 131. When the random signal CLK_TRNG flips to an active level for the second time, the system switches to the next bias unit 131 to output the corresponding input current or input voltage. The preset order can be from left to right or from right to left, and the active level can be high. Since the N bias units 131 are mirror images of each other and the aspect ratio of each bias unit 131 is different, the values ​​of the input current or input voltage output to the dynamic matching module 110 by each bias unit 131 are different. This allows the dynamic matching module 110 to obtain different values ​​of input current or input voltage in each two adjacent switching operations, which can effectively enhance the jitter of the first jitter voltage output by the dynamic matching module 110. Since the time when the random signal CLK_TRNG flips to an active level is random, the jitter of the first jitter voltage output by the dynamic matching module 110 can be further enhanced.

[0050] In this embodiment, the bias unit 131 includes a second MOS transistor MOS2. MOS transistor is short for Metal-Oxide-Semiconductor Field-Effect Transistor. The second MOS transistor MOS2 can be a PMOS transistor. N second MOS transistors MOS2 are mirror images of each other, and each second MOS transistor MOS2 has a different width-to-length ratio. By making the N second MOS transistors MOS2 mirror images of each other and each second MOS transistor MOS2 has a different width-to-length ratio, the N second MOS transistors MOS2 are mismatched, which makes the input current or input voltage output by each second MOS transistor MOS2 different. In actual layout (i.e., printed circuit board layout and wiring), the mismatch of the N second MOS transistors MOS2 can be achieved by making the N second MOS transistors MOS2 mirror images of each other, each second MOS transistor MOS2 has a different width-to-length ratio, and each second MOS transistor MOS2 is asymmetrical in position.

[0051] like Figure 3 and Figure 4As shown in the embodiment of this application, the dynamic matching module 110 may include N third flip-flops FF3, N third MOS transistors MOS3, and NOR gates 111. The third MOS transistors MOS3 can be NMOS transistors, and the third flip-flops FF3 can be D flip-flops. The number of third flip-flops FF3 and third MOS transistors MOS3 is the same as the number of second MOS transistors MOS2. The clock input terminal of each third flip-flop FF3 is connected to the output terminal of the sampling module 200 as the control terminal of the dynamic matching module 110, and is used to input a random signal CLK_TRNG. The data output terminal of the first third flip-flop FF3 is connected to the data input terminal of the next third flip-flop FF3 and the control terminal of the first third MOS transistor MOS3. The data output of a third flip-flop FF3 is connected to the data input of the next third flip-flop FF3 or the control terminal of the next third MOS transistor MOS3. The inputs of each third MOS transistor MOS3 are connected one-to-one with the outputs of each second MOS transistor MOS2. The outputs of each third MOS transistor MOS3 are connected to the input of NOR gate 111, and the output of NOR gate 111 is connected to the data input of the first third flip-flop FF3. Since the initial level of the outputs of each third MOS transistor MOS3 is low, a high level is output through NOR gate 111, and the value of the data input of the first third flip-flop FF3 is 1. When the random signal CLK_TRN is output from the sampling module 200... When the first high level appears at G, the first third flip-flop FF3 is triggered to output the value 1 at its data input terminal, causing the first third MOSFET MOS3 to conduct. The remaining third MOSFETs MOS3 are in the off state, causing the output terminal of the first second MOSFET MOS2 to output input current or voltage to the first third MOSFET MOS3. When the random signal CLK_TRNG output from the sampling module 200 reaches the next high level, the data output terminal of the first third flip-flop FF3 is triggered to output 0, causing the first third MOSFET MOS3 to turn off. This triggers the data output terminal of the next third flip-flop FF3 to output 1, causing the next third MOSFET MOS3 to conduct, and the next second MOSFET MOS2 to conduct. The output of OS2 sends an input current or voltage to the next third MOSFET, MOS3. After the output of the last second MOSFET, MOS2, sends an input current or voltage to the last third MOSFET, MOS3, when the random signal CLK_TRNG output by the sampling module 200 reaches a high level, the data output of the last third flip-flop, FF3, is triggered to output 0, causing the last third MOSFET, MOS3, to turn off. This triggers the data output of the first third flip-flop, FF3, to output 1, causing the first third MOSFET, MOS3, to turn on. This allows the input current or voltage from the output of the first second MOSFET, MOS2, to be sent to the first third MOSFET, MOS3.This process repeats until the true random number generation circuit stops working. Because the switching action of changing the input current or input voltage outputs of the two adjacent second MOSFETs MOS2 increases the jitter of the first jitter voltage output by the dynamic matching module 110, and because the high level of the random signal CLK_TRNG is random for a certain period, it further enhances the jitter of the first jitter voltage output by the dynamic matching module 110.

[0052] For example, the second MOSFET MOS2 is a PMOS transistor, the third MOSFET MOS3 is an NMOS transistor, and the third flip-flop FF3 is a D flip-flop with N=4. Since the initial output level of each of the third MOSFETs MOS3 is low, a high level is output through a NOR gate 111. The data input value of the first third flip-flop FF3 is 1. When the random signal CLK_TRNG reaches its first high level, it triggers the first third flip-flop FF3 to output the value 1, turning on the first third MOSFET MOS3. All other third MOSFETs MOS3 are in the off state, causing the output of the first second MOSFET MOS2 to output an input current or voltage to the first third MOSFET MOS3. When the random signal CLK_TRNG reaches its second high level, it triggers the data output of the second third flip-flop FF3 to output 1, turning on the second third MOSFET MOS3. This triggers the data outputs of the other third flip-flops FF3 to output 0, turning off the other third MOSFETs MOS3. The output of the second second MOSFET MOS2 then outputs an input current or voltage to the second third MOSFET MOS3. When the random signal CLK_TRNG reaches its third high level... The third flip-flop FF3 is triggered to output 1, and the second flip-flop FF3 and other flip-flops are triggered to output 0, causing all MOS3 transistors except the third MOS3 to be turned off, turning on the third MOS3, and causing the output of the third second MOS2 to output input current or voltage to the third MOS3. When the random signal CLK_TRNG reaches a fourth high level, the fourth flip-flop FF3 is triggered to output 1, and the other flip-flops FF3 are triggered to output 0, turning on the fourth MOS3, and causing the output of the fourth second MOS2 to output input current or voltage to the fourth MOS3. When the random signal CLK_TRNG reaches a fifth high level, the first flip-flop FF3 is triggered to output 1, and the other flip-flops FF3 are triggered to output 0, turning on the first MOS3, and causing the output of the first second MOS2 to output input current or voltage to the first third MOS3. This cycle repeats until the true random number generation circuit stops working.

[0053] This application also provides a chip including any of the above-mentioned true random number generation circuits.

[0054] The embodiments in this specification are described in a progressive manner, with each embodiment focusing on the related aspects. For any differences between the embodiments, or for the same or similar parts between the embodiments, please refer to each other.

[0055] The above description of the disclosed embodiments enables those skilled in the art to make or use this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A true random number generation circuit, characterized in that, It includes a clock signal generation module and a sampling module, wherein the output terminal of the clock signal generation module is connected to an input terminal of the sampling module; The clock signal generation module is used to randomly switch the input current or voltage of the clock signal generation module according to a random signal, thereby generating a jitter clock signal; The sampling module is used to sample the target clock signal based on the jittered clock signal to generate true random numbers; The clock signal generation module includes a dynamic matching module and an oscillation module; The output of the dynamic matching module is connected to one input of the oscillation module, and the output of the oscillation module is connected to one input of the sampling module. The dynamic matching module is equipped with N input terminals to receive N sets of input current or N sets of input voltage, where N is a positive integer greater than 1. The dynamic matching module is used to randomly switch the input current or input voltage according to the random signal, so that the input time of each group of input current or input voltage is random, and output a first jitter voltage according to the input current or input voltage, wherein the jitter degree of the first jitter voltage is positively correlated with the number of groups of input currents with different current values ​​or the number of groups of input voltages with different voltage values; The oscillation module is used to generate the jitter clock signal based on the first jitter voltage.

2. The true random number generation circuit according to claim 1, characterized in that, The control terminal of the clock signal generation module is connected to the output terminal of the sampling module, and the random signal is associated with the true random number.

3. The true random number generation circuit according to claim 1, characterized in that, The clock signal generation circuit also includes a bias module, and each output terminal of the bias module is connected to the input terminal of the dynamic matching module. The bias module is used to output the input current or voltage.

4. The true random number generation circuit according to claim 1, characterized in that, The oscillation module includes an oscillation unit and a first trigger; One input terminal of the oscillation unit is connected to the output terminal of the dynamic matching module, and the output terminal of the oscillation unit is connected to one input terminal of the first trigger. The oscillation unit is used to output a jitter signal according to the first jitter voltage; The first trigger is used to generate the jitter clock signal based on the jitter signal.

5. The true random number generation circuit according to claim 4, characterized in that, The oscillation unit includes a comparator, a control unit, and a capacitor; The first terminal of the capacitor, the first terminal of the control unit, and the first input terminal of the comparator are connected, and the common terminal of the three connections is connected to the output terminal of the dynamic matching module; the second input terminal of the comparator is used to input a reference voltage; the second terminal of the capacitor and the third terminal of the control unit are connected, and the common terminal of the two connections is grounded; the output terminal of the comparator is connected to the second terminal of the control unit, and the common terminal of the two connections is connected to the first input terminal of the first trigger. The control unit is used to control the voltage at the first input terminal of the comparator to fluctuate within a preset voltage range after the capacitor has discharged.

6. The true random number generation circuit according to claim 5, characterized in that, The control unit includes a first MOSFET; The first MOSFET is used to control the voltage at the first input terminal of the comparator to fluctuate within a preset voltage range after the capacitor has discharged; wherein the preset voltage value is greater than 0V.

7. The true random number generation circuit according to claim 1, characterized in that, The sampling module includes a second flip-flop, and the other input terminal of the second flip-flop is used to input the target clock signal; The second trigger is used to sample the target clock signal based on the jittered clock signal to generate the true random number.

8. The true random number generation circuit according to any one of claims 1-7, characterized in that, The input current or voltage includes multiple values, and each two adjacent switching operations can produce different values ​​of the input current or voltage.

9. A chip, characterized in that, Includes the true random number generation circuit as described in any one of claims 1 to 8.

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