A uhd liquid crystal driving method based on fhd chip

Abstract

The application belongs to the technical field of liquid crystal screens, and provides a UHD liquid crystal driving method based on an FHD chip, which comprises the following steps: performing GOA double-line scanning control, wherein the GOA double-line scanning control comprises the following steps: outputting the same pulse to adjacent gate driving clock signals on a liquid crystal display screen to simultaneously open two adjacent gate lines, so that the number of scanned lines of each frame is reduced from 2160 lines to 1080 lines; performing MINI-LVDS data channel parallel transmission, wherein the MINI-LVDS data channel parallel transmission comprises the following steps: dividing the MINI-LVDS video data output channel of the FHD chip into two groups and connecting them in parallel, so that the effective pixel data bit width transmitted in each clock cycle is reduced by half, and the horizontal resolution is compressed from 3840 pixels to 1920 pixels; and the application can realize high-resolution liquid crystal driving by using a low-specification chip.

Description

Technical Field

[0001] This invention relates to the field of liquid crystal display technology, and in particular to a UHD liquid crystal driving method based on an FHD chip. Background Technology

[0002] In existing LCD technology, driving 4K UHD (3840×2160) LCD panels typically employs a matching 4K motherboard and a 4K TCON (timing control) board. While this approach offers excellent display quality, the high specifications of the components used result in a high overall cost. Alternatively, conversion chips can be used to convert signals of different formats or resolutions into 4K signals to drive the LCD screen. However, this approach requires additional chips and circuit resources, increasing both BOM costs and PCB design complexity, which is detrimental to system integration.

[0003] Another approach uses specific 2K chips and special encoding methods to drive 4K panels, but this approach is highly dependent on the chip model and encoding logic, has poor versatility, and is not suitable for large-scale applications. Therefore, how to achieve high-resolution LCD driving using low-specification chips while reducing system cost and design complexity has become a pressing technical problem in this field. Summary of the Invention

[0004] In view of the above technical problems, the present invention provides a UHD liquid crystal driving method based on an FHD chip to achieve high-resolution liquid crystal driving with a low-specification chip.

[0005] Other features and advantages of this disclosure will become apparent from the following detailed description, or may be learned in part from practice of this disclosure.

[0006] This invention discloses a UHD liquid crystal driving method based on an FHD chip, the method comprising: The GOA dual-line scan control includes: outputting the same pulse to the adjacent gate drive clock signals on the liquid crystal display screen to simultaneously turn on two adjacent gate lines, thereby halving the number of lines scanned per frame from 2160 lines to 1080 lines. Parallel transmission of MINI-LVDS data channels is performed, which includes: dividing the MINI-LVDS video data output channels of the FHD chip into two groups and connecting them in parallel, thereby halving the effective pixel data bit width transmitted in each clock cycle and compressing the horizontal resolution from 3840 pixels to 1920 pixels.

[0007] Furthermore, in the GOA dual-line scan control, the pulse waveforms of the two adjacent gate drive clock signals output by the FHD chip are the same, so as to simultaneously select two adjacent rows of pixels of the liquid crystal display.

[0008] Furthermore, in the parallel transmission of the MINI-LVDS data channels, the MINI-LVDS data output channels of the FHD chip are divided into a first group and a second group, and the corresponding channels in the first group and the second group are connected in parallel.

[0009] Furthermore, by setting the output mode of the gate level conversion chip from a single-line output mode to a dual-line output mode, the GOA dual-line scan control is achieved, so that each gate drive pulse acts simultaneously on two adjacent gate lines.

[0010] Furthermore, the FHD chip is a KV1626 chip, and the LCD screen is a JR425R3HC0K LCD screen.

[0011] Furthermore, by using dual-line scanning and parallel transmission of MINI-LVDS channels, the 2×2 physical pixels formed by every two adjacent rows and two columns on the liquid crystal display screen receive the same image data, thereby jointly displaying the same pixel content in a frame of image.

[0012] The technical solution disclosed herein has the following beneficial effects: This invention utilizes the characteristic of liquid crystals opening line by line to output the same pulse for adjacent clock signals. At this time, the opening is changed from line by line to two lines opening simultaneously, and the vertical data volume is halved, reducing the rate required for differential. By using the MINI-LVDS encoding format, the required differential pin resources are reduced through differential parallel connection, so that a 1080p TCON board and motherboard can be used to light up the UHD liquid crystal screen, which significantly reduces material costs and design difficulty, and improves economy. Attached Figure Description

[0013] Figure 1 This is a flowchart of the UHD liquid crystal driving method based on an FHD chip in the embodiments of this specification; Figure 2 This is the basic equivalent circuit of the TFT-LCD in the embodiments of this specification; Figure 3 This is a schematic diagram of the MINI-LVDS video signal output format in the embodiments of this specification; Figure 4 This is a schematic diagram of the GOA control timing in the embodiments of this specification; Figure 5 This is a schematic diagram of pixel four-point combination in the embodiments of this specification; Figure 6This is a schematic diagram of the KV1626 TX output signal in the embodiments of this specification; Figure 7 This is a schematic diagram of the COF port wiring method in the embodiments of this specification. Detailed Implementation

[0014] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided to make this disclosure more comprehensive and complete, and to fully convey the concept of the exemplary embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a full understanding of embodiments of this disclosure. However, those skilled in the art will recognize that the technical solutions of this disclosure may be practiced with one or more of the specific details omitted, or other methods, components, apparatus, steps, etc., may be employed. In other instances, well-known technical solutions are not shown or described in detail to avoid obscuring various aspects of this disclosure.

[0015] like Figure 1 As shown in the embodiments of this specification, a UHD liquid crystal driving method based on an FHD chip is provided. The method specifically includes steps S101-102: In step S101, GOA dual-line scan control is performed. The GOA dual-line scan control includes: outputting the same pulse to the adjacent gate drive clock signals on the liquid crystal display screen to simultaneously turn on two adjacent gate lines, thereby halving the number of lines scanned per frame from 2160 lines to 1080 lines. In step S102, parallel transmission of MINI-LVDS data channels is performed. The parallel transmission of MINI-LVDS data channels includes: dividing the MINI-LVDS video data output channels of the FHD chip into two groups and connecting them in parallel, so that the effective pixel data bit width transmitted in each clock cycle is halved, and the horizontal resolution is compressed from 3840 pixels to 1920 pixels.

[0016] In the GOA dual-line scan control, the FHD chip outputs two adjacent gate drive clock signals with identical pulse waveforms to simultaneously select two adjacent rows of pixels on the liquid crystal display. In the parallel transmission of the MINI-LVDS data channel, the MINI-LVDS data output channel of the FHD chip is divided into a first group and a second group, and the corresponding channels in the first and second groups are connected in parallel. The GOA dual-line scan control is achieved by setting the output mode of the gate level converter chip from single-line output mode to dual-line output mode, ensuring that each gate drive pulse simultaneously acts on two adjacent gate lines. Through dual-line scanning and parallel transmission of the MINI-LVDS channel, every 2×2 physical pixels (2 rows and 2 columns) on the liquid crystal display receive the same image data, thus collectively displaying the same pixel content in a single frame of image.

[0017] As an explanation, such as Figure 2 As shown, in LCD imaging, the Gate Driver scans and activates the Gate line line by line according to the timing signal. At the same time, the Source Driver converts the data signal transmitted by miniLVDS into the voltage amplitude of the corresponding Source line. By adjusting the deflection angle of the liquid crystal cell, the transmittance is controlled. Combined with the color ratio of the R / G / B sub-pixels, the target color is finally synthesized.

[0018] like Figure 3 As shown, data channels 0-2 transmit the 24-bit data of the first pixel (8 bits each for R / G / B), while channels 3-5 transmit the 24-bit data of the second pixel in parallel, realizing the transmission of 12 bits of valid data per clock cycle, and finally completing the 48-bit / 4-cycle pixel data transmission.

[0019] like Figure 4-5 As shown, Figure 4 In the zSigal-gate GOA control timing, the start signal ST emits a pulse to start the row scanning of 1 Frame. When the first pulse of HC(N) rises, the G(N) row pixels of the display panel are selected. At this time, the first row data signal Source Driver can write. When the second pulse of HC(N) rises, the G(N+HC number) row pixels of the panel are selected. At this time, the second row data signal Source Driver writes. The data is written sequentially until the G(2160) data is completed, thus completing the display of 1 Frame.

[0020] The UHD 4K Sigal-gate TFT LCD screen consists of 3840×2160 pixels. When the FHD chip implements the technical control method, when the first pulse rises, the row pixels of the display panel are selected. At the same time, the Source Driver converts the data signal transmitted by miniLVDS into the voltage amplitude of the corresponding Source line and writes it. By adjusting the deflection angle of the liquid crystal unit, the transmittance is controlled and the target color is synthesized by combining the color ratio of R / G / B sub-pixels. This process is executed sequentially until 2160 rows of data are written and one frame is displayed. At this point, the adjacent CK outputs the same pulse, changing from sequential activation to simultaneous activation of two lines, halving the vertical data volume (2160 / 2=1080), and reducing the rate required for differential input. Then, data channels 0-2 and 3-5 are connected in parallel differentially to enable the Three Pairs MINI-LVDS TCON to drive the Six Pairs MINI-LVDS SDIC, halving the differential bit width (3840 / 2=1920), thus reducing the required differential pin resources. Finally, a 1080p TCON board and motherboard (low frequency / few pins / small chip) can be used to light up a UHD LCD screen, significantly reducing system cost and design complexity.

[0021] In one implementation, as an exemplary case, such as Figure 6-7 As shown, using the TCON chip KV1626, in conjunction with an LCD screen of model JR425R3HC0K, data channels 0-2 and 3-5 are connected to realize the Three Pairs MINI-LVDS STCON driving the Six Pairs MINI-LVDS SDIC. The Level Shifter chip is set from 1-Line to 2-Line, and the adjacent CK outputs the same pulse, which changes from turning on line by line to turning on two lines simultaneously. Finally, the FHD chip of model KV1626 is used to light up the 4K UHD screen.

[0022] In summary, this invention utilizes the characteristic of liquid crystals opening line by line to output the same pulse for adjacent clock signals. At this time, the opening is changed from line by line to two lines opening simultaneously, and the vertical data volume is halved, reducing the rate required for differential switching. By using the MINI-LVDS encoding format, the required differential pin resources are reduced through differential parallel connection, thereby using a 1080p TCON board and motherboard to light up the UHD liquid crystal screen, which significantly reduces material costs and design difficulty, and improves economy.

[0023] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and embodiments are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the claims.

Claims

1. A UHD liquid crystal driving method based on an FHD chip, characterized in that, The method includes: The GOA dual-line scan control includes: outputting the same pulse to the adjacent gate drive clock signals on the liquid crystal display screen to simultaneously turn on two adjacent gate lines, thereby halving the number of lines scanned per frame from 2160 lines to 1080 lines. Parallel transmission of MINI-LVDS data channels is performed, which includes: dividing the MINI-LVDS video data output channels of the FHD chip into two groups and connecting them in parallel, thereby halving the effective pixel data bit width transmitted in each clock cycle and compressing the horizontal resolution from 3840 pixels to 1920 pixels. In the GOA dual-line scan control, the pulse waveforms of the two adjacent gate drive clock signals output by the FHD chip are the same, so as to simultaneously select two adjacent rows of pixels of the liquid crystal display screen; in the parallel transmission of the MINI-LVDS data channel, the MINI-LVDS data output channel of the FHD chip is divided into a first group and a second group, and the corresponding channels in the first group and the second group are connected in parallel; by setting the output mode of the gate level conversion chip from single-line output mode to dual-line output mode, the GOA dual-line scan control is realized, so that each gate drive pulse acts on two adjacent gate lines simultaneously.

2. The UHD liquid crystal driving method based on an FHD chip according to claim 1, characterized in that, The FHD chip is a KV1626 chip, and the LCD screen is a JR425R3HC0K LCD screen.

3. The UHD liquid crystal driving method based on an FHD chip according to claim 1, characterized in that, in, By using dual-line scanning and parallel transmission of MINI-LVDS channels, the 2×2 physical pixels formed by every two adjacent rows and two columns on the liquid crystal display screen receive the same image data, thereby jointly displaying the same pixel content in a frame of image.

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