A method for manufacturing a solar cell, a solar cell, and a photovoltaic module

Abstract

The application discloses a solar cell manufacturing method, a solar cell and a photovoltaic module, and relates to the technical field of photovoltaics. The solar cell manufacturing method comprises the following steps: providing a semiconductor substrate, the semiconductor substrate having a first surface and a second surface opposite to each other; forming a first semiconductor layer on the first surface, the first semiconductor layer comprising amorphous silicon and / or nanocrystalline silicon, and the first semiconductor layer comprising at least one treatment area; irradiating a part of the treatment area along multiple paths by using a laser, and the irradiation areas of the laser along the multiple paths are not overlapped, so that the crystallization degree of the first semiconductor layer in the irradiated part is increased to form a crystallization area. Thus, the crystallization degree of the first semiconductor layer in the irradiated part is increased to form a crystallization area, and meanwhile, the irradiated area in the treatment area is prevented from being damaged due to the laser effect, and thus, the power generation performance of the solar cell is ensured while the contact resistance and the transmission loss are reduced.

Description

Technical Field

[0001] This application relates to the field of photovoltaic technology, and in particular to a method for manufacturing a solar cell, a solar cell, and a photovoltaic module. Background Technology

[0002] A solar cell is a device that converts sunlight into electrical energy. Specifically, when a solar cell is in operation, sunlight shines on the semiconductor pn junction, forming new electron-hole pairs. Under the influence of the built-in electric field of the pn junction, photogenerated holes flow to the p-region, and photogenerated electrons flow to the n-region. When the circuit is connected, an electric current is generated. For growth films of the same thickness, amorphous silicon layers have a faster growth rate than crystalline (microcrystalline or nanocrystalline) layers. However, amorphous silicon does not possess the high electrical conductivity of crystalline silicon; its contact resistance is higher, resulting in higher transmission losses, which is detrimental to the electrical contact of the solar cell. Summary of the Invention

[0003] The purpose of this application is to provide a method for manufacturing a solar cell, a solar cell, and a photovoltaic module, so as to ensure production efficiency while reducing contact resistance and transmission loss; and, during the manufacturing process, while increasing the crystallinity of the first semiconductor layer in the laser-irradiated part to form a crystallized region, the laser-irradiated area in the processing area is prevented from being damaged by the laser, thereby reducing contact resistance and transmission loss while ensuring the power generation performance of the solar cell.

[0004] To achieve the above objectives, this application provides the following technical solution:

[0005] A method for manufacturing a solar cell includes:

[0006] A semiconductor substrate is provided, the semiconductor substrate having opposing first and second surfaces;

[0007] A first semiconductor layer is formed on a first surface, the first semiconductor layer comprising amorphous silicon and / or nanocrystalline silicon, and the first semiconductor layer comprising at least one processing region;

[0008] By using a laser to irradiate a portion of the processing area along multiple paths, and ensuring that the irradiated areas do not overlap, the degree of crystallization of the first semiconductor layer in the irradiated portion is increased, forming a crystallized region.

[0009] The applicant discovered through research that, after a portion of the laser-irradiated treatment area, such as Figure 5As shown, a large number of porous structures often appear in the processing area of ​​the first semiconductor layer, which damages the first semiconductor layer and reduces the power generation efficiency of the solar cell. In view of the above, in this application, during laser irradiation, the laser irradiates multiple areas without repetition; that is, no location within the processing area can be repeatedly irradiated by the laser. This minimizes the impact of laser thermal radiation on the laser-irradiated area, thereby increasing the crystallinity of the first semiconductor layer in the laser-irradiated portion, forming a crystallized region, while preventing damage to the laser-irradiated area within the processing area due to laser action. This reduces contact resistance and transmission loss while ensuring the power generation performance of the solar cell.

[0010] This application also provides a solar cell, comprising:

[0011] A semiconductor substrate having opposing first and second surfaces;

[0012] A first semiconductor layer is disposed on a first surface. The first semiconductor layer includes amorphous silicon and / or nanocrystalline silicon. The first semiconductor layer includes at least one processing region. The processing region includes a plurality of strip-shaped crystallization regions extending along a first direction and spaced apart along a second direction, and a spacer region located between adjacent crystallization regions. The crystallization degree of the crystallization region is greater than that of the spacer region. The crystallization region includes nanocrystalline silicon and / or microcrystalline silicon.

[0013] The first electrode, the orthographic projection of the first electrode on the first surface, at least partially overlaps with the orthographic projection of the crystallized region within a processing area on the first surface.

[0014] In the solar cell provided in this application, there are gaps between the crystallized regions within the same processing area. Thus, during laser irradiation, the areas irradiated by the laser along multiple paths do not overlap. That is, there is a gap between the edges of the laser spots of two adjacent paths. No location within the processing area can be repeatedly irradiated by the laser. As a result, the area within the processing area irradiated by the laser is less affected by laser thermal radiation. This increases the degree of crystallization of the first semiconductor layer in the irradiated portion, forming a crystallized region, while preventing damage to the irradiated area within the processing area due to laser action. Consequently, while reducing contact resistance and transmission loss, the power generation performance of the solar cell is guaranteed.

[0015] This application also provides a photovoltaic module, including a plurality of solar cells as described above and at least one interconnecting element, wherein the interconnecting element connects two adjacent solar cells in series or in parallel. Attached Figure Description

[0016] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings:

[0017] Figure 1 A top view of a solar cell provided in an embodiment of this application;

[0018] Figure 2 A microscope image of a portion of a solar cell provided in an embodiment of this application;

[0019] Figure 3 Top-view SEM image of the crystallization point provided in the embodiments of this application;

[0020] Figure 4 TEM images of crystallization points provided in embodiments of this application;

[0021] Figure 5 Top-view SEM image of the overlapping region of the first semiconductor layer after laser irradiation;

[0022] Figure 6 A cross-sectional TEM image of the overlapping region of the first semiconductor layer after laser irradiation;

[0023] Figures 7-9 A flowchart illustrating a solar cell manufacturing method provided in this application embodiment;

[0024] Figures 10-12 A flowchart illustrating a method for manufacturing a solar cell according to another embodiment of this application;

[0025] Figures 13-14 A flowchart illustrating a method for manufacturing a solar cell according to another embodiment of this application;

[0026] Figure 15 A top view of a solar cell provided in another embodiment of this application;

[0027] Figure 16 This is a top view of a photovoltaic module provided in an embodiment of this application.

[0028] Figure label:

[0029] 01-Processing region, 1-Crystallization region, 1a-Bubble, 2-Spacer region, 10-Semiconductor substrate, 11-First intrinsic semiconductor layer, 12-First doped semiconductor layer, 13-Transparent conductive layer, 14-Second intrinsic semiconductor layer, 15-Second doped semiconductor layer, 16-First electrode, 17-Second electrode, 18-Tunneling oxide layer, 19-Polycrystalline silicon layer, 20-First interconnect, 21-Second interconnect. Detailed Implementation

[0030] To make the technical problems, technical solutions, and beneficial effects to be solved by this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and are not intended to limit the scope of this application.

[0031] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.

[0032] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise expressly specified. "Several" means one or more, unless otherwise expressly specified.

[0033] In the description of this application, it should be understood that the terms "upper", "lower", "front", "rear", "left", "right", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0034] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0035] The method for manufacturing a solar cell provided in this application includes:

[0036] S100: A semiconductor substrate 10 is provided, the semiconductor substrate 10 having opposing first and second surfaces;

[0037] That is, the two surfaces opposite each other along the thickness direction of the semiconductor substrate 10 are designated as the first surface and the second surface, respectively. Prior to this step, in some embodiments, the semiconductor substrate 10 may be immersed in a polishing and cleaning machine to remove the cutting damage layer of the semiconductor substrate 10 using a polishing slurry. Furthermore, in this step, the morphology of the first and second surfaces of the semiconductor substrate 10 after polishing and cleaning can be adjusted by regulating parameters such as temperature, time, type of cleaning slurry, and concentration of the cleaning slurry. It should be noted that in some examples, the polishing and cleaning step can be omitted.

[0038] S200: A first semiconductor layer is formed on the first surface, the first semiconductor layer comprising amorphous silicon and / or nanocrystalline silicon, and the first semiconductor layer comprising at least one processing region O1;

[0039] The first semiconductor layer includes a first doped semiconductor layer 12, wherein the first doped semiconductor layer 12 can be formed entirely on the first surface or partially; when the first doped semiconductor layer 12 is partially formed on the first surface, the first doped semiconductor layer 12 can be distributed in multiple strip-like or multiple X-shaped patterns. The first doped semiconductor layer 12 can be additionally formed on the first surface of the semiconductor substrate 10 by deposition technology, or it can be formed within the semiconductor substrate 10 by diffusion, ion implantation, or other methods.

[0040] The first semiconductor layer includes amorphous silicon and / or nanocrystalline silicon. The amorphous silicon and / or nanocrystalline silicon materials contain a large amount of hydrogen, which makes the first semiconductor layer contain a large amount of hydrogen. This facilitates the hydrogenation of dangling bonds on the surface of the semiconductor substrate 10, reduces surface defects, and thus provides a high passivation effect on the semiconductor substrate 10.

[0041] There can be one or more processing areas 01. When there are multiple processing areas 01, such as... Figure 1 As shown, multiple processing zones 01 can be distributed at intervals along the second direction.

[0042] S300: A portion of the processing region 01 is irradiated by a laser along multiple paths, and the irradiated areas along the multiple paths do not overlap, thereby increasing the crystallization degree of the first semiconductor layer in the irradiated portion to form a crystallized region 1.

[0043] Specifically, a portion of the processing area 01 is irradiated with laser light, and the areas irradiated by the laser along multiple paths are not repeated. That is, during the irradiation process along multiple paths, there is a gap between the edges of the laser spots of adjacent paths, and no location within the processing area 01 can be irradiated by the laser repeatedly. For example... Figure 1 and Figure 2As shown, the degree of crystallization of the first semiconductor layer irradiated by the laser increases, forming a crystallized region 1. That is, a region irradiated by the laser along one path forms a crystallized region 1, and regions irradiated by the laser along multiple paths form multiple crystallized regions 1 respectively. There is a gap region 2 between regions irradiated by the laser along two adjacent paths, that is, there is a gap region 2 between two adjacent crystallized regions 1. In the embodiments of this application, the increase in the degree of crystallization can refer to an increase in crystallization rate, an increase in grain size, and / or an increase in the number of grains.

[0044] Understandably, all other things being equal, the lower the crystallinity of the semiconductor layer, the smaller the grains and the more amorphous structures in the semiconductor layer. The first semiconductor layer includes amorphous silicon, whose atoms are randomly arranged. The grains in the first semiconductor layer are small and there are many grain interfaces, resulting in a higher resistance. Similarly, the first semiconductor layer includes nanocrystalline silicon, whose atoms are also mostly randomly arranged. The grains in the first semiconductor layer are small and there are many grain interfaces, resulting in a higher resistance compared to microcrystalline silicon and nanocrystalline silicon with larger grain sizes or a higher proportion of nanocrystals. In the solar cell manufacturing method provided in this application, at least a portion of the processing region 01 of the first semiconductor layer is irradiated with a laser, thereby increasing the crystallinity of the irradiated portion of the first semiconductor layer to form a crystallized region 1. Within the crystallized region 1, the grain size increases, the number of grains increases, and the number of grain interfaces decreases, thereby reducing the contact resistance of the crystallized region 1, and consequently reducing the contact resistance between the crystallized region 1 and the transparent conductive layer 13, and further reducing the transport loss of charge carriers collected within the first semiconductor layer. Thus, in the actual manufacturing process, a first semiconductor layer containing amorphous silicon can be rapidly grown first, and then laser irradiation can be used to increase the crystallinity of at least a local area within the processing region 01, thereby reducing the contact resistance of the doped layer, so as to ensure production efficiency while reducing contact resistance and transmission loss.

[0045] The applicant discovered through research that, after laser irradiation of a portion of the treatment area 01, such as Figure 5 As shown, the processing region 01 of the first semiconductor layer often exhibits numerous porous structures, which damages the first semiconductor layer and reduces the power generation efficiency of the solar cell. In view of this, in this application, during laser irradiation, the laser irradiates multiple areas without repetition; that is, no location within the processing region 01 can be repeatedly irradiated by the laser. Thus, the area within the processing region 01 irradiated by the laser is less affected by laser thermal radiation, thereby increasing the crystallinity of the first semiconductor layer in the irradiated portion to form crystallized region 1, while preventing damage to the irradiated area within the processing region 01 due to laser action. This reduces contact resistance and transmission loss while ensuring the power generation performance of the solar cell.

[0046] It should be noted that in this application, "higher crystallinity" refers to regions with a higher degree of crystallinity that have relatively larger grain sizes and / or a relatively greater number of grains, and / or a higher crystallinity rate compared to other regions. For example, when the first semiconductor layer is amorphous silicon, nanocrystals (i.e., larger grain sizes) will be generated in crystallization region 1. Simultaneously, the amorphous silicon material, which originally had virtually no grains, will generate nanocrystals in crystallization region 1 (i.e., an increase in the number of grains), thus improving the final crystallinity rate. These three factors may occur individually or in combination. When the first semiconductor layer is nanocrystalline silicon (meaning the first semiconductor layer is mainly composed of nanocrystals, but may also include some amorphous silicon and microcrystalline silicon), nanocrystal growth (i.e., larger grain sizes, possibly even larger nanocrystals or microcrystalline grains) will also occur in crystallization region 1. Simultaneously, nanocrystals may be regenerated internally (i.e., an increase in the number of grains), further improving the final crystallinity rate. These three factors may occur individually or in combination.

[0047] In some embodiments, such as Figure 1 As shown, the laser irradiation path can extend in a straight line along the first direction, which facilitates operation. Alternatively, the laser irradiation path can also extend along a bend or curve along the first direction, thus increasing the irradiated area and forming a larger crystallization region 1, which helps to further reduce the transmission resistance of the processing region 01. The processing region 01 includes at least two crystallization regions 1 spaced apart along the second direction, preferably two or three crystallization regions.

[0048] In some embodiments, such as Figure 1 As shown, on the one hand, if the width D1 of the crystallized region 1 is too small, the purpose of reducing the transmission resistance cannot be achieved; on the other hand, if the width D1 of the crystallized region 1 is too large, the spacing region 2 between adjacent crystallized regions 1 will shrink. During laser irradiation, the adjacent crystallized regions 1 will have mutual thermal influence, damaging the first semiconductor layer. In this technical solution, in order to balance the above two aspects, the width D1 of the crystallized region 1 along the second direction is 20μm to 600μm, so as to reduce the transmission resistance while reducing the damage of the laser to the first semiconductor layer. For example, D1 can be 20μm, 50μm, 100μm, 150μm, 200μm, 250μm, 300μm, 350μm, 400μm, 450μm, 500μm, 550μm, or 600μm, etc.

[0049] In some embodiments, such as Figure 1 As shown, within the same processing area 01, multiple laser irradiation paths are parallel to each other to simplify processing and improve processing efficiency.

[0050] On the one hand, if the width D2 of the spacer region 2 between adjacent crystallization regions 1 is too large, the area of ​​the crystallization region 1 will be reduced, failing to achieve the purpose of reducing transmission resistance. On the other hand, if the width D2 of the spacer region 2 between adjacent crystallization regions 1 is too small, it may cause damage to the first semiconductor layer during laser irradiation along two adjacent paths, reducing the power generation efficiency of the solar cell. In this technical solution, in order to balance the above two aspects, along the second direction, within the same processing region 01, the width D2 of the spacer region 2 between adjacent crystallization regions 1 is 2μm to 300μm, so as to reduce transmission resistance while reducing laser damage to the first semiconductor layer.

[0051] For example, the width D2 of spacer region 2 can be 2μm, 4μm, 6μm, 10μm, 30μm, 50μm, 80μm, 100μm, 120μm, 150μm, 180μm, 200μm, 220μm, 250μm, 280μm, or 300μm, etc. The specific value of the width D2 of spacer region 2 may be affected by factors such as precision, and it may be slightly smaller than the set value. Therefore, a small number of crystallization points (such as the orderly arrangement of grains or lattice in amorphous silicon) may appear in spacer region 2, but its overall degree of crystallization is less than that of crystallization region 1.

[0052] In some embodiments, such as Figure 1 As shown, there are multiple processing regions 01 arranged along a second direction. Along this second direction, the distance D3 between adjacent processing regions 01 (between the boundaries of adjacent processing regions) is 500 μm to 1500 μm. In some embodiments, along the second direction, the width of each processing region 01 should be less than the distance between adjacent processing regions 01, preferably less than or equal to half the distance between adjacent processing regions 01. For example, the ratio of the width of one processing region 01 to the distance between adjacent processing regions 01 is between 0.1 and 0.5. This arrangement prevents the distance D3 between adjacent processing regions 01 from being too large, affecting carrier collection efficiency, and also prevents the distance D3 from being too small, leading to increased process steps and reduced production efficiency.

[0053] For example, the distance D3 between adjacent processing areas 01 can be 500μm, 600μm, 700μm, 800μm, 900μm, 1000μm, 1100μm, 1200μm, 1300μm, 1400μm or 1500μm.

[0054] The applicant discovered through research that, due to the thinness of the semiconductor layer at its edges, laser irradiation of this thinner layer can cause damage and blackening, reducing the passivation effect and consequently affecting the overall photoelectric conversion efficiency of the solar cell. Therefore, in this technical solution, if... Figure 1As shown, along the first direction, the minimum distance D4 between the edge of the crystallization region 1 and the edge of the first semiconductor layer is greater than or equal to 100 μm. This ensures a sufficient safety distance between the laser-irradiated area and the edge of the first semiconductor layer to prevent damage and blackening of the first semiconductor layer's edge, thereby improving the passivation effect of the thinner edge region of the first semiconductor layer and increasing the battery's power generation efficiency.

[0055] For example, D4 ​​can be 100μm, 300μm, 500μm, 800μm, 1000μm, 1200μm, 1500μm, 1800μm, 2000μm, 2200μm, or 2500μm, etc. Optionally, 100μm ≤ D4 ≤ 2000μm.

[0056] In some embodiments, the width of the processing region 01 along the second direction is 100 μm to 600 μm. This width design of the processing region 01 is within a reasonable range, which, when forming the first electrode 16, facilitates at least a partial correspondence between the first electrode 16 and the crystallization region 1 within the processing region 01, widening the process window for processing the first electrode 16 and improving processing efficiency and product yield. For example, the width of the processing region 01 is 100 μm, 150 μm, 200 μm, 250 μm, 300 μm, 350 μm, 400 μm, 450 μm, 500 μm, 550 μm, or 600 μm.

[0057] In some embodiments, such as Figure 2 As shown, along the second direction, the minimum distance D5 between the edge of the crystallization region 1 and the edge of the first semiconductor layer is greater than or equal to 20 μm to prevent the risk of leakage caused by processing errors.

[0058] For example, D5 can be 20μm, 50μm, 100μm, 150μm, 200μm, 250μm, 300μm, 350μm, 400μm, 450μm, 500μm, 550μm, or 600μm, etc. Optionally, 20μm ≤ D5 ≤ 500μm.

[0059] In some embodiments, after the first semiconductor layer is formed on the first surface in S200 and before a portion of the processing area 01 is irradiated with a laser along multiple paths in S300, the method of manufacturing the solar cell further includes: in S201 forming a transparent conductive layer 13 on the first surface, the transparent conductive layer 13 being located on the side of the first semiconductor layer away from the semiconductor substrate 10.

[0060] Using the above technical solution, after forming the transparent conductive layer 13 on the first surface, the transparent conductive layer 13 is also irradiated simultaneously with the first semiconductor layer using a laser. This allows the area corresponding to the transparent conductive layer 13 and the crystallization region 1 to include cracks and / or pores. Specifically, the area corresponding to the transparent conductive layer 13 and the crystallization region 1 can have regular or irregular cracks, and the pores can be through-holes penetrating the thickness of the transparent conductive layer 13 or blind holes. With this configuration, during the formation of the first electrode 16, the paste used to form the first electrode 16 can penetrate into the cracks and / or pores, thereby increasing the contact area between the transparent conductive layer 13 and the first electrode 16, further reducing the transmission resistance between the transparent conductive layer 13 and the first electrode 16, and improving the photoelectric conversion efficiency.

[0061] In some embodiments, after S300 irradiating a portion of the processing region 01 with a laser along multiple paths, the method for manufacturing the solar cell further includes: S301 forming a transparent conductive layer 13 on the first surface, the transparent conductive layer 13 being located on the side of the first semiconductor layer facing away from the semiconductor substrate 10. By employing the above technical solution, irradiating a portion of the processing region 01 before forming the transparent conductive layer 13 ensures the stability of the performance of the transparent conductive layer 13.

[0062] Specifically, the transparent conductive layer 13 can be formed by deposition or other methods. The material of the transparent conductive layer 13 can include at least one of fluorine-doped tin oxide, aluminum-doped zinc oxide, tin-doped indium oxide, tungsten-doped indium oxide, molybdenum-doped indium oxide, cerium-doped indium oxide, and indium hydroxide. The transparent conductive layer 13 can be a single-layer thin film or a multilayer thin film.

[0063] In some embodiments, such as Figure 15 As shown, after step S300 irradiates a portion of the processing region 01 along multiple paths using a laser, the method for manufacturing the solar cell further includes: step S302 forming a first electrode 16 on a first surface, wherein the orthographic projection of each first electrode 16 on the first surface at least partially overlaps with the orthographic projection of a crystallized region 1 within a processing region 01 on the first surface. Using this technical solution, at least a portion of the first electrode 16 corresponds to the crystallized region 1, and the crystallized region 1 has a higher degree of crystallization, thereby reducing the transmission resistance and current transmission loss between the first electrode 16 and the crystallized region 1, and improving the efficiency of the solar cell. Optionally, along the second direction, the width of the orthographic projection of the first electrode 16 onto the semiconductor substrate 10 is smaller than the width of the orthographic projection of the processing region 01 onto the semiconductor substrate 10.

[0064] The material of the first electrode 16 may include silver, copper, aluminum, and their alloys. Specifically, the first electrode 16 may be formed using processes such as screen printing, electroplating, sputtering, or vapor deposition.

[0065] It is understood that when the manufacturing method of the solar cell includes the step of forming a transparent conductive layer 13, the transparent conductive layer 13 is first formed on the first surface, and then the first electrode 16 is formed on the side of the transparent conductive layer 13 away from the semiconductor substrate 10.

[0066] In some embodiments, at least a portion of the first surface of the semiconductor substrate 10 is textured, and a plurality of pyramid-like structures are formed on the textured surface. A first semiconductor layer is formed at least on the textured surface of the first surface. When the first semiconductor layer is disposed on the textured surface, the side of the first semiconductor layer facing away from the semiconductor substrate 10 has a undulating morphology that is substantially the same as the textured surface. In this case, the first semiconductor layer has a larger specific surface area, which can increase the contact area between the first semiconductor layer and the transparent conductive layer 13, further reducing carrier transport losses.

[0067] In terms of the pyramid-like structure, the embodiments of the present invention do not specifically limit the shape, size and distribution of the pyramid-like structure formed on the textured surface, as long as it can be applied to the solar cell provided in the embodiments of the present invention.

[0068] For example, the aforementioned pyramid-like structure can be a pyramid with sharp apex corners; or, it can be a pyramid-like structure with rounded chamfers; or, it can be a pyramid-like structure with flattened apex corners. In this case, the pyramid-like structure can have at least three of the above examples, which is beneficial to improving the applicability of the solar cell provided by the embodiments of the present invention in different application scenarios. In addition, it is not necessary to strictly control the manufacturing precision in order to obtain a pyramid-like structure with a single morphology, which reduces the difficulty of the process and helps to improve the yield of solar cells.

[0069] In some embodiments, such as Figure 3 and Figure 4 As shown, a first semiconductor layer is formed at least on the textured surface of the first surface; a crystallization region 1 covers the textured surface, and the crystallization region 1 includes multiple crystallization points, which cover the top regions of multiple pyramid-like structures. That is, the degree of crystallization of the portion of the first semiconductor layer covering the top of the pyramid-like structure is greater than the degree of crystallization of the portion of the first semiconductor layer covering the base of the pyramid-like structure. Figure 3 In the pyramid-like structure, the lighter-colored area at the top is the crystallization point, or as... Figure 4 The region at the top of the pyramid-like structure where grains are concentrated is called the crystallization point. The height of the crystallization point along the direction perpendicular to the first surface is less than 1 / 3 of the height of the corresponding pyramid-like structure.

[0070] By adopting the above technical solution, the laser energy used for laser irradiation can be appropriately reduced, allowing the first semiconductor layer covering the base of the pyramid-like structure to still have a relatively high hydrogen content. This results in a higher passivation effect on the textured surface, reducing the number of defects and improving the working efficiency of the solar cell. In short, the portion of the first semiconductor layer covering the top of the pyramid-like structure forms highly crystalline points, reducing the contact resistance between the transparent conductive layer 13 and the first semiconductor layer. Simultaneously, the portion of the first semiconductor layer covering the base of the pyramid-like structure maintains its original degree of crystallinity and a relatively high hydrogen content, ensuring the passivation effect of the first semiconductor layer. This achieves a balance between contact resistance and passivation effect.

[0071] In some embodiments, the orthographic projection of the crystallization point on the semiconductor substrate 10 is circular, elliptical, square, or irregular in shape; that is, the orthographic projection of the crystallization point on the semiconductor substrate 10 can be any shape, and is not limited herein.

[0072] In some embodiments, the equivalent radius of the orthographic projection of the crystallization point onto the semiconductor substrate 10 is 50 nm to 600 nm. Maintaining the area of ​​the crystallization point within this reasonable range reduces the laser energy used, minimizing laser damage to the semiconductor substrate 10, while simultaneously ensuring a low transmission resistance in the crystallization point region. For example, the equivalent radius of the orthographic projection of the crystallization point onto the semiconductor substrate 10 can be 50 nm, 100 nm, 150 nm, 200 nm, 250 nm, 300 nm, 350 nm, 400 nm, 450 nm, 500 nm, 550 nm, or 600 nm.

[0073] It is understood that when at least a portion of the first surface of the semiconductor substrate 10 is textured, multiple pyramid-like structures are formed on the textured surface. A first semiconductor layer is conformally disposed on the textured surface, and the degree of crystallization of the portion of the first semiconductor layer covering the top of at least a portion of the pyramid-like structures is greater than the degree of crystallization of the other portion covering the base of the pyramid-like structures. When observing the degree of crystallization of the first semiconductor layer, if the observed area is too small, the degree of crystallization of the first semiconductor layer cannot be accurately obtained by observing only the base region of the pyramid-like structures. Therefore, the observed area should at least contain one pyramid-like structure; preferably, the observed area should be greater than or equal to 5*5μm. 2 This is to prevent the crystallization degree of the first semiconductor layer from being inaccurately obtained by only observing the base region of the pyramid-like structure.

[0074] In some embodiments, the first semiconductor layer may include a first doped semiconductor layer 12 and a first intrinsic semiconductor layer 11; forming the first semiconductor layer on the first surface includes: forming a first intrinsic semiconductor layer 11 on the first surface, the first intrinsic semiconductor layer 11 including intrinsic amorphous silicon and / or nanocrystalline silicon; forming the first doped semiconductor layer 12 on the side of the first intrinsic semiconductor layer 11 opposite to the semiconductor substrate 10. The thickness of the crystallized region 1 formed in the first semiconductor layer may be less than or equal to the sum of the thickness of the first doped semiconductor layer 12 and the thickness of the first intrinsic semiconductor layer 11, or the thickness of the crystallized region 1 formed in the first semiconductor layer may be less than or equal to the thickness of the first doped semiconductor layer 12.

[0075] In some embodiments, when the manufactured solar cell is a bifacial contact cell, the method of manufacturing the solar cell further includes, before or after forming the first semiconductor layer on the first surface, forming a second semiconductor layer on the second surface. The second semiconductor layer has an opposite conductivity type to the first semiconductor layer, so as to collect and export electrons and holes respectively, facilitating the formation of photocurrent. Specifically, the second semiconductor layer can be formed on the second surface of the semiconductor substrate 10 before or after forming the first semiconductor layer and before forming the transparent conductive layer 13. The second semiconductor layer can be additionally formed on the semiconductor substrate 10 by deposition technology, or it can be formed within the semiconductor substrate 10 by diffusion, ion implantation, or other methods. The second semiconductor layer can be at least one of monocrystalline silicon, polycrystalline silicon, microcrystalline silicon, amorphous silicon, or nanocrystalline silicon.

[0076] like Figures 7-9 As shown, in cases where the second semiconductor layer of the double-sided contact battery also includes amorphous silicon and / or nanocrystalline silicon, a first semiconductor layer is formed on the first surface of the semiconductor substrate 10, and after the second semiconductor layer is formed on the second surface, as... Figure 8 As shown, at least a portion of the processing region 01 of the first semiconductor layer is irradiated with a laser, and at least a portion of the processing region 01 of the second semiconductor layer is also irradiated with a laser, thereby increasing the degree of crystallization of the first semiconductor layer in the irradiated portion to form a crystallized region 1, and also increasing the degree of crystallization of the second semiconductor layer in the irradiated portion to form a crystallized region 1.

[0077] Next, as Figure 9As shown, a transparent conductive layer 13 is formed on a first surface and a second surface. A first electrode 16 is formed on the first surface, on the side of the transparent conductive layer 13 facing away from the semiconductor substrate 10. A second electrode 17 is formed on the second surface, on the side of the transparent conductive layer 13 facing away from the semiconductor substrate 10. The orthogonal projection of the first electrode 16 onto the semiconductor substrate 10 at least partially overlaps with the orthogonal projection of the crystallized region 1 of the first semiconductor layer onto the semiconductor substrate 10. The orthogonal projection of the second electrode 17 onto the semiconductor substrate 10 at least partially overlaps with the orthogonal projection of the crystallized region 1 of the second semiconductor layer onto the semiconductor substrate 10.

[0078] In the case where the manufactured solar cell is a back-contact cell, such as Figures 10-12 As shown, the method for manufacturing a solar cell further includes: forming a second semiconductor layer in at least a localized region of a first surface, wherein the second semiconductor layer has an opposite conductivity type to the first semiconductor layer, and the second semiconductor layer and the first semiconductor layer are alternately distributed. The second semiconductor layer can be at least one of monocrystalline silicon, polycrystalline silicon, microcrystalline silicon, amorphous silicon, or nanocrystalline silicon. It should be noted that when the second semiconductor layer includes a polycrystalline silicon layer 19, the second semiconductor layer is formed first on the first surface, followed by the formation of the first semiconductor layer. When the second semiconductor layer includes amorphous silicon and / or nanocrystalline silicon, the second semiconductor layer can be formed first on the first surface, followed by the formation of the first semiconductor layer, or vice versa.

[0079] like Figure 12 As shown, the first surface has an overlapping region, and the first semiconductor layer and the second semiconductor layer can be stacked in the overlapping region. The transparent conductive layer 13 covers the side of the first semiconductor layer and the second semiconductor layer away from the semiconductor substrate 10, and the transparent conductive layer 13 has an opening that extends through its thickness to prevent short circuits.

[0080] like Figure 11 As shown, when the second semiconductor layer comprises amorphous silicon and / or nanocrystalline silicon, at least a portion of the processing region 01 of the second semiconductor layer can be irradiated with a laser to increase the crystallinity of at least a local region of the laser-irradiated portion of the second semiconductor layer, forming a crystallized region 1. The laser irradiation of the first and second semiconductor layers can be performed simultaneously or separately.

[0081] Next, as Figure 12 As shown, a transparent conductive layer 13 is formed on the first surface, covering the side of the first semiconductor layer and the second semiconductor layer away from the semiconductor substrate 10. A first electrode 16 is formed on the side of the transparent conductive layer 13 away from the first semiconductor layer, and a second electrode 17 is formed on the side of the transparent conductive layer 13 away from the second semiconductor layer.

[0082] The characteristics and parameters of the crystallized region 1 formed at least partially in the second semiconductor layer can be referred to the characteristics and parameters of the crystallized region 1 formed at least partially in the first semiconductor layer, and will not be repeated here.

[0083] When the second semiconductor layer comprises amorphous silicon and / or nanocrystalline silicon, the second semiconductor layer may include a second doped semiconductor layer 15 and a second intrinsic semiconductor layer 14. Forming the second semiconductor layer on the second surface includes: forming a second intrinsic semiconductor layer 14 on the second surface, the second intrinsic semiconductor layer 14 comprising intrinsic amorphous silicon and / or nanocrystalline silicon; and forming a second doped semiconductor layer 15 on the side of the second intrinsic semiconductor layer 14 facing away from the semiconductor substrate 10. The thickness of the crystallized region 1 formed in the second semiconductor layer may be less than or equal to the sum of the thickness of the second doped semiconductor layer 15 and the thickness of the second intrinsic semiconductor layer 14, or the thickness of the crystallized region 1 formed in the second semiconductor layer may be less than or equal to the thickness of the second doped semiconductor layer 15. It is understood that the first semiconductor layer can be irradiated first and then the second semiconductor layer, or the second semiconductor layer can be irradiated first and then the first semiconductor layer, or both semiconductor layers can be irradiated simultaneously. Of course, when the second semiconductor layer may also include a polycrystalline silicon layer 19, a laser crystallization process is not required, and a tunneling oxide layer 18 may be present between the polycrystalline silicon layer 19 and the semiconductor substrate 10.

[0084] In other embodiments, such as Figure 13 and Figure 14 As shown, it is also possible to use laser to irradiate only a portion of the first semiconductor layer, while the second semiconductor layer is not irradiated by the laser. In this case, the second semiconductor layer can be selected from at least one of monocrystalline silicon, polycrystalline silicon, and microcrystalline silicon.

[0085] When the second semiconductor layer includes a polycrystalline silicon layer 19, a tunneling oxide layer 18 may also be disposed between the second semiconductor layer and the semiconductor substrate 10 to improve the passivation effect and reduce the carrier recombination rate in the region of the semiconductor substrate 10 where the second semiconductor layer is formed. When the second semiconductor layer includes amorphous silicon, nanocrystalline silicon, or microcrystalline silicon, the second semiconductor layer includes a second doped semiconductor layer 15 and a second intrinsic semiconductor layer 14, wherein the second intrinsic semiconductor layer 14 may include one or more of intrinsic amorphous silicon, intrinsic nanocrystalline silicon, and intrinsic microcrystalline silicon.

[0086] When the second semiconductor layer comprises amorphous silicon and / or nanocrystalline silicon, the second semiconductor layer is preferably also irradiated by a laser to form a crystallization region 1, so as to reduce the transport loss of the second semiconductor layer in collecting charge carriers.

[0087] In some embodiments, along the second direction, the width of the processing region 01 of a single first semiconductor layer can be greater than the width of a single second semiconductor layer. This ensures current collection of the amorphous or nanocrystalline silicon material while also accommodating current matching of the other polarity. Optionally, the conductivity type of the second semiconductor layer is the same as that of the semiconductor substrate 10, while the conductivity type of the first semiconductor layer is opposite to that of the semiconductor substrate 10. In some preferred embodiments, the width of the processing region 01 of a single first semiconductor layer can be greater than the width of the portion of the single second semiconductor layer not covered by the first semiconductor layer, because the portion not covered by the first semiconductor layer is the effective power generation portion of the second semiconductor layer.

[0088] In some embodiments, parameters such as the processing wavelength, pulse width, laser energy density, and processing time of the laser irradiation process can be determined based on requirements such as the extension range of the crystallization region 1, which covers the top of the pyramid-shaped structure and has a greater degree of crystallization, in the actual application scenario. No specific limitations are made here. It is understood that the smaller the processing wavelength, the larger the pulse width, the higher the laser energy density, and the longer the processing time of the laser irradiation process, the greater the temperature rise of the first semiconductor layer when processed by the laser irradiation process, which is more conducive to forming a crystallization region 1 with a greater crystallization depth and a longer extension length.

[0089] For example, the processing wavelength of the laser irradiation process can be greater than or equal to 325nm and less than or equal to 532nm. For instance, the processing wavelength can be 325nm, 330nm, 350nm, 80nm, 400nm, 430nm, 450nm, 480nm, 500nm, or 532nm, etc.

[0090] For example, the pulse width of the laser irradiation process can be in the picosecond or nanosecond range. For instance, the pulse width can be 10 ps, ​​50 ps, ​​100 ps, ​​300 ps, ​​500 ps, ​​800 ps, ​​1 ns, or 5 ns, etc.

[0091] For example, the laser energy density of the laser irradiation process can be greater than or equal to 100 mJ / cm². 2 For example, the laser energy density can be 100 mJ / cm². 2 140mJ / cm 2 180mJ / cm 2 200mJ / cm 2 240mJ / cm 2 280mJ / cm 2 300mJ / cm 2 400mJ / cm 2 500mJ / cm 2 1000mJ / cm2 2000mJ / cm 2 3000mJ / cm 2 4000mJ / cm 2 5000mJ / cm 2 Or 6000mJ / cm 2 wait.

[0092] Furthermore, this application also provides a solar cell, including a semiconductor substrate 10, a first semiconductor layer, and a first electrode 16. The semiconductor substrate 10 has opposing first and second surfaces. The first semiconductor layer is disposed on the first surface, which may correspond to the back surface of the solar cell, and the second surface may correspond to the light-facing surface of the solar cell. The first semiconductor layer includes amorphous silicon and / or nanocrystalline silicon, and includes at least one processing region 01. The processing region 01 includes a plurality of strip-shaped crystallization regions 1 and a spacer region 2 located between adjacent crystallization regions 1. The plurality of crystallization regions 1 and the spacer region 2 are both strip-shaped along a first direction, and the crystallization regions 1 are spaced apart along a second direction. The spacer region 2 separates two adjacent crystallization regions 1. The degree of crystallization in crystallization region 1 is greater than that in spacer region 2. Crystallization region 1 includes nanocrystalline silicon and / or microcrystalline silicon. Specifically, after laser irradiation, the amorphous silicon in a local area of ​​the laser-irradiated processing region 01 will crystallize to form nanocrystals. Nanocrystalline silicon refers to a crystallization structure in which most of the grain size is at the nanometer size, for example, the grain size is below 200nm.

[0093] The orthographic projection of the first electrode 16 on the first surface at least partially overlaps with the orthographic projection of the crystallized region 1 within a processing region 01 on the first surface. Specifically, the first electrode 16 extends along a first direction, that is, the extension direction of the first electrode 1 is consistent with that of the crystallized region 1 and the spacer region 2.

[0094] In the solar cell provided in this application, there are spacer regions 2 between the crystallization regions 1 within the same processing region 01. Thus, during laser irradiation, the areas irradiated by the laser along multiple paths do not overlap, that is, there is a gap between the edges of the laser spots of two adjacent paths. No position within the processing region 01 can be repeatedly irradiated by the laser. As a result, the area within the processing region 01 irradiated by the laser is less affected by laser thermal radiation. This increases the degree of crystallization of the first semiconductor layer in the laser-irradiated part, forming the crystallization region 1, while avoiding damage to the area within the processing region 01 irradiated by the laser due to the laser action. In this way, the power generation performance of the solar cell is guaranteed while reducing contact resistance and transmission loss.

[0095] In some embodiments, such as Figure 15As shown, there are multiple first electrodes 16 and processing regions 01 extending along a first direction and spaced apart along a second direction, with each first electrode 16 corresponding to one processing region 01. That is, each first electrode 16 is electrically connected to a crystallized region 1 within a processing region 01. This arrangement allows the multiple processing regions 01 and the multiple first electrodes 16 to extract the charge carriers collected at various locations in the first semiconductor layer, and facilitates the positioning of the multiple first electrodes 16 during their formation, thereby further improving production efficiency.

[0096] In some embodiments, such as Figure 1 and Figure 2 As shown, the multiple processing regions 01 contain the same number of crystallization regions 1, and the multiple processing regions 01 contain the same number of spacer regions 2. For example, each processing region 01 includes 2, 3, 4 or more crystallization regions 1, and each processing region 01 includes 1, 2, 3 or more isolation regions. With this configuration, the crystallization areas within each processing region 01 are more similar, enabling more uniform collection and extraction of charge carriers collected at various locations in the first semiconductor layer. This reduces the current differences at various locations in the first semiconductor layer, thereby avoiding localized overheating of the solar cell.

[0097] In other embodiments, see Figure 1 and Figure 2 The semiconductor substrate 10 includes a first edge and a second edge disposed opposite to each other along a second direction. However, the semiconductor substrate 10 and the first semiconductor layer near the first and second edges have more defects, which easily lead to recombination centers and are detrimental to improving photoelectric efficiency. Therefore, along the second direction, the width of the processing region 01 closest to the first and second edges can be smaller than the width of the processing region 01 farther from the first or second edge. This avoids passivation of the first semiconductor layer in the edge region due to laser crystallization, while ensuring low contact resistance and current collection efficiency at that location. In a back-contact battery, see... Figure 12 and Figure 14 The first semiconductor layer closest to the first edge and / or the second edge may have no processing region to ensure passivation of the edge region. Specifically, along the second direction, the processing region 01 closest to the first and second edges can be the second processing region, while the processing region 01 adjacent to the second processing region but far from the first and / or second edges is the first processing region. That is, the width of the second processing region along the second direction is less than the width of the first processing region along the second direction. Optionally, the number of second processing regions can be one, two, or more.

[0098] Optionally, the width of at least one processing region 01 near the first edge is greater than the width of multiple processing regions 01 away from the first edge. Similarly, the width of at least one processing region 01 near the second edge is greater than the width of multiple processing regions 01 away from the second edge. The processing regions 01 near the first or second edge need to be larger to output current faster and improve edge current collection efficiency. Therefore, the width of at least one processing region 01 near the first edge is greater than the width of multiple processing regions 01 away from the first edge, and similarly, the width of at least one processing region 01 near the second edge is greater than the width of multiple processing regions 01 away from the second edge. In this case, the processing region 01 closest to the first or second edge can be off-center on its corresponding first semiconductor layer, and can be positioned further away from the first or second edge than the center line extending along the first direction of the strip-shaped first semiconductor layer.

[0099] Optionally, the processing area 01 furthest from the first edge or the second edge is designated as the first processing area, and the width of the first processing area is substantially uniform. The processing area 01 closer to the first edge or the second edge is designated as the second processing area, and the width of the second processing area is greater than the width of the first processing area. For example, the number of second processing areas closer to the first edge can be one, two, or more, and the number of second processing areas closer to the second edge can also be one, two, or more. Optionally, the widths of the second processing areas are equal, and the number of second processing areas closer to the first edge is the same as the number of second processing areas closer to the second edge. Further, the number of crystallized regions 1 contained in the first processing area is less than the number of crystallized regions 1 contained in the second processing area.

[0100] Optionally, the processing area 01 may contain only two types of processing areas, namely a first processing area and a second processing area, wherein the second processing area is located between a plurality of first processing areas and a first edge or a second edge.

[0101] In some embodiments, along the second direction, the absolute value of the difference in width between any two processing regions 01 is less than or equal to 50 μm, meaning that the widths of the multiple processing regions 01 are essentially the same. This also helps to make the crystallization areas within each processing region 01 more similar, reducing the current differences at various locations in the first semiconductor layer and thus avoiding localized overheating of the solar cell. For example, the absolute value of the difference in width between any two processing regions 01 can be 50 μm, 45 μm, 40 μm, 35 μm, 30 μm, 25 μm, 20 μm, 15 μm, 10 μm, 5 μm, 4 μm, 3 μm, 2 μm, 1 μm, or 0, etc.

[0102] In some embodiments, the orthographic projection of the first electrode 16 on the first surface at least partially overlaps with the orthographic projection of the spacer region 2 within a processing region 01 on the first surface. This arrangement, along the second direction, ensures that the first electrode 16 extends beyond the edge of at least one crystallization region 1, further increasing the overlap area between the first electrode 16 and the crystallization region 1, which helps reduce transmission resistance and current transmission loss.

[0103] In some embodiments, along the second direction, the ratio of the width of the first electrode 16 to the width of the spacer region 2 is greater than or equal to 2. This configuration ensures that the width of the first electrode 16 is sufficiently wide to at least partially overlap with the crystallization region 1, preventing the first electrode 16 from failing to cover the crystallization region 1, thereby reducing the transmission resistance between the first electrode 16 and the crystallization region 1. For example, the ratio of the width of the first electrode 16 to the width of the spacer region 2 can be 2, 2.2, 2.5, 2.8, 3, 3.2, 3.5, 3.8, or 4, etc.

[0104] In some embodiments, the solar cell further includes a transparent conductive layer 13, which is located at least on the side of the first semiconductor layer opposite to the semiconductor substrate 10, and a first electrode 16 is formed on the side of the transparent conductive layer 13 opposite to the semiconductor substrate 10. The transparent conductive layer 13 has high conductivity, which can promptly export the collected charge carriers and reduce the charge carrier recombination rate. As for the material of the transparent conductive layer 13, please refer to the previous text, and it will not be repeated here.

[0105] In some embodiments, along the thickness direction of the semiconductor substrate 10, the number of grains within the crystallization point gradually decreases; in other words, the degree of crystallization at the crystallization point closer to the semiconductor substrate 10 is lower than the degree of crystallization at the crystallization point farther from the semiconductor substrate 10. This arrangement improves the surface conductivity of the crystallization point of the first semiconductor layer closer to the transparent conductive layer 13, which helps to reduce the contact resistance between the transparent conductive layer 13 and the first semiconductor layer, further reducing current loss.

[0106] In some embodiments, the crystallization point includes a bubble 1a. Light irradiated onto the bubble 1a can be scattered back into the semiconductor substrate 10 through the inner wall of the bubble 1a, thereby improving the light absorption and utilization rate. The bubble 1a can be any shape, such as circular, quasi-spherical, ellipsoidal, or linear.

[0107] Bubble 1a can be closed. The interior of bubble 1a is generally hollow, but may contain a small amount of semiconductor material. Bubble 1a can also be open, with its inner diameter larger than the diameter of its opening. For example, some bubbles 1a formed inside the first semiconductor layer are closed, while others formed on the surface of the first semiconductor layer away from the semiconductor substrate 10 are open. The maximum size of the open-type bubble 1a is larger than the size of its opening on the surface of the first semiconductor layer away from the semiconductor substrate 10; that is, the opening size of the open-type bubble 1a is relatively small.

[0108] In some embodiments, the diameter of a single bubble 1a is 2nm to 100nm. The diameter of a single bubble 1a can refer to the equivalent diameter of a single bubble 1a within a pore, specifically the volume equivalent diameter of a single bubble 1a. For example, the diameter of a single bubble 1a can be 2nm, 5nm, 10nm, 20nm, 30nm, 40nm, 50nm, 60nm, 70nm, 80nm, 90nm, or 100nm, etc.

[0109] In some embodiments, multiple bubbles 1a aggregate to form a bubble cluster. The number of bubbles 1a in the bubble cluster can be tens, hundreds, or even thousands, that is, the number of bubbles 1a in the bubble cluster is greater than or equal to 10. For example, the number of bubbles 1a in the bubble cluster can be 10, 50, 100, 150, 200, 300, 400, 500, 600, 700, 800, 900, 1000, 1200, 1500, 2000, etc. The diameter of the bubble cluster is 200nm to 1000nm, where the diameter of the bubble cluster is the maximum distance between the two farthest bubbles 1a, that is, the distance between the edges of the two farthest bubbles 1a away from each other. For example, the diameter of the bubble cluster can be 200nm, 300nm, 400nm, 500nm, 600nm, 700nm, 800nm, 900nm, or 1000nm, etc.

[0110] When the crystallization point covers the top region of the pyramid-like structure, the size of the bubble 1a closer to the top of the pyramid-like structure is larger than the size of the bubble 1a farther away from the top of the pyramid-like structure. In other words, along the thickness direction of the semiconductor substrate 10, the closer to the top of the pyramid-like structure, the larger the size of the bubble 1a. The number of bubbles 1a closer to the top of the pyramid-like structure is greater than the number of bubbles 1a farther away from the top of the pyramid-like structure; that is, the closer to the top of the pyramid-like structure, the more bubbles 1a there are. Given that the top of the pyramid-like structure has poor light reflection and scattering effects, in this technical solution, more bubbles 1a or larger bubble 1a inner walls can be used to reflect light back into the semiconductor substrate 10, thereby further improving the light absorption and utilization rate.

[0111] In some embodiments, as shown in FIG14, the thickness of the portion of the first semiconductor layer in which crystallization points are formed is greater than the thickness of the remaining regions of the first semiconductor layer. Specifically, the orthographic projection of the portion of the first semiconductor layer in which crystallization points are formed overlaps with the orthographic projection of the crystallization points on the first surface. For example, the thickness of the first semiconductor layer covering the top region of the pyramid-like structure is greater than the thickness of the remaining regions of the first semiconductor layer. This configuration is beneficial for improving the absorption efficiency of long-wavelength light and the collection efficiency of the first semiconductor layer, thereby improving the power generation efficiency of the solar cell.

[0112] In some embodiments, the thickness of the crystallization region 1 is less than or equal to the thickness of the first semiconductor layer; when the first semiconductor layer includes a first doped semiconductor layer 12 and a first intrinsic semiconductor layer 11, the thickness of the crystallization region 1 is less than or equal to the sum of the thickness of the first doped semiconductor layer 12 and the thickness of the first intrinsic semiconductor layer 11.

[0113] For example, along the thickness direction of the semiconductor substrate 10, the crystallization region 1 may not be entirely crystallized (i.e., only some locations show increased crystallization, such as grains or ordered lattice arrangement in the amorphous layer). Starting from the surface of the first semiconductor layer away from the first surface, the thickness (i.e., depth) of the increased crystallization portion (i.e., the crystallization point) is greater than or equal to 3 nm to prevent the thickness of the crystallization region 1 from being too small, which would be detrimental to reducing the contact resistance of the crystallization region 1. For example, the thickness of the crystallization region 1 can be 3 nm, 3.5 nm, 4 nm, 4.5 nm, 5 nm, 5.5 nm, or 6 nm. Optionally, the thickness of the crystallization region 1 can be 5 nm to 10 nm.

[0114] The thickness of the first semiconductor layer is not specifically limited in this embodiment of the invention. For example, the thickness of the first doped semiconductor layer 12 can be 5nm to 60nm. For instance, the thickness of the first doped semiconductor layer 12 can be 5nm, 10nm, 15nm, 20nm, 25nm, 30nm, 35nm, 40nm, 45nm, 50nm, 55nm, or 60nm.

[0115] The thickness of the first intrinsic semiconductor layer 11 is 3nm to 25nm. For example, the thickness of the first intrinsic semiconductor layer 11 is 3nm, 5nm, 8nm, 10nm, 12nm, 15nm, 18nm, 20nm, 22nm or 25nm.

[0116] In some embodiments, the solar cell further includes a second semiconductor layer, the second semiconductor layer having the opposite conductivity type to the first semiconductor layer.

[0117] The solar cell can be a double-contact cell, with a second semiconductor layer disposed on a second surface. Alternatively, it can be a back-contact cell, with a second semiconductor layer disposed on a first surface, and the first and second semiconductor layers are alternately distributed. The first and second semiconductor layers on the first surface can be alternately distributed in a stripe pattern or an interdigitated pattern.

[0118] In this technical solution, when the second semiconductor layer comprises amorphous silicon and / or nanocrystalline silicon, the second semiconductor layer includes at least one processing region 01. The processing region 01 includes a plurality of strip-shaped crystallization regions 1 extending along a first direction and spaced apart along a second direction, and spacer regions 2 located between adjacent crystallization regions 1. The crystallization degree of the crystallization region 1 is greater than that of the spacer region 2. The crystallization region 1 includes nanocrystalline silicon and / or microcrystalline silicon. The characteristics and parameters of the second semiconductor layer and its crystallization regions 1 can be referred to those of the first semiconductor layer, and will not be repeated here. Of course, in some other embodiments, when the second semiconductor layer may include nanocrystalline silicon and / or microcrystalline silicon, it does not need to undergo crystallization treatment as a whole, and the second semiconductor layer as a whole or as a single strip has the same degree of crystallization.

[0119] In some embodiments, a second semiconductor layer is disposed on a first surface, and the first and second semiconductor layers are disposed alternately in sequence; along the second direction, the width of the processing area 01 disposed on the first semiconductor layer is smaller than the width of the first semiconductor layer. In the case of a back-contact solar cell, it is necessary to prevent the processing area 01 from extending along the second direction to the edge of the second semiconductor layer adjacent to the first semiconductor layer, in order to prevent the processing area 01 from extending to a region of opposite polarity, resulting in leakage.

[0120] like Figure 11 As shown, the second semiconductor layer may include amorphous silicon and / or nanocrystalline silicon, such as... Figure 13 As shown, the second semiconductor layer can be polycrystalline silicon or microcrystalline silicon. The second semiconductor layer has an adjacent side close to the adjacent first semiconductor layer, and the distance between the processing region 01 and the adjacent side is greater than zero. That is, a single processing region 01 is located between two adjacent second semiconductor layers, and the processing region 01 generally does not reach the adjacent side of either second semiconductor layer, unless there are laser precision or process errors. This configuration prevents the crystallized region 1 within the processing region 01 from extending to the adjacent side, avoiding leakage caused by lateral current transmission along the adjacent side, thereby improving battery efficiency.

[0121] In other embodiments, adding a first intrinsic semiconductor layer 11 can prevent leakage problems on the adjacent side of the second semiconductor layer. Therefore, when the thickness of the first intrinsic semiconductor layer 11 is greater than or equal to 7nm, the processing region 01 can also reach the adjacent side of the second semiconductor layer, and even the part where the first semiconductor layer and the second semiconductor layer are stacked.

[0122] See Figure 12 and Figure 15 Or see Figure 14 and Figure 15 Along the first direction, the semiconductor substrate 10 includes opposing third and fourth edges; the end of the first electrode 16 (e.g. Figure 15 The right end) and the third edge of the semiconductor substrate 10 (e.g. Figure 15 The distance between the right edges is less than the end of the processing area 01 (e.g., the distance between the right edges). Figure 15 The distance between the left end of the first electrode 16 and the third edge is configured such that the first electrode 16 can fully collect the current from the edge of the battery, while preventing the processing area 01 from being too close to the edge of the battery, which could lead to leakage. Along the first direction, the distance between the end of the first electrode 16 and the third edge can be 0.1-0.6 mm, while the distance between the end of the processing area 01 and the third edge can be 0.5-1.5 mm. Similarly, the other end of the first electrode 16 (e.g., the left end of the first electrode 16) and the third edge is also configured such that the first electrode 16 can fully collect the current from the edge of the battery, while preventing the processing area 01 from being too close to the edge of the battery, thus avoiding leakage. Figure 15 The left end) and the fourth edge of the semiconductor substrate 10 (e.g., the left end) and the fourth edge of the semiconductor substrate 10 (e.g. Figure 15 The distance between the right edges is smaller than that between the other end of the processing area (e.g., the distance between the right edges) and the other end of the processing area. Figure 15 The distance between the left end of the fourth edge and the fourth edge is within the range of the distance between the third edge and the fourth edge.

[0123] In some embodiments, see Figure 14 and Figure 15 For back-contact solar cells, the projection of a single processing region 01 on the first surface does not coincide with the projection of the second semiconductor layer on the first surface. Generally, see... Figure 14 and Figure 15 The processing region 01 is adjacent to the second semiconductor layer in both the first and second directions, but the distance from the adjacent side is greater than 0. Furthermore, the first surface where the second semiconductor layer is located is protruding compared to other first surfaces; that is, the substrate at the location of the first semiconductor layer between two adjacent semiconductor layers is a recessed surface, and the processing region 01 is located within the recessed surface. Optionally, the recessed surface has a textured structure with multiple pyramid-like structures. The first surface at the location of the second semiconductor layer is a polished surface with a recessed or protruding pyramidal base structure.

[0124] In practical applications, the embodiments of the present invention do not specifically limit the material and conductivity type of the semiconductor substrate 10. For example, the semiconductor substrate 10 can be a silicon substrate. Alternatively, the semiconductor substrate 10 can also be a substrate made of any semiconductor material, such as a germanium-silicon substrate, a germanium substrate, or a gallium arsenide substrate. The conductivity type of the semiconductor substrate 10 can be an N-type semiconductor substrate, a P-type semiconductor substrate, or an intrinsic semiconductor substrate.

[0125] Regarding the first and second semiconductor layers described above, in terms of doping type, the first semiconductor layer can be N-type doped, in which case the second semiconductor layer is P-type doped; alternatively, the first semiconductor layer can also be P-type doped, in which case the second semiconductor layer is N-type doped. This embodiment of the invention does not specifically limit the doping types of the first and second semiconductor layers, as long as their doping types are opposite. When the doping type is P-type, it is generally doped with Group III elements. When the doping type is N-type, it is generally doped with Group V or Group VI elements.

[0126] In addition, this application also provides a photovoltaic module, such as Figure 16 As shown, the photovoltaic module includes multiple solar cells as provided in any of the above embodiments and at least one interconnecting element, which connects two adjacent solar cells in series or parallel. When the solar cell is a double-sided contact cell, the interconnecting element includes a first interconnecting element 20 and a second interconnecting element 21. The two adjacent solar cells are the first solar cell and the second solar cell, respectively. The first interconnecting element 20 is connected to the electrode on the first surface of the first solar cell and extends to the electrode on the second surface of the second solar cell. Similarly, the second interconnecting element 21 is connected in the same way, forming an interconnect. When the solar cell is a back-contact solar cell, the interconnecting elements are all connected to the electrode on the first surface of the solar cell, forming an interconnect. In addition, when the first electrode 16 and the second electrode 17 are both fine grids, a main grid can be provided at the corresponding position of the interconnecting element. Current is transmitted through the semiconductor layer, the fine grid, the main grid, and the interconnecting element. Alternatively, a main grid can be omitted at the corresponding position of the interconnecting element, or only an end line near the edge of the cell can be provided. Current is transmitted through the semiconductor layer, the fine grid, and the interconnecting element.

[0127] Compared with the prior art, the beneficial effects of the photovoltaic module provided in this application are the same as those of the solar cell and the manufacturing method of the solar cell described above, and will not be repeated here.

[0128] In some embodiments, the projection of the interconnect on the semiconductor substrate 10 at least partially coincides with the projection of the crystallized region 1 on the semiconductor substrate 10. This arrangement reduces transmission losses between the crystallized region 1, the electrodes, and the interconnect, thereby improving power generation efficiency.

[0129] In some embodiments, the extension direction of the interconnect is perpendicular or parallel to the extension direction of the processing area 01, preferably, as shown in the figure. Figure 16 As shown, the extension direction of the interconnect is perpendicular to the extension direction of the processing region 01, so that the interconnect can be electrically connected to the crystallization region 1 of the multiple processing regions 01, and the current collected by the multiple processing regions 01 can be discharged in a timely manner.

[0130] In the description of the above embodiments, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.

[0131] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A method for manufacturing a solar cell, characterized in that, include: A semiconductor substrate is provided, the semiconductor substrate having opposing first and second surfaces; A first semiconductor layer and a second semiconductor layer are formed on the first surface. The first semiconductor layer and the second semiconductor layer have opposite conductivity types. The first semiconductor layer and the second semiconductor layer are alternately distributed. The first semiconductor layer includes amorphous silicon and / or nanocrystalline silicon. The first semiconductor layer includes at least one processing region. Along the second direction, the width of the processing area disposed on the first semiconductor layer is smaller than the width of the first semiconductor layer, such that the processing area cannot extend along the second direction to the edge of the second semiconductor layer adjacent to the first semiconductor layer; A portion of the processing area is irradiated with a laser along multiple paths, and the irradiated areas do not overlap, thereby increasing the crystallinity of the first semiconductor layer in the irradiated portion to form a crystallized region. The irradiated areas along the multiple paths each form a plurality of crystallized regions, and adjacent crystallized regions are separated by a spacer region.

2. The method for manufacturing a solar cell according to claim 1, characterized in that, Along the first direction, the laser irradiation path extends along a straight line, a bend, or a curve; and / or, along the second direction, the width D1 of the crystallized region is 20 μm to 600 μm; and / or, within the same processing region, multiple laser irradiation paths are parallel to each other, and along the second direction, the width D2 of the gap between adjacent crystallized regions is 2 μm to 300 μm; and / or, the number of processing regions is multiple and arranged along the second direction, and along the second direction, the distance D3 between adjacent processing regions is 500 μm to 1500 μm.

3. The method for manufacturing a solar cell according to claim 1, characterized in that, Along the first direction, the minimum distance D4 between the edge of the crystallized region and the edge of the first semiconductor layer is greater than or equal to 100 μm; and / or, along the second direction, the minimum distance D5 between the edge of the crystallized region and the edge of the first semiconductor layer is greater than or equal to 20 μm.

4. The method for manufacturing a solar cell according to claim 1, characterized in that, After forming a first semiconductor layer on the first surface and before irradiating a portion of the processed area with a laser along multiple paths, the method for manufacturing the solar cell further includes: forming a transparent conductive layer on the first surface, the transparent conductive layer being located on the side of the first semiconductor layer facing away from the semiconductor substrate; or, After irradiating a portion of the processing area with a laser along multiple paths, the method of manufacturing the solar cell further includes: forming a transparent conductive layer on the first surface, the transparent conductive layer being located on the side of the first semiconductor layer opposite to the semiconductor substrate.

5. The method for manufacturing a solar cell according to claim 1, characterized in that, After irradiating a portion of the processing area with a laser along multiple paths, the method of manufacturing the solar cell further includes: forming a first electrode on the first surface, wherein the orthographic projection of each first electrode on the first surface at least partially overlaps with the orthographic projection of a crystallized region within the processing area on the first surface.

6. The method for manufacturing a solar cell according to claim 1, characterized in that, At least a portion of the first surface of the semiconductor substrate is textured, and multiple pyramid-like structures are formed on the textured surface; The first semiconductor layer is formed at least on the textured surface of the first surface; the crystallization region covers the textured surface, and the crystallization region includes a plurality of crystallization points, which cover the top regions of the plurality of pyramid-like structures.

7. A solar cell, characterized in that, include: A semiconductor substrate having opposing first and second surfaces; A first semiconductor layer and a second semiconductor layer are disposed on the first surface, and the first semiconductor layer and the second semiconductor layer are alternately distributed. The first semiconductor layer includes amorphous silicon and / or nanocrystalline silicon. The first semiconductor layer includes at least one processing region. A portion of the processing region is irradiated by a laser along multiple paths, and the irradiated areas along the multiple paths do not overlap, thereby increasing the crystallinity of the first semiconductor layer in the irradiated portion to form a crystallized region. The irradiated areas along the multiple paths respectively form multiple crystallized regions. The processing region includes multiple strip-shaped crystallized regions extending along a first direction and spaced apart along a second direction, as well as spacer regions located between adjacent crystallized regions. The crystallinity of the crystallized region is greater than that of the spacer regions. The crystallized region includes nanocrystalline silicon and / or microcrystalline silicon. Along the second direction, the width of the processing area disposed on the first semiconductor layer is smaller than the width of the first semiconductor layer, such that the processing area cannot extend along the second direction to the edge of the second semiconductor layer adjacent to the first semiconductor layer; A first electrode, the orthographic projection of the first electrode onto the first surface at least partially overlaps with the orthographic projection of a crystallized region within the processing region onto the first surface.

8. The solar cell according to claim 7, characterized in that, Within the same processing region, along the second direction, the width D2 of the interval between adjacent crystallization regions is 2μm-300μm; and / or, along the second direction, the width D1 of the crystallization region is 20μm-600μm; and / or, along the second direction, the width of the processing region is 100μm-600μm.

9. The solar cell according to claim 7, characterized in that, Both the first electrode and the processing area are multiple electrodes that extend along a first direction and are spaced apart along a second direction, with each of the multiple first electrodes corresponding to one of the multiple processing areas.

10. The solar cell according to claim 7, characterized in that, The semiconductor substrate includes a first edge and a second edge disposed opposite to each other along a first direction, and the processing region includes a first processing region and a second processing region; along a second direction, the second processing region is located between the first processing region and the first edge; Wherein, the number of crystallized regions contained in the first processing region is the same as the number of crystallized regions contained in the second processing region; or, there are multiple first processing regions, and along the second direction, the absolute value of the difference between the widths of any two first processing regions is less than or equal to 50 μm; or, the number of crystallized regions contained in the second processing region is less than the number of crystallized regions contained in the first processing region.

11. The solar cell according to claim 7, characterized in that, The orthographic projection of the first electrode onto the first surface at least partially overlaps with the orthographic projection of a spacer region within the processing area onto the first surface.

12. The solar cell according to claim 7, characterized in that, Along the second direction, the ratio of the width of the first electrode to the width of the spacing region is greater than or equal to 2; and / or, along the first direction, the distance between the end of the first electrode and the third edge of the semiconductor layer substrate is less than the distance between the end of the processing region and the third edge, the third edge being adjacent to the end of the first electrode.

13. The solar cell according to claim 7, characterized in that, At least a portion of the first surface of the semiconductor substrate is textured, and multiple pyramid-like structures are formed on the textured surface; The crystallized region covers the velvety surface, and the crystallized region includes multiple crystallization points, which cover the top areas of the multiple pyramid-like structures.

14. The solar cell according to claim 13, characterized in that, Along the thickness direction of the semiconductor substrate, the number of grains within the crystallization point gradually decreases; and / or, the crystallization point includes bubbles, with the diameter of a single bubble being 2 nm to 100 nm; and / or, the crystallization point includes bubbles, with multiple bubbles agglomerated to form a bubble cluster, the diameter of the bubble cluster being 200 nm to 1000 nm; and / or, the crystallization point includes bubbles, with the size of bubbles closer to the top of the pyramid-like structure being larger than the size of bubbles farther from the top of the pyramid-like structure; and / or, the crystallization point includes bubbles, with the number of bubbles closer to the top of the pyramid-like structure being greater than the number of bubbles farther from the top of the pyramid-like structure; and / or, the thickness of the portion of the first semiconductor layer in which the crystallization point is formed is greater than the thickness of the remaining area of ​​the first semiconductor layer; and / or, the orthographic projection of the crystallization point on the semiconductor substrate is circular, elliptical, square, or irregular in shape.

15. The solar cell according to claim 7, characterized in that, Along the thickness direction of the semiconductor substrate, the thickness of the crystallization point of the crystallization region is greater than or equal to 3 nm; and / or, the first semiconductor layer includes a first doped semiconductor layer and a first intrinsic semiconductor layer, the first intrinsic semiconductor layer is located on the side of the first doped semiconductor layer close to the semiconductor substrate, the thickness of the first doped semiconductor layer is 5 nm to 60 nm, and the thickness of the first intrinsic semiconductor layer is 3 nm to 25 nm.

16. The solar cell according to claim 7, characterized in that, The solar cell also includes a second electrode.

17. The solar cell according to claim 7, characterized in that, The second semiconductor layer has an adjacent side close to the first semiconductor layer, and the distance between the processing region and the adjacent side is greater than 0; and / or, along the second direction, the width of the processing region is greater than the width of the second semiconductor layer; And / or, along the second direction, the width of the processing area is greater than the width of the portion of the second semiconductor layer not covered by the first semiconductor layer.

18. The solar cell according to claim 7, characterized in that, The solar cell also includes a transparent conductive layer, which is disposed at least between the first semiconductor layer and the first electrode.

19. A photovoltaic module, characterized in that, It includes a plurality of solar cells as described in any one of claims 7 to 18 and at least one interconnecting element, said interconnecting element connecting two adjacent solar cells in series or in parallel.

20. The photovoltaic module according to claim 19, characterized in that, The projection of the interconnect on the semiconductor substrate at least partially coincides with the projection of the crystallized region on the semiconductor substrate; and / or, the extension direction of the interconnect is perpendicular or parallel to the extension direction of the processing region.

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