A method for testing a microsystem interconnect based on a core particle

Abstract

The application discloses a kind of based on core particle microsystem interconnection test method, belong to chip test technical field;Among them, the structure of core particle microsystem is analyzed, the number of core particle microsystem interconnection network is determined, classification is carried out for interconnection network, mainly including boundary scan chip interconnection network and mixed interconnection network, test vector is automatically generated based on boundary scan technology, test vector is loaded and run by ATE, and the mixed interconnection network is tested by design implementation test system, if determining that the mixed interconnection network has fault, boundary scan test program is triggered, and the fault type is diagnosed by boundary scan test method. By boundary scan test in combination with implementation test technology, under the premise that hardware cost is not increased, implementation test and boundary scan test cross-platform fusion are realized, high coverage rate test of core particle microsystem interconnection network is realized, and the application quality of core particle microsystem is guaranteed.

Description

Technical Field

[0001] This application relates to the field of integrated circuit testing technology, and in particular to a chip-based microsystem interconnection testing method. Background Technology

[0002] In the field of microsystems technology, chiplet microsystems, as an emerging technological architecture, are gradually gaining prominence. A chiplet microsystem integrates multiple chips into a single package, achieving advantages such as high density, miniaturization, and high performance. The interconnections between the chips in a chiplet microsystem are extremely complex.

[0003] However, interconnectivity is crucial in the construction of microsystem-on-chips (MICs), and the stability and maturity of the packaging process are key factors affecting interconnect quality, which in turn impacts the overall performance of the MIC. Therefore, conducting comprehensive and in-depth interconnect testing on MICs is particularly important and critical. The testing must fully cover all possible fault scenarios in the inter-chip connections, such as open circuits, short circuits, and bridging, to ensure the stable operation and performance of the MIC in practical applications.

[0004] Currently, existing interconnect testing methods have the following defects and shortcomings:

[0005] 1. Limited testing strategies and insufficient coverage: Existing methods fail to achieve ideal fault coverage for hybrid interconnect networks that simultaneously contain boundary scan chips and non-boundary scan chips due to the lack of classification testing strategies.

[0006] 2. Vague localization: Real-world testing addresses the overall interconnect testing problem. If an interconnect testing problem occurs during real-world testing, the system can only locate the problem in a group of interconnects, but cannot pinpoint which specific line is faulty. Furthermore, boundary scan technology is limited by the chip's support characteristics, making it difficult to effectively cover the interconnect network of non-scanned chips, resulting in a relatively coarse granularity of fault diagnosis.

[0007] 3. Low testing efficiency: Traditional boundary scan testing methods rely on dedicated testing equipment and are extremely cumbersome and complex in terms of test vector generation and loading processes, which is difficult to match with the high-efficiency production pace pursued by automated test equipment (ATE), thus seriously affecting the overall testing efficiency.

[0008] 4. Cost and compatibility issues: Existing interconnect testing methods often require additional dedicated hardware and software, which undoubtedly increases testing costs. Moreover, such methods are difficult to be compatible with diverse chip microsystem architectures, which greatly limits their application scope and flexibility.

[0009] Existing technologies have not yet provided effective solutions to the aforementioned problems. For example, relying solely on boundary scan testing may overlook interconnect defects in non-scanned chips, while practical testing alone cannot achieve accurate fault location. Furthermore, traditional interconnect testing methods have not adequately considered optimizations for the design for testability of chip microsystems, resulting in poor versatility of testing solutions, especially in high-density packaging scenarios, making it difficult to meet the stringent quality control requirements of mass production. Summary of the Invention

[0010] To address the shortcomings of the existing technologies, this application provides a chip-based microsystem interconnection testing method that achieves high coverage testing of chip-based microsystem interconnection networks without increasing hardware costs.

[0011] The technical solution is as follows:

[0012] A chip-based microsystem interconnect testing method is provided, including:

[0013] Step S1: Analyze the chip microsystem structure and classify the chip microsystem interconnect network into boundary scan chip interconnect network and hybrid interconnect network;

[0014] Step S2: Generate test vectors based on boundary scan technology, load and run the test vectors through automated test equipment (ATE) to cover faults in the boundary scan chip interconnect network;

[0015] Step S3: Design an actual test system to test the hybrid interconnection network. If the hybrid interconnection network is found to be faulty, trigger the boundary scan test program to diagnose the fault type through the boundary scan test method.

[0016] Step S4: Combining the test results from steps S2 and S3, output the global fault coverage of the chip microsystem interconnect network.

[0017] Furthermore, the interconnect networks of the chip microsystems are classified according to whether the chip supports boundary scan technology, specifically including:

[0018] Boundary scan chip interconnect network: The chips connected at both ends of the interconnect network support boundary scan technology;

[0019] Hybrid interconnection network: One end of the interconnection network is connected to the boundary scan chip, and the other end is connected to the non-boundary scan chip.

[0020] Furthermore, the boundary scan chip interconnect network includes an interconnect network of DSP microcomponents and FPGA microcomponents.

[0021] Furthermore, the hybrid interconnect network includes at least the interconnect network between NAND FLASH and CIB, the interconnect network between DSP microcomponents and CIB, the interconnect network between FPGA microcomponents and CIB, the interconnect network between NOR FLASH single chip and FPGA single chip, the interconnect network between DDR single chip and FPGA single chip, and the interconnect network between NOR FLASH single chip and DSP single chip.

[0022] Furthermore, the physical testing system includes: a DC regulated power supply, a DC / DC converter, a programmable device, a host computer, a CPU core board, a crystal oscillator, a memory, an FPGA core board, and a microsystem chip. The DC regulated power supply is connected to the DC / DC converter, the DC / DC converter is connected to the microsystem chip, the programmable device is connected to both the DC / DC converter and the host computer, the host computer is connected to both the programmable device and the microsystem chip, and the microsystem chip is connected to the CPU core board, the crystal oscillator, the memory, and the FPGA core board. Simultaneously, the physical system is integrated with the boundary scan system. The host computer is connected to the boundary scan testing system, and the boundary scan testing system is connected to the microsystem chip. The programmable device controls the power-on timing and reset signal, and runs a functional test program to perform full address read / write verification and interface protocol testing on the non-boundary scan chip interconnect network.

[0023] Furthermore, the full address read / write verification includes:

[0024] DSP and NOR FLASH interconnection verification: Perform full address erase and read / write tests on the NOR FLASH through the DSP's SPI interface, and compare the consistency of read and write data. If they are consistent, the interconnection network between the DSP and NOR FLASH is determined to be fault-free.

[0025] FPGA and DDR interconnection verification: The DDR is initialized and full address read and write tests are performed by loading the test program on the FPGA. The consistency of read and write data is compared. If the consistency is consistent, the FPGA and DDR interconnection network is determined to be fault-free.

[0026] DSP and DDR interconnection verification: The DSP loads the test program to initialize the DDR and perform full address read and write tests. The consistency of read and write data is compared. If they are consistent, the DSP and DDR interconnection network is determined to be fault-free.

[0027] CIB and NAND Flash Interconnection Verification: Connect the CIB chip to the simulator and run the test program to perform full address read and write tests on the NAND Flash. Compare the read and write data consistency. If they are consistent, the CIB and NAND Flash interconnection network is determined to be fault-free.

[0028] Furthermore, the interface protocol test includes:

[0029] SRIO write operation verification: Run the SRIO data write request instruction in the FPGA or DSP to send a write data packet request to the SRIO interface of the CIB. After receiving the write request, the CIB chip performs a data packet exchange operation and returns a write response packet to the FPGA or DSP after the operation is completed.

[0030] SRIO read operation verification involves running an SRIO data read request instruction in the FPGA or DSP to send a read data packet request to the CIB's SRIO interface; after receiving the read request, the CIB chip performs a data packet exchange operation and returns a read response packet to the FPGA or DSP after the operation is completed.

[0031] If both the write response packet and the read response packet conform to the protocol specifications and the data is complete, then the SRIO interconnect network between the CIB chip and the FPGA / DSP chip is determined to be fault-free.

[0032] Furthermore, the method is applicable to chip microsystems comprising the following components:

[0033] At least one CIB chip, FPGA micro-component, DSP micro-component, and NAND Flash micro-component;

[0034] The FPGA micro-component and DSP micro-component are interconnected through SRIO X4 interface and EMIF interface, and the CIB chip is connected to the FPGA micro-component and DSP micro-component respectively through SRIO X4 interface.

[0035] The technical solution includes at least the following technical effects:

[0036] The structure of the chip-level microsystem was analyzed to determine the number of interconnect networks. These interconnect networks were then categorized, primarily including boundary scan chip interconnect networks and hybrid interconnect networks (combining boundary scan and non-boundary scan chip interconnect networks). Test vectors were automatically generated based on boundary scan technology, and these vectors were loaded and run using ATE (Automatic Test Equipment) to cover faults in the boundary scan chip interconnect networks. Simultaneously, a practical testing system was designed to cover faults in the hybrid interconnect networks, incorporating practical testing techniques. By combining boundary scan testing with practical testing techniques, high coverage testing of the chip-level microsystem interconnect networks (target coverage reaching 100%) was achieved without increasing hardware costs, ensuring the application quality of the chip-level microsystem.

[0037] It should be understood that the above general description and the following detailed description are merely exemplary and do not limit this application. Attached Figure Description

[0038] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0039] Figure 1 A flowchart of a chip-based microsystem interconnection testing method provided in one embodiment of this application;

[0040] Figure 2 This is a schematic diagram of a chip microsystem structure provided in an embodiment of this application;

[0041] Figure 3 This application provides a flowchart for testing the interconnect network of a boundary scan chip according to an embodiment of the present application.

[0042] Figure 4 This is a schematic diagram of the physical and boundary scan test system structure provided in an embodiment of this application. Detailed Implementation

[0043] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0044] As attached Figure 1 As shown, this application provides a chip-based microsystem interconnect testing method that addresses the problem of testing interconnects between chips, enabling high-coverage microsystem interconnect testing without increasing the cost of existing microsystem testing methods; it includes the following steps:

[0045] Step S1: Analyze the chip microsystem structure and classify the chip microsystem interconnect network into boundary scan chip interconnect network and hybrid interconnect network (boundary scan chip and non-boundary scan chip interconnect network);

[0046] Step S2: Generate test vectors based on boundary scan technology, load and run the test vectors through an automated test device to cover faults in the interconnect network of the boundary scan chip;

[0047] Step S3: Design an implementation test system to test the hybrid interconnection network. If the hybrid interconnection network is found to be faulty, trigger the boundary scan test program to diagnose the fault type and cover the faults of the hybrid interconnection network.

[0048] Step S4: Combining the test results from steps S2 and S3, output the global fault coverage of the chip microsystem interconnect network.

[0049] By combining boundary scan testing with actual testing techniques, high coverage testing of the interconnect network of the chip microsystem can be achieved without increasing hardware costs, with a target coverage of 100%, thereby effectively ensuring the application quality of the chip microsystem.

[0050] It's important to note that boundary scan testing isn't limited to boundary scan-based chip interconnects; it can also test hybrid interconnects. Prioritizing boundary scan testing for chip interconnects improves testing efficiency, while using a physical test system is more efficient for hybrid interconnects. Therefore, for hybrid networks, the physical test system is used first to detect faults. Only when the physical test system detects a problem (i.e., a fault in the interconnect) is boundary scan testing initiated to pinpoint whether it's an open-circuit or short-circuit fault. The physical test system addresses overall interconnect testing; if an interconnect testing problem occurs during physical testing, it can only locate a group of interconnects with a problem, not the specific wire. Boundary scan testing can pinpoint the location of the faulty wire, compensating for the limitations of physical testing.

[0051] Existing technologies use physical testing systems for module functional testing, while the physical testing system used in this application is for interconnection testing between modules. The physical testing system detects interconnection network faults, triggers a boundary scan test program, and then locates the faulty interconnect line through the boundary scan test. Unlike functional testing solutions, the physical testing system used in this application focuses more on interconnection coverage, not just the functional testing of a specific module. Furthermore, unlike existing technologies where physical testing and boundary scan testing are distributed platforms, this application integrates physical testing and boundary scan testing across platforms, improving both testing efficiency and fault location accuracy.

[0052] In one embodiment, such as Figure 2 As shown, the chip microsystem structure is analyzed, mainly consisting of one CIB (Chiplet Interconnect Bus), two FPGA micro-components, two DSP micro-components, and one Nand Flash micro-component. The FPGA micro-components include Nor Flash, FPGA, and DDR micro-components, while the DSP micro-components include DSP, Nor Flash, and DDR micro-components. The CIB connects to the FPGA and DSP micro-components via SRIO X4 interfaces and to the Nand Flash micro-component via a Nand interface. The FPGA and DSP micro-components are connected via SRIO X4 and EMIF interfaces.

[0053] Determine the number of interconnects in the chip microsystem, classify the interconnects, first perform microsystem testability design, and then classify the interconnects according to the specific product.

[0054] In one embodiment, the interconnect network of the chip microsystem is classified according to whether the chip supports boundary scan technology. Interconnect networks where both ends of the interconnect network support boundary scan technology are classified as boundary scan chip interconnect networks; interconnect networks where one end connects to a boundary scan chip and the other end connects to a non-boundary scan chip are classified as hybrid interconnect networks (boundary scan chip and non-boundary scan chip interconnect networks).

[0055] In this embodiment, the chip microsystem interconnect network mainly includes a boundary scan chip interconnect network and a hybrid interconnect network, as shown in Table 1.

[0056] Table 1 Classification of Internetworks

[0057]

[0058]

[0059] Test vectors are automatically generated based on boundary scan technology. These test vectors are then loaded and run using an ATE (Automatic Test Equipment) to cover faults in the interconnect network of the boundary scan chip. The microsystem is configured according to the type and model of the integrated circuit. The DSP's EXTEST instruction is parsed from the DSP's boundary scan file (BSDL), and the FPGA's EXTEST instruction is parsed from the FPGA's boundary scan file (BSDL). After the microsystem is configured, test vectors adapted to the ATE are generated based on the EXTEST instructions. These test vectors are compared with the actual response vectors. If they match, the interconnect network is considered fault-free, and the chip under test is normal; otherwise, the chip under test is considered faulty, and the interconnect network is faulty. Specifically, as shown... Figure 3 As shown.

[0060] DSP stands for Digital Signal Processing chip. Internally, DSP chips employ a Harvard architecture that separates program and data processing, have dedicated hardware multipliers, widely utilize pipelined operation, and provide special DSP instructions for rapidly implementing various digital signal processing algorithms. FPGA is a further development based on programmable devices such as PAL and GAL. It emerged as a semi-custom circuit in the field of Application-Specific Integrated Circuits (ASICs), addressing the shortcomings of custom circuits while overcoming the limited gate count of traditional programmable devices. A BSDL file is an IEEE 1149.1 or JTAG design datasheet describing an IC. The EXTEST instruction indicates that the IC is operating in boundary scan external test mode, meaning that operations on the IC affect its normal operation. It is used for external chip testing. The output pins in test mode have BSC update latch drivers and BSCscan latch-captured input data shift operations. Test stimuli can be input from TDI, and the test response can be observed from TDO. After the shift operation, the new test stimulus is stored in the BSC update latch.

[0061] like Figure 4 As shown, a practical system is designed to test a hybrid interconnect network. If a fault is detected in the hybrid interconnect network, a boundary scan test method is used to diagnose the fault type and cover the faults in the hybrid interconnect network. The practical system mainly includes a DC regulated power supply, a DC / DC converter, a programmable device, a host computer, a CPU core board, a crystal oscillator, a memory, an FPGA core board, and a microsystem chip. The DC regulated power supply is connected to the DC / DC converter, the DC / DC converter is connected to the microsystem chip, the programmable device is connected to both the DC / DC converter and the host computer, and the host computer is connected to both the programmable device and the microsystem chip. Simultaneously, the microsystem chip is connected to the CPU core board, the crystal oscillator, the memory, and the FPGA core board. Furthermore, the practical system is integrated with the boundary scan system. The host computer is connected to the boundary scan test system, and the boundary scan test system is connected to the microsystem chip. The programmable device controls the power-on timing and reset signal, and runs a functional test program to perform full address read / write verification and interface protocol testing on the non-boundary scan chip interconnect network.

[0062] The implemented system uses a series of testing steps, such as FPGA programming, DSP SPI interface testing, DDR initialization and read / write testing, NAND Flash full address testing, and SRIO interface testing, to detect faults in the interconnect network between chips in the microprocessor system. If a fault is found in the hybrid interconnect network, a boundary scan test program is triggered to diagnose the fault type using the boundary scan test method. The specific steps are as follows:

[0063] The voltage regulator provides the necessary voltage for the microsystem chip to operate via a DC / DC converter. The circuit's power-on timing and reset signal are controlled by the onboard programmable device (FPGA). The host computer inputs instructions to the FPGA to control its operation. The crystal oscillator provides the clock signal to the microsystem.

[0064] If the FPGA program can be successfully programmed into the internal NOR FLASH and the FPGA can be successfully booted, it indicates that there is no fault in the interconnection network between the FPGA chip and the NOR FLASH chip.

[0065] The DSP erases the built-in NOR FLASH through the SPI interface, traverses all addresses for read and write tests, and compares whether the read and written data are consistent. If they are consistent, the test passes, indicating that the interconnection network between the DSP chip and the NOR FLASH chip is fault-free.

[0066] The FPGA chip loads the test program from the NOR FLASH and initializes the DDR. After initialization, the test program performs full address read and write operations on the DDR and compares the read and write data to see if they are consistent. If they are consistent, the test passes, indicating that the interconnection network between the FPGA chip and the DDR chip is fault-free.

[0067] The DSP chip loads the test program from the NOR FLASH and initializes the DDR. After initialization, the test program performs full address read and write operations on the DDR and compares the read and write data to see if they are consistent. If they are consistent, the test passes, indicating that the interconnection network between the DSP chip and the DDR chip is fault-free.

[0068] Connect the CIB chip to the emulator and run the test program to perform a full address test on the NAND Flash. Compare whether the read and write data are consistent. If they are consistent, the test passes, indicating that the interconnection network between the CIB chip and the NAND Flash chip is fault-free.

[0069] Configure the CIB's SRIO interface mode. Run an SRIO data write request command in the FPGA / DSP to send a write data packet request to the CIB's SRIO interface. After the CIB chip receives the write request command, it performs a data packet exchange operation and returns a write response packet to the FPGA / DSP after the exchange is complete. After this event, run an SRIO data read request command in the FPGA / DSP to send a read data packet request to the CIB's SRIO interface. After the CIB chip receives the read request command, it performs a data packet exchange operation and returns a read response packet to the FPGA / DSP after the exchange is complete. If this functionality is achieved, it indicates that the interconnection network between the CIB chip and the FPGA / DSP chip is fault-free.

[0070] If a fault is detected in the hybrid interconnection network, a boundary scan test program is triggered. The fault type is then diagnosed using the boundary scan test method, specifically identifying which line is faulty and whether it is an open circuit or a short circuit.

[0071] The boundary scanning system is integrated with the physical system, the host computer is connected to the boundary scanning test system, and the boundary scanning test system is connected to the microsystem chip.

[0072] Based on the test results of the two testing methods mentioned above, the global fault coverage of the chip microsystem interconnect network is output.

[0073] This method achieves high coverage testing (target coverage of 100%) of microsystem interconnect networks without increasing hardware costs through the coordinated use of chip-level microsystem interconnect network classification, boundary scan testing, and implementation testing. The specific logic is as follows:

[0074] First, interconnect network classification serves as the basis for testing strategy decisions. By analyzing the chip microsystem architecture, interconnect networks are divided into two categories: one is chip interconnects where both ends support boundary scan technology (such as the EMIF interface between a DSP and an FPGA); the other is hybrid interconnects where one end is a boundary scan chip and the other end is a non-boundary scan chip (such as the SPI interface between an FPGA and NOR Flash, or the interconnect between a CIB and NAND Flash). This classification directly determines the allocation of test resources—boundary scan testing is prioritized for boundary scan interconnect networks to reduce costs, while physical testing must be relied upon to cover the physical connections for hybrid interconnect networks. This classification mechanism avoids the resource waste caused by blindly selecting methods in traditional testing, such as avoiding invalid tests resulting from forcibly using boundary scan technology on non-scanning chips.

[0075] Secondly, boundary scan testing and physical testing complement each other. For boundary scan interconnect networks, the EXTEST instruction set is generated by parsing the BSDL files of chips such as DSPs and FPGAs, and the test vectors are loaded by the automated test equipment (ATE). By comparing the response data bit by bit, the specific faulty pin or line can be accurately located (e.g., a short circuit in a data line of the EMIF interface). However, this method cannot cover interconnects with non-boundary scan chips (such as Flash and DDR). In this case, physical testing needs to be initiated: by constructing a physical test system that includes programmable devices, clock modules, and multiple types of memory interfaces, full address read / write verification (e.g., DSP traversing the NOR Flash address space via the SPI interface) and protocol interaction testing (e.g., SRIO data packet exchange between FPGA and CIB) are performed to verify the physical connectivity and signal integrity of the hybrid interconnect network. However, physical testing can only determine whether there is an anomaly in the interconnect group (e.g., "FPGA and DDR interconnect failure"), but cannot locate the specific faulty line. Further boundary scan testing is required for root cause diagnosis.

[0076] Ultimately, the dynamic collaboration of these three components achieves global coverage. When the implementation test detects an anomaly in a hybrid interconnect network (such as a communication failure between the CIB and NAND Flash), the system automatically triggers a boundary scan test, scanning the interconnect lines of the relevant boundary scan chips line by line (such as the SRIO interface connected to the CIB) to quickly locate the specific fault point (such as an open circuit in the SRIO data line). A classification mechanism ensures no interconnect network is missed, boundary scan testing provides high-precision diagnostics, and implementation testing covers physical layer blind spots. The combination of these two methods outputs a global fault coverage report. This collaborative mechanism reduces costs while addressing the shortcomings of traditional implementation testing—"only detecting problems, but not locating them"—and overcoming the limitation of single boundary scan technology being ineffective for non-scanned devices, ultimately achieving a complete closed-loop test for the microsystem interconnect network.

[0077] Although preferred embodiments of the invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including both the preferred embodiments and all changes and modifications falling within the scope of the invention.

[0078] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.

Claims

1. A chip-based microsystem interconnection testing method, characterized in that, include: Step S1: Analyze the chip microsystem structure and classify the interconnect network of the chip microsystem into boundary scan chip interconnect network and hybrid interconnect network; wherein, the boundary scan chip interconnect network is in which the chips connected at both ends of the interconnect network support boundary scan technology; the hybrid interconnect network is in which one end of the interconnect network is connected to a boundary scan chip and the other end is connected to a non-boundary scan chip. Step S2: Generate test vectors based on boundary scan technology, load and run the test vectors through an automated test device to cover faults in the interconnect network of the boundary scan chip; Step S3: Design an actual test system to test the hybrid interconnection network. If the hybrid interconnection network is found to be faulty, trigger the boundary scan test program to diagnose the fault type through the boundary scan test method. Step S4: Combining the test results from steps S2 and S3, output the global fault coverage of the chip microsystem interconnect network.

2. The chip-based microsystem interconnection testing method according to claim 1, characterized in that, The boundary scan chip interconnect network includes an interconnect network of DSP microcomponents and FPGA microcomponents.

3. The chip-based microsystem interconnection testing method according to claim 1, characterized in that, The hybrid interconnect network includes at least the following interconnect networks: the interconnect network between NAND FLASH and CIB, the interconnect network between DSP microcomponents and CIB, the interconnect network between FPGA microcomponents and CIB, the interconnect network between NOR FLASH single chip and FPGA single chip, the interconnect network between DDR single chip and FPGA single chip, and the interconnect network between NOR FLASH single chip and DSP single chip.

4. The chip-based microsystem interconnection testing method according to claim 1, characterized in that, The specific steps for generating test vectors based on boundary scan technology and loading and running the test vectors using automated testing equipment include: Configure the state of the chip microsystem according to the type and model of the integrated circuit; The EXTEST instruction of the DSP is parsed from the DSP's boundary scan file BSDL; The EXTEST instruction of the FPGA is parsed from the FPGA boundary scan file BSDL. After the microsystem is configured, test vectors adapted to the ATE device are generated according to the EXTEST command; The test vector is compared with the actual response vector. If they match, the interconnection network is determined to be fault-free and the chip under test is normal.

5. The chip-based microsystem interconnection testing method according to claim 1, characterized in that, The physical test system includes: a DC regulated power supply, a DC / DC converter, a programmable device, a host computer, a CPU core board, a crystal oscillator, a memory, an FPGA core board, and a microsystem chip. The DC regulated power supply is connected to the DC / DC converter, the DC / DC converter is connected to the microsystem chip, the programmable device is connected to both the DC / DC converter and the host computer, the host computer is connected to both the programmable device and the microsystem chip, and the microsystem chip is connected to the CPU core board, the crystal oscillator, the memory, and the FPGA core board. The physical test system is integrated with the boundary scan test system, the host computer is connected to the boundary scan test system, and the boundary scan test system is connected to the microsystem chip. The programmable device controls the power-on timing and reset signal, and runs a functional test program to perform full address read / write verification and interface protocol testing on the hybrid interconnect network.

6. The chip-based microsystem interconnection testing method according to claim 5, characterized in that, The full address read / write verification includes: DSP and NOR FLASH interconnection verification: Perform full address erase and read / write tests on the NOR FLASH through the DSP's SPI interface, and compare the consistency of read and write data. If they are consistent, the interconnection network between the DSP and NOR FLASH is determined to be fault-free. FPGA and DDR interconnection verification: The DDR is initialized and full address read and write tests are performed by loading the test program on the FPGA. The consistency of read and write data is compared. If the consistency is consistent, the FPGA and DDR interconnection network is determined to be fault-free. DSP and DDR interconnection verification: The DSP loads the test program to initialize the DDR and perform full address read and write tests. The consistency of read and write data is compared. If they are consistent, the DSP and DDR interconnection network is determined to be fault-free. CIB and NAND FLASH Interconnection Verification: Connect the CIB chip to the simulator and run the test program to perform full address read and write tests on the NAND FLASH. Compare the read and write data consistency. If they are consistent, the CIB and NAND FLASH interconnection network is determined to be fault-free.

7. The chip-based microsystem interconnection testing method according to claim 5, characterized in that, The interface protocol test includes: SRIO write operation verification: Run the SRIO data write request instruction in the FPGA or DSP to send a write data packet request to the SRIO interface of the CIB. After receiving the write request, the CIB chip performs a data packet exchange operation and returns a write response packet to the FPGA or DSP after the operation is completed. SRIO read operation verification involves running an SRIO data read request instruction in the FPGA or DSP to send a read data packet request to the CIB's SRIO interface; after receiving the read request, the CIB chip performs a data packet exchange operation and returns a read response packet to the FPGA or DSP after the operation is completed. If both the write response packet and the read response packet conform to the protocol specifications and the data is complete, then the SRIO interconnect network between the CIB chip and the FPGA / DSP chip is determined to be fault-free.

8. The chip-based microsystem interconnection testing method according to claim 1, characterized in that, The method is applicable to chip microsystems that include the following components: At least one CIB chip, FPGA micro-component, DSP micro-component, or NAND FLASH micro-component; The FPGA micro-component and DSP micro-component are interconnected through SRIO X4 interface and EMIF interface, and the CIB chip is connected to the FPGA micro-component and DSP micro-component respectively through SRIO X4 interface.

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