A method and apparatus for determining a storage device timing pattern calibration delay combination

Abstract

The embodiment of the application provides a kind of storage device timing mode calibration delay combination determination method and device, it is related to storage technical field.The method comprises: obtaining a first delay value that is set for the write channel of storage device in advance, and b second delay value that is set for the read channel of storage device in advance, respectively using all delay combinations formed by each first delay value and each second delay value to carry out timing mode calibration test;According to the test result of timing mode calibration test, determine the first element corresponding to each delay combination respectively, and determine the first test result set;According to the delay combination corresponding to each first element in the first test result set, determine target delay combination and set the delay of the write channel of storage device as the first delay value in target delay combination, set the delay of the read channel of storage device as the second delay value in target delay combination.The robustness of data transmission can be improved by using the embodiment of the application.

Description

Technical Field

[0001] This application relates to the field of storage technology, and in particular to a method and apparatus for determining the timing mode calibration delay combination of a storage device. Background Technology

[0002] To ensure that the storage device controller can accurately write and read data from the non-volatile storage medium, it is necessary to properly configure the read and write latency between the storage device controller and the non-volatile storage medium.

[0003] In related technologies, when setting read latency and write latency, the performance of different latency combinations consisting of read latency and write latency is usually tested through TMC (Timing Mode Calibration). Then, based on the test results, a latency combination that can be read and written normally is selected from the multiple latency combinations tested, and the read latency and write latency are configured for the storage medium according to the selected latency combination.

[0004] However, due to various limitations, the actual read and write latency may differ from the set read and write latency. Therefore, although the selected latency combination may allow for normal read and write operations, the actual read and write latency may still prevent normal read and write operations. It is evident that determining the read and write latency directly affects the robustness of data transmission. Summary of the Invention

[0005] The purpose of this application is to provide a method and apparatus for determining the timing mode calibration latency combination of a storage device, so as to determine a more reasonable read latency and write latency, thereby improving the robustness of data transmission. The specific technical solution is as follows:

[0006] A first aspect of this application provides a method for determining a timing mode calibration delay combination for a storage device, the method comprising:

[0007] Obtain *a* first delay values ​​pre-set for the write channel of the storage device, and *b* second delay values ​​pre-set for the read channel of the storage device, X i >X i+1 or X i <X i+1 And Y i >Y i+1 Or Y i <Y i+1 X i For the i-th first delay value, Y j Let be the j-th second delay value, i = 1, 2, 3...a, j = 1, 2, 3...b, where a and b are natural numbers greater than 1;

[0008] Timing mode calibration tests were performed using all delay combinations formed by each of the first delay values ​​and each of the second delay values.

[0009] Based on the test results of the timing mode calibration test, the first element corresponding to each of the delay combinations is determined. If no error occurs when the timing mode calibration test is performed using the delay combination, the first element corresponding to the delay combination is a first value. If an error occurs when the timing mode calibration test is performed using the delay combination, the first element corresponding to the delay combination is a second value.

[0010] In a set consisting of first elements and satisfying a first condition, determine the set containing the most first elements as the first test result set, wherein the first condition is that all first elements in the set have the first value and all delay combinations corresponding to the first elements in the set are adjacent.

[0011] Based on the delay combination corresponding to each first element in the first test result set, a target delay combination is determined, and the delay of the write channel of the storage device is set to the first delay value in the target delay combination, and the delay of the read channel of the storage device is set to the second delay value in the target delay combination.

[0012] In one possible implementation, determining the first element corresponding to each of the delay combinations based on the test results of the timing mode calibration test includes:

[0013] Based on the test results of the timing mode calibration test, a first matrix with a rows and b columns is generated, wherein the element in the i-th row and j-th column of the first matrix is ​​the first element corresponding to the delay combination formed by the i-th first delay value and the j-th second delay value;

[0014] The step of determining the set containing the most first elements from the set consisting of the first elements and satisfying the first condition, as the first test result set, includes:

[0015] In the first matrix, determine the submatrix that contains the most first elements and where each first element has the first value, and use this submatrix as the first test result set.

[0016] In one possible implementation, determining a submatrix within the first matrix that contains the most first elements and where each first element takes the first value, as the first test result set, includes:

[0017] For each first element in the first matrix, determine a submatrix that contains the first element and whose elements all have the first value, and use this submatrix as the first submatrix.

[0018] The first submatrix containing the most elements is determined and used as the first test result set.

[0019] In one possible implementation, the method further includes:

[0020] Based on the test results of the timing mode calibration test, determine the second element corresponding to each of the delay combinations, wherein the second element is used to represent the number of bits that were erroneous when the timing mode calibration test was performed using the delay combination;

[0021] The step of determining the target delay combination based on the delay combination corresponding to each first element in the first test result set includes:

[0022] If the number of the first test result set is 1, then the target delay combination is determined according to the delay combination corresponding to each first element in the first test result set;

[0023] If the number of the first test result sets is greater than 1, then for each of the first test result sets, the sum of the second elements corresponding to all adjacent delay combinations of the first test result set is counted as the result value corresponding to the first test result set, wherein the adjacent delay combination is the delay combination located in the neighborhood of the delay combination corresponding to the first test result set.

[0024] Determine the first set of test results with the smallest corresponding result value as the target first set of test results;

[0025] The target delay combination is determined based on the delay combination corresponding to each first element in the target first test result set.

[0026] In one possible implementation, determining the first element corresponding to each of the delay combinations based on the test results of the timing mode calibration test includes:

[0027] Based on the test results of the timing mode calibration test, a first matrix with a rows and b columns is generated, wherein the element in the i-th row and j-th column of the first matrix is ​​the first element corresponding to the delay combination formed by the i-th first delay value and the j-th second delay value;

[0028] The step of determining the set containing the most first elements from the set consisting of the first elements and satisfying the first condition, as the first test result set, includes:

[0029] In the first matrix, determine the submatrix that contains the most first elements and whose first elements all take the first value, and use it as the first test result set;

[0030] The step of determining the second element corresponding to each of the delay combinations based on the test results of the timing mode calibration test includes:

[0031] Based on the test results of the timing mode calibration test, a second matrix with a rows and b columns is generated, wherein the element in the i-th row and j-th column of the second matrix is ​​the second element corresponding to the delay combination formed by the i-th first delay value and the j-th second delay value;

[0032] The step of summing the second elements corresponding to all adjacent delay combinations in the first test result set as the result value corresponding to the first test result set includes:

[0033] In the second matrix, a submatrix that has the same position as the first test result set in the first matrix is ​​determined and used as the second submatrix;

[0034] The sum of all row elements and column elements of the second submatrix in the second matrix is ​​used as the result value corresponding to the first test result set. The row elements are elements located in rows x1 to x2 that do not belong to the second submatrix, and the column elements are elements located in columns y1 to y2 that do not belong to the second submatrix. Here, x1 is the first row of the second submatrix, x2 is the last row of the second submatrix, y1 is the first column of the second submatrix, and y2 is the last column of the second submatrix.

[0035] In one possible implementation, determining a submatrix within the first matrix that contains the most first elements and whose first elements all take the first value, as the first test result set, includes:

[0036] For each element in the first matrix, determine a submatrix that contains the first element and whose elements all have the first value, and use this submatrix as the first test result submatrix.

[0037] Record the first determined submatrix of the first test results;

[0038] Whenever a new first test result submatrix is ​​determined, if the number of first elements in the new first test result submatrix is ​​greater than the number of first elements in the recorded first test result submatrix, then the recorded first test result submatrix is ​​updated to the new first test result submatrix. If the number of first elements in the new first test result submatrix is ​​equal to the number of first elements in the recorded first test result submatrix, and the position of the new first test result submatrix in the first matrix is ​​different from the position of the recorded first test result submatrix in the first matrix, then the new first test result submatrix is ​​recorded.

[0039] Until all the first test result sub-matrices are determined, each recorded first test result sub-matrix is ​​used as the first test result set.

[0040] In one possible implementation, the first value is m, and the second value is n; determining the first element corresponding to each of the delay combinations based on the test results of the timing mode calibration test includes:

[0041] Based on the test results of the timing mode calibration test, a first matrix with a rows and b columns is generated, wherein the element in the i-th row and j-th column of the first matrix is ​​the first element corresponding to the delay combination formed by the i-th first delay value and the j-th second delay value;

[0042] The step of determining the set containing the most first elements from the set consisting of the first elements and satisfying the first condition, as the first test result set, includes:

[0043] The first matrix is ​​transformed into a third matrix according to a preset transformation rule. The preset transformation rule is as follows: For each first element in the first column of the first matrix, if the value of the first element is n, then the value of the third element in the third matrix that is in the same position as the first element is 0; if the value of the first element is m, then the value of the third element in the third matrix that is in the same position as the first element is 1. For any first element in the first matrix other than the first column, if the value of the first element is n, then the value of the third element in the third matrix that is in the same position as the first element is 0; if the value of the first element is m, then the value of the third element in the third matrix that is in the same position as the first element is c+1; where c is the value of the element to the left of the third element in the third matrix.

[0044] For each third element in each row of the third matrix, the third element with a non-zero value is taken as the target starting point, and the position of the third element with a non-zero value in the third matrix is ​​obtained and determined as the target starting point position;

[0045] Traverse the column direction of the column where the target starting point is located, and use the third element that satisfies the preset first sub-condition as the fourth element; wherein, the preset first sub-condition is: each of the fourth elements is adjacent to each other and the value of all the fourth elements is greater than or equal to the third element;

[0046] In the first matrix, starting from the first element corresponding to the target starting position, traverse s×c first elements to the left to obtain the submatrix corresponding to the target starting position, where s is the number of fourth elements obtained by traversal plus 1;

[0047] The submatrix containing the first element the most times is determined as the target test result subset.

[0048] A second aspect of this application provides a storage device timing mode calibration delay combination determination apparatus, the apparatus comprising:

[0049] The acquisition module is used to acquire a first delay values ​​pre-set for the write channel of the storage device, and b second delay values ​​pre-set for the read channel of the storage device, X i >X i+1 or X i <X i+1 And Y i >Y i+1 Or Y i <Y i+1 X i For the i-th first delay value, Y j Let be the j-th second delay value, i = 1, 2, 3...a, j = 1, 2, 3...b, where a and b are natural numbers greater than 1;

[0050] The test module is used to perform timing mode calibration tests using all delay combinations formed by each of the first delay values ​​and each of the second delay values.

[0051] The first element determination module is used to determine the first element corresponding to each delay combination based on the test results of the timing mode calibration test. If no error occurs when the timing mode calibration test is performed using the delay combination, the first element corresponding to the delay combination is a first value. If an error occurs when the timing mode calibration test is performed using the delay combination, the first element corresponding to the delay combination is a second value.

[0052] The set determination module is used to determine the set containing the most first elements from the set consisting of first elements and satisfying the first condition, and use it as the first test result set. The first condition is that the values ​​of all first elements in the set are first values, and the delay combinations corresponding to all first elements in the set are adjacent.

[0053] The delay combination determination module is used to determine a target delay combination based on the delay combination corresponding to each first element in the first test result set, and set the delay of the write channel of the storage device to the first delay value in the target delay combination, and set the delay of the read channel of the storage device to the second delay value in the target delay combination.

[0054] In one possible implementation, the first element determining module is specifically used for:

[0055] Based on the test results of the timing mode calibration test, a first matrix with a rows and b columns is generated, wherein the element in the i-th row and j-th column of the first matrix is ​​the first element corresponding to the delay combination formed by the i-th first delay value and the j-th second delay value;

[0056] The step of determining the set containing the most first elements from the set consisting of the first elements and satisfying the first condition, as the first test result set, includes:

[0057] In the first matrix, determine the submatrix that contains the most first elements and where each first element has the first value, and use it as the first test result set;

[0058] In one possible implementation, determining a submatrix within the first matrix that contains the most first elements and where each first element takes the first value, as the first test result set, includes:

[0059] For each first element in the first matrix, determine a submatrix that contains the first element and whose elements all have the first value, and use this submatrix as the first submatrix.

[0060] Determine the first submatrix containing the most elements as the first test result set;

[0061] In one possible implementation, the device further includes:

[0062] The second element determination module is used to determine the second element corresponding to each of the delay combinations based on the test results of the timing mode calibration test, wherein the second element is used to represent the number of bits that were erroneous when the timing mode calibration test was performed using the delay combination;

[0063] The delay combination determination module is specifically used for:

[0064] If the number of the first test result set is 1, then the target delay combination is determined according to the delay combination corresponding to each first element in the first test result set;

[0065] If the number of the first test result sets is greater than 1, then for each of the first test result sets, the sum of the second elements corresponding to all adjacent delay combinations of the first test result set is counted as the result value corresponding to the first test result set, wherein the adjacent delay combination is the delay combination located in the neighborhood of the delay combination corresponding to the first test result set.

[0066] Determine the first set of test results with the smallest corresponding result value as the target first set of test results;

[0067] The target delay combination is determined based on the delay combination corresponding to each first element in the target first test result set;

[0068] In one possible implementation, the first element determining module is specifically used for:

[0069] Based on the test results of the timing mode calibration test, a first matrix with a rows and b columns is generated, wherein the element in the i-th row and j-th column of the first matrix is ​​the first element corresponding to the delay combination formed by the i-th first delay value and the j-th second delay value;

[0070] The set determination module is specifically used for:

[0071] In the first matrix, determine the submatrix that contains the most first elements and whose first elements all take the first value, and use it as the first test result set;

[0072] The second element determination module is specifically used for:

[0073] Based on the test results of the timing mode calibration test, a second matrix with a rows and b columns is generated, wherein the element in the i-th row and j-th column of the second matrix is ​​the second element corresponding to the delay combination formed by the i-th first delay value and the j-th second delay value;

[0074] The step of summing the second elements corresponding to all adjacent delay combinations in the first test result set as the result value corresponding to the first test result set includes:

[0075] In the second matrix, a submatrix that has the same position as the first test result set in the first matrix is ​​determined and used as the second submatrix;

[0076] The sum of all row elements and column elements of the second submatrix in the second matrix is ​​used as the result value corresponding to the first test result set. The row elements are elements located in rows x1 to x2 that do not belong to the second submatrix, and the column elements are elements located in columns y1 to y2 that do not belong to the second submatrix. Here, x1 is the first row of the second submatrix, x2 is the last row of the second submatrix, y1 is the first column of the second submatrix, and y2 is the last column of the second submatrix.

[0077] In one possible implementation, determining a submatrix within the first matrix that contains the most first elements and whose first elements all take the first value, as the first test result set, includes:

[0078] For each element in the first matrix, determine a submatrix that contains the first element and whose elements all have the first value, and use this submatrix as the first test result submatrix.

[0079] Record the first determined submatrix of the first test results;

[0080] Whenever a new first test result submatrix is ​​determined, if the number of first elements in the new first test result submatrix is ​​greater than the number of first elements in the recorded first test result submatrix, then the recorded first test result submatrix is ​​updated to the new first test result submatrix. If the number of first elements in the new first test result submatrix is ​​equal to the number of first elements in the recorded first test result submatrix, and the position of the new first test result submatrix in the first matrix is ​​different from the position of the recorded first test result submatrix in the first matrix, then the new first test result submatrix is ​​recorded.

[0081] Until all the first test result sub-matrices are determined, each recorded first test result sub-matrix is ​​used as the first test result set.

[0082] In one possible implementation, the first value is m, and the second value is n; determining the first element corresponding to each of the delay combinations based on the test results of the timing mode calibration test includes:

[0083] Based on the test results of the timing mode calibration test, a first matrix with a rows and b columns is generated, wherein the element in the i-th row and j-th column of the first matrix is ​​the first element corresponding to the delay combination formed by the i-th first delay value and the j-th second delay value;

[0084] The step of determining the set containing the most first elements from the set consisting of the first elements and satisfying the first condition, as the first test result set, includes:

[0085] The first matrix is ​​transformed into a third matrix according to a preset transformation rule. The preset transformation rule is as follows: For each first element in the first column of the first matrix, if the value of the first element is n, then the value of the third element in the third matrix that is in the same position as the first element is 0; if the value of the first element is m, then the value of the third element in the third matrix that is in the same position as the first element is 1. For any first element in the first matrix other than the first column, if the value of the first element is n, then the value of the third element in the third matrix that is in the same position as the first element is 0; if the value of the first element is m, then the value of the third element in the third matrix that is in the same position as the first element is c+1; where c is the value of the element to the left of the third element in the third matrix.

[0086] For each third element in each row of the third matrix, the third element with a non-zero value is taken as the target starting point, and the position of the third element with a non-zero value in the third matrix is ​​obtained and determined as the target starting point position;

[0087] Traverse the column direction of the column where the target starting point is located, and use the third element that satisfies the preset first sub-condition as the fourth element; wherein, the preset first sub-condition is: each of the fourth elements is adjacent to each other and the value of all the fourth elements is greater than or equal to the third element;

[0088] In the first matrix, starting from the first element corresponding to the target starting position, traverse s×c first elements to the left to obtain the submatrix corresponding to the target starting position, where s is the number of fourth elements obtained by traversal plus 1;

[0089] The submatrix containing the first element the most times is determined as the target test result subset.

[0090] A third aspect of the embodiments of this application provides a storage device, the storage device being used for:

[0091] Obtain a first delay values ​​pre-set for the write channel of the storage device, and b second delay values ​​pre-set for the read channel of the storage device, where Xi > Xi+1 or Xi < Xi+1, and Yi > Yi+1 or Yi < Yi+1, where Xi is the i-th first delay value, Yj is the j-th second delay value, i = 1, 2, 3...a, j = 1, 2, 3...b, and a and b are natural numbers greater than 1;

[0092] Timing mode calibration tests were performed using all delay combinations formed by each of the first delay values ​​and each of the second delay values.

[0093] Based on the test results of the timing mode calibration test, the first element corresponding to each of the delay combinations is determined. If no error occurs when the timing mode calibration test is performed using the delay combination, the first element corresponding to the delay combination is a first value. If an error occurs when the timing mode calibration test is performed using the delay combination, the first element corresponding to the delay combination is a second value.

[0094] In a set consisting of first elements and satisfying a first condition, determine the set containing the most first elements as the first test result set, wherein the first condition is that all first elements in the set have the first value and all delay combinations corresponding to the first elements in the set are adjacent.

[0095] Based on the delay combination corresponding to each first element in the first test result set, a target delay combination is determined, and the delay of the write channel of the storage device is set to the first delay value in the target delay combination, and the delay of the read channel of the storage device is set to the second delay value in the target delay combination.

[0096] Beneficial effects of the embodiments in this application:

[0097] This application provides a method and apparatus for determining timing mode calibration delay combinations for storage devices. Since the first condition is that all first elements in the set have the first value, and all delay combinations corresponding to the first elements in the set are adjacent, the first elements in the first test result set determined according to the first condition all have the first value. Furthermore, since a first element having the first value indicates that no errors occurred during timing mode calibration testing using the delay combination, these delay combinations can be considered to have high performance. Simultaneously, the delay combinations corresponding to each first element are adjacent, meaning that the storage device meets timing requirements when using this delay combination. Therefore, these delay combinations can be considered to be within the same window, i.e., these delay combinations can be regarded as TMC delay combinations. Since the first test result set has the largest number of first elements, the delay combinations corresponding to each first element in the first test result set can be considered as the optimal TMC delay combinations. Thus, the first test result subset can be determined solely through the first condition, thereby determining the optimal TMC delay combination and improving the robustness of data transmission.

[0098] Of course, implementing any product or method of this application does not necessarily require achieving all of the advantages described above at the same time. Attached Figure Description

[0099] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other embodiments can be obtained based on these drawings.

[0100] Figure 1 A schematic diagram of the read operation timing;

[0101] Figure 2 A schematic diagram illustrating the principle of master control data reading;

[0102] Figure 3 A schematic diagram of the write operation timing;

[0103] Figure 4 This is a diagram illustrating a data transmission error.

[0104] Figure 5A first flowchart of a method for determining timing mode calibration delay combination provided in an embodiment of this application;

[0105] Figure 6 This is a second flowchart of the timing mode calibration delay combination determination method provided in the embodiments of this application;

[0106] Figure 7 A third flowchart of the timing mode calibration delay combination determination method provided in the embodiments of this application;

[0107] Figure 8 This is a fourth flowchart of the timing mode calibration delay combination determination method provided in the embodiments of this application;

[0108] Figure 9 A fifth flowchart of the timing mode calibration delay combination determination method provided in the embodiments of this application;

[0109] Figure 10 Example diagram of the second matrix and second submatrix provided in the embodiments of this application;

[0110] Figure 11 A sixth flowchart of the timing mode calibration delay combination determination method provided in the embodiments of this application;

[0111] Figure 12 The seventh flowchart of the timing mode calibration delay combination determination method provided in the embodiments of this application;

[0112] Figure 13 Example diagram of an all-1 submatrix provided in the embodiments of this application;

[0113] Figure 14 Example diagrams showing the adjacent submatrices of each all-1 submatrix in an N matrix;

[0114] Figure 15 This is a schematic diagram of the timing mode calibration delay combination determination device provided in the embodiments of this application. Detailed Implementation

[0115] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art based on this application are within the scope of protection of this application.

[0116] To more clearly explain the method for determining the timing mode calibration delay combination provided in this application, the relevant terms used in this document will be explained below:

[0117] NAND flash memory is a non-volatile storage technology.

[0118] FCL (Flash Control Level or Flash Control Layer) refers to the fineness of the controller's operation on the storage cells and the management strategy in NAND flash memory management, which directly affects the performance, lifespan, and reliability of the flash memory.

[0119] FC (Flash Control) refers to the technologies and strategies for managing and operating NAND flash memory to ensure its efficient and reliable operation.

[0120] An OSC (oscillator) is an electronic circuit or device that generates periodic signals and is used in clock signal generation, radio frequency transmission, audio synthesis, and other applications.

[0121] DQ (full name Data Queue), DQ[7:0]: refers to DQ0 to DQ7, which is the data bus identifier in the memory interface, representing an 8-bit wide bidirectional data bus used to transmit commands, addresses and data between the host and NAND. When NAND is not selected, it is in a high-impedance state.

[0122] DQS (Data Strobe) is a source-synchronous clock generated by the DQ signal transmitter, and the signal receiver latches data on the rising and falling edges of the DQS signal.

[0123] ECC (Error Correction Code) is a technology used to detect and correct data errors.

[0124] An error bit (short for Error bit) refers to a single binary bit that has an error during data transmission or storage.

[0125] err bit cnt (full name: error bite count) refers to the number of binary bits that have been corrupted during data transmission or storage.

[0126] TMC testing ensures that data can be correctly transmitted and received between the data buffer and the NAND Flash cache within the operating temperature and voltage range. The standard for correct transmission is: the FC (Flash Controller) places data into the data buffer, then writes it to the NAND Flash cache without writing it to disk. The FC then reads data from the NAND Flash cache into the data buffer. During this process, there are no error bits in the data. Ideally, when the receiving end uses DQS (Distributed Quadrature Sampling) to sample the data, the data should be precisely centered. However, in reality, clock frequency, DQS latency, and drive capability can all affect the data latching result.

[0127] Different controllers have one or more crystal oscillators. By dividing or multiplying the frequency, the clocks of different control modules are obtained. Different clocks will generate different frequencies of DQ and DQS. When the frequency is too high, the probability of latching the correct data is small. However, the frequency directly affects the data transfer rate, which affects the performance of the disk. Therefore, it is necessary to choose a frequency that can keep the FCL speed fast and latch the data correctly.

[0128] The driving capability determines the quality of the generated signal. If the driving capability is too weak, the generated signal quality will be low and err bits will be easily generated. If the driving capability is too strong, the power consumption of the chip will be too high. Therefore, it is necessary to select an appropriate driving capability to generate a better quality signal within a reasonable power consumption range.

[0129] In addition to the two factors mentioned above, DQS in / out delay (i.e., the second delay value of the read channel and the first delay value of the write channel in the following text) is also a key factor affecting whether data can be latched correctly.

[0130] When performing read operations on a storage device, DQ and DQS are generated by the NAND Flash, such as... Figure 1 As shown, Figure 1 This diagram illustrates the timing sequence of a read operation. To ensure the master controller latches the correct data, the edge of the DQS signal must be directly aligned with the center of the DQ signal. Ideally, the DQ and DQS signals in a read operation are perfectly synchronized, meaning their edges are perfectly aligned. Therefore, to ensure the edge of the DQS signal is directly aligned with the center of the DQ signal, the following steps are required: Figure 2 As shown, a delay is added to the DQS signal line.

[0131] like Figure 3The diagram shows the timing sequence of a write operation. During a write operation to the storage device, the DQ and DQS signals are generated by the master controller, and the edge of the DQS signal is aligned with the center of the DQ signal. IO registers [15:0] (a 16-bit input / output register) are 16-bit data registers. Data D0 and D1 are generated by the NE register (Negative Edge Register, triggered on the falling edge of the clock signal) and the pos register (Positive Edge Register, triggered on the rising edge of the clock signal), respectively. Ideally, the edge of the DQS signal during a write operation should be aligned with the center of the DQ signal. However, delays may occur during data transmission, leading to... Figure 4 The error shown.

[0132] TMC testing aims to determine the optimal combination of three parameters—drive capability, frequency, and drive power—to achieve fast data transmission, high signal quality, accurate data transmission, low power consumption, and the ability to cope with different temperatures and environments.

[0133] When adapting the signal path delay between the storage device controller and non-volatile memory, TMC testing is generally performed using two methods: the first is by reading the FLASH ID (the ID of the non-volatile memory), and the second is by reading and writing the NAND Cache (the flash cache of the non-volatile memory). Since reading the FLASH ID provides known data and a short data volume, results can be obtained quickly. However, due to the limited data volume, the robustness of the obtained parameters is low, and this method finds a local optimum rather than a global optimum. To improve parameter robustness, related technologies using the NAND Cache read / write method typically involve first adjusting the OSC and transmission line delay of the DQ (Distributed Query Controller) to find a delay without ECC errors or err bits, then adjusting the OSC and transmission line delay of the DQS (Distributed Query Controller), taking the intermediate value, and then adjusting the DQ delay again to form the TMC delay combination. However, in related technologies, this solution usually uses manual search to determine the TMC delay combination. The delay combination determined manually often has few surrounding usable delay combinations, resulting in low parameter robustness. Furthermore, the configuration time is probabilistic and may miss feasible solutions, leading to a long adaptation time.

[0134] To address the aforementioned problems, a first aspect of this application provides a method for determining the timing mode calibration delay combination of a storage device. This method is applied to the main control MCU (Microcontroller Unit) of the storage device, which can be a solid-state drive or other storage media. See also... Figure 5 , Figure 5 A first flowchart of the timing mode calibration delay combination determination method provided in the embodiments of this application is shown. The method includes the following steps:

[0135] Step S10: Obtain a first delay values ​​that are pre-set for the write channel of the storage device, and b second delay values ​​that are pre-set for the read channel of the storage device;

[0136] Among them, X i >X i+1 or X i <X i+1 And Y i >Y i+1 Or Y i <Y i+1 That is, there are four possible scenarios:

[0137] Case 1: X i >X i+1 And Y i >Y i+1 ;

[0138] Case 2: X i <X i+1 And Y i >Y i+1 ;

[0139] Case 3: X i >X i+1 And Y i <Y i+1 ;

[0140] Case 4: X i <X i+1 And Y i <Y i+1 ;

[0141] X i For the i-th first delay value, Y j Let be the j-th second delay value, i = 1, 2, 3...a, j = 1, 2, 3...b, where a and b are natural numbers greater than 1.

[0142] Step S20: Perform timing mode calibration test using all delay combinations formed by each first delay value and each second delay value;

[0143] Step S30: Based on the test results of the timing mode calibration test, determine the first element corresponding to each delay combination;

[0144] If no error occurs when using the delay combination for timing mode calibration test, the first element corresponding to the delay combination takes the first value; if an error occurs when using the delay combination for timing mode calibration test, the first element corresponding to the delay combination takes the second value.

[0145] Step S40: In the set consisting of the first element and satisfying the first condition, determine the set containing the most first elements, and use it as the first test result set;

[0146] The first condition is that all the first elements in the set have the first value, and all the delay combinations corresponding to the first elements in the set are adjacent.

[0147] Step S50: Based on the delay combination corresponding to each first element in the first test result set, determine the target delay combination and set the delay of the write channel of the storage device to the first delay value in the target delay combination, and set the delay of the read channel of the storage device to the second delay value in the target delay combination.

[0148] Using the method of this application embodiment, since the first condition is that all first elements in the set have the first value, and the delay combinations corresponding to all first elements in the set are adjacent, the first elements in the first test result set determined according to the first condition all have the first value. Furthermore, since the first element having the first value indicates that no errors occurred during timing mode calibration testing using the delay combination, these delay combinations can be considered to have high performance. Simultaneously, the delay combinations corresponding to each first element are adjacent, meaning that the storage device meets timing requirements when using this delay combination. Therefore, these delay combinations can be considered to be within the same window, i.e., these delay combinations can be regarded as TMC delay combinations. Since the first test result set has the largest number of first elements, the delay combinations corresponding to each first element in the first test result set can be considered as the optimal TMC delay combinations. Thus, the first test result subset can be determined solely through the first condition, thereby determining the optimal TMC delay combination and improving the robustness of data transmission.

[0149] The following explains steps S10 to S50:

[0150] It is understandable that the signal transmission paths and methods within a storage device differ during read and write operations, resulting in different transmission times for signals in the read and write channels. Therefore, delay values ​​need to be set separately for the write and read channels to compensate for signal transmission delays, i.e., the first delay value and the second delay value in step S10 above. There can be multiple first and second delay values, and the number of first and second delay values ​​can be the same or different. The first delay value, the second delay value, and the number of first and second delay values ​​are set by the user based on experience, and this application embodiment does not limit this.

[0151] When there are multiple first delay values ​​and second delay values, each first delay value is different from the others and each first delay value is monotonically increasing or monotonically decreasing, and each second delay value is different from the others and each second delay value is monotonically increasing or monotonically decreasing.

[0152] The following example, using 'a' and 'b' both 64, and 'first delay value' and 'second delay value' both 0, 1, 2, 3, ... 63, illustrates the TMC delay combination determination method provided in this application. It is understood that the above are merely examples of the first and second delay values, and do not limit the first and second delay values.

[0153] In step S20 above, during the TMC test, all drive capabilities are first cycled through, set one by one from low to high. For each drive capability set, the read / write latency combination is adapted. Before writing data to the NAND Flash cache, the DQS latency of the write channel (i.e., the second latency value) is set, gradually increasing from 0 to 63. After 16K or 64K data is written to the NAND Flash cache, the DQS latency of the read channel (i.e., the first latency value) is set, gradually increasing from 0 to 63. Then, data is read into the data buffer via backend commands. The read data is compared with the previously written data to check if they are completely identical. If they are identical, it indicates that the DQS latency of the write channel and the DQS latency of the read channel are reasonable and acceptable under this drive capability.

[0154] Understandably, different delay combinations will result in different TMC test outcomes depending on whether an error occurs or not. Specifically, the value of the first element differs for each delay combination depending on whether an error occurs. The value of the first element is related to the test result: if the TMC test is successful, the first element has the first value; if the TMC test fails, the first element has the second value.

[0155] The test result can indicate whether a TMC test failed, or it can indicate the number of bits that failed the TMC test. When the test result indicates whether a TMC test failed, a first value indicates that the TMC test did not fail, and a second value indicates that the TMC test failed. In this case, the first and second values ​​are fixed values ​​that are different from each other. That is, the first element has the same value when different delay combinations of TMC tests all fail, and the first element also has the same value when different delay combinations of TMC tests all fail. For example, a first value of 0 indicates that the TMC test did not fail, and a second value of 1 indicates that the TMC test failed. It is understood that in this case, the first and second values ​​can also be other values, and this application embodiment does not limit this.

[0156] When the test result indicates the number of bits that failed the TMC test, the first value is 0, which means that the TMC test did not fail. The second value is the number of bits that failed the TMC test. For example, if the number of bits that failed the TMC test is 2 when using a certain delay combination, then the second element corresponding to that delay combination is 2.

[0157] After performing TMC testing using all delay combinations, the first element corresponding to each delay combination can be obtained. Then, based on each first element, a set consisting of the first elements and satisfying the first condition is determined, which is referred to as the candidate set below. The number of candidate sets can be one or more.

[0158] The first condition is that all elements in the set have the first value, and all delay combinations corresponding to the first element in the set are adjacent. Adjacent delay combinations for each first element mean that the first delay value or the second delay value corresponding to each first element is adjacent. For example, suppose the set consisting of first elements and satisfying the first condition includes R11, R12, R13, R21, R22, and R23. R11 represents the test result of TMC testing using the first first delay value and the first second delay value; R12 represents the test result of TMC testing using the first first delay value and the second second delay value; R13 represents the test result of TMC testing using the first first delay value and the third second delay value; and R21 represents the test result of TMC testing using the second first delay value and the third second delay value. The test results of the TMC test using the first delay value and the first second delay value are given. R22 represents the test results of the TMC test using the second first delay value and the second second delay value. R23 represents the test results of the TMC test using the second first delay value and the third second delay value. Since the first first delay value is adjacent to the second first delay value, the first second delay value is adjacent, and the second second delay value is also adjacent to the third second delay value, the delay combinations corresponding to all first elements in this set are adjacent.

[0159] To ensure robustness of the delay combination, a wide range of usable delay combinations are needed around the selected one. This requires finding the delay combination with the largest window among different drive capabilities, i.e., the optimal TMC delay combination. It is understood that the candidate set containing the most first elements can be considered to have the largest delay combination window corresponding to each first element. Therefore, in step S40 above, the set containing the most first elements among the sets that satisfy the first condition is determined as the first test result set.

[0160] For example, assuming that after performing TMC testing using all delay combinations, the first element corresponding to each delay combination can be obtained as: R11, R12, R13, R21, R22, R23, R31, R32, R33, where R11 represents the test result of TMC testing using the first first delay value and the first second delay value, R12 represents the test result of TMC testing using the first first delay value and the second second delay value, R13 represents the test result of TMC testing using the first first delay value and the third second delay value, and R21 represents the test result of TMC testing using the second first delay value and the third second delay value. The test results for the TMC test using the first second delay value are as follows: R22 represents the test results using the second first delay value and the second second delay value; R23 represents the test results using the second first delay value and the third second delay value; R31 represents the test results using the third first delay value and the first second delay value; R32 represents the test results using the third first delay value and the second second delay value; and R33 represents the test results using the third first delay value and the third second delay value.

[0161] If the first value is 1 and the second value is 0, and the values ​​of R11, R12, R13, R21, R22, R23, R31, R32, and R33 are 1, 0, 0, 1, 1, 1, 1, 1, 1 respectively, then the sets consisting of the first element and satisfying the first condition are set 1 and set 2. The elements in set 1 are R11, R21, and R31, and the elements in set 2 are R21, R22, R23, R31, R32, and R33.

[0162] Since set 2 contains the largest number of first elements, set 2 is the first test result set.

[0163] The first set of test results can be represented as a set, that is, listing each first element in curly braces, with each first element separated by a comma; or it can be represented as a matrix, where the element in the i-th row and j-th column is the first element corresponding to the delay combination formed by the i-th first delay value and the j-th second delay value.

[0164] Understandably, if the first test result set is represented in the form of a set, since the elements in the set are unordered, and the order of each first element needs to be known when determining the first test result set in this application, it may be necessary to obtain the delay combination corresponding to each first element, which increases the amount of computation.

[0165] Since a matrix has defined rows and columns, and each element in the matrix corresponds to storage space, it is suitable for representing each first element in this application. Therefore, in one possible implementation, a matrix can be used to represent the first test result set, and each element in the matrix can represent each first element in the first test result set.

[0166] In this case, such as Figure 6 The diagram shown is a second flowchart of the timing mode calibration delay combination determination method provided in this application embodiment. Step S30 includes:

[0167] Step S31: Based on the test results of the timing mode calibration test, generate the first matrix with a row and b columns;

[0168] In this application, the element in the i-th row and j-th column of the first matrix is ​​the first element corresponding to the delay combination formed by the i-th first delay value and the j-th second delay value. In this application, "row" can refer to a row or a column in a matrix. When "row" refers to a row in a matrix, "column" refers to a column in a matrix; conversely, when "row" refers to a column in a matrix, "column" refers to a row in a matrix. For ease of description, "row" in the following text refers to a row in a matrix, and "column" refers to a column in a matrix.

[0169] For example, suppose the first matrix is , The element in the 2nd row and 2nd column of the first matrix. The first element corresponding to the delay combination formed by the second first delay value and the second second delay value; The element in the 3rd row and 1st column of the first matrix. The first element is the delay combination consisting of the third first delay value and the first second delay value.

[0170] Step S40 above includes:

[0171] Step S41: Determine the submatrix in the first matrix that contains the most first elements and where each first element has the first value, and use it as the first test result set.

[0172] Taking the matrix M above as an example, suppose the first element is used to indicate whether the TMC test has an error. The first value is 1, indicating no error, and the second value is 0, indicating that the TMC test has an error. In matrix M... , , , , , , , , The values ​​are 1, 0, 0, 1, 1, 1, 1, 1, 1, that is... The submatrix containing the most first elements in the first matrix M, where each first element has a value of 1, is: Then determine This is the first set of test results.

[0173] In another embodiment, assuming the first element represents the number of bits that failed the TMC test, and the first value is 0, it means that the number of bits that failed the TMC test is 0, that is, the TMC test did not fail. The second value is the number of bits that failed the TMC test. In the M matrix... , , , , , , , , The values ​​are 1, 2, 0, 2, 0, 0, 0, 0, 0, which are 1, 2, 0 ... The submatrix containing the most first elements in the first matrix M, where each first element has a value of 1, is: = Then determine This is the first set of test results.

[0174] Using the embodiments of this application, a first matrix is ​​generated based on the test results of the timing mode calibration test. The computational load is small when determining the submatrix containing the most first elements from the first matrix as the first test result set, which improves the efficiency of determining the first test result set and thus improves the efficiency of determining the optimal TMC delay combination.

[0175] It is understandable that when determining the first test result set from the first matrix, one could first determine a submatrix from the first matrix that contains the first element and whose values ​​are all the first values, and then determine the submatrix containing the most first elements from multiple submatrixes as the first test result set.

[0176] like Figure 7 The diagram shown is a third flowchart of the timing mode calibration delay combination determination method provided in this application embodiment. In this case, step S41 includes:

[0177] Step S411: For each first element in the first matrix, determine a submatrix that contains the first element and whose contained elements all have the first value, and use this submatrix as the first submatrix.

[0178] Step S412: Determine the first submatrix containing the most elements, and use it as the first test result set.

[0179] Taking the matrix M above as an example, suppose the first element is used to indicate whether the TMC test has an error. The first value is 1, indicating no error, and the second value is 0, indicating that the TMC test has an error. In matrix M... , , , , , , , , The values ​​are 1, 0, 0, 1, 1, 1, 1, 1, 1, that is... The first matrix M is determined to contain two submatrices, namely, a submatrix consisting entirely of 1s. and Due to the submatrix If the first element is the most frequent and all first elements are 1, then it is determined. This is the first set of test results.

[0180] In another embodiment, assuming the first element represents the number of bits that failed the TMC test, and the first value is 0, it means that the number of bits that failed the TMC test is 0, that is, the TMC test did not fail. The second value is the number of bits that failed the TMC test. In the M matrix... , , , , , , , , The values ​​are 1, 2, 0, 2, 0, 0, 0, 0, 0, which are 1, 2, 0 ... The first matrix M is determined to include a submatrix whose first element has a value of 0 for all three elements, i.e., a submatrix consisting entirely of zeros. as well as = , Due to the submatrix If the first element is the most frequent and all first elements are 0, then it is determined. This is the first set of test results.

[0181] By adopting the embodiments of this application, multiple sub-matrices containing the first element and whose values ​​are all the first value are first determined from the first matrix. Then, the sub-matrix containing the most first elements is determined from each sub-matrix as the first test result set. This can avoid omitting the actual maximum matrix and improve the accuracy of determining the optimal TMC delay combination.

[0182] It is understandable that the first matrix may contain more than one submatrix with the same number of elements, all of which contain the first value. In this case, one submatrix can be arbitrarily selected from the multiple submatrixes as the first test result set. Alternatively, the first test result set can be determined in the following way: Figure 8 The diagram shown is a fourth flowchart of the timing mode calibration delay combination determination method provided in this application embodiment. After performing the above steps S10 to S30, the following step S301 is executed:

[0183] Step S301: Based on the test results of the timing mode calibration test, determine the second element corresponding to each delay combination;

[0184] The second element represents the number of bits that err during timing mode calibration testing using a delay combination. For example, if the data written by the write channel and the data read by the read channel are different during TMC testing using a certain delay combination, and the number of erroneous bits is 1, then the second element corresponding to that delay combination is 1. If the data written by the write channel and the data read by the read channel are the same during TMC testing using a certain delay combination, and the number of erroneous bits is 0, then the second element corresponding to that delay combination is 0. If the data written by the write channel and the data read by the read channel are different during TMC testing using a certain delay combination, and the number of erroneous bits is 4, then the second element corresponding to that delay combination is 4.

[0185] In this embodiment, step S50, which determines the target delay combination based on the delay combinations corresponding to each first element in the first test result set, includes:

[0186] If the number of the first test results is 1, then proceed to step S501;

[0187] Step S501: Determine the target delay combination based on the delay combination corresponding to each first element in the first test result set;

[0188] If the number of the first test results is greater than 1, then proceed to steps S502 to S504.

[0189] Step S502: For each first test result set, calculate the sum of the second elements corresponding to all adjacent delay combinations in the first test result set, and use it as the result value corresponding to the first test result set;

[0190] Here, adjacent delay combinations are delay combinations located within the neighborhood of the delay combination corresponding to the first test result set. It is understood that the range of the neighborhood is determined by the user based on practical experience. For example, delay combinations with the same first or second delay value as the delay combination corresponding to the first test result set can be defined as adjacent delay combinations. Alternatively, delay combinations whose first or second delay values ​​are adjacent to the delay combination corresponding to the first test result set can be defined as adjacent delay combinations.

[0191] For example, assuming that after performing TMC testing using all delay combinations, the first element corresponding to each delay combination is: R11, R12, R13, R21, R22, R23, R31, R32, R33, and the second element is: S11, S12, S13, R21, S22, S23, S31, S32, S33, the first test result set is: set 1 = {R11, R12, R13}, set 2 = { If the adjacent delay combinations are delay combinations that are adjacent to the first delay value or the second delay value of the delay combination corresponding to the first test result set, then the adjacent delay combinations of set 1 are determined to be: S21, S22, S23, and the adjacent delay combinations of set 2 are: S12, S22, S32. The result value corresponding to set 1 is calculated to be: S21+S22+S23, and the result value corresponding to set 2 is: S12+S22+S32. If the adjacent delay combination is the same as the first delay value or the second delay value corresponding to the delay combination corresponding to the first test result set, then the adjacent delay combinations of set 1 are determined to be: S21, S22, S23, S31, S32, S33, and the adjacent delay combinations of set 1 are: S12, S13, S22, S23, S32, S33. The corresponding result value of set 1 is calculated to be: S12+S13+S22+S23+S32+S33.

[0192] Step S503: Determine the first test result set with the smallest corresponding result value, and use it as the target first test result set;

[0193] Taking the above embodiment as an example, if the result value corresponding to set 1 is less than the result value corresponding to set 2, then set 1 will be used as the target first test result set.

[0194] Step S504: Determine the target delay combination based on the delay combination corresponding to each first element in the target first test result set.

[0195] In this embodiment, the sum of the second elements corresponding to all adjacent delay combinations in the first test result set is calculated as the result value corresponding to the first test result set. The smaller the result value, the fewer errors there are when using the delay combinations adjacent to the delay combination corresponding to the first test result to perform TMC testing. The first test result set with the smallest result value is determined as the target first test result set, and the target delay combination is determined according to the delay combination corresponding to each first element in the target first test result set, thereby improving the accuracy of determining the optimal TMC delay combination.

[0196] Similarly, each second element can also be represented using a matrix. Based on this, in one possible implementation, such as... Figure 9 The diagram shown is a fifth flowchart of the timing mode calibration delay combination determination method provided in this application embodiment. If a first matrix is ​​used to represent each first element, after determining the submatrix containing the most first elements and whose first element values ​​are all first values ​​based on the first matrix, the above step S301 determines the second element corresponding to each delay combination according to the test results of the timing mode calibration test, specifically including:

[0197] Step S3011: Based on the test results of the timing mode calibration test, generate a second matrix with a row and b columns;

[0198] In this second matrix, the element in the i-th row and j-th column is the second element corresponding to the delay combination formed by the i-th first delay value and the j-th second delay value. It can be understood that if the rows mentioned earlier represent rows in a matrix, then the rows here also represent rows in a matrix; similarly, if the rows mentioned earlier represent columns in a matrix, then the rows here also represent columns in a matrix.

[0199] In the second matrix, the first delay value of each second element is the same as the first delay value of the first element at the same position in the first matrix, and the second delay value of each second element is the same as the second delay value of the first element at the same position in the first matrix.

[0200] For example, suppose the first matrix is The second matrix is , and These are the elements in the 2nd row and 2nd column of the first and second matrices, respectively. The first element corresponds to the delay combination formed by the second first delay value and the second second delay value. The second element is the delay combination corresponding to the second first delay value and the second second delay value; and These are the elements in the 3rd row and 1st column of the first and second matrices, respectively. The first element corresponds to the delay combination formed by the third first delay value and the first second delay value. The second element is the delay combination corresponding to the third first delay value and the first second delay value.

[0201] In this embodiment, step S502 specifically includes:

[0202] Step S5021: In the second matrix, determine the submatrix that has the same position as the first test result set in the first matrix, and use it as the second submatrix;

[0203] Step S5022: Calculate the sum of all row elements and column elements of the second submatrix in the second matrix, and use it as the result value corresponding to the first test result set;

[0204] In this context, elements in the same row are those located in rows x1 to x2 that do not belong to the second submatrix, and elements in the same column are those located in columns y1 to y2 that do not belong to the second submatrix. Here, x1 is the first row of the second submatrix, x2 is the last row of the second submatrix, y1 is the first column of the second submatrix, and y2 is the last column of the second submatrix.

[0205] For example, such as Figure 10 The diagram shown is an example of the second matrix and the second submatrix provided in an embodiment of this application. Figure 10 The thick solid line box represents the second submatrix, and the dashed line box represents all row elements and column elements of the second submatrix.

[0206] Using the embodiments of this application, a first matrix and a second matrix are generated based on the test results of the timing mode calibration test. The target first test result set is determined based on the first matrix and the second matrix, and then the target delay combination is determined, which improves the efficiency of determining the optimal TMC delay combination.

[0207] In the process of determining the submatrix that contains the most first elements and whose first elements all take the first value, a large number of intermediate results need to be saved, resulting in a waste of storage resources.

[0208] To reduce the consumption of storage resources, in one possible implementation, such as Figure 11 The diagram shown is the sixth flowchart of the timing mode calibration delay combination determination method provided in this application embodiment. The above step S41 specifically includes:

[0209] Step S4101: For each element in the first matrix, determine a submatrix that contains the first element and whose contained elements all have the first value, and use this submatrix as the first test result submatrix.

[0210] Step S4102: Record the first determined first test result submatrix;

[0211] Step S4103: Whenever a new first test result submatrix is ​​determined, if the number of first elements in the new first test result submatrix is ​​greater than the number of first elements in the recorded first test result submatrix, then the recorded first test result submatrix is ​​updated to the new first test result submatrix; if the number of first elements in the new first test result submatrix is ​​equal to the number of first elements in the recorded first test result submatrix, and the position of the new first test result submatrix in the first matrix is ​​different from the position of the recorded first test result submatrix in the first matrix, then the new first test result submatrix is ​​recorded.

[0212] Step S4104: Continue until all first test result sub-matrices are determined, and then use each recorded first test result sub-matrix as the first test result set.

[0213] For example, suppose the first matrix For the first element in the first row and first column, determine the submatrix containing the first element and whose contained elements all have the first value. Then record the submatrix. Then, for the elements in the first row and second column, determine the submatrix that contains the first element and whose contained elements all have the first value. This submatrix is ​​the same as the recorded submatrix. Then, for the elements in the first row and third column, determine the submatrix that contains the first element and whose contained elements all have the first value. Continue this process to obtain the submatrix. Submatrix However, submatrix The number of first elements in the array is less than the number of recorded submatrices. The number of the first element in the matrix is ​​not recorded in the submatrix. And due to the submatrix Position in the first matrix and submatrix If the positions in the first matrix are different, then the submatrix is ​​also recorded. Submatrix Submatrices Submatrix As the first set of test results.

[0214] In this embodiment, recording the determined first test result submatrix can refer to recording the rows, columns, and positions of the first test result submatrix within the first matrix. To reduce space complexity, in one possible implementation, a monotonic stack can be used to store the first test result submatrix. After determining the first matrix, the determined first test result submatrix is ​​compared with the first test result submatrix in the monotonic stack. If the determined first test result submatrix and the first test result submatrix in the monotonic stack contain the same number of first elements but are in different positions within the first matrix, the determined first test result submatrix is ​​pushed onto the stack. If the determined first test result submatrix contains fewer first elements than the first test result submatrix in the monotonic stack, the determined first test result submatrix is ​​not pushed onto the stack. If the determined first test result submatrix contains more first elements than the first test result submatrix in the monotonic stack, the first matrix is ​​popped from the monotonic stack, and the determined first test result submatrix is ​​pushed onto the stack.

[0215] By adopting the embodiments of this application, for each element in the first matrix, a submatrix containing the first element and whose contained elements all have the first value is determined as the first test result submatrix and recorded. When a submatrix with more elements is determined, the recorded first test result submatrix is ​​updated. This can reduce the storage of intermediate data and reduce the occupation of storage resources.

[0216] To further improve the speed of determining the first set of test results, assuming the first value is m and the second value is n, in one possible implementation, such as Figure 12 The diagram shown is the seventh flowchart of the timing mode calibration delay combination determination method provided in this application embodiment. Step S30, based on the test results of the timing mode calibration test, determines the first element corresponding to each delay combination, specifically including:

[0217] Step S31: Based on the test results of the timing mode calibration test, generate the first matrix with a row and b columns;

[0218] Step S40 above involves determining, from the set consisting of the first element and satisfying the first condition, the set containing the most of the first element, as the first test result set, including:

[0219] Step S401: Transform the first matrix into a third matrix according to a preset transformation rule. The preset transformation rule is as follows: For each first element in the first column of the first matrix, if the value of the first element is n, then the value of the third element in the third matrix that is at the same position as the first element is 0; if the value of the first element is m, then the value of the third element in the third matrix that is at the same position as the first element is 1. For any first element in the first matrix other than the first column, if the value of the first element is n, then the value of the third element in the third matrix that is at the same position as the first element is 0; if the value of the first element is m, then the value of the third element in the third matrix that is at the same position as the first element is c+1; where c is the value of the element to the left of the third element in the third matrix.

[0220] In other words, the above-mentioned pre-defined change rules can be expressed by formula (1-1):

[0221] (1-1)

[0222] in, This represents the third element in the i-th row and j-th column of the third matrix. This represents the first element in the i-th row and j-th column of the first matrix. Let represent the third element in the i-th row and j-1-th column of the third matrix. For the case where n=0 and m=1, formula (1-1) can be rewritten as formula (1-2):

[0223] (1-2)

[0224] As can be seen from formula (1-2), when j=0, and Since the values ​​of are the same, formula (1-2) can be rewritten as formula (1-3):

[0225] (1-3)

[0226] Furthermore, due to the third sub-equation in formula (1-3) Since the value is equal to 1, formula (1-3) can be rewritten as formula (1-4):

[0227] (1-4)

[0228] In this case, assume the first matrix Then the third matrix C = .

[0229] Step S402: For each third element in each row of the third matrix, take the third element with a non-zero value as the target starting point and obtain the position of the third element with a non-zero value in the third matrix, and determine it as the target starting point position.

[0230] For example, suppose the third matrix C = Then, the 0th row and 0th column, the 0th row and 1st column, the 1st row and 0th column, the 1st row and 1st column, the 1st row and 2nd column, the 2nd row and 1st column, and the 2nd row and 2nd column of the third matrix are respectively determined as the target starting position.

[0231] Step S403: Traverse the column direction of the column where the target starting point is located to find the third element that satisfies the preset first sub-condition, and use it as the fourth element;

[0232] The first preset sub-condition is: each of the fourth elements is adjacent to the other two and the value of all the fourth elements is greater than or equal to the third element.

[0233] For example, suppose the third matrix C = Taking the target starting position as row 0 and column 0 as an example, the value of the third element at the target starting position is 1. There are two other third elements in the column direction of the target starting position, namely the third element "1" in row 1 and column 0 and the third element "0" in row 2 and column 0. Since the third element "1" in row 1 and column 0 is adjacent to the target starting position and is not less than 1, the third element "1" in row 1 and column 0 can be regarded as the fourth element. However, the third element "0" in row 2 and column 0 is less than 1, so it cannot be regarded as the fourth element.

[0234] Step S404: In the first matrix, take the first element corresponding to the target starting position as the starting column, and traverse to the left through the first element of s×c to obtain the submatrix corresponding to the target starting position.

[0235] Where s is the number of fourth elements obtained by traversal plus 1.

[0236] Assume the first matrix Then the third matrix C = Taking the target starting position as row 0, column 0 as an example, as explained above, the number of fourth elements obtained in this case is 1, so s=2. Since the value of row 0, column 0 in the third matrix is ​​1, c=1. Therefore, in the first matrix, starting with the first element of row 0, column 0, we traverse 2×1 (i.e., 2 rows, 1 column) to obtain the submatrix corresponding to the target starting position. This submatrix is ​​clearly composed of the submatrix of row 0, column 0 and row 1, column 0 in the first matrix. .

[0237] For the case where the target starting position is the first row and first column, as explained above, the number of fourth elements obtained by traversal is 1, therefore s=2. Since the value of the first row and first column in the third matrix is ​​2, c=2. Therefore, by traversing 2×2 (i.e., 2 rows and 2 columns) starting with the first element of the first row and first column in the first matrix, we obtain the submatrix corresponding to the target starting position. This submatrix is ​​clearly composed of the first row and first column, the first row and first column, the first row and first column, and the first row and first column of the first matrix. .

[0238] Step S405: The submatrix containing the first element the most times in each submatrix is ​​determined as the target test result subset.

[0239] By using the embodiments of this application, a third matrix is ​​obtained by transforming the first matrix. Based on the third matrix, a submatrix containing the first element whose values ​​are all first values ​​can be quickly determined, thereby quickly determining the first test result set and further improving the efficiency of determining the optimal delay combination.

[0240] To expedite the determination of the first set of test results, in one possible implementation, a fourth matrix can also be determined based on the first and third matrices, where the value of each element in the fourth matrix is ​​equal to the product of the number of times the third element at the same position in the third matrix and the first element at the same position in the first matrix appear as the first value in their respective columns from top to bottom.

[0241] For example, still using the first matrix The third matrix C= For example, the "1" in the third column and second row of the first matrix appears for the first time in the third column; the "2" in the first row of the second column appears for the first time in the second column, and so on, to determine the fourth matrix S. .

[0242] Then, determine the position of the element with the largest value in the fourth matrix, and determine the first test result set in the first matrix starting from that position.

[0243] To more clearly illustrate the TMC delay combination determination method provided in the embodiments of this application, the following description is provided in conjunction with specific embodiments:

[0244] The TMC testing process can be described as follows: x is the second delay value, y is the first delay value, x ranges from [0:63], y ranges from [0:63]; z represents the data programmed into the NAND Cache, whether the data can be read successfully through the data reading process, z = 0 indicates that the data reading failed, err bit cnt = w, w indicates that there is an err bit value or is 0xFF; z = 1 indicates that the data reading was successful and err bit cnt = 0; the relationship between z and w can be expressed by the following formula (2):

[0245] (2)

[0246] Specifically, when the number of bits that erroneously read data is less than a preset bit threshold, , This represents the actual number of bits that resulted in data reading errors. When the number of bits that resulted in data reading errors is greater than or equal to a preset bit count threshold, .

[0247] Assume that the z-value matrix M (i.e., the first matrix mentioned above) can be obtained during the TMC test as follows:

[0248] (3)

[0249] Each element of matrix M (i.e., the first element mentioned above) is used to indicate whether the data was successfully read at each value point of x and y; according to the above formula (2), matrix N (i.e., the second matrix mentioned above) can be obtained:

[0250] (4)

[0251] Each element of matrix N (i.e., the second element above) represents the number of bits that erroneously read data at each value of x and y. Since the TMC test process aims to find the maximum fault tolerance margin for the first and second delay values, that is, to find the widest all-one submatrix in matrix M with the widest row and column widths, in other words, the TMC test is the problem of finding the largest all-one submatrix M_P in matrix M.

[0252] If multiple all-one submatrices M_P with the same area exist in the M matrix, the best submatrix is ​​the one with the smallest sum of the number of erroneous bits in the four directions of the N matrix (the corresponding submatrices in the top, bottom, left, and right directions of the N matrix, i.e., the adjacent delay combinations mentioned above) corresponding to the position of the M_P matrix.

[0253] For example, matrix M , ;

[0254] First, transform each element in matrix M according to the above formula (1) to obtain matrix C (corresponding to the third matrix above):

[0255]

[0256] Then, the C matrix is ​​transformed into the S matrix, and the values ​​of each element of the S matrix are shown in equation (5):

[0257] (5)

[0258] Where S_i_j is equal to the area of ​​a submatrix of all 1s extended upwards or downwards with M_i_j as the vertex (or intermediate point). The number of rows of this submatrix is ​​the number of nodes in the (i,j) column of matrix C whose vertical scan is greater than or equal to C_i_j (including itself; the expansion stops when encountering a node smaller than itself). According to formula (5), matrix C can be transformed into matrix S:

[0259]

[0260] Then, by comparing the values ​​of each element in matrix S and finding the maximum value, the area of ​​the largest submatrix of matrix M consisting entirely of 1s can be determined. For example, the maximum value in the above matrix S is " If we calculate the value of each element in matrix S, we can determine that the area of ​​the largest submatrix of all 1s is 9. During the calculation of each element in matrix S, we simultaneously save the row, column, and four vertex values ​​of that submatrix (i.e., the first test result submatrix determined by the above records), and maintain a monotonic stack. The nodes in the stack always contain the row / column values ​​and vertex values ​​of the largest submatrix of all 1s. When pushing a submatrix onto the stack, we check if the four vertices of the submatrix match the four vertices of an existing submatrix in the stack; if they match, it cannot be pushed. After calculating the value of each element in matrix S, we can obtain matrix S, and then obtain the position and size of all the largest submatrixes of all 1s in the first matrix.

[0261] Based on the above, it can be seen that there exist two window-identical submatrices M_P_1 and M_P_2, both consisting of only 1s, in the M matrix, as follows: Figure 13 The image shown is an example of a submatrix consisting entirely of 1s. Figure 13 A solid line box represents a submatrix consisting entirely of 1s.

[0262] At this point, the matrix information of the largest all-one submatrix needs to be popped from the stack sequentially. For each largest all-one submatrix, the sum of the ERR BIT CNT in the four directions of the N matrix is ​​calculated, such as... Figure 10 and Figure 14 The figures shown are example diagrams of the adjacent submatrices of each all-one submatrix in the N matrix. Figure 10The solid box represents the submatrix M_P_1 in matrix M corresponding to the submatrix M_P_1 in matrix N (i.e., the second submatrix mentioned above), and the dashed box represents all row and column elements of this second submatrix. Figure 14 The solid box represents the submatrix M_P_2 in matrix M corresponding to the submatrix in matrix N, and the dashed box represents all row and column elements of this second submatrix.

[0263] according to Figure 10 The sum of the err bits cnt of the submatrix M_P_1 in the four directions of the N matrix can be calculated from the N matrix, which is ERR_1. Figure 14 The sum of the err bits cnt of the submatrix M_P_2 in the four directions of the submatrix M_P_2 in the N matrix can be calculated as ERR_2.

[0264] Then ERR_1 and ERR_2 are compared, and the smaller M_P submatrix is ​​taken as the best submatrix in the M matrix (i.e., the target first test result set mentioned above).

[0265] Corresponding to the first aspect mentioned above, a second aspect of the embodiments of this application provides a timing mode calibration delay combination determination device, such as... Figure 15 The diagram shown is a schematic representation of the timing mode calibration delay combination determination device provided in an embodiment of this application. The device includes:

[0266] The acquisition module 1501 is used to acquire a first delay values ​​pre-set for the write channel of the storage device, and b second delay values ​​pre-set for the read channel of the storage device, X i >X i+1 or X i <X i+1 And Y i >Y i+1 Or Y i <Y i+1 X i For the i-th first delay value, Y j Let be the j-th second delay value, i = 1, 2, 3...a, j = 1, 2, 3...b, where a and b are natural numbers greater than 1;

[0267] Test module 1502 is used to perform timing mode calibration tests using all delay combinations formed by each of the first delay values ​​and each of the second delay values ​​respectively;

[0268] The first element determination module 1503 is used to determine the first element corresponding to each delay combination based on the test results of the timing mode calibration test. If no error occurs when the timing mode calibration test is performed using the delay combination, the first element corresponding to the delay combination is a first value. If an error occurs when the timing mode calibration test is performed using the delay combination, the first element corresponding to the delay combination is a second value.

[0269] The set determination module 1504 is used to determine the set containing the most first elements in a set composed of first elements and satisfying a first condition, as the first test result set, wherein the first condition is that the values ​​of all first elements in the set are first values, and the delay combinations corresponding to all first elements in the set are adjacent.

[0270] The delay combination determination module 1505 is used to determine a target delay combination based on the delay combination corresponding to each first element in the first test result set, and set the delay of the write channel of the storage device to the first delay value in the target delay combination, and set the delay of the read channel of the storage device to the second delay value in the target delay combination.

[0271] In this embodiment, since the first condition is that all first elements in the set have the first value, and all delay combinations corresponding to the first elements in the set are adjacent, the first elements in the first test result set determined according to the first condition all have the first value. Since a first element having the first value indicates that no errors occurred during timing mode calibration testing using the delay combination, these delay combinations can be considered to have high performance. Furthermore, since the delay combinations corresponding to each first element are adjacent, the storage device meets timing requirements when using this delay combination. Therefore, these delay combinations can be considered to be within the same window, meaning they can be regarded as TMC delay combinations. Since the first test result set has the largest number of first elements, the delay combinations corresponding to each first element in the first test result set can be considered the optimal TMC delay combination. Thus, the first test result subset can be determined solely through the first condition, thereby determining the optimal TMC delay combination and improving the robustness of data transmission.

[0272] In one possible implementation, the first element determining module is specifically used for:

[0273] Based on the test results of the timing mode calibration test, a first matrix with a rows and b columns is generated, wherein the element in the i-th row and j-th column of the first matrix is ​​the first element corresponding to the delay combination formed by the i-th first delay value and the j-th second delay value; the step of determining the set containing the most first elements in the set composed of first elements and satisfying the first condition, as the first test result set, includes: determining the sub-matrix containing the most first elements in the first matrix and where the value of each first element is the first value, as the first test result set;

[0274] In one possible implementation, determining the submatrix containing the most first elements and whose values ​​are all first values ​​in the first matrix as the first test result set includes: sequentially determining, for each first element in the first matrix, a submatrix containing the first element and whose values ​​are all first values ​​as the first submatrix; and determining the first submatrix containing the most elements as the first test result set.

[0275] In one possible implementation, the apparatus further includes: a second element determination module, configured to determine a second element corresponding to each of the delay combinations based on the test results of the timing mode calibration test, wherein the second element represents the number of bits erroneous when performing the timing mode calibration test using the delay combination; the delay combination determination module is specifically configured to: if the number of the first test result sets is 1, determine a target delay combination based on the delay combination corresponding to each first element in the first test result sets; if the number of the first test result sets is greater than 1, for each first test result set, calculate the sum of the second elements corresponding to all adjacent delay combinations of the first test result sets as the result value corresponding to the first test result set, wherein the adjacent delay combinations are delay combinations located in the neighborhood of the delay combination corresponding to the first test result set; determine the first test result set with the smallest corresponding result value as the target first test result set; and determine the target delay combination based on the delay combination corresponding to each first element in the target first test result set.

[0276] In one possible implementation, the first element determination module is specifically used to: generate a first matrix of a rows and b columns based on the test results of the timing mode calibration test, wherein the element in the i-th row and j-th column of the first matrix is ​​the first element corresponding to the delay combination formed by the i-th first delay value and the j-th second delay value; the set determination module is specifically used to: determine a sub-matrix in the first matrix that contains the most first elements and whose first element values ​​are all first values, as the first test result set; the second element determination module is specifically used to: generate a second matrix of a rows and b columns based on the test results of the timing mode calibration test, wherein the element in the i-th row and j-th column of the second matrix is ​​the second element corresponding to the delay combination formed by the i-th first delay value and the j-th second delay value; the statistical analysis of the first test results... The sum of the second elements corresponding to all adjacent delay combinations in the test result set is used as the result value corresponding to the first test result set. This includes: in the second matrix, determining a submatrix with the same position as the first test result set in the first matrix, as the second submatrix; and calculating the sum of all row-column elements and column-column elements of the second submatrix in the second matrix, as the result value corresponding to the first test result set. The row-column elements are elements located in rows x1 to x2 that do not belong to the second submatrix, and the column-column elements are elements located in columns y1 to y2 that do not belong to the second submatrix. Here, x1 is the first row of the second submatrix, x2 is the last row of the second submatrix, y1 is the first column of the second submatrix, and y2 is the last column of the second submatrix.

[0277] In one possible implementation, determining the submatrix containing the most first elements and whose first elements all have the first value as the first test result set in the first matrix includes: sequentially determining, for each element in the first matrix, a submatrix containing the first element and whose contained elements all have the first value as the first test result submatrix; recording the first determined first test result submatrix; whenever a new first test result submatrix is ​​determined, if the number of first elements in the new first test result submatrix is ​​greater than the number of first elements in the recorded first test result submatrix, then updating the recorded first test result submatrix to the new first test result submatrix; if the number of first elements in the new first test result submatrix is ​​equal to the number of first elements in the recorded first test result submatrix, and the position of the new first test result submatrix in the first matrix is ​​different from the position of the recorded first test result submatrix in the first matrix, then recording the new first test result submatrix; until all first test result submatrixes are determined, and each recorded first test result submatrix is ​​used as the first test result set;

[0278] In one possible implementation, the first value is m, and the second value is n; determining the first element corresponding to each delay combination based on the test results of the timing mode calibration test includes: generating a first matrix of a rows and b columns based on the test results of the timing mode calibration test, wherein the element in the i-th row and j-th column of the first matrix is ​​the first element corresponding to the delay combination formed by the i-th first delay value and the j-th second delay value; determining the set containing the most first elements in the set composed of first elements and satisfying the first condition, as the first test result set, includes: transforming the first matrix into a third matrix according to a preset transformation rule, wherein the preset transformation rule is: for each first element in the first column of the first matrix, if the value of the first element is n, then the value of the third element in the third matrix that is at the same position as the first element is 0; if the value of the first element is m, then the value of the third element in the third matrix that is at the same position as the first element is 1; for any first element in the first matrix other than the first column, if the value of the first element is n If the value of the first element is m, then the value of the third element in the third matrix that is in the same position as the first element is c+1; where c is the value of the element to the left of the third element in the third matrix; for each third element in each row of the third matrix, the third element with a non-zero value is taken as the target starting point, and the position of the third element with a non-zero value in the third matrix is ​​obtained and determined as the target starting point position; the third elements that satisfy the preset first sub-condition are traversed in the column direction of the column where the target starting point is located, and are taken as the fourth elements; where the preset first sub-condition is: each of the fourth elements is adjacent to each other and the value of all the fourth elements is greater than or equal to the third element; in the first matrix, with the first element corresponding to the target starting point position as the starting column, traverse s×c first elements to the left to obtain the submatrix corresponding to the target starting point, where s is the number of fourth elements obtained by traversal plus 1; the submatrix containing the most first elements in each of the submatrices is determined as the target test result subset.

[0279] This application embodiment also provides a storage device, the storage device being used for:

[0280] Obtain a first delay values ​​pre-set for the write channel of the storage device, and b second delay values ​​pre-set for the read channel of the storage device, where Xi > Xi+1 or Xi < Xi+1, and Yi > Yi+1 or Yi < Yi+1, where Xi is the i-th first delay value, Yj is the j-th second delay value, i = 1, 2, 3...a, j = 1, 2, 3...b, and a and b are natural numbers greater than 1;

[0281] Timing mode calibration tests were performed using all delay combinations formed by each of the first delay values ​​and each of the second delay values.

[0282] Based on the test results of the timing mode calibration test, the first element corresponding to each of the delay combinations is determined. If no error occurs when the timing mode calibration test is performed using the delay combination, the first element corresponding to the delay combination is a first value. If an error occurs when the timing mode calibration test is performed using the delay combination, the first element corresponding to the delay combination is a second value.

[0283] In a set consisting of first elements and satisfying a first condition, determine the set containing the most first elements as the first test result set, wherein the first condition is that all first elements in the set have the first value and all delay combinations corresponding to the first elements in the set are adjacent.

[0284] Based on the delay combination corresponding to each first element in the first test result set, a target delay combination is determined, and the delay of the write channel of the storage device is set to the first delay value in the target delay combination, and the delay of the read channel of the storage device is set to the second delay value in the target delay combination.

[0285] The storage device mentioned in this article may refer to a solid-state drive, a portable storage device, or other types of storage devices; this application makes no limitation on this.

[0286] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0287] The various embodiments in this specification are described in a related manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the apparatus embodiments are basically similar to the method embodiments, so the description is relatively simple; relevant parts can be referred to the descriptions of the method embodiments.

[0288] The above description is merely a preferred embodiment of this application and is not intended to limit the scope of protection of this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application are included within the scope of protection of this application.

Claims

1. A method for determining the timing mode calibration delay combination of a storage device, characterized in that, The method includes: Obtain *a* first delay values ​​pre-set for the write channel of the storage device, and *b* second delay values ​​pre-set for the read channel of the storage device, X i >X i+1 or X i <X i+1 And Y i >Y i+1 Or Y i <Y i+1 X i For the i-th first delay value, Y j Let be the j-th second delay value, i = 1, 2, 3...a, j = 1, 2, 3...b, where a and b are natural numbers greater than 1; Timing mode calibration tests were performed using all delay combinations formed by each of the first delay values ​​and each of the second delay values. Based on the test results of the timing mode calibration test, the first element corresponding to each of the delay combinations is determined. If no error occurs when the timing mode calibration test is performed using the delay combination, the first element corresponding to the delay combination is a first value. If an error occurs when the timing mode calibration test is performed using the delay combination, the first element corresponding to the delay combination is a second value. In a set consisting of first elements and satisfying a first condition, determine the set containing the most first elements as the first test result set, wherein the first condition is that all first elements in the set have the first value and all delay combinations corresponding to the first elements in the set are adjacent. Based on the delay combination corresponding to each first element in the first test result set, a target delay combination is determined, and the delay of the write channel of the storage device is set to the first delay value in the target delay combination, and the delay of the read channel of the storage device is set to the second delay value in the target delay combination.

2. The method according to claim 1, characterized in that, The step of determining the first element corresponding to each of the delay combinations based on the test results of the timing mode calibration test includes: Based on the test results of the timing mode calibration test, a first matrix with a rows and b columns is generated, wherein the element in the i-th row and j-th column of the first matrix is ​​the first element corresponding to the delay combination formed by the i-th first delay value and the j-th second delay value; The step of determining the set containing the most first elements from the set consisting of the first elements and satisfying the first condition, as the first test result set, includes: In the first matrix, determine the submatrix that contains the most first elements and where each first element has the first value, and use this submatrix as the first test result set.

3. The method according to claim 2, characterized in that, The step of determining a submatrix within the first matrix that contains the most first elements and where each first element takes the first value, as the first test result set, includes: For each first element in the first matrix, determine a submatrix that contains the first element and whose elements all have the first value, and use this submatrix as the first submatrix. The first submatrix containing the most elements is determined and used as the first test result set.

4. The method according to claim 1, characterized in that, The method further includes: Based on the test results of the timing mode calibration test, determine the second element corresponding to each of the delay combinations, wherein the second element is used to represent the number of bits that were erroneous when the timing mode calibration test was performed using the delay combination; The step of determining the target delay combination based on the delay combination corresponding to each first element in the first test result set includes: If the number of the first test result set is 1, then the target delay combination is determined according to the delay combination corresponding to each first element in the first test result set; If the number of the first test result sets is greater than 1, then for each of the first test result sets, the sum of the second elements corresponding to all adjacent delay combinations of the first test result set is counted as the result value corresponding to the first test result set, wherein the adjacent delay combination is the delay combination located in the neighborhood of the delay combination corresponding to the first test result set. Determine the first set of test results with the smallest corresponding result value as the target first set of test results; The target delay combination is determined based on the delay combination corresponding to each first element in the target first test result set.

5. The method according to claim 4, characterized in that, The step of determining the first element corresponding to each of the delay combinations based on the test results of the timing mode calibration test includes: Based on the test results of the timing mode calibration test, a first matrix with a rows and b columns is generated, wherein the element in the i-th row and j-th column of the first matrix is ​​the first element corresponding to the delay combination formed by the i-th first delay value and the j-th second delay value; The step of determining the set containing the most first elements from the set consisting of the first elements and satisfying the first condition, as the first test result set, includes: In the first matrix, determine the submatrix that contains the most first elements and whose first elements all take the first value, and use it as the first test result set; The step of determining the second element corresponding to each of the delay combinations based on the test results of the timing mode calibration test includes: Based on the test results of the timing mode calibration test, a second matrix with a rows and b columns is generated, wherein the element in the i-th row and j-th column of the second matrix is ​​the second element corresponding to the delay combination formed by the i-th first delay value and the j-th second delay value; The step of summing the second elements corresponding to all adjacent delay combinations in the first test result set, and using this sum as the result value for the first test result set, includes: In the second matrix, a submatrix that has the same position as the first test result set in the first matrix is ​​determined and used as the second submatrix; The sum of all row elements and column elements of the second submatrix in the second matrix is ​​used as the result value corresponding to the first test result set. The row elements are elements located in rows x1 to x2 that do not belong to the second submatrix, and the column elements are elements located in columns y1 to y2 that do not belong to the second submatrix. Here, x1 is the first row of the second submatrix, x2 is the last row of the second submatrix, y1 is the first column of the second submatrix, and y2 is the last column of the second submatrix.

6. The method according to claim 5, characterized in that, The step of determining the submatrix containing the most first elements and whose first elements all take the first value, as the first test result set, includes: For each element in the first matrix, determine a submatrix that contains the first element and whose elements all have the first value, and use this submatrix as the first test result submatrix. Record the first determined submatrix of the first test results; Whenever a new first test result submatrix is ​​determined, if the number of first elements in the new first test result submatrix is ​​greater than the number of first elements in the recorded first test result submatrix, then the recorded first test result submatrix is ​​updated to the new first test result submatrix. If the number of first elements in the new first test result submatrix is ​​equal to the number of first elements in the recorded first test result submatrix, and the position of the new first test result submatrix in the first matrix is ​​different from the position of the recorded first test result submatrix in the first matrix, then the new first test result submatrix is ​​recorded. Until all the first test result sub-matrices are determined, each recorded first test result sub-matrix is ​​used as the first test result set.

7. The method according to claim 1, characterized in that, The first value is m, and the second value is n; determining the first element corresponding to each delay combination based on the test results of the timing mode calibration test includes: Based on the test results of the timing mode calibration test, a first matrix with a rows and b columns is generated, wherein the element in the i-th row and j-th column of the first matrix is ​​the first element corresponding to the delay combination formed by the i-th first delay value and the j-th second delay value; The step of determining the set containing the most first elements from the set consisting of the first elements and satisfying the first condition, as the first test result set, includes: The first matrix is ​​transformed into a third matrix according to a preset transformation rule. The preset transformation rule is as follows: For each first element in the first column of the first matrix, if the value of the first element is n, then the value of the third element in the third matrix that is in the same position as the first element is 0; if the value of the first element is m, then the value of the third element in the third matrix that is in the same position as the first element is 1. For any first element in the first matrix other than the first column, if the value of the first element is n, then the value of the third element in the third matrix that is in the same position as the first element is 0; if the value of the first element is m, then the value of the third element in the third matrix that is in the same position as the first element is c+1; where c is the value of the element to the left of the third element in the third matrix. For each third element in each row of the third matrix, the third element with a non-zero value is taken as the target starting point, and the position of the third element with a non-zero value in the third matrix is ​​obtained and determined as the target starting point position; Traverse the column direction of the column where the target starting point is located, and use the third element that satisfies the preset first sub-condition as the fourth element; wherein, the preset first sub-condition is: each of the fourth elements is adjacent to each other and the value of all the fourth elements is greater than or equal to the third element; In the first matrix, starting from the first element corresponding to the target starting position, traverse s×c first elements to the left to obtain the submatrix corresponding to the target starting position, where s is the number of fourth elements obtained by traversal plus 1; The submatrix containing the first element the most times is determined as the target test result subset.

8. A device for determining the timing mode calibration delay combination of a storage device, characterized in that, The device includes: The acquisition module is used to acquire a first delay values ​​pre-set for the write channel of the storage device, and b second delay values ​​pre-set for the read channel of the storage device, X i >X i+1 or X i <X i+1 And Y i >Y i+1 Or Y i <Y i+1 X i For the i-th first delay value, Y j Let be the j-th second delay value, i = 1, 2, 3...a, j = 1, 2, 3...b, where a and b are natural numbers greater than 1; The test module is used to perform timing mode calibration tests using all delay combinations formed by each of the first delay values ​​and each of the second delay values. The first element determination module is used to determine the first element corresponding to each delay combination based on the test results of the timing mode calibration test. If no error occurs when the timing mode calibration test is performed using the delay combination, the first element corresponding to the delay combination is a first value. If an error occurs when the timing mode calibration test is performed using the delay combination, the first element corresponding to the delay combination is a second value. The set determination module is used to determine the set containing the most first elements from the set consisting of first elements and satisfying the first condition, and use it as the first test result set. The first condition is that the values ​​of all first elements in the set are first values, and the delay combinations corresponding to all first elements in the set are adjacent. The delay combination determination module is used to determine a target delay combination based on the delay combination corresponding to each first element in the first test result set, and set the delay of the write channel of the storage device to the first delay value in the target delay combination, and set the delay of the read channel of the storage device to the second delay value in the target delay combination.

9. The apparatus according to claim 8, characterized in that, The first element determination module is specifically used for: Based on the test results of the timing mode calibration test, a first matrix with a rows and b columns is generated, wherein the element in the i-th row and j-th column of the first matrix is ​​the first element corresponding to the delay combination formed by the i-th first delay value and the j-th second delay value; The step of determining the set containing the most first elements from the set consisting of the first elements and satisfying the first condition, as the first test result set, includes: In the first matrix, determine the submatrix that contains the most first elements and where each first element has the first value, and use it as the first test result set; The step of determining a submatrix within the first matrix that contains the most first elements and where each first element takes the first value, as the first test result set, includes: For each first element in the first matrix, determine a submatrix that contains the first element and whose elements all have the first value, and use this submatrix as the first submatrix. Determine the first submatrix containing the most elements as the first test result set; The device further includes: The second element determination module is used to determine the second element corresponding to each of the delay combinations based on the test results of the timing mode calibration test, wherein the second element is used to represent the number of bits that were erroneous when the timing mode calibration test was performed using the delay combination; The delay combination determination module is specifically used for: If the number of the first test result set is 1, then the target delay combination is determined according to the delay combination corresponding to each first element in the first test result set; If the number of the first test result sets is greater than 1, then for each of the first test result sets, the sum of the second elements corresponding to all adjacent delay combinations of the first test result set is counted as the result value corresponding to the first test result set, wherein the adjacent delay combination is the delay combination located in the neighborhood of the delay combination corresponding to the first test result set. Determine the first set of test results with the smallest corresponding result value as the target first set of test results; The target delay combination is determined based on the delay combination corresponding to each first element in the target first test result set; The first element determination module is specifically used for: Based on the test results of the timing mode calibration test, a first matrix with a rows and b columns is generated, wherein the element in the i-th row and j-th column of the first matrix is ​​the first element corresponding to the delay combination formed by the i-th first delay value and the j-th second delay value; The set determination module is specifically used for: In the first matrix, determine the submatrix that contains the most first elements and whose first elements all take the first value, and use it as the first test result set; The second element determination module is specifically used for: Based on the test results of the timing mode calibration test, a second matrix with a rows and b columns is generated, wherein the element in the i-th row and j-th column of the second matrix is ​​the second element corresponding to the delay combination formed by the i-th first delay value and the j-th second delay value; The step of summing the second elements corresponding to all adjacent delay combinations in the first test result set, and using this sum as the result value for the first test result set, includes: In the second matrix, a submatrix that has the same position as the first test result set in the first matrix is ​​determined and used as the second submatrix; The sum of all row elements and column elements of the second submatrix in the second matrix is ​​used as the result value corresponding to the first test result set. The row elements are elements located in rows x1 to x2 that do not belong to the second submatrix, and the column elements are elements located in columns y1 to y2 that do not belong to the second submatrix. Here, x1 is the first row of the second submatrix, x2 is the last row of the second submatrix, y1 is the first column of the second submatrix, and y2 is the last column of the second submatrix. The step of determining the submatrix containing the most first elements and whose first elements all take the first value, as the first test result set, includes: For each element in the first matrix, determine a submatrix that contains the first element and whose elements all have the first value, and use this submatrix as the first test result submatrix. Record the first determined submatrix of the first test results; Whenever a new first test result submatrix is ​​determined, if the number of first elements in the new first test result submatrix is ​​greater than the number of first elements in the recorded first test result submatrix, then the recorded first test result submatrix is ​​updated to the new first test result submatrix. If the number of first elements in the new first test result submatrix is ​​equal to the number of first elements in the recorded first test result submatrix, and the position of the new first test result submatrix in the first matrix is ​​different from the position of the recorded first test result submatrix in the first matrix, then the new first test result submatrix is ​​recorded. Until all the first test result sub-matrices are determined, each recorded first test result sub-matrix is ​​used as the first test result set. The first value is m, and the second value is n; the first element determination module is specifically used for: Based on the test results of the timing mode calibration test, a first matrix with a rows and b columns is generated, wherein the element in the i-th row and j-th column of the first matrix is ​​the first element corresponding to the delay combination formed by the i-th first delay value and the j-th second delay value; The step of determining the set containing the most first elements from the set consisting of the first elements and satisfying the first condition, as the first test result set, includes: The first matrix is ​​transformed into a third matrix according to a preset transformation rule. The preset transformation rule is as follows: For each first element in the first column of the first matrix, if the value of the first element is n, then the value of the third element in the third matrix that is in the same position as the first element is 0; if the value of the first element is m, then the value of the third element in the third matrix that is in the same position as the first element is 1. For any first element in the first matrix other than the first column, if the value of the first element is n, then the value of the third element in the third matrix that is in the same position as the first element is 0; if the value of the first element is m, then the value of the third element in the third matrix that is in the same position as the first element is c+1; where c is the value of the element to the left of the third element in the third matrix. For each third element in each row of the third matrix, the third element with a non-zero value is taken as the target starting point, and the position of the third element with a non-zero value in the third matrix is ​​obtained and determined as the target starting point position; Traverse the column direction of the column where the target starting point is located, and use the third element that satisfies the preset first sub-condition as the fourth element; wherein, the preset first sub-condition is: each of the fourth elements is adjacent to each other and the value of all the fourth elements is greater than or equal to the third element; In the first matrix, starting from the first element corresponding to the target starting position, traverse s×c first elements to the left to obtain the submatrix corresponding to the target starting position, where s is the number of fourth elements obtained by traversal plus 1; The submatrix containing the first element the most times is determined as the target test result subset.

10. A storage device, characterized in that, The storage device is used for: Obtain a first delay values ​​pre-set for the write channel of the storage device, and b second delay values ​​pre-set for the read channel of the storage device, where Xi > Xi+1 or Xi < Xi+1, and Yi > Yi+1 or Yi < Yi+1, where Xi is the i-th first delay value, Yj is the j-th second delay value, i = 1, 2, 3...a, j = 1, 2, 3...b, and a and b are natural numbers greater than 1; Timing mode calibration tests were performed using all delay combinations formed by each of the first delay values ​​and each of the second delay values. Based on the test results of the timing mode calibration test, the first element corresponding to each of the delay combinations is determined. If no error occurs when the timing mode calibration test is performed using the delay combination, the first element corresponding to the delay combination is a first value. If an error occurs when the timing mode calibration test is performed using the delay combination, the first element corresponding to the delay combination is a second value. In a set consisting of first elements and satisfying a first condition, determine the set containing the most first elements as the first test result set, wherein the first condition is that all first elements in the set have the first value and all delay combinations corresponding to the first elements in the set are adjacent. Based on the delay combination corresponding to each first element in the first test result set, a target delay combination is determined, and the delay of the write channel of the storage device is set to the first delay value in the target delay combination, and the delay of the read channel of the storage device is set to the second delay value in the target delay combination.

Images