Integrated circuits, integrated circuit control methods and control systems

Abstract

This application discloses an integrated circuit, a control method for an integrated circuit, and a control system for an integrated circuit, relating to the field of electronic circuit technology. The integrated circuit includes an enable circuit and a digital circuit module. The enable circuit includes a first input terminal, a second input terminal, a third input terminal, and an output terminal. The first input terminal receives a serial data input signal, the second input terminal receives a chip select signal, the third input terminal receives a hold signal, and the output terminal outputs an internal enable signal that controls the power-on or power-off of the integrated circuit. The digital circuit module outputs the hold signal and, after the enable branch outputs the internal enable signal controlling the power-on of the integrated circuit based on the serial data input signal and the chip select signal, configures the hold signal to ensure that the output terminal maintains the output of the internal enable signal controlling the power-on of the integrated circuit. This approach reduces cost and the size of the integrated circuit.

Description

Technical Field

[0001] This application relates to the field of electronic circuit technology, and in particular to an integrated circuit, a control method for an integrated circuit, and a control system for an integrated circuit. Background Technology

[0002] The Serial Peripheral Interface (SPI) bus was created in the 1980s to facilitate communication between a microcontroller and the various integrated circuits coupled to it. Most integrated circuits have an enable port for controlling the power-on and power-off of the integrated circuit. Figure 1 This illustrates an integrated circuit with an enable port. For example... Figure 1 As shown, the integrated circuit 100 includes a power management module 101, a digital circuit module 102, and an analog circuit module 103.

[0003] Integrated circuit 100 also includes at least eight input / output ports: a power bus port VBB, an output voltage port Vo, a ground port GND, an enable port EN, a serial data input port SDI, a serial data output port SDO, a serial clock port SCK, and a chip select port nCS. The serial data input port SDI, serial data output port SDO, serial clock port SCK, and chip select port nCS are used to communicate with the microcontroller using SPI signals. The serial data input port SDI is configured to receive serial data generated by the microcontroller, and the serial data output port SDO is configured to transmit serial signals to the microcontroller. The serial clock port SCK is configured to receive a clock signal generated by the microcontroller. The chip select port nCS is configured to receive a chip select signal that determines whether the integrated circuit is communicating with the microcontroller at a given time. The enable port EN is configured to receive an enable signal generated by the microcontroller. The enable signal is used to control the power-on and power-off of the integrated circuit.

[0004] Figure 2 An exemplary schematic diagram of a control system including a microcontroller and multiple integrated circuits with enable ports EN is shown. The control system includes a microcontroller 200 and multiple integrated circuits 100. A serial communication protocol (e.g., SPI) is used to provide a communication channel between the various elements of the control system. Figure 2 As shown, the microcontroller 200 includes three serial peripheral interface ports: master output / slave input port MOSI, master input / slave output port MISO, and serial clock port SCK. The master output / slave input port MOSI, master input / slave output port MISO, and serial clock port SCK of the microcontroller 200 are respectively connected to the serial data input port SDI, serial data output port SDO, and serial clock port SCK of each integrated circuit.

[0005] The microcontroller 200 also includes multiple chip select ports, namely SS1, SS2, ..., SSn. One chip select port of the microcontroller 200 is connected to the chip select port of an integrated circuit 100. In practical applications, the chip select port of the microcontroller 200 is configured to generate a chip select signal, specifying which integrated circuit the microcontroller 200 communicates with at a given time. When the chip select signal is low, it indicates that communication with the integrated circuit corresponding to that chip select signal is activated.

[0006] The microcontroller 200 also includes multiple enable ports, namely enable port EN1, enable port EN2, ..., enable port ENn. One enable port of the microcontroller 200 is connected to the enable port EN of an integrated circuit 100. A dedicated enable port of the integrated circuit is required to control the power-on and power-off of the integrated circuit 100. Once the integrated circuit 100 is powered on, SPI communication can be established, enabling the microcontroller 200 to communicate with the integrated circuit 100 via the SPI interface.

[0007] exist Figure 2 In the control system shown, there may be many integrated circuits 100, each requiring a dedicated enable port and a connection cable between the enable port and the microcontroller 200. The enable ports of the integrated circuits 100 and the connection cables between the enable ports and the microcontroller 200 increase the cost and size of the control system. Summary of the Invention

[0008] This application aims to provide an integrated circuit, a method for controlling an integrated circuit, and a control system for an integrated circuit, which can reduce costs and decrease the size of the integrated circuit.

[0009] To achieve the above objectives, in a first aspect, this application provides an integrated circuit, comprising:

[0010] The enable circuit includes a first input terminal, a second input terminal, a third input terminal, and an output terminal. The first input terminal is used to receive a serial data input signal, the second input terminal is used to receive a chip select signal, the third input terminal is used to receive a hold signal, and the output terminal is used to output an internal enable signal that controls the power-on or power-off of the integrated circuit.

[0011] A digital circuit module is configured to output the hold signal and, after the enable branch outputs an internal enable signal controlling the power-on of the integrated circuit based on the serial data input signal and the chip select signal, configure the hold signal to keep the output terminal outputting the internal enable signal controlling the power-on of the integrated circuit.

[0012] In an alternative embodiment, the enabling circuit is further configured to configure the internal enabling signal to a first enabling logic state when the chip select signal is in a first chip select logic state and the serial data input signal is in a first data logic state, so as to power on the integrated circuit.

[0013] The digital circuit module is further configured to set the hold signal to the first hold logic state when the internal enable signal is the first enable logic state;

[0014] The enabling circuit is further configured to set the internal enabling signal to the first enabling logic state when the holding signal is in the first holding logic state, so as to keep the integrated circuit powered on.

[0015] The first chip select logic state, the first data logic state, the first enable logic state, and the first hold logic state all include a high level or a low level.

[0016] In one alternative approach, the first chip select logic state is low, and the first data logic state, the first enable logic state, and the first hold logic state are all high.

[0017] In one alternative, when the hold signal is in the first hold logic state, the hold signal covers the chip select signal and the serial data input signal, so that the chip select signal and the serial data input signal cannot be applied to the integrated circuit through the enable circuit.

[0018] In an alternative embodiment, the digital circuit module is further configured to receive a power-down command output by the controller, and configure the hold signal based on the power-down command so that the output of the enable circuit outputs an internal enable signal that controls the power-down of the integrated circuit.

[0019] In an alternative embodiment, the digital circuit module is further configured to configure the holding signal to a second holding logic state based on the power-down command, thereby configuring the internal enable signal to a second enable logic state to power down the integrated circuit;

[0020] Both the second enable logic state and the second hold logic state include a high level or a low level.

[0021] In one alternative approach, both the second enable logic state and the second hold logic state are low.

[0022] In one alternative embodiment, the enabling circuit includes a first N-type transistor, a second N-type transistor, a third N-type transistor, a first P-type transistor, a second P-type transistor, a first resistor, a second resistor, a third resistor, and a Zener diode;

[0023] The first P-type transistor, the second N-type transistor, and the second resistor are connected in series between the power bus and ground;

[0024] The gate of the third N-type transistor receives the hold signal, and the third N-type transistor is connected between the first P-type transistor and ground;

[0025] The third resistor is connected in parallel with the Zener diode;

[0026] The gate of the second N-type transistor receives the serial data input signal through the first resistor;

[0027] The gate of the first N-type transistor receives the chip select signal, and the first N-type transistor is connected between the gate of the second N-type transistor and ground;

[0028] The second P-type transistor and the Zener diode are connected in series between the power bus and ground, and the gate of the second P-type transistor is connected to the gate and drain of the first P-type transistor, respectively.

[0029] The internal enable signal is generated at the common node of the second P-type transistor and the Zener diode.

[0030] In one alternative embodiment, the enabling circuit further includes a fourth N-type transistor;

[0031] The gate of the fourth N-type transistor receives the hold signal, and the fourth N-type transistor is connected between the gate of the second N-type transistor and ground.

[0032] Secondly, this application provides a control method for an integrated circuit, wherein the integrated circuit inputs a serial data input signal and a chip select signal, the method comprising:

[0033] Configure the chip select signal to a first chip select logic state to allow external devices to control the integrated circuit;

[0034] When the serial data input signal is in the first data logic state, the internal enable signal is configured to be in the first enable logic state, wherein the integrated circuit is powered on when the internal enable signal is in the first enable logic state.

[0035] When the internal enable signal is in the first enable logic state, the hold signal is configured to be in the first hold logic state, wherein when the hold signal is in the first hold logic state, the internal enable signal is held to be in the first enable logic state.

[0036] The first chip select logic state, the first data logic state, the first enable logic state, and the first hold logic state all include a high level or a low level.

[0037] In one alternative approach, the first chip select logic state is low, and the first data logic state, the first enable logic state, and the first hold logic state are all high.

[0038] In an alternative approach, the method further includes:

[0039] If a power-down command is received from the controller, the holding signal is configured to switch from the first holding logic state to the second holding logic state, wherein the second holding logic state includes a high level or a low level, and the level of the second holding logic state is different from that of the first holding logic state.

[0040] When the hold signal is in the second hold logic state, the internal enable signal is configured to be in the second enable logic state, wherein the second enable logic state includes a high level or a low level, and the level of the second enable logic state is different from that of the first enable logic state.

[0041] Specifically, when the internal enable signal is in the second enable logic state, the integrated circuit is powered down.

[0042] In one alternative approach, both the second hold logic state and the second enable logic state are low.

[0043] In an alternative approach, the method further includes:

[0044] After receiving the power-down command, and when the hold signal switches from the first hold logic state to the second hold logic state, configure the chip select signal to the second chip select logic state and / or configure the serial data input signal to the second data logic state;

[0045] The second chip select logic state and the second data logic state include a high level or a low level.

[0046] In one alternative approach, both the second chip select logic state and the second data logic state are at a low level.

[0047] In an alternative approach, the method further includes:

[0048] Configure the enable circuit to generate the internal enable signal, and configure the digital circuit module to generate the hold signal;

[0049] The enable circuit includes a first input terminal, a second input terminal, a third input terminal, and an output terminal. The first input terminal is used to receive the serial data input signal, the second input terminal is used to receive the chip select signal, the third input terminal is used to receive the hold signal, and the output terminal is used to output the internal enable signal.

[0050] In an alternative approach, the method further includes:

[0051] When the hold signal is in the first hold logic state, the hold signal covers the chip select signal and the serial data input signal, so that the chip select signal and the serial data input signal cannot affect the internal enable signal through the enable circuit.

[0052] In one alternative embodiment, the enabling circuit includes a first N-type transistor, a second N-type transistor, a third N-type transistor, a first P-type transistor, a second P-type transistor, a first resistor, a second resistor, a third resistor, and a Zener diode;

[0053] The first P-type transistor, the second N-type transistor, and the second resistor are connected in series between the power bus and ground;

[0054] The gate of the third N-type transistor receives the hold signal, and the third N-type transistor is connected between the first P-type transistor and ground;

[0055] The third resistor is connected in parallel with the Zener diode;

[0056] The gate of the second N-type transistor receives the serial data input signal through the first resistor;

[0057] The gate of the first N-type transistor receives the chip select signal, and the first N-type transistor is connected between the gate of the second N-type transistor and ground;

[0058] The second P-type transistor and the Zener diode are connected in series between the power bus and ground, and the gate of the second P-type transistor is connected to the gate and drain of the first P-type transistor, respectively.

[0059] The internal enable signal is generated at the common node of the second P-type transistor and the Zener diode.

[0060] In one alternative embodiment, the enabling circuit further includes a fourth N-type transistor;

[0061] The gate of the fourth N-type transistor receives the hold signal, and the fourth N-type transistor is connected between the gate of the second N-type transistor and ground.

[0062] Thirdly, this application provides a control system including a controller and an integrated circuit as described above, wherein the controller is connected to the integrated circuit.

[0063] The beneficial effects of this application are as follows: The integrated circuit provided in this application includes an enable circuit and a digital circuit module. The enable circuit includes a first input terminal, a second input terminal, a third input terminal, and an output terminal. The first input terminal is used to receive a serial data input signal, the second input terminal is used to receive a chip select signal, the third input terminal is used to receive a hold signal, and the output terminal is used to output an internal enable signal that controls the power-on or power-off of the integrated circuit. The digital circuit module is used to output the hold signal. The digital circuit module is also used to configure the hold signal so that the output terminal holds the output of the internal enable signal that controls the power-on of the integrated circuit after the enable branch outputs the internal enable signal based on the serial data input signal and the chip select signal. Therefore, this integrated circuit no longer needs to have an enable port, no longer needs to have a connection line between it and the controller, and does not need to occupy an output port of the controller. Compared with the related technologies that require a dedicated enable port and a connection line between the enable port and the microcontroller, this application can reduce costs and the size of the integrated circuit. Attached Figure Description

[0064] One or more embodiments are illustrated by way of example with reference numerals in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are denoted as similar elements. Unless otherwise stated, the figures in the drawings are not to be limited by scale.

[0065] Figure 1 This is a schematic diagram of the structure of an integrated circuit in related technologies;

[0066] Figure 2 This is a schematic diagram of the structure of an integrated circuit in related technologies;

[0067] Figure 3 This is a schematic diagram of the control system provided in Embodiment 1 of this application;

[0068] Figure 4 This is a schematic diagram of the integrated circuit structure provided in Embodiment 1 of this application;

[0069] Figure 5 A schematic diagram of the circuit structure of the integrated circuit provided in Embodiment 1 of this application;

[0070] Figure 6 This is a schematic diagram of the signals in the integrated circuit provided in Embodiment 1 of this application;

[0071] Figure 7 This is a schematic diagram of the signals in the integrated circuit provided in Embodiment 2 of this application;

[0072] Figure 8 This is a flowchart of the control method for an integrated circuit provided in Embodiment 1 of this application. Detailed Implementation

[0073] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0074] Please refer to Figure 3 , Figure 3 This is a schematic diagram of the structure of the control system 1000 provided in an embodiment of this application. Figure 3 As shown, the control system 1000 includes a controller 400 and at least one integrated circuit 300. The controller 400 is connected to each integrated circuit 300. The controller 400 communicates with each integrated circuit 300 via a serial communication protocol.

[0075] The controller 400 includes three serial peripheral interface ports: a master-slave input port (MOSI), a master-slave output port (MISO), and a serial clock port (SCK). Each integrated circuit 300 also includes a serial data input port (SDI), a serial data output port (SDO), and a serial clock port (SCK). The master-slave input port (MOSI), master-slave output port (MISO), and serial clock port (SCK) of the controller 400 are respectively connected to the serial data input port (SDI), serial data output port (SDO), and serial clock port (SCK) of each integrated circuit 300. Each integrated circuit 300 receives serial data through the serial data input port (SDI) and transmits serial data through the serial data output port (SDO). The serial clock port (SCK) is a clock signal used to synchronize data transmission between devices. The clock signal ensures that the transmitting and receiving devices are synchronized in time, enabling them to correctly interpret the transmitted data.

[0076] The controller 400 also includes multiple chip select ports, namely chip select port SS1, chip select port SS2, ..., chip select port SSn. Each integrated circuit 300 also includes a chip select port nCS. One chip select port of the controller 400 is connected to the chip select port of an integrated circuit 300. The chip select port of the controller 400 is configured to generate a chip select signal that specifies which integrated circuit the controller 400 communicates with at a given time. In practical applications, the controller 400 pulls the chip select port of the integrated circuit 300 to be communicated with (or the integrated circuit 300 to be controlled) low. Then, the controller 400 sends and receives data according to a clock signal. After the data transmission is complete, the controller 400 pulls the chip select port of the integrated circuit 300 high to release the data transmission line. The state change of the chip select port indicates that communication with a specific integrated circuit 300 is about to begin or has been completed. The chip select port and associated chip select signal allow multiple integrated circuits 300 to share the same SPI bus without interfering with each other, because only the selected integrated circuit 300 responds to the data (i.e., SDO transmits data and SDI receives data) and clock SCK signal.

[0077] and Figure 2 Compared to the control systems in the related technologies shown, Figure 3 The control system provided in the embodiment of this application, as shown, eliminates the enable port for each integrated circuit, saving numerous input / output ports and thus reducing overall system cost. Furthermore, reducing the total number of ports simplifies wiring in large integrated circuit systems, which is beneficial for reducing printed circuit board (PCB) area and cost. Therefore, the goals of cost reduction and integrated circuit size reduction are achieved.

[0078] In practical applications, the control system 1000 provided in this application embodiment relies on a specific combination of chip select signals and serial data input signals to control the power-on and power-off of each integrated circuit 300. The detailed working principle of the power-on and power-off process of the integrated circuit 300 will be described in detail below.

[0079] Please refer to Figure 4 , Figure 4 This is a schematic diagram of the structure of the integrated circuit 300 provided in an embodiment of this application. Figure 4 As shown, the integrated circuit 300 includes an enable circuit 301 and a digital circuit module 302.

[0080] The enable circuit 301 includes a first input terminal, a second input terminal, a third input terminal, and an output terminal. The first input terminal is used to receive the serial data input signal S_SDI; the second input terminal is used to receive the chip select signal S_nCS; the third input terminal is used to receive the hold signal HLD; and the output terminal is used to output the internal enable signal INT_EN for controlling the power-on or power-off of the integrated circuit 300.

[0081] The digital circuit module 302 is used to output a hold signal HLD, and is used to configure the hold signal HLD so that the output terminal of the enable circuit 301 holds the internal enable signal INT_EN of the power-on control integrated circuit 300 after the enable branch 301 outputs the power-on control integrated circuit 300 based on the serial data input signal S_SDI and the chip select signal S_nCS.

[0082] Specifically, during the power-on process of integrated circuit 300, the chip select logic state (including high and low levels) of the chip select signal S_nCS input to integrated circuit 300 is changed to allow controller 400 to control integrated circuit 300. For example, in one embodiment, the chip select signal S_nCS is configured to a first chip select logic state to allow controller 400 to control integrated circuit 300. Simultaneously, in response to the serial data input signal S_SDI being in a first data logic state (including high and low levels), the internal enable signal INT_EN is configured to a first enable logic state (including high and low levels) to power on integrated circuit 300. In summary, the enable circuit 301 can configure the internal enable signal INT_EN to a first enable logic state to power on integrated circuit 300 when the chip select signal S_nCS is in the first chip select logic state and the serial data input signal S_SDI is in the first data logic state. Next, in response to the internal enable signal INT_EN being in the first enable logic state, the digital circuit module 302 configures the hold signal HLD to be in the first hold logic state (including high and low levels). Specifically, when the hold signal HLD is in the first hold logic state, the internal enable signal remains in the first enable logic state. In other words, the enable circuit 301 can also configure the internal enable signal INT_EN to be in the first enable logic state when the hold signal HLD is in the first hold logic state, to keep the integrated circuit 300 powered on.

[0083] In one embodiment, the first chip select logic state is low, and the first data logic state, the first enable logic state, and the first hold logic state are all high.

[0084] In one embodiment, when the hold signal HLD is in the first hold logic state, the hold signal HLD covers the chip select signal S_nCS and the serial data input signal S_SDI, so that the internal enable signal INT_EN is not affected by the chip select signal S_nCS and the serial data input signal S_SDI. In other words, when the hold signal HLD is in the first hold logic state, the chip select signal S_nCS and the serial data input signal S_SDI cannot act on the integrated circuit 300 through the enable circuit 301. Therefore, the integrated circuit 300 can be kept in the power-on state.

[0085] During the power-down process of integrated circuit 300, digital circuit module 302 is also used to receive the power-down command output by controller 400 via SPI bus, and configure the holding signal HLD based on the power-down command so that the output terminal of enable circuit 301 outputs the internal enable signal INT_EN to control the power-down of integrated circuit 300. Specifically, in one embodiment, in response to the power-down command from controller 400, digital circuit module 302 configures the holding signal HLD to a second holding logic state (including high level or low level, and the level of the second holding logic state is different from that of the first holding logic state). Specifically, the chip select signal S_nCS corresponding to integrated circuit 300 is configured to the first chip select logic state, and the power-down command output by controller 400 is transmitted to the digital circuit module 302 of the integrated circuit via serial data input signal S_SDI. When the holding signal HLD is in the second holding logic state, the internal enable signal INT_EN switches from the first enable logic state to the second enable logic state (including high level or low level, and the level of the second enable logic state is different from that of the first enable logic state). Once the internal enable signal INT_EN is in the second enable logic state, the integrated circuit 300 will power down.

[0086] In one embodiment, both the second enable logic state and the second hold logic state are at a low level.

[0087] Please refer to Figure 5 , Figure 5 An exemplary circuit structure of integrated circuit 300 is shown. For example... Figure 5 As shown, the enable circuit 301 includes a first N-type transistor M1, a second N-type transistor M2, a third N-type transistor M3, a first P-type transistor MP1, a second P-type transistor MP2, a first resistor R1, a second resistor R2, a third resistor R3, and a Zener diode Z1.

[0088] In this configuration, the first P-type transistor MP1, the second N-type transistor M2, and the second resistor R2 are connected in series between the power bus L_VBB and ground. The gate of the third N-type transistor M3 receives the hold signal HLD, and the third N-type transistor M3 is connected between the first P-type transistor MP1 and ground. The third resistor R3 is connected in parallel with the Zener diode Z1. The gate of the second N-type transistor M2 receives the serial data input signal S_SDI through the first resistor R1. The gate of the first N-type transistor M1 receives the chip select signal S_nCS, and the first N-type transistor M1 is connected between the gate of the second N-type transistor M2 and ground. The second P-type transistor MP1 and the Zener diode Z1 are connected in series between the power bus L_VBB and ground, and the gate of the second P-type transistor MP2 is connected to both the gate and drain of the first P-type transistor MP1. The internal enable signal INT_EN is generated at the common node of the second P-type transistor MP2 and the Zener diode Z1. The gate of the fourth N-type transistor M4 receives the hold signal HLD, and the fourth N-type transistor M4 is connected between the gate of the second N-type transistor M2 and ground.

[0089] Specifically, the power bus L_VBB is connected to the positive terminal of the battery (not shown). The drain of the third N-type transistor M3 is connected to the drain of the first P-type transistor MP1. The source of the third N-type transistor M3 is connected to the source of the second N-type transistor M2. In this embodiment, the source of the third N-type transistor M3 is grounded through the second resistor R2. In other embodiments, a separate resistor can be provided between the source of the third N-type transistor M3 and ground. In this configuration, the source of the third N-type transistor M3 is not directly connected to the source of the second N-type transistor M2 or ground. The serial data input signal S_SDI is fed into the gate of the second N-type transistor M2 through the first resistor R1, while the chip select signal S_nCS is applied to the gate of the first N-type transistor M1. The gate of the third N-type transistor M3 is configured to receive the hold signal HLD generated by the digital circuit module 302. The gates of the first P-type transistor MP1 and the second P-type transistor MP2 are connected together and further connected to the drain of the first P-type transistor MP1. The first P-type transistor MP1 and the second P-type transistor MP2 form a current mirror structure. The drain of the first N-type transistor M1 is connected to the gate of the second N-type transistor M2. The source of the first N-type transistor M1 is connected to ground. The drain of the fourth N-type transistor M4 is connected to the drain of the first N-type transistor M1. The source of the fourth N-type transistor M4 is connected to the source of the first N-type transistor M1. The gate of the fourth N-type transistor M4 is configured to receive the hold signal HLD.

[0090] In this embodiment, the integrated circuit 300 further includes a low-dropout linear regulator 303 and a main circuit 304. An internal enable signal INT_EN is input to the low-dropout linear regulator 303. When the internal enable signal INT_EN is in a first enable logic state, the low-dropout linear regulator 303 provides a bias voltage VDD to the digital circuit module 302 and the main circuit 304 based on the power supply on the power bus L_VBB, thereby enabling the digital circuit module 302 and the main circuit 304 to operate. The main circuit 304 is configured to perform the main functions of the integrated circuit 300. In one embodiment, the main circuit 304 corresponds to... Figure 1 The analog circuit module 103 shown is used to process analog signals; the low dropout linear regulator 303 corresponds to this. Figure 1 The power management module 101 and digital circuit module 302 shown are in... Figure 1 Improvements made to the digital circuit module 102 shown.

[0091] In practical applications, before the integrated circuit 300 is powered on, when the serial data input signal S_SDI is high and the chip select signal S_nCS is low, the first N-type transistor M1 is turned off. The serial data input signal S_SDI drives the gate of the second N-type transistor M2 to a high level to turn it on. The current flowing through the second N-type transistor M2 is mirrored to the right-hand circuit formed by the second P-type transistor MP2 and the Zener diode Z1. The current flowing through the second P-type transistor MP2 provides the initial power supply for the low-dropout linear regulator 303. The Zener diode Z1 is used to stabilize the voltage of this power supply. The voltage at the common node of the second P-type transistor MP2 and the Zener diode Z1 can be considered as the internal enable signal INT_EN. The internal enable signal INT_EN is used to enable the low-dropout linear regulator 303. After the low-dropout linear regulator 303 is started, the voltage on the power bus L_VBB is converted into the bias voltage VDD of the digital circuit module 302 and the main circuit 303. After the digital circuit module 302 is powered on, it configures its output hold signal HLD to be high. Then, the hold signal HLD (which is high at this time) turns on the third N-type transistor M3 to maintain the current flowing through the first P-type transistor MP1, thereby maintaining the internal enable signal INT_EN at a high level.

[0092] In an optional implementation, the fourth N-type transistor M4 can be configured to be turned on by a hold signal HLD. Turning on the fourth N-type transistor M4 will turn off the second N-type transistor M2. Therefore, the hold signal HLD, by turning on the fourth N-type transistor M4, covers the serial data input signal S_SDI and the chip select signal S_nCS, thereby preventing the serial data input signal S_SDI and the chip select signal S_nCS from affecting the internal enable signal INT_EN through the enable circuit 301 after the integrated circuit 300 is powered on. Specifically, when the hold signal HLD is high, the turn on of the fourth N-type transistor M4 pulls the gate of the second N-type transistor M2 low, thereby preventing the combination of the serial data input signal S_SDI and the chip select signal S_nCS from changing the operating state of the second N-type transistor M2 and thus affecting the enable state of the integrated circuit 300.

[0093] The power-down process is entirely conducted via SPI communication between the controller 400 and the integrated circuit 300. The controller 400 sends a power-down command to the digital circuit module 302 of the integrated circuit 300 via the SPI bus, causing the digital circuit module 302 to configure its output hold signal HLD low. In response to the hold signal HLD being low, the power-down process of the integrated circuit 300 begins. Once the hold signal HLD is logic low, the third N-type transistor M3 is turned off. The turning off of the third N-type transistor M3 causes the current flowing through the first P-type transistor MP1 to stop, thereby turning off the second P-type transistor MP2. Once the second P-type transistor MP2 is turned off, the third resistor R3 pulls the internal enable signal INT_EN low, thereby turning off the low-dropout linear regulator 303 to complete the power-down process of the integrated circuit 300.

[0094] It should be noted that the first N-type transistor M1, the second N-type transistor M2, the third N-type transistor M3, the first P-type transistor MP1, the second P-type transistor MP2, the second resistor R2, the third resistor R3, and the Zener diode Z1 form the initial bias circuit 3011. The initial bias circuit 3011 functions similarly to an OR gate. Specifically, when both the serial data input signal S_SDI and the inverted signal S_nCS are at logic high, or when the hold signal HLD is at logic high, the initial bias circuit 3011 can configure the internal enable signal INT_EN to be at logic high.

[0095] Furthermore, the fourth N-type transistor M4 forms an optional module 3012. Optional module 3012 is used to further reduce the power consumption of the enable circuit 301. Once the controller 400 sends a command to set the enable signal HLD to a low level (e.g., a power-down command PD) via the SPI interface, the chip select signal S_nCS can be set to a logic high level to prevent the second N-type transistor M2 from being mistakenly turned on during power-down; alternatively, the serial data input signal S_SDI can be set to a logic low level to prevent the second N-type transistor M2 from being mistakenly turned on during power-down.

[0096] The application scenario for enable circuit 301 is as follows: Before enabling, the disabled integrated circuit 300 has no internal power supply. At this time, although integrated circuit 300 is connected to the power bus L_VBB, the digital circuit module 302 is not powered on before being enabled because no bias voltage VDD is available. As described above, by using enable circuit 301, integrated circuit 300 can be enabled via SPI signal, and integrated circuit 300 can be powered on via enable circuit 301. After integrated circuit 300 is powered on, it can communicate with controller 400 via SPI bus.

[0097] Please refer to Figure 6 , Figure 6 An example is shown Figure 5 The circuit shown is illustrated in a first schematic diagram of the signals. (See diagram below.) Figure 6 As shown, Figure 6 The horizontal axis represents time. Figure 6 The vertical axis has five rows. The first row represents the chip select signal S_nCS; the second row represents the serial data input signal S_SDI; the third row represents the internal enable signal INT_EN; the fourth row represents the hold signal HLD; and the fifth row represents the output Vo of the integrated circuit 300 (in this embodiment, a high level output Vo indicates that the integrated circuit 300 has completed power-on). In the serial data input signal S_SDI, "X" indicates that it can be any data, "1" indicates a high level, and "PD" indicates a power-down command.

[0098] Please refer to the above as well. Figure 5 and Figure 6Before time t1, integrated circuit 300 is in a powered-down state. Output Vo is low, and chip select signal S_nCS is high. At time t1, chip select signal S_nCS changes from logic high to logic low. In response to chip select signal S_nCS being low, the first N-type transistor M1 is turned off, allowing controller 400 to configure the gate voltage of the second N-type transistor M2 via serial data input signal S_SDI. At time t1, to power on integrated circuit 300, serial data input signal S_SDI is configured to be high. The logic high level of serial data input signal S_SDI causes the internal enable signal INT_ENT to go high. Specifically, when serial data input signal S_SDI is high, the second N-type transistor M2 is turned on. The current flowing through the second N-type transistor M2 is mirrored by a current mirror composed of the first P-type transistor MP1 and the second P-type transistor MP2 to the right-side circuit formed by the second P-type transistor MP2 and Zener diode Z1 connected in series. At this point, the current flowing through the second P-type transistor MP2 establishes an internal enable signal INT_EN with a logic high level.

[0099] In response to the internal enable signal INT_EN going high, the digital circuit module 302 configures the hold signal HLD to change from logic low to logic high at time t2. After a predetermined delay, the output voltage Vo is established at time t3. At time t4, SPI communication between the controller 400 and the integrated circuit 300 proceeds normally. The serial data input signal S_SDI can have any value according to the requirements of the function and / or instructions sent by the controller 400.

[0100] After time t4, to prevent the internal enable signal INT_EN from being changed when integrated circuit 300 stops communicating with controller 400 (e.g., when the chip select signal S_nCS goes high between time t5 and t6), the hold signal HLD can be used to cover the serial data input signal S_SDI, the chip select signal S_nCS, and combinations of the serial data input signal S_SDI and the chip select signal S_nCS. This prevents the combinations of the serial data input signal S_SDI, the chip select signal S_nCS, and combinations of the serial data input signal S_SDI and the chip select signal S_nCS from affecting the internal enable signal INT_EN through enable circuit 301, maintaining the logic high level state of the internal enable signal INT_EN. Once the hold signal HLD is high, the third N-type transistor M3 is turned on. The turn-on of the third N-type transistor M3 replaces the second N-type transistor M2 to maintain the internal enable signal INT_EN in a logic high level state. In addition, once the hold signal HLD is high, the fourth N-type transistor M4 is turned on. The conduction of the fourth N-type transistor M4 pulls the gate of the second N-type transistor M2 low, keeping the second N-type transistor M2 off, thereby preventing at least one of the serial data input signal S_SDI and the chip select signal S_nCS from affecting the enable state of the integrated circuit 300 through the enable circuit 301.

[0101] At time t7, the controller 400 sends a power-down command PD to the integrated circuit 300 via the SPI bus through the serial data input signal S_SDI. After the communication related to the power-down command PD is completed, the chip select signal S_nCS is pulled high at time t8, ending the communication with the integrated circuit 300. In response to the power-down command from the controller 400, after a certain delay, at time t9, the configuration hold signal HLD of the digital circuit module 302 switches from logic high to logic low.

[0102] It should be noted that, depending on the application and design requirements, the delay time in the above embodiments can also be zero.

[0103] In this embodiment, the internal enable signal INT_EN immediately changes from logic high to logic low after the HLD signal switches to low at time t9. After a predetermined delay (e.g., the power-down time of integrated circuit 300), at time t10, the output voltage Vo of integrated circuit 300 also returns to low after the internal enable signal INT_EN is at logic low, at which point the power-down of integrated circuit 300 is completed.

[0104] In this embodiment, the following is adopted: Figure 6An advantageous feature of the control method shown is that it utilizes the existing SPI interface to power on and off the integrated circuit 300, without relying on a dedicated enable terminal. Removing the dedicated enable terminal from the integrated circuit 300 and controller 400 saves numerous input / output terminals, thereby reducing the complexity and cost of the entire control system.

[0105] Please refer to Figure 7 , Figure 6 An example is shown Figure 5 The circuit shown is illustrated in a second schematic diagram of the signals. Figure 7 The implementation method shown is the same as Figure 6 The implementation shown is similar, the only difference being that the chip select signal S_nCS changes from logic low to logic high after the power-down process is complete. For example... Figure 7 As shown, during the period from time t13 to t15, the serial data input signal S_SDI remains at a logic low level after the power-down signal PD is transmitted (where "0" in the serial data input signal S_SDI represents a low level). Therefore, as long as the serial data input signal S_SDI remains low after sending the power-down command PD, it is not necessary to immediately pull the chip select signal S_nCS high after sending the power-down command PD. After the hold signal HLD is pulled low, the integrated circuit 300 is powered down.

[0106] In short, when the hold signal HLD is pulled low, at least one of the following conditions ensures that the integrated circuit can be powered down: the first condition is to pull the chip select signal S_nCS high; the second condition is to keep the serial data input signal S_SDI low.

[0107] It should be noted that after the hold signal HLD is pulled low, if the chip select signal S_nCS and the serial data input signal S_SDI show the following... Figure 6 As shown in the state between time t1 and t4, the hold signal HLD will be reconfigured to a high level. In this case, because the hold signal HLD is in a logic high state, the integrated circuit 300 cannot be powered down.

[0108] Please refer to Figure 8 , Figure 8 A flowchart illustrating a control method for an integrated circuit provided in an embodiment of this application. The integrated circuit inputs a serial data input signal and a chip select signal. Figure 8 As shown, the control method of this integrated circuit includes the following steps:

[0109] Step 801: Configure the chip select signal to the first chip select logic state to allow external devices to control the integrated circuit.

[0110] Step 802: When the serial data input signal is in the first data logic state, configure the internal enable signal to be in the first enable logic state, wherein the integrated circuit is powered on when the internal enable signal is in the first enable logic state.

[0111] Step 803: When the internal enable signal is in the first enable logic state, configure the hold signal to the first hold logic state, wherein when the hold signal is in the first hold logic state, the internal enable signal is held to the first enable logic state.

[0112] The first chip select logic state, the first data logic state, the first enable logic state, and the first hold logic state all include a high level or a low level.

[0113] In one embodiment, the first chip select logic state is low, and the first data logic state, the first enable logic state, and the first hold logic state are all high.

[0114] In one embodiment, the control method of the integrated circuit further includes the following steps: when the hold signal is in a first hold logic state, the hold signal covers the chip select signal and the serial data input signal, so that the chip select signal and the serial data input signal cannot affect the internal enable signal through the enable circuit.

[0115] In one embodiment, the control method of the integrated circuit further includes the following steps: if a power-down command is received from the controller, the holding signal is configured to switch from a first holding logic state to a second holding logic state, wherein the second holding logic state includes a high level or a low level, and the level of the second holding logic state is different from that of the first holding logic state; when the holding signal is in the second holding logic state, the internal enable signal is configured to a second enable logic state, wherein the second enable logic state includes a high level or a low level, and the level of the second enable logic state is different from that of the first enable logic state; wherein when the internal enable signal is in the second enable logic state, the integrated circuit is powered down.

[0116] In one embodiment, both the second hold logic state and the second enable logic state are at a low level.

[0117] In one embodiment, the control method of the integrated circuit further includes the following steps: after receiving a power-down command, and when the holding signal switches from a first holding logic state to a second holding logic state, configuring the chip select signal to a second chip select logic state and / or configuring the serial data input signal to a second data logic state; wherein the second chip select logic state and the second data logic state include a high level or a low level.

[0118] In one embodiment, both the second chip select logic state and the second data logic state are at a low level.

[0119] In one embodiment, the control method of the integrated circuit further includes the following steps: configuring an enable circuit to generate an internal enable signal and configuring a digital circuit module to generate a hold signal; wherein the enable circuit includes a first input terminal, a second input terminal, a third input terminal and an output terminal, the first input terminal is used to receive a serial data input signal, the second input terminal is used to receive a chip select signal, the third input terminal is used to receive a hold signal, and the output terminal is used to output the internal enable signal.

[0120] In one embodiment, the enable circuit includes a first N-type transistor, a second N-type transistor, a third N-type transistor, a first P-type transistor, a second P-type transistor, a first resistor, a second resistor, a third resistor, and a Zener diode; the first P-type transistor, the second N-type transistor, and the second resistor are connected in series between the power supply bus and ground; the gate of the third N-type transistor receives a hold signal, and the third N-type transistor is connected between the first P-type transistor and ground; the third resistor is connected in parallel with the Zener diode; the gate of the second N-type transistor receives a serial data input signal through the first resistor; the gate of the first N-type transistor receives a chip select signal, and the first N-type transistor is connected between the gate of the second N-type transistor and ground; the second P-type transistor and the Zener diode are connected in series between the power supply bus and ground, and the gate of the second P-type transistor is connected to the gate and drain of the first P-type transistor, respectively; an internal enable signal is generated at the common node of the second P-type transistor and the Zener diode.

[0121] In one embodiment, the enabling circuit further includes a fourth N-type transistor; the gate of the fourth N-type transistor receives a hold signal, and the fourth N-type transistor is connected between the gate of the second N-type transistor and ground.

[0122] It should be understood that the specific control of the integrated circuit and the beneficial effects produced in the method embodiments can be referred to the corresponding descriptions in the above integrated circuit embodiments, which will not be repeated here for the sake of brevity.

[0123] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and not to limit them; under the concept of this application, the technical features of the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations of different aspects of this application as described above, which are not provided in detail for the sake of brevity; although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or make equivalent substitutions for some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. An integrated circuit, characterized in that, include: The enable circuit includes a first input terminal, a second input terminal, a third input terminal, and an output terminal. The first input terminal is used to receive a serial data input signal, the second input terminal is used to receive a chip select signal, the third input terminal is used to receive a hold signal, and the output terminal is used to output an internal enable signal that controls the power-on or power-off of the integrated circuit. A digital circuit module is used to output the hold signal and to configure the hold signal so that the output terminal holds the output of the internal enable signal controlling the power-on of the integrated circuit after the enable circuit outputs an internal enable signal controlling the power-on of the integrated circuit based on the serial data input signal and the chip select signal. The enabling circuit is further configured to configure the internal enabling signal to the first enabling logic state when the chip select signal is in the first chip select logic state and the serial data input signal is in the first data logic state, so as to power on the integrated circuit. The digital circuit module is further configured to set the hold signal to the first hold logic state when the internal enable signal is the first enable logic state; The enabling circuit is further configured to set the internal enabling signal to the first enabling logic state when the holding signal is in the first holding logic state, so as to keep the integrated circuit powered on. The first chip select logic state, the first data logic state, the first enable logic state, and the first hold logic state all include a high level or a low level.

2. The integrated circuit according to claim 1, characterized in that, The first chip select logic state is low, and the first data logic state, the first enable logic state, and the first hold logic state are all high.

3. The integrated circuit according to claim 1, characterized in that, When the hold signal is in the first hold logic state, the hold signal covers the chip select signal and the serial data input signal, so that the chip select signal and the serial data input signal cannot be applied to the integrated circuit through the enable circuit.

4. The integrated circuit according to claim 1, characterized in that, The digital circuit module is also used to receive a power-down command output by the controller, and configure the hold signal based on the power-down command so that the output terminal of the enable circuit outputs an internal enable signal that controls the power-down of the integrated circuit.

5. The integrated circuit according to claim 4, characterized in that, The digital circuit module is further configured to configure the holding signal to a second holding logic state based on the power-down command, and to configure the internal enable signal to a second enable logic state, so as to power down the integrated circuit; Both the second enable logic state and the second hold logic state include a high level or a low level.

6. The integrated circuit according to claim 5, characterized in that, Both the second enable logic state and the second hold logic state are at a low level.

7. The integrated circuit according to any one of claims 1-6, characterized in that, The enabling circuit includes a first N-type transistor, a second N-type transistor, a third N-type transistor, a first P-type transistor, a second P-type transistor, a first resistor, a second resistor, a third resistor, and a Zener diode; The first P-type transistor, the second N-type transistor, and the second resistor are connected in series between the power bus and ground; The gate of the third N-type transistor receives the hold signal, and the third N-type transistor is connected between the first P-type transistor and ground; The third resistor is connected in parallel with the Zener diode; The gate of the second N-type transistor receives the serial data input signal through the first resistor; The gate of the first N-type transistor receives the chip select signal, and the first N-type transistor is connected between the gate of the second N-type transistor and ground; The second P-type transistor and the Zener diode are connected in series between the power bus and ground, and the gate of the second P-type transistor is connected to the gate and drain of the first P-type transistor, respectively. The internal enable signal is generated at the common node of the second P-type transistor and the Zener diode.

8. The integrated circuit according to claim 7, characterized in that, The enabling circuit also includes a fourth N-type transistor; The gate of the fourth N-type transistor receives the hold signal, and the fourth N-type transistor is connected between the gate of the second N-type transistor and ground.

9. A control method based on an integrated circuit as described in any one of claims 1-8, characterized in that, The integrated circuit inputs a serial data input signal and a chip select signal, and the method includes: Configure the chip select signal to a first chip select logic state to allow external devices to control the integrated circuit; When the serial data input signal is in the first data logic state, the internal enable signal is configured to be in the first enable logic state, wherein the integrated circuit is powered on when the internal enable signal is in the first enable logic state. When the internal enable signal is in the first enable logic state, the hold signal is configured to be in the first hold logic state, wherein when the hold signal is in the first hold logic state, the internal enable signal is held to be in the first enable logic state. The first chip select logic state, the first data logic state, the first enable logic state, and the first hold logic state all include a high level or a low level.

10. The method according to claim 9, characterized in that, The first chip select logic state is low, and the first data logic state, the first enable logic state, and the first hold logic state are all high.

11. The method according to claim 9, characterized in that, The method further includes: If a power-down command is received from the controller, the holding signal is configured to switch from the first holding logic state to the second holding logic state, wherein the second holding logic state includes a high level or a low level, and the level of the second holding logic state is different from that of the first holding logic state. When the hold signal is in the second hold logic state, the internal enable signal is configured to be in the second enable logic state, wherein the second enable logic state includes a high level or a low level, and the level of the second enable logic state is different from that of the first enable logic state. Specifically, when the internal enable signal is in the second enable logic state, the integrated circuit is powered down.

12. The method according to claim 11, characterized in that, Both the second hold logic state and the second enable logic state are at a low level.

13. The method according to claim 11, characterized in that, The method further includes: After receiving the power-down command, and when the hold signal switches from the first hold logic state to the second hold logic state, configure the chip select signal to the second chip select logic state and / or configure the serial data input signal to the second data logic state; The second chip select logic state and the second data logic state include a high level or a low level.

14. The method according to claim 13, characterized in that, Both the second chip select logic state and the second data logic state are at a low level.

15. The method according to claim 9, characterized in that, The method further includes: Configure the enable circuit to generate the internal enable signal, and configure the digital circuit module to generate the hold signal; The enable circuit includes a first input terminal, a second input terminal, a third input terminal, and an output terminal. The first input terminal is used to receive the serial data input signal, the second input terminal is used to receive the chip select signal, the third input terminal is used to receive the hold signal, and the output terminal is used to output the internal enable signal.

16. The method according to claim 15, characterized in that, The method further includes: When the hold signal is in the first hold logic state, the hold signal covers the chip select signal and the serial data input signal, so that the chip select signal and the serial data input signal cannot affect the internal enable signal through the enable circuit.

17. The method according to claim 15, characterized in that, The enabling circuit includes a first N-type transistor, a second N-type transistor, a third N-type transistor, a first P-type transistor, a second P-type transistor, a first resistor, a second resistor, a third resistor, and a Zener diode; The first P-type transistor, the second N-type transistor, and the second resistor are connected in series between the power bus and ground; The gate of the third N-type transistor receives the hold signal, and the third N-type transistor is connected between the first P-type transistor and ground; The third resistor is connected in parallel with the Zener diode; The gate of the second N-type transistor receives the serial data input signal through the first resistor; The gate of the first N-type transistor receives the chip select signal, and the first N-type transistor is connected between the gate of the second N-type transistor and ground; The second P-type transistor and the Zener diode are connected in series between the power bus and ground, and the gate of the second P-type transistor is connected to the gate and drain of the first P-type transistor, respectively. The internal enable signal is generated at the common node of the second P-type transistor and the Zener diode.

18. The method according to claim 17, characterized in that, The enabling circuit also includes a fourth N-type transistor; The gate of the fourth N-type transistor receives the hold signal, and the fourth N-type transistor is connected between the gate of the second N-type transistor and ground.

19. A control system, characterized in that, It includes a controller and at least one integrated circuit as described in any one of claims 1-8, wherein the controller is connected to the integrated circuit.

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