A high-speed signal detection device

Abstract

The application discloses a high-speed signal detection device, which comprises a first power detector module, a preset module, a CPU controller module and a second power detector module; when the preset module is triggered, the CPU controller module reads the signal state output by the first power detector module and the signal state output by the second power detector module respectively, and stores the read signal state as a preset state; when the preset module is disconnected, the CPU controller module reads the output signal of the first power detector module and the output signal of the second power detector module in real time, compares the received signal with the preset signal, and determines whether there is an input signal according to the comparison result. The application realizes fast and convenient detection of common high-speed signals at a very low cost, and displays whether a signal is detected and the type of the detected signal in real time.

Description

Technical Field

[0001] This invention relates to the field of signal communication technology, and in particular to a cross-domain high-speed signal detection device based on power detector applications. Background Technology

[0002] A high-speed signal detection device is a device that applies detection equipment from the field of radio frequency signals to high-speed digital signals. Through the design of a signal preset library, it can determine the presence or absence of a detection signal and the type of the detection signal, and display it in real time.

[0003] Electronic communication products have permeated every corner of people's lives, enabling the transmission, application, and storage of information through signal communication. During the design, development, and after-sales service of electronic communication products, most product malfunctions require the use of large testing equipment such as oscilloscopes and signal logic analyzers to determine signal continuity. These devices are not only bulky and inconvenient to move, but also typically expensive, especially those used for high-speed signal testing, which poses significant inconvenience for R&D, design, and after-sales maintenance personnel. Summary of the Invention

[0004] This invention provides a high-speed signal detection device. This invention achieves rapid and convenient detection of common high-speed signals at extremely low cost, and displays in real time whether a signal is detected and the type of signal detected. See the description below for details:

[0005] A high-speed signal detection device, the detection device comprising: a first power detector module, a preset module, a CPU controller module, and a second power detector module;

[0006] When the preset module is triggered, the CPU controller module reads the signal state output by the first power detector module and the signal state output by the second power detector module respectively, and stores the read signal state as the preset state.

[0007] When the preset module is disconnected, the CPU controller module reads the signal output by the first power detector module and the output signal of the second power detector module in real time, compares the received signal with the preset signal, and determines whether there is an input signal based on the comparison result.

[0008] The device further includes a first signal input module and a second signal input module, which can simultaneously detect one high-speed signal, or simultaneously detect two high-speed signals, or simultaneously detect a set of differential signals.

[0009] The first signal input module and the second signal input module support input signal bandwidth of 0.001GHz to 10GHz.

[0010] The device further includes: a first signal preset library and a second signal preset library. The first signal preset library is the signal amplitude of a high-speed signal with a fixed amplitude that is actually acquired and passes through a power detector. The acquired signal amplitude is recorded and marked and stored in the CPU controller module.

[0011] The second signal preset library is a temporary preset library. After each signal detection is completed, the CPU controller module will clear the preset second signal library.

[0012] The CPU controller module compares the received signal amplitude with the second signal preset library to determine whether the signal to be detected exists. If it exists, the CPU controller module extracts the frequency of the received signal and compares the signal amplitude and signal frequency with the first signal preset library to determine the type of the signal to be detected. The detection results are then output to the first detection result indication module, the second detection result indication module, and the third detection result indication module for indication.

[0013] The first detection result indication module, the second detection result indication module, and the third detection result indication module are all directly connected to the CPU controller module and are used to indicate the presence of a detection signal, the absence of a detection signal, and the type of detection signal, respectively.

[0014] The first test result indicator module, the second test result indicator module, and the third test result indicator module are respectively a green indicator light, a red indicator light, and an LCD screen.

[0015] The device integrates a lithium battery module.

[0016] Furthermore, the signal input nodes of the first signal input module and the second signal input module adopt a functional multiplexed signal design.

[0017] The CPU controller module uses an STM32F103X series chip with a built-in storage area to store the first signal preset in the internal storage area; the internal signal receiver uses an AD8319 radio frequency detector chip.

[0018] The beneficial effects of the technical solution provided by this invention are:

[0019] 1. This device applies a power detector from the radio frequency field to the field of signal detection, enabling rapid detection of both high-speed and low-speed signals. In particular, it solves the problems of complex high-speed signal detection and difficult small signal detection, and also makes the detection of low-speed signals convenient and fast.

[0020] 2. The design principle of this device is simple, the device itself is small and easy to carry and move, and the cost is extremely low. While being convenient and practical, it can detect high-speed signals at a very low cost.

[0021] 3. This device can help quickly determine the presence or absence of a signal to be detected, and supports displaying the amplitude and signal type of the signal to be detected, providing users with intuitive detection results;

[0022] 4. The external signal input interface of this device is equipped with SMA connector terminals and pin header access points, which facilitates the rapid access of high-speed and low-speed signals. Users can flexibly choose the signal access point method of the device according to the output of the signal to be detected, thereby improving the practicality of the device.

[0023] 5. This device has a built-in lithium battery, which supports continuous operation for 10 hours without an external power source, improving the ease of use of the product. Attached Figure Description

[0024] Figure 1 This is a schematic diagram of a high-speed signal detection device;

[0025] Figure 2 The flowchart generated for the first signal pre-set library;

[0026] Figure 3 Here is a flowchart for determining the signal to be detected;

[0027] Figure 4 This is a hardware circuit design diagram for the input signal. Detailed Implementation

[0028] To make the objectives, technical solutions, and advantages of the present invention clearer, the embodiments of the present invention will be described in further detail below.

[0029] Example 1

[0030] A high-speed signal detection device, see Figure 1 The detection device includes: a first signal input module A, a first power detector module B, a preset module C, a power conversion module D, a CPU controller module E, a lithium battery module F, a second signal input module G, a second power detector module H, a switch control module I, a first detection result indication module J, a second detection result indication module K, and a third detection result indication module L;

[0031] When there is no signal input, pressing the button of preset module C causes CPU controller module E to read the signal status output by the first power detector module B and the second power detector module H respectively, and store the read signal status as a preset state. After the button of preset module C is released, CPU controller module E reads the signal output by the first power detector module B and the second power detector module H in real time, compares the received signal with the preset signal, and determines whether there is an input signal based on the comparison result.

[0032] The first signal input module A and the second signal input module G support input signal bandwidths of 0.001 GHz to 10 GHz.

[0033] Among them, the first power detector module B and the second power detector module H are devices used in the field of radio frequency signals to detect the transmission power level of radio frequency signals. After actual hardware circuit design, software design and testing verification, they can be used to detect high-speed signals, including single-ended signals and differential signals.

[0034] The preset module C is used to control the CPU controller module E to collect the signal status output by the first power detector module B and the second power detector module H of the device when the detected signal is disconnected, and to store the collected signals as the second signal preset library, which serves as the criterion for determining whether the detected signal exists.

[0035] Furthermore, for any application environment, the device itself uses the pre-set module C to collect and detect the judgment criteria, which not only improves the accuracy of signal detection but also greatly enhances the device's environmental applicability.

[0036] In practical implementation, based on actual high-speed signal measurement requirements, the device is configured with two signal input channels (i.e., the first signal input module A and the second signal input module G), which can support the simultaneous detection of one high-speed signal or two high-speed signals, and can meet the simultaneous detection of a set of differential signals.

[0037] The device incorporates a first signal preset library. This library is created by acquiring the amplitude values ​​of common, fixed-amplitude high-speed signals after passing them through a power detector. The acquired amplitude values ​​are recorded, marked, and stored in the CPU controller module as the built-in first signal preset library. Fixed amplitude means the signal voltage amplitude has only one possible value.

[0038] The aforementioned built-in first signal preset library includes commonly used high-speed signals such as MIPI, DVP, SATA, PCIe, DDR, HDMI, DP, and USB.

[0039] After entering normal working state, the CPU controller module E first compares the received signal with the second signal preset library to determine whether the signal exists. If the signal exists, it continues to compare the received signal with the first signal preset library to further determine the specific type of the signal.

[0040] In practice, the second signal preset library is a temporary signal preset library. After each signal detection is completed, the CPU controller module E will clear the preset second signal preset library to ensure that it will not affect the signal detection result of the next time.

[0041] The detection result indication module includes: a first detection result indication module J, a second detection result indication module K, and a third detection result indication module L. The first detection result indication module J, the second detection result indication module K, and the third detection result indication module L are all directly connected to the CPU controller module E and are used to indicate the presence of a detection signal, the absence of a detection signal, and the type of detection signal, respectively.

[0042] The signal detection result is first determined by comparing the signal amplitude received by the CPU controller module E with the second signal preset library to determine whether the signal to be detected exists. If the signal to be detected exists, the CPU controller module E further extracts the frequency of the received signal and compares the signal amplitude and signal frequency with the first signal preset library to determine the type of the signal to be detected. The detection results are then output to the first detection result indication module J, the second detection result indication module K, and the third detection result indication module L for indication.

[0043] In practical applications, this detection device can be used not only for high-speed signal detection, but also for common low-speed signal detection.

[0044] Among them, the first detection result indication module J, the second detection result indication module K, and the third detection result indication module L are a green indicator light, a red indicator light, and an LCD screen, respectively.

[0045] The device integrates a lithium battery module, enabling it to operate continuously for 10 hours without an external power source.

[0046] Example 2

[0047] The solution in Example 1 will be further described below with specific examples and device models:

[0048] Whether or not an external power supply is available, the device can be powered on and off by pressing and holding the power button. After powering on, the device enters normal operating mode and signal detection can be performed. If the signal to be detected is a low-speed signal, it can be connected to the external pin header connection point of the detection device through a regular wire; if the signal to be detected is a high-speed signal, it can be connected to the SMA terminal of the detection device through a high-speed signal coaxial cable with SMP terminals.

[0049] For the signal to be detected, the user needs to manually disconnect the output of the signal during signal detection. The specific method for disconnecting the signal depends on the specific situation of the signal to be detected. Disconnecting the signal to be detected means establishing a state so that the signal to be detected has no output. The simplest method is:

[0050] Power off the path of the signal to be detected. At this time, press the button of preset module C for 5 seconds. The device will collect the signal and extract the amplitude and mark the signal. The marked signal is temporarily stored in the second signal preset library. When the button of preset module C is released, the user powers on the signal to be detected, so that the signal to be detected is in a normal output or input state. The device continues to collect the signal and extracts the amplitude and marks the signal in real time. At the same time, it compares the marked signal with the temporary preset signal in the second signal preset library. If the difference between the amplitude of the newly marked signal and the amplitude of the signal in the temporary preset library exceeds 20mV, the signal is determined to exist. If the difference between the amplitude of the newly marked signal and the amplitude of the signal in the temporary preset library is less than 20mV, the signal is determined to not exist.

[0051] Once the device detects the presence of a signal, it extracts the frequency of the new marker signal and compares the extracted frequency and amplitude with the data in the first signal preset library. If the detected signal type matches the data in the first signal preset library, the detected signal type is output to the display screen for real-time display. When the device compares the acquired signal with the second preset signal library and determines that the signal exists, the green light of the first detection result indicator module J flashes; when the device compares the acquired signal with the second preset signal library and determines that the signal does not exist, the red light of the second detection result indicator module K flashes; when the device compares the acquired signal with the second preset signal library and determines that the signal exists, the device extracts the features of the acquired signal and continues to compare it with the first preset signal library to determine the type of the currently acquired signal. If the newly acquired signal has a matching signal type after comparison with the first preset signal library, the CPU controller module E outputs the determined signal type to the third detection result indicator module L in real time to display the current signal type to be detected; if the newly acquired signal does not have a matching signal type after comparison with the first preset signal library, the CPU controller module E outputs "No signal type determined" to the third detection result indicator module L to display the current signal type to be detected. At the same time, the device outputs and displays the amplitude of the extracted signal to be detected in voltage unit V (volts) through the third detection result indicator module L.

[0052] The first signal preset library is determined through a large amount of measured data. Known signals are repeatedly collected under different application scenarios. The amplitude and frequency of each collected signal are extracted, and the extracted data is marked as a sample. After collecting a large number of samples, the amplitude and frequency characteristic value ranges of the known signals corresponding to the samples are determined through data analysis and comparison, that is, the signals are classified. After a large number of actual tests on common high-speed signals, the amplitude and frequency characteristic value ranges are determined according to the above method, and the signals are classified as the first signal preset library of the device, which is stored inside the CPU controller module E.

[0053] Among them, the power conversion module D is used to supply power to the internal CPU controller module E, the first detection result indicator module J, the second detection result indicator module K, the third detection result indicator module L, the first power detector module B, the second power detector module H, the switch control module I and the lithium battery module F when an external power supply is connected.

[0054] The signal input nodes of the first signal input module (i.e., signal input 1) and the second signal input module (i.e., signal input 2) adopt a co-lay (function multiplexing) signal design. The signal connectors use a multiplexing design of high-speed signal connection terminal SAM (Subminiature Version A connector) and low-speed signal connection terminal Pin Header, which allows the high-speed signal under test to be connected to the device through a coaxial connection cable, ensuring the lowest transmission link loss of the signal under test to the device. At the same time, the low-speed signal connection terminal Pin Header is configured to facilitate the connection of the test circuit for low-speed signals.

[0055] The hardware circuit design for signal detection is as follows: Figure 4 As shown, the CPU controller module E uses an STM32F103X series chip with a built-in storage area, which can store the first signal preset in the storage area inside the CPU controller module E; the first power detector module and the second power detector module both use the AD8319 radio frequency detector chip, which can identify high-speed signals, low-speed signals and small amplitude signals. As the core device for signal detection, it is especially used for high-speed signal detection, saving detection costs and simplifying the detection procedure.

[0056] In the hardware circuit design for high-speed signal detection, capacitors C1 and C3, as DC (Direct Current) coupling capacitors, are designed with a value of 47nF to block DC signals and select AC signals. Capacitor C2 is a filter capacitor; by placing a capacitor between pin CLPF and ground, the low-pass corner frequency of the circuit driving the VOUT pin can be reduced. Increasing the capacitance of C2 will increase the overall rise / fall time of the AD8319 for pulse input signals. Through debugging and measurement on the actual circuit board, the optimal capacitance value for C2 was determined to be 8.2pF. Capacitors C4 and C5 are used for voltage regulation and filtering of the AD8319 chip's power supply. After measurement on the actual motherboard, the optimal values ​​were determined to be: C4 100pF, C5 100pF, and C4 100pF, C5 100pF, ... 0.1uF; Resistor R1 is connected in series between the power supply pin of AD8319 and the power supply, mainly for current limiting. This circuit is designed to be 0R for debugging purposes. Resistor R2 is used as a compensation resistor for the internal temperature network, connected in series between the temperature compensation interface and ground. By adjusting the value of the compensation resistor of the internal temperature network, this circuit can be adjusted to optimize the performance of input signals at different frequencies. Through testing the performance of the actual circuit board, the optimal design value for resistor R2 is determined to be 200R. Resistor R3 is the feedback resistor when AD8319 is working in measurement mode, that is, when AD8319 is performing signal detection. Part of the voltage of the output signal is fed back to the VSET pin through resistor R3. In actual operation, the slope of the VOUT output voltage response can be increased by reducing the voltage fed back to VSET. At the same time, resistor R3 can also be used as a reverse termination resistor or as part of a single-pole low-pass filter. The ultimate goal is to improve the output voltage response efficiency of VOUT, that is, to increase the detection accuracy. Through testing the performance of the actual circuit board, the optimal design value for resistor R3 is determined to be 1KΩ.

[0057] The design values ​​for the resistors and capacitors in the circuit design of the second signal input module G channel are the same as those in the circuit design of the first signal input module A channel.

[0058] Unless otherwise specified, the model numbers of the various devices in this embodiment of the invention are not limited, and any device that can perform the above functions is acceptable.

[0059] Those skilled in the art will understand that the accompanying drawings are merely schematic diagrams of a preferred embodiment, and the sequence numbers of the above embodiments of the present invention are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0060] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A high-speed signal detection device, characterized by comprising: The detection device includes: a first power detector module, a preset module, a CPU controller module, and a second power detector module; When the preset module is triggered, the CPU controller module reads the signal status output by the first power detector module and the signal status output by the second power detector module respectively, and stores the collected signals as the second signal preset library; When the preset module is disconnected, the CPU controller module reads the signal output by the first power detector module and the output signal of the second power detector module in real time, compares the received signal with the second signal preset library, and determines whether there is an input signal based on the comparison result. The device further includes: a first signal preset library; The first signal preset library uses the amplitude of a high-speed signal with a fixed amplitude that is actually acquired and passes through a power detector. The acquired signal amplitude is recorded and marked and stored in the CPU controller module. The second signal preset library is a temporary preset library. After each signal detection is completed, the CPU controller module will clear the preset second signal library. The CPU controller module compares the received signal amplitude with the second signal preset library to determine whether the signal to be detected exists. If it exists, the CPU controller module extracts the frequency of the received signal and compares the signal amplitude and signal frequency with the first signal preset library to determine the type of the signal to be detected. The detection results are then output to the first detection result indication module, the second detection result indication module and the third detection result indication module for indication. If the signal to be detected is a low-speed signal, it is connected to the external pin header connection point of the detection device through a normal wire; if the signal to be detected is a high-speed signal, it is connected to the SMA terminal of the detection device through a high-speed signal coaxial cable with an SMP terminal; for the signal to be detected, the user needs to manually disconnect the output of the signal to be detected during signal detection so that there is no output of the signal to be detected.

2. The high speed signal detection device of claim 1, wherein The device further includes: a first signal input module and a second signal input module, which can simultaneously detect one high-speed signal, or simultaneously detect two high-speed signals, or simultaneously detect a set of differential signals.

3. The high speed signal detection device of claim 2, wherein The first signal input module and the second signal input module support input signal bandwidth of 0.001GHz to 10GHz.

4. The high speed signal detection device of claim 1, wherein The first detection result indication module, the second detection result indication module, and the third detection result indication module are all directly connected to the CPU controller module and are used to indicate the presence of a detection signal, the absence of a detection signal, and the type of detection signal, respectively.

5. A high-speed signal detection device according to claim 1 or 4, characterized in that, The first test result indication module, the second test result indication module, and the third test result indication module are respectively a green indicator light, a red indicator light, and an LCD screen.

6. The high-speed signal detection device according to claim 1, characterized in that, The device integrates a lithium battery module.

7. A high-speed signal detection device according to claim 2, characterized in that, The signal input nodes of the first signal input module and the second signal input module adopt a function multiplexing signal design.

8. A high-speed signal detection device according to claim 1, characterized in that, The CPU controller module uses an STM32F103X series chip with a built-in storage area to store the first signal preset in the internal storage area; both the first power detector module and the second power detector module use the AD8319 radio frequency detector chip.

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