Capacitor and electronic device including same

Abstract

A capacitor and an electronic device including the same are provided. The capacitor includes a first electrode, a second electrode facing the first electrode, and a dielectric layer between the first electrode and the second electrode. The dielectric layer includes an intermediate layer within the dielectric layer, and the intermediate layer includes aluminum oxide and gallium oxide.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority based on Korean Patent Application No. 10-2024-0018420, filed with the Korean Intellectual Property Office on February 6, 2024, the disclosure of which is incorporated herein by reference in its entirety. Technical field

[0003] The present disclosure relates to a capacitor and an electronic device (apparatus) including the same. Background art

[0004] As the integration degree of electronic devices such as memories increases, the demand for miniaturization of electronic components in electronic devices is also increasing. However, since the capacitance of a capacitor is proportional to the area of the capacitor, the capacitance may decrease as the capacitor is miniaturized. Therefore, in order to compensate for the reduction in the size of the capacitor and ensure a desired capacitance, methods for further increasing the dielectric constant of the dielectric layer have been studied. In addition, methods for suppressing an increase in leakage current due to the miniaturization of the capacitor have been studied. Summary of the invention

[0005] Provided are a capacitor having improved leakage current characteristics and an electronic device including the capacitor.

[0006] Provided are a capacitor having a dielectric layer with a relatively high dielectric constant and an electronic device including the capacitor. [[ID=2x]]

[0007] Additional aspects will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the presented embodiments of the present disclosure.

[0008] According to an aspect of the present disclosure, a capacitor includes a first electrode, a second electrode facing the first electrode, and a dielectric layer between the first electrode and the second electrode, the dielectric layer including an intermediate layer within the dielectric layer, and the intermediate layer including aluminum oxide (aluminum oxide) and gallium oxide (gallium oxide).

[0009] The intermediate layer may include Al a Ga b O3, where 0 < a < 2 and 0 < b < 2.

[0010] The ratio of aluminum to gallium in the intermediate layer may satisfy 0.1 ≤ b / a ≤ 1.

[0011] Alternatively or for example, the ratio of aluminum to gallium in the intermediate layer may satisfy 0.33 ≤ b / a ≤ 1.

[0012] The dielectric layer may further include a first dielectric material layer adjacent to the first electrode and a second dielectric material layer adjacent to the second electrode, and wherein the intermediate layer may be between the first dielectric material layer and the second dielectric material layer.

[0013] The first dielectric material layer and the second dielectric material layer may include the same dielectric material.

[0014] The first dielectric material layer and the second dielectric material layer may each include a dielectric material different from the dielectric material of the intermediate layer.

[0015] For example, the first dielectric material layer and the second dielectric material layer may each include at least one dielectric material selected from the group consisting of zirconium oxide, hafnium oxide, hafnium zirconium oxide, perovskite, or a mixture thereof.

[0016] The composition ratio (proportion) of aluminum oxide and the composition ratio of gallium oxide may continuously change along a boundary (also referred to as an interface) between the first dielectric material layer and the intermediate layer, the intermediate layer, and a boundary between the second dielectric material layer and the intermediate layer.

[0017] The peak of the composition ratio of aluminum oxide and the peak of the composition ratio of gallium oxide may be inside the intermediate layer.

[0018] The peak of the composition ratio of aluminum oxide and the peak of the composition ratio of gallium oxide may be at the same position inside the intermediate layer.

[0019] The composition ratio of aluminum oxide and the composition ratio of gallium oxide may continuously increase from the outside of the boundary between the first dielectric material layer and the intermediate layer toward the intermediate layer, and may continuously decrease from the intermediate layer toward the outside of the boundary between the second dielectric material layer and the intermediate layer.

[0020] The materials of the first dielectric material layer and the second dielectric material layer may be distributed in an intermediate layer.

[0021] At the center of the intermediate layer, a sum of composition ratios of materials of the first dielectric material layer and the second dielectric material layer may be smaller than a sum of composition ratios of aluminum oxide and gallium oxide.

[0022] At the center of the intermediate layer, a sum of composition ratios of materials of the first dielectric material layer and the second dielectric material layer may be smaller than a composition ratio of aluminum oxide.

[0023] At the center of the intermediate layer, a sum of composition ratios of materials of the first dielectric material layer and the second dielectric material layer may be greater than a composition ratio of gallium oxide.

[0024] For example, the dielectric layer may have a thickness of about 3 nm to about 10 nm.

[0025] For example, the intermediate layer may have a thickness of 1 nm or less.

[0026] The first electrode and the second electrode may each include at least one conductive metal selected from titanium (Ti), nickel (Ni), aluminum (Al), tantalum (Ta), tungsten (W), platinum (Pt), lead (Pd), gold (Au), iridium (Ir), rhodium (Rh), molybdenum (Mo), vanadium (V), niobium (Nb), ruthenium (Ru) and cobalt (Co), a conductive metal oxide of the at least one conductive metal, a conductive metal nitride of the at least one conductive metal, or a combination thereof.

[0027] According to another aspect of the present disclosure, an electronic device includes a transistor and a capacitor electrically connected to the transistor, wherein the capacitor includes a first electrode, a second electrode facing the first electrode, and a dielectric layer between the first electrode and the second electrode, the dielectric layer includes an intermediate layer within the dielectric layer, and the intermediate layer includes aluminum oxide and gallium oxide. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The above and other aspects, features, and advantages of some embodiments of the present disclosure will become more apparent from the following description considered in conjunction with the accompanying drawings, in which:

[0029] Figure 1 is a cross-sectional view illustrating a schematic structure of a capacitor according to at least one embodiment;

[0030] Figure 2 is a graph showing radial distribution functions (RDFs) of dielectric layers according to materials included in an intermediate layer;

[0031] Figure 3 A diagram showing the tetragonality of various materials;

[0032] Figure 4A is a graph showing an X-ray diffraction (XRD) pattern for an intermediate layer including only aluminum (Al), and Figure 4B and Figure 4C is a diagram showing an X-ray diffraction (XRD) pattern for an intermediate layer including both aluminum (Al) and gallium (Ga);

[0033] Figure 5 is a graph showing examples of capacitance of capacitors for various materials of the intermediate layer;

[0034] Figure 6 is a diagram showing an example of oxygen composition distribution in a capacitor for various materials of the intermediate layer;

[0035] Figure 7 is a graph showing examples of leakage current characteristics of capacitors for various materials of the intermediate layer;

[0036] Figure 8 is a cross-sectional view illustrating a schematic structure of a capacitor according to another embodiment;

[0037] Figure 9 and Figure 10 is a diagram showing an example of changes in the composition of materials in a capacitor according to at least one embodiment;

[0038] Figure 11 is a circuit diagram for describing a schematic circuit configuration and operation of an electronic device employing a capacitor according to an embodiment;

[0039] Figure 12 is a schematic diagram illustrating an electronic device according to at least one embodiment;

[0040] Figure 13 is a schematic diagram illustrating an electronic device according to at least one further embodiment;

[0041] Figure 14 is a plan view illustrating an electronic device according to at least one further embodiment;

[0042] Figure 15 It is along Figure 14 A cross-sectional view of the electronic device taken along line AA';

[0043] Figure 16 is a cross-sectional view illustrating an electronic device according to at least one further embodiment; and

[0044] Figure 17 and 18 is a conceptual diagram schematically illustrating a device architecture applicable to a device according to at least one embodiment. DETAILED DESCRIPTION

[0045] Embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings, wherein the same reference numerals refer to the same elements throughout. In this regard, the present embodiment may have different forms and should not be construed as being limited to the description set forth herein. Therefore, the embodiments are described below with reference to the accompanying drawings only to illustrate aspects. As used herein, the term "and / or" includes any and all combinations of one or more of the relevant listed items. Expressions such as "at least one (kind)" when before or after a list of elements modify the entire list of elements and do not modify the individual elements of the list.

[0046] Hereinafter, a capacitor and an electronic device including the same will be described in detail with reference to the accompanying drawings. In the following drawings, the same reference numerals represent the same elements, and the sizes of the elements in the drawings may be exaggerated for clarity and ease of description. In addition, the embodiments described herein are merely examples, and various modifications may be made thereto.

[0047] Hereinafter, the term "above..." or "on..." may include not only those that are directly on..." in a contacting manner, but also those that are above..." in a non-contacting manner. In addition, it will be understood that, in addition to the directions (orientations) depicted in the figures, such spatially relative terms such as "above...", "top", etc. are also intended to cover different orientations of the device in use or operation, and the device can be oriented in other ways (rotated 90 degrees or in other directions), and the spatially relative terms used herein are interpreted accordingly. Unless the context clearly indicates otherwise, the singular form as used herein is also intended to include the plural form. It should be understood that the terms "comprising", "including" or "having" as used herein indicate the presence of the stated elements, but do not exclude the presence or addition of one or more additional elements.

[0048] The use of the term "said (the)" and similar demonstrative pronouns may correspond to both the singular and the plural. The operations constituting the method may be performed in any suitable order, unless otherwise specified herein or otherwise clearly contradictory to the context, and are not necessarily limited to the stated order. In addition, whenever a range of values is enumerated, the range includes all values within the range, as if clearly stated, and may further include the boundaries of the range. Therefore, the range of "X" to "Y" includes all values between X and Y, including X and Y. In addition, when the term "about" or "substantially" is used in this specification regarding numerical values and / or geometric terms, it is intended that the relevant numerical values include manufacturing tolerances (e.g., ± 10%) around the stated numerical values. In addition, regardless of whether numerical values and / or geometric terms are modified with "about" or "substantially", it will be understood that these values should be interpreted as including manufacturing or operating tolerances (e.g., ± 10%) around the stated numerical values and / or geometric shapes.

[0049] As used herein, the term "metal" encompasses metals and metalloids such as B, Si, and the like.

[0050] In addition, terms such as "unit" and "module" described in the specification mean a unit that performs at least one function or operation, and can be implemented as a processing circuit system such as hardware, software, or a combination of hardware and software. For example, the processing circuit system may more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a system on a chip (SoC), a programmable logic unit, a microprocessor, an application-specific integrated circuit (ASIC), etc. The processing circuit system may also include at least one of electronic components such as transistors, resistors, capacitors, etc., and / or an electronic circuit including the components.

[0051] The connecting lines or connecting members illustrated in the figures are intended to represent exemplary functional relationships and / or physical or logical connections between the various elements. It should be noted that many alternative or additional functional relationships, physical connections or logical connections may exist in a practical device.

[0052] All exemplifications or exemplary terms in the embodiments are used only to describe the technical ideas in detail, and the scope of the inventive concept is not limited by the exemplifications or exemplary terms unless they are limited by the claims.

[0053] Figure 1 1 is a cross-sectional view illustrating a schematic structure of a capacitor 100 according to at least one embodiment. Figure 1 The capacitor 100 may include a first electrode 110, a second electrode 120 facing the first electrode 110, and a dielectric layer 130 disposed between the first electrode 110 and the second electrode 120. In addition, the dielectric layer 130 may include an intermediate layer 132 disposed within the dielectric layer 130.

[0054] In at least some embodiments, the first electrode 110 may be disposed on a substrate (not shown). The substrate may be part of a structure supporting the capacitor 100 and / or may be part of an element connected to the capacitor 100. The substrate may include a pattern of semiconductor material, a pattern of insulating material, and / or a pattern of conductive material. The substrate may include, for example, a semiconductor material such as silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), or indium phosphide (InP), and / or an insulating material such as silicon oxide, silicon nitride, or silicon oxynitride.

[0055] The second electrode 120 may be spaced apart from the first electrode 110 and disposed facing the first electrode 110. The first electrode 110 and the second electrode 120 may each include a conductive material, such as a metal, a metal nitride, a metal oxide, and / or a combination thereof. For example, the first electrode 110 and the second electrode 120 may each include at least one conductive metal selected from titanium (Ti), nickel (Ni), aluminum (Al), tantalum (Ta), tungsten (W), platinum (Pt), lead (Pd), gold (Au), iridium (Ir), rhodium (Rh), molybdenum (Mo), vanadium (V), niobium (Nb), ruthenium (Ru), and cobalt (Co), and / or may include a conductive metal oxide of the at least one conductive metal and / or a conductive metal nitride of the at least one conductive metal. Conductive metal oxides may include, for example, platinum oxide (PtO), iridium oxide (IrO 2 ), ruthenium oxide (RuO 2 ), strontium ruthenium oxide (SrRuO 3 ), barium strontium ruthenium oxide ((Ba,Sr)RuO 3 ), calcium ruthenium oxide (CaRuO 3 ), lanthanum strontium cobalt oxide ((La,Sr)CoO 3 ), and / or the like. Conductive metal nitrides may include, for example, titanium nitride (TiN), tantalum nitride (TaN), niobium nitride (NbN), molybdenum nitride (MoN), cobalt nitride (CoN), tungsten nitride (WN), and / or the like.

[0056] Each of the first electrode 110 and the second electrode 120 may have a single-layer structure or a stacked structure of multiple material layers. For example, each of the first electrode 110 and the second electrode 120 may include a single layer of titanium nitride (TiN) or a single layer of niobium nitride (NbN). Alternatively, each of the first electrode 110 and the second electrode 120 may have a stacked structure in which a titanium nitride (TiN) layer and a niobium nitride (NbN) layer are repeatedly and alternately stacked at least once.

[0057] In another example, the first electrode 110 and the second electrode 120 may each include a metal nitride represented by MM'N. M is a metal element, M' is an element different from M and N, and N is nitrogen. For example, the MM'N metal nitride may include an MN metal nitride doped with the element M'. M may be at least one element selected from Be, B, Na, Mg, Al, Si, K, Ca, Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zn, Ga, Ge, Rb, Sr, Y, Zr, Nb, Mo, Tc, Ru, Rh, Pd, Ag, Cd, In, Sn, Sb, Te, Cs, Ba, La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, Hf, Ta, W, Re, Os, Ir, Pt, Au, Hg, Tl, Pb, Bi, Po, Fr, Ra, Ac, Th, Pa, and U. M' may be at least one element selected from H, Li, As, Se, O, P, S, Be, B, Na, Mg, Al, Si, K, Ca, Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zn, Ga, Ge, Rb, Sr, Y, Zr, Nb, Mo, Tc, Ru, Rh, Pd, Ag, Cd, In, Sn, Sb, Te, Cs' Ba, La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, Hf, Ta, W, Re, Os, Ir, Pt, Au, Hg, Tl, Pb, Bi, Po, Fr, Ra, Ac, Th, Pa, and U. In at least some embodiments, the composition ratio of M, M', and N in the metal nitride MM′N is x:y:z, where 0 ≤ x ≤ 2, 0 ≤ y ≤ 2, and 0 < z ≤ 4, and where at least one of x or y cannot be 0.

[0058] The dielectric layer 130 may include a first dielectric material layer 131, an intermediate layer 132, and a second dielectric material layer 133. The first dielectric material layer 131 may be disposed adjacent to the first electrode 110, and the second dielectric material layer 133 may be separated from the first dielectric material layer 131 and disposed adjacent to the second electrode 120. The intermediate layer 132 may be disposed between the first dielectric material layer 131 and the second dielectric material layer 133. In other words, the first dielectric material layer 131, the intermediate layer 132, and the second dielectric material layer 133 may be sequentially disposed in this stated order in the thickness direction of the dielectric layer 130.

[0059] The first dielectric material layer 131 and the second dielectric material layer 133 may include the same dielectric material. In this regard, it can be said that the intermediate layer 132 is further disposed within one of the dielectric materials of the dielectric layer 130. The first dielectric material layer 131 and the second dielectric material layer 133 may each include a metal oxide material having a tetragonal crystal structure and / or a crystal structure similar thereto and a dielectric constant of about 20 to about 70. For example, the first dielectric material layer 131 and the second dielectric material layer 133 may each include at least one dielectric material selected from the following: zirconia (ZrO2), hafnium oxide (HfO2), hafnium zirconium oxide (HfZrO2), perovskite, and / or a mixture thereof. For example, perovskite may include SrTiO3, CaTiO3, BaTiO3, Pb(Zr,Ti)O3, PbZnNbO3, etc.

[0060] The intermediate layer 132 may include a dielectric material different from the dielectric materials of the first dielectric material layer 131 and the second dielectric material layer 133, respectively. According to at least one embodiment, the intermediate layer 132 may include aluminum oxide (AlO) and gallium oxide (GaO). For example, the intermediate layer 132 may include Al a Ga b O3, where 0 < a < 2 and 0 < b < 2. Aluminum oxide (AlO) and gallium oxide (GaO) may inhibit or reduce the formation of oxygen vacancies in the dielectric layer 130 without deteriorating the overall crystal characteristics of the dielectric layer 130 including the first dielectric material layer 131 and the second dielectric material layer 133.

[0061] Figure 2 is a graph showing the radial distribution function (RDF) of the dielectric layer 130 according to the material included in the intermediate layer 132. For example, when the first dielectric material layer 131 and the second dielectric material layer 133 of the dielectric layer 130 each include zirconia (ZrO2), Figure 2 the horizontal axis in may represent the atomic distance between zirconium atoms and oxygen atoms, and Figure 2 the vertical axis in may represent the number of oxygen atoms distributed as the spatial distance from the Zr atom increases. Referring to Figure 2 , when the dielectric layer 130 includes only zirconia (ZrO2) (for example, without the intermediate layer 132), the first maximum peak appears between about 2.1 Å and about 2.2 Å, and the second peak appears between about 2.3 Å and about 2.4 Å. The second peak is a unique feature of the tetragonal phase crystal.

[0062] On the other hand, when the intermediate layer 132 includes only aluminum (Al), the second peak hardly appears. Therefore, when the intermediate layer 132 includes only aluminum (Al), the crystallinity (crystallinity) of the dielectric layer 130 deteriorates, and therefore, the dielectric constant of the dielectric layer 130 decreases. As a result, the capacitance of the capacitor 100 can be reduced. In addition, when the intermediate layer 132 includes only gallium (Ga), the second peak may appear. Even when the intermediate layer 132 further includes aluminum (Al) and thus includes both gallium (Ga) and aluminum (Al), a second peak smaller than when the intermediate layer 132 includes only gallium (Ga) and larger than when the intermediate layer 132 includes only aluminum (Al) may appear.

[0063] Figure 3 is a graph showing the tetragonality of various materials. Figure 3 In the formula, tetragonality is an index representing the degree to which the crystals of a material deviate from the tetragonal phase. As the index approaches 0, the tetragonal phase becomes more ideal. Figure 3 , the tetragonality of zirconium oxide (ZrO2) is 0. The tetragonality decreases in the following order: a material further including only aluminum (Al) in zirconium oxide (Al-ZrO2), a material including aluminum (Al) and gallium (Ga) in zirconium oxide (GaAl-ZrO2), and a material further including only gallium (Ga) in zirconium oxide (Ga-ZrO2). This is because gallium ions (Ga 3+ ) has a larger ionic radius (about 0.76Å) than the aluminum ion (Al 3+ ) ionic radius (about 0.68Å), and is closer to the zirconium ion (Zr 4+ ) has an ionic radius of approximately 0.86 Å.

[0064] Figure 4A is a graph showing an X-ray diffraction (XRD) pattern for an intermediate layer including only aluminum (Al), and Figure 4B and Figure 4C is a graph showing an X-ray diffraction (XRD) pattern for an intermediate layer including both aluminum (Al) and gallium (Ga). Figure 4A 、 Figure 4B and Figure 4C In the case where the intermediate layer 132 includes both aluminum (Al) and gallium (Ga) ("Al / (Ga low)" or "Al / (Ga high)"), a peak closer to 30.298 degrees appears and the intensity of the peak is higher than in the case where the intermediate layer 132 includes only aluminum (Al) ("Al only"). As can be seen from the peak of 30.298 degrees in the XRD pattern, the crystallinity of the tetragonal phase is improved in the case where the intermediate layer 132 includes both aluminum (Al) and gallium (Ga) as compared to the case where the intermediate layer 132 includes only aluminum (Al). In addition, Figure 4B and Figure 4C, “Al / (Ga low)” indicates a case where the ratio of gallium (Ga) to aluminum (Al) in the intermediate layer 132 is 10%, and “Al / (Ga high)” indicates a case where the ratio of gallium (Ga) to aluminum (Al) in the intermediate layer 132 is 100%. Figure 4B and Figure 4C , the crystallinity of the tetragonal phase in “Al / (Ga high)” may be more improved than that in “Al / (Ga low)”.

[0065] As described above, gallium (Ga), which has an ion radius larger than that of aluminum ions and has a distribution structure similar to that of the materials of the first and second dielectric material layers 131 and 133 within the intermediate layer 132, is used together as the oxide material of the intermediate layer 132. Therefore, the deterioration of the crystallinity of the dielectric layer 130 due to the intermediate layer 132 can be minimized. Therefore, the reduction in the capacitance of the capacitor 100 due to the intermediate layer 132 can be minimized.

[0066] Figure 5 is a diagram showing examples of capacitance of the capacitor 100 for various materials of the intermediate layer 132. Figure 5 In the case where the intermediate layer 132 includes both aluminum (Al) and gallium (Ga) ("Al / (Ga low)" or "Al / (Ga high)"), the capacitance of the capacitor 100 increases compared to the case where the intermediate layer 132 includes only aluminum (Al) ("Al only"). In addition, as the ratio of gallium (Ga) to aluminum (Al) in the intermediate layer 132 increases, the capacitance of the capacitor 100 further increases.

[0067] On the other hand, in zirconium oxide (ZrO 2 ), the oxygen vacancy formation energy of aluminum (Al) is about -1.00 eV, the oxygen vacancy formation energy of gallium (Ga) is about -0.89 eV, and the oxygen vacancy formation energy when both aluminum (Al) and gallium (Ga) are included is about -0.86 eV. Therefore, when the intermediate layer 132 includes both aluminum oxide and gallium oxide, the oxygen vacancy formation energy can be increased, and thus, the formation of oxygen vacancies in the dielectric layer 130 can be suppressed and the concentration of oxygen vacancies in the dielectric layer 130 can be reduced.

[0068] Figure 6 is a diagram showing an example of oxygen composition distribution in the capacitor 100 for various materials of the intermediate layer 132 . Figure 6 The graph is obtained by measuring the oxygen distribution in the capacitor 100 by using secondary ion mass spectrometry (SIMS). Figure 6, in the case where the intermediate layer 132 includes only aluminum (Al), as indicated by the arrow, the amount of oxygen increases near the first electrode 110 compared to the case where the intermediate layer 132 includes both aluminum (Al) and gallium (Ga) ("Al / (Ga low)" or "Al / (Ga high)"). The increase in oxygen near the first electrode 110 may mean that the oxygen in the dielectric layer 130 has diffused into the first electrode 110. The expression "the oxygen in the dielectric layer 130 has diffused into the first electrode 110" may imply that the oxygen in the dielectric layer 130 has correspondingly decreased, and thus the oxygen vacancies in the dielectric layer 130 have increased. In addition, since oxygen vacancies may suppress the dielectric constant of oxide-based dielectrics, the increase in oxygen vacancies may reduce the capacitance of the capacitor 100. Therefore, by including the intermediate layer 132 of both aluminum (Al) and gallium (Ga) ("Al / (Ga low)" or "Al / (Ga high)"), diffusion of oxygen in the dielectric layer 130 into the first electrode 110 can be prevented and / or mitigated while maintaining the tetragonal phase.

[0069] Therefore, in the case where the intermediate layer 132 includes both aluminum (Al) and gallium (Ga), the formation of oxygen vacancies in the dielectric layer 130 can be suppressed, and the concentration of oxygen vacancies in the dielectric layer 130 can be reduced, compared to the case where the intermediate layer 132 includes only aluminum (Al). Due to this, leakage current due to oxygen vacancies in the dielectric layer 130 can be reduced. In addition, when the intermediate layer 132 includes both gallium (Ga) and aluminum (Al), leakage current characteristics can be further improved by reducing the valence band offset (VBO) at the interfaces between the dielectric layer 130 and the first electrode 110 and between the dielectric layer 130 and the second electrode 120, compared to the case where the intermediate layer 132 includes only aluminum (Al). For example, when the intermediate layer 132 includes both gallium (Ga) and aluminum (Al), the VBO can be reduced by up to approximately 0.4 eV, compared to the case where the intermediate layer 132 includes only aluminum (Al).

[0070] Figure 7 is a graph showing an example of leakage current characteristics of the capacitor 100 for various materials of the intermediate layer. Figure 7 When the ratio of gallium (Ga) to aluminum (Al) in the intermediate layer 132 is 100% ("Al / (Ga high)"), the equivalent oxide thickness (Toxeq) is reduced by approximately 4.5% and the leakage current is reduced by approximately 45.3% compared to the case where the intermediate layer 132 includes only aluminum (Al). In addition, when the ratio of gallium (Ga) to aluminum (Al) in the intermediate layer 132 is 10% ("Al / (Ga low)"), the equivalent oxide thickness (Toxeq) is reduced by approximately 2.9% and the leakage current is reduced by approximately 55.6% compared to the case where the intermediate layer 132 includes only aluminum (Al).

[0071] from Figure 7As can be seen from the figure, as the proportion of gallium (Ga) in the intermediate layer 132 increases, the effect of reducing the equivalent oxide thickness (Toxeq) can be enhanced, and as the proportion of gallium (Ga) in the intermediate layer 132 decreases, the effect of reducing the leakage current can be enhanced. In view of this, the ratio of gallium (Ga) to aluminum (Al) in the intermediate layer 132 can be selected within an appropriate range. For example, the ratio of gallium (Ga) to aluminum (Al) in the intermediate layer 132 can be selected within a range of about 10% to about 100%. Alternatively or for example, the ratio of gallium (Ga) to aluminum (Al) in the intermediate layer 132 can be selected within a range of about 25% to about 100%, a range of about 33% to about 100%, a range of about 25% to about 80%, or a range of about 33% to about 80%. In other words, when the intermediate layer 132 includes Al a Ga b When O3, the relationship of 0.1≤b / a≤1 may be satisfied. Alternatively, the relationship of 0.25≤b / a≤1, 0.33≤b / a≤1, 0.25≤b / a≤0.8, or 0.33≤b / a≤0.8 may be satisfied.

[0072] As described above, according to the disclosed embodiments, because the intermediate layer 132 inserted into the dielectric layer 130 of the capacitor 100 has a tetragonality similar to that of the material of the dielectric layer 130, the crystallinity of the dielectric layer 130 may not be deteriorated. In addition, the intermediate layer 132 may suppress or reduce the formation of oxygen vacancies within the dielectric layer 130. Therefore, the intermediate layer 132 may reduce leakage current while improving the capacitance of the capacitor 100. According to these embodiments, because the dielectric layer 130 has a high dielectric constant, the thickness of the dielectric layer 130 may be reduced and the capacitor 100 may be further miniaturized. For example, the dielectric layer 130 may have a thickness of about 3 nm to about 10 nm. In addition, the intermediate layer 132 may have a thickness of about 0.1 nm to about 1 nm.

[0073] Figure 8 1 is a cross-sectional view illustrating a schematic structure of a capacitor 100a according to at least one further embodiment. Figure 8 , the dielectric layer 130a of the capacitor 100a according to at least one other embodiment may include a first dielectric material layer 131a, an intermediate layer 132a, and a second dielectric material layer 133a. Figure 1 The capacitor 100 shown in FIG. Figure 8In the dielectric layer 130a of the capacitor 100a shown in FIG, the composition ratio of the materials may continuously change at the boundary between the first dielectric material layer 131a and the intermediate layer 132a, and at the boundary between the second dielectric material layer 133a and the intermediate layer 132a. In other words, the composition ratio of aluminum oxide and gallium oxide continuously changes along the first dielectric material layer 131a, the intermediate layer 132a, and the second dielectric material layer 133a, and the peaks of the composition ratio of aluminum oxide and the composition ratio of gallium oxide may be formed in the intermediate layer 132a. In addition, the materials of the first and second dielectric material layers 131a and 133a may also be distributed within the intermediate layer 132a. In this way, the interface between the intermediate layer 132a and the first dielectric material layer 131a and / or the second dielectric material layer 133a can be described as unclear (fuzzy), and the aluminum oxide and gallium oxide can be said to gradually (or continuously) change in the intermediate layer 132a.

[0074] Figure 9 and Figure 10 is a diagram showing an example of changes in the composition of the material around the intermediate layer 132 a of the capacitor 100 a according to at least one embodiment. Figure 9 and Figure 10 The only difference is the composition ratio of gallium (Ga) to aluminum (Al). Figure 9 and Figure 10 The graph is obtained by measuring the distribution of aluminum (Al), gallium (Ga), and zirconium (Zr) in the intermediate layer 132a of the capacitor 100a by using secondary ion mass spectrometry (SIMS). Figure 9 and Figure 10 , the composition ratio of aluminum oxide and the composition ratio of gallium oxide gradually increase from the outside of the boundary between the first dielectric material layer 131a and the intermediate layer 132a (i.e., the side away from the intermediate layer 132a) toward the intermediate layer 132a, and the peak of the composition ratio may be formed inside the intermediate layer 132a. Then, the composition ratio of aluminum oxide and the composition ratio of gallium oxide may gradually decrease from the peak inside the intermediate layer 132a toward the outside of the boundary between the second dielectric material layer 133a and the intermediate layer 132a (i.e., the side away from the intermediate layer 132a). Figure 9 and 10 As shown in FIG, the peak of the aluminum oxide composition ratio and the peak of the gallium oxide composition ratio may be formed at the same position within the intermediate layer 132a. For example, the peak of the aluminum oxide composition ratio and the peak of the gallium oxide composition ratio may be formed at the center of the intermediate layer 132a indicated by the dotted line. In addition, when the ratio of aluminum (Al) to gallium (Ga) is large, aluminum (Al) may be more widely dispersed than gallium (Ga), and therefore, aluminum (Al) may be distributed in a wider range than gallium (Ga) within the dielectric layer 130.

[0075] Additionally, the materials of the first and second dielectric material layers 131a and 133a may also be distributed in the intermediate layer 132a. For example, zirconium oxide may be distributed in the first and second dielectric material layers 131a and 133a, as well as in the intermediate layer 132a. The zirconium oxide composition ratio may peak in the first dielectric material layer 131a or the second dielectric material layer 133a. In the dielectric layer 130, the peak position of the zirconium oxide composition ratio may differ from the peak positions of the aluminum oxide composition ratio and the gallium oxide composition ratio. For example, at the center of the intermediate layer 132a (indicated by the dotted line), at the peak position of the aluminum oxide composition ratio, or at the peak position of the gallium oxide composition ratio, the zirconium oxide composition ratio may be less than the sum of the aluminum oxide and gallium oxide composition ratios. For example, at the center of the intermediate layer 132a, at the peak position of the aluminum oxide composition ratio, or at the peak position of the gallium oxide composition ratio, the zirconium oxide composition ratio may be less than the aluminum oxide composition ratio and greater than the gallium oxide composition ratio. In the first and second dielectric material layers 131a and 133a, the composition ratio of zirconium oxide may be greater than the composition ratio of aluminum oxide and greater than the composition ratio of gallium oxide. As used herein, the term "center of the middle layer" refers to a plane perpendicular to the thickness direction of the middle layer at half the thickness of the middle layer.

[0076] The capacitor can be used in a variety of electronic devices. For example, the capacitor can be used together with a transistor as a dynamic random access memory (DRAM). In addition, the capacitor can be used together with other circuit elements as part of an electronic circuit constituting an electronic device.

[0077] Figure 11 is a circuit diagram for describing a schematic circuit configuration and operation of an electronic device 1000 employing a capacitor according to an embodiment.

[0078] The circuit diagram of the electronic device 1000 is a unit cell of a DRAM, and the electronic device 1000 includes a transistor TR, a capacitor CA, a word line WL, and a bit line BL. The capacitor CA can be a reference Figures 1 to 10 Capacitors 100 and / or 100a are described.

[0079] The method for writing data to a DRAM is as follows. After a gate voltage (high) is applied to the gate electrode of transistor TR via word line WL to turn on the transistor ("on" state), VDD (hereinafter referred to as a high voltage) or 0 (hereinafter referred to as a low voltage) (which is the data voltage value to be input) is applied to bit line BL. When a high voltage is applied to word line WL and bit line BL, capacitor CA is charged, that is, data "1" is written. When a high voltage is applied to word line WL and a low voltage is applied to bit line BL, capacitor CA is discharged, that is, data "0" is written.

[0080] When reading data, a high voltage is applied to word line WL to turn on the DRAM's transistor TR, and a voltage of VDD / 2 is applied to bit line BL. When the DRAM data is "1," that is, when the voltage of capacitor CA is VDD, the charge stored in capacitor CA slowly moves to bit line BL, and the voltage of bit line BL becomes slightly higher than VDD / 2. Conversely, when the data on capacitor CA is "0," the charge on bit line BL moves to capacitor CA, and the voltage of bit line BL becomes slightly lower than VDD / 2. The sense amplifier senses and amplifies the potential difference on bit line BL, determining whether the data is "0" or "1."

[0081] Figure 12 is a schematic diagram illustrating an electronic device 1001 according to at least one embodiment.

[0082] Reference Figure 12 , the electronic device 1001 may include a structure in which the capacitor CA1 and the transistor TR are electrically connected to each other through the contact 20. The capacitor CA1 may include a first electrode 110, a second electrode 120, and a dielectric layer 130 disposed between the first electrode 110 and the second electrode 120, wherein the dielectric layer 130 includes an intermediate layer 132 disposed inside the dielectric layer 130. The capacitor CA1 may be a reference Figures 1 to 10 Since this has been described above, a detailed description thereof will be omitted.

[0083] The transistor TR may be a field-effect transistor. The transistor TR includes a semiconductor substrate SU and a gate stack GS. The semiconductor substrate SU includes a source region SR, a drain region DR, and a channel region CH. The gate stack GS is disposed on the semiconductor substrate SU and faces the channel region CH. The gate stack GS includes a gate insulating layer GI and a gate electrode GA.

[0084] The channel region CH is a region between the source region SR and the drain region DR and is electrically connected to the source region SR and the drain region DR. The source region SR may be electrically connected to or in contact with one end of the channel region CH, and the drain region DR may be electrically connected to or in contact with the other end of the channel region CH. The channel region CH may be defined as a substrate region between the source region SR and the drain region DR in the semiconductor substrate SU.

[0085] The semiconductor substrate SU may include a semiconductor material. The semiconductor substrate SU may include, for example, an elemental semiconductor material and / or a compound semiconductor material, such as silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), or indium phosphide (InP). In addition, the semiconductor substrate SU may include a silicon-on-insulator (SOI) substrate.

[0086] In at least some embodiments, the source region SR, the drain region DR, and the channel region CH may each be independently formed by implanting impurities into different regions of the semiconductor substrate SU. In this case, the source region SR, the channel region CH, and the drain region DR may each include the material of the substrate as a base material. In some embodiments, the source region SR and the drain region DR may each include a conductive material. In this case, the source region SR and the drain region DR may each include, for example, a metal, a metal compound, or a conductive polymer.

[0087] In some embodiments, unlike the illustration, the channel region CH may be implemented as a separate material layer (thin film). In this case, for example, the channel region CH may include at least one of Si, Ge, SiGe, a III-V semiconductor, an oxide semiconductor, a nitride semiconductor, an oxynitride semiconductor, a two-dimensional (2D) material, a quantum dot (QD), and an organic semiconductor. For example, the oxide semiconductor may include InGaZnO, etc., the 2D material may include a transition metal dichalcogenide (TMD) or graphene, and the QD may include a colloidal QD or a nanocrystalline structure.

[0088] The gate electrode GA may be provided on the semiconductor substrate SU and may face the channel region CH while being separated from the semiconductor substrate SU. The gate electrode GA may include at least one of a metal, a metal nitride, a metal carbide, and polycrystalline silicon. For example, the metal may include at least one of aluminum (Al), tungsten (W), molybdenum (Mo), titanium (Ti), and tantalum (Ta), and the metal nitride may include at least one of titanium nitride (TiN) and tantalum nitride (TaN). The metal carbide may include at least one of an aluminum-doped (or aluminum-containing) metal carbide and a silicon-doped (or silicon-containing) metal carbide. Specific examples of the metal carbide may include TiAlC, TaAlC, TiSiC, or TaSiC.

[0089] The gate electrode GA may have a structure in which a plurality of materials are stacked. For example, the gate electrode GA may have a structure in which a metal nitride layer and a metal layer are stacked (e.g., TiN / Al), or a structure in which a metal nitride layer, a metal carbide layer, and a metal layer are stacked (e.g., TiN / TiAlC / W). However, the materials described above are merely examples.

[0090] A gate insulating layer GI may be further disposed between the semiconductor substrate SU and the gate electrode GA. The gate insulating layer GI may include a paraelectric material or a high-k dielectric material and may have a dielectric constant of about 20 to about 70.

[0091] The gate insulating layer GI may include silicon oxide, silicon nitride, aluminum oxide, hafnium oxide, zirconium oxide, etc., or may include a 2D insulator such as hexagonal boron nitride (h-BN). For example, the gate insulating layer GI may include silicon oxide (SiO2), silicon nitride (SiNx), etc., and may include hafnium oxide (HfO2), hafnium silicon oxide (HfSiO4), lanthanum oxide (La2O3), lanthanum aluminum oxide (LaAlO3), zirconium oxide (ZrO2), hafnium zirconium oxide (HfZrO2), zirconium silicon oxide (ZrSiO4), tantalum oxide (Ta2O5), titanium oxide (TiO2), strontium titanium oxide (SrTiO3), yttrium oxide (Y2O3), aluminum oxide (Al2O3), lead scandium tantalum oxide (PbSc ... lead scandium tantalum oxide (PbSc2O5), lead scandium tantalum oxide (PbSc2O5), lead scandium tanta 0.5 Ta 0.5 O3), lead zinc niobate (PbZnNbO3), etc. In addition, the gate insulating layer GI may include a metal oxynitride (e.g., aluminum oxynitride (AlON), zirconium oxynitride (ZrON), hafnium oxynitride (HfON), lanthanum oxynitride (LaON), yttrium oxynitride (YON), etc.), a silicate (e.g., ZrSiON, HfSiON, YSiON, LaSiON, etc.), or an aluminate (e.g., ZrAlON, HfAlON, etc.). The gate insulating layer GI may form a gate stack together with the gate electrode GA.

[0092] One of the first and second electrodes 110 and 120 of the capacitor CA1 and one of the source and drain regions SR and DR of the transistor TR may be electrically connected to each other through a contact 20. The contact 20 may include a suitable conductive material, such as tungsten, copper, aluminum, or polysilicon.

[0093] The arrangement of the capacitor CA1 and the transistor TR may be modified variously. For example, the capacitor CA1 may be provided on the semiconductor substrate SU, or may be buried in the semiconductor substrate SU.

[0094] Figure 12 It is described that the electronic device 1001 includes one capacitor CA1 and one transistor TR, but this is merely an example, and the electronic device 1001 may be included as one of a plurality of electronic devices 1001 including a plurality of capacitors CA1 and a plurality of corresponding transistors TR.

[0095] Figure 13 is a schematic diagram illustrating an electronic device 1002 according to at least one further embodiment.

[0096] refer to Figure 13Electronic device 1002 may include a structure in which capacitor CA2 and transistor TR are electrically connected to each other via contact 21. Transistor TR includes a semiconductor substrate SU and a gate stack GS. Semiconductor substrate SU includes a source region SR, a drain region DR, and a channel region CH. Gate stack GS is disposed on semiconductor substrate SU, facing channel region CH, and includes a gate insulating layer GI and a gate electrode GA.

[0097] An interlayer insulating layer 25 may be provided on the semiconductor substrate SU to cover the gate stack GS. The interlayer insulating layer 25 may include an insulating material. For example, the interlayer insulating layer 25 may include Si oxide (e.g., SiO2), Al oxide (e.g., Al2O3), or a high-k material (e.g., HfO2). The contact 21 passes through the interlayer insulating layer 25 to electrically connect the transistor TR to the capacitor CA2.

[0098] The capacitor CA2 may include a first electrode 110, a second electrode 120, and a dielectric layer 130 disposed between the first electrode 110 and the second electrode 120, wherein the dielectric layer 130 includes an intermediate layer 132 disposed inside the dielectric layer 130. The first electrode 110 and the second electrode 120 are disposed in a shape that increases the contact area with the dielectric layer 130, and the material of the capacitor CA2 is the same as that of the reference electrode. Figures 1 to 10 The materials depicted for capacitors 100 and 100a are the same and / or substantially similar.

[0099] Figure 14 is a plan view illustrating an electronic device 1003 according to at least one further embodiment.

[0100] refer to Figure 14 , the electronic device 1003 may include a structure in which a plurality of capacitors and a plurality of field effect transistors are repeatedly arranged. The electronic device 1003 may include a field effect transistor, a contact structure 20', and a capacitor CA3. The field effect transistor includes a semiconductor substrate 11' and a gate stack 12, and the semiconductor substrate 11' includes a source, a drain, and a channel. The contact structure 20' is arranged on the semiconductor substrate 11' in a manner not overlapping with the gate stack 12. The capacitor CA3 is arranged on the contact structure 20'. The electronic device 1003 may further include a bit line structure 13 that electrically connects the field effect transistors to each other.

[0101] although Figure 14 The contact structures 20' and capacitors CA3 are described as being repeatedly arranged in the X and Y directions, but the present disclosure is not limited thereto. For example, the contact structures 20' may be arranged in the X and Y directions, and the capacitors CA3 may be arranged in a hexagonal shape, such as a honeycomb structure.

[0102] Figure 15 It is along Figure 14The line A-A' intercepts Figure 14 Cross-sectional view of an electronic device.

[0103] refer to Figure 15 , the semiconductor substrate 11 ' may have a shallow trench isolation (STI) structure including a device isolation layer 14. The device isolation layer 14 may be a single layer including one type of insulating layer, or a multilayer including a combination of two or more types of insulating layers. The device isolation layer 14 may include a device isolation trench 14T in the semiconductor substrate 11 ', and the device isolation trench 14T may be filled with an insulating material. The insulating material may include at least one of fluorosilicate glass (FSG), undoped silicate glass (USG), borophosphosilicate glass (BPSG), phosphosilicate glass (PSG), flowable oxide (FOX), plasma-enhanced tetraethyl orthosilicate (PE-TEOS), and tonen silazene (TOSZ), but the present disclosure is not limited thereto.

[0104] The semiconductor substrate 11' may further include a channel region CH defined by a device isolation layer 14, and a gate line trench 12T parallel to the upper surface of the semiconductor substrate 11' and extending in the X direction. The channel region CH may have a relatively long island shape having a short axis and a long axis. The long axis of the channel region CH may be arranged in a direction D3 parallel to the upper surface of the semiconductor substrate 11', as shown in FIG. Figure 14 As shown in .

[0105] The gate line trench 12T may be arranged to traverse the channel region CH at a certain depth from the upper surface of the semiconductor substrate 11', or may be arranged within the channel region CH. The gate line trench 12T may also be arranged within the device isolation trench 14T. The gate line trench 12T within the device isolation trench 14T may have a bottom surface lower than the bottom surface of the gate line trench 12T in the channel region CH. The first source / drain 11'ab and the second source / drain 11"ab may be arranged in the upper portion of the channel region CH located on both sides of the gate line trench 12T.

[0106] The gate stack 12 may be disposed within the gate line trench 12T. Specifically, a gate insulating layer 12a, a gate electrode 12b, and a gate capping layer 12c may be sequentially disposed within the gate line trench 12T. The gate insulating layer 12a and the gate electrode 12b may be the same as those described above, and the gate capping layer 12c may include at least one of silicon oxide, silicon oxynitride, and silicon nitride. The gate capping layer 12c may be disposed on the gate electrode 12b to fill the remaining portion of the gate line trench 12T.

[0107] The bitline structure 13 may be disposed on the first source / drain 11'ab. The bitline structure 13 may be arranged parallel to the upper surface of the semiconductor substrate 11' and extend in the Y direction. The bitline structure 13 may be electrically connected to the first source / drain 11'ab and may include a bitline contact 13a, a bitline 13b, and a bitline capping layer 13c sequentially stacked on the semiconductor substrate 11'. For example, the bitline contact 13a may include polysilicon, the bitline 13b may include a metal material, and the bitline capping layer 13c may include an insulating material, such as silicon nitride or silicon oxynitride.

[0108] although Figure 15 While the bit line contact 13a is described as having a bottom surface at the same level as the upper surface of the semiconductor substrate 11', this is merely an example and the present disclosure is not limited thereto. For example, in at least one further embodiment, a recess may be further provided that is formed to a certain depth from the upper surface of the semiconductor substrate 11'. The bit line contact 13a may extend into the interior of the recess so that the bottom surface of the bit line contact 13a is lower than the upper surface of the semiconductor substrate 11'.

[0109] The bitline structure 13 may further include a bitline interlayer (not shown) between the bitline contact 13a and the bitline 13b. The bitline interlayer may include a metal silicide, such as tungsten silicide, or a metal nitride, such as tungsten nitride. In addition, a bitline spacer (not shown) may be further formed on the sidewalls of the bitline structure 13. The bitline spacer may have a single-layer structure or a multi-layer structure and may include an insulating material, such as silicon oxide, silicon oxynitride, or silicon nitride. In addition, the bitline spacer may further include an air space (air gap) (not shown).

[0110] The contact structure 20' may be disposed on the second source / drain 11''ab. The contact structure 20' and the bit line structure 13 may be disposed on different sources / drains on the semiconductor substrate 11'. The contact structure 20' may have a structure in which a lower contact pattern (not shown), a metal silicide layer (not shown), and an upper contact pattern (not shown) are sequentially stacked on the second source / drain 11''ab. The contact structure 20' may further include a barrier layer (not shown) surrounding the side surface and bottom surface of the upper contact pattern. For example, the lower contact pattern may include polysilicon, the upper contact pattern may include a metal material, and the barrier layer may include a conductive metal nitride.

[0111] The capacitor CA3 may be disposed on the semiconductor substrate 11' and electrically connected to the contact structure 20'. Specifically, the capacitor CA3 includes a first electrode 110 electrically connected to the contact structure 20', a second electrode 120 separated from the first electrode 110, and a dielectric layer 130 disposed between the first electrode 110 and the second electrode 120, wherein the dielectric layer 130 includes an intermediate layer 132 disposed inside the dielectric layer 130. The first electrode 110 may have a cylindrical cup shape, an elongated cup shape, or the like, having an internal space with a closed bottom. The second electrode 120 may have a comb shape having comb teeth extending into the internal space formed by the first electrode 110 and the area between adjacent first electrodes 110. The dielectric layer 130 may be arranged between the first electrode 110 and the second electrode 120 to be parallel to the surfaces of the first electrode 110 and the second electrode 120. Because the materials of the first electrode 110, the second electrode 120, the dielectric layer 130, and the intermediate layer 132 constituting the capacitor CA3 are the same as those of the reference Figures 1 to 10 The described capacitors 100 and 100 a are identical and / or substantially similar to those thereof, so a detailed description thereof is omitted.

[0112] An interlayer insulating layer 15 may be further arranged between the capacitor CA3 and the semiconductor substrate 11'. The interlayer insulating layer 15 may be arranged in a space between the capacitor CA3 and the semiconductor substrate 11', in which no other structure is arranged. Specifically, the interlayer insulating layer 15 may be arranged to cover wiring and / or electrode structures, such as the bit line structure 13 and the contact structure 20' on the semiconductor substrate 11' and the gate stack 12 in the semiconductor substrate 11'. For example, the interlayer insulating layer 15 may surround the wall of the contact structure 20'. The interlayer insulating layer 15 may include a first interlayer insulating layer 15a surrounding the bit line contact 13a, and a second interlayer insulating layer 15b covering the side surfaces and / or upper surfaces of the bit line 13b and the bit line cap layer 13c.

[0113] The first electrode 110 of the capacitor CA3 may be arranged on the interlayer insulating layer 15, specifically on the second interlayer insulating layer 15b. In addition, when a plurality of capacitors CA3 are arranged, the bottom surfaces of the plurality of first electrodes 110 may be separated from each other by the etch stop layer 16. In other words, the etch stop layer 16 may include an opening 16T, and the bottom surface of the first electrode 110 of the capacitor CA3 may be arranged in the opening 16T. As shown, the first electrode 110 may have a cylindrical shape or a cup shape having an internal space with a closed bottom. The capacitor CA3 may further include a support member (not shown) that prevents the first electrode 110 from tilting or collapsing. The support member may be provided on the sidewall of the first electrode 110.

[0114] Figure 16is a cross-sectional view illustrating an electronic device 1004 according to at least one further embodiment.

[0115] The cross-sectional view of the electronic device 1004 according to this embodiment corresponds to the cross-sectional view taken along Figure 14 A cross-sectional view taken along line AA', and Figure 16 The electronic device 1004 and Figure 15 The difference between the electronic device 1003 and the embodiment of the present invention is only in the shape of the capacitor CA4. The capacitor CA4 is disposed on the semiconductor substrate 11' and is electrically connected to the contact structure 20'. The capacitor CA4 includes a first electrode 110 electrically connected to the contact structure 20', a second electrode 120 separated from the first electrode 110, and a dielectric layer 130 disposed between the first electrode 110 and the second electrode 120, wherein the dielectric layer 130 includes an intermediate layer 132 disposed within the dielectric layer 130. The materials of the first electrode 110, the second electrode 120, the dielectric layer 130, and the intermediate layer 132 are the same as those of the reference 10. Figures 1 to 10 The capacitors 100 and 100a described are identical to those.

[0116] The first electrode 110 may have a column shape, such as a circular column, a square column, or a polygonal column, extending in the vertical direction (Z direction). The second electrode 120 may have a comb shape having comb teeth extending into the region between adjacent first electrodes 110. The dielectric layer 130 may be arranged between the first electrode 110 and the second electrode 120 so as to be parallel to the surfaces of the first electrode 110 and the second electrode 120.

[0117] The capacitor and the electronic device according to the embodiments described above can be applied to a variety of application fields. For example, the electronic device according to the embodiments can be applied as a logic device or a storage device. The electronic device according to the embodiments can be used for arithmetic operations, program execution, temporary data storage, etc. in devices such as mobile devices, computers, laptop computers, sensors, network devices, and neuromorphic devices. In addition, the electronic device according to the embodiments can be useful for devices in which the amount of data transmission is large and data transmission is performed continuously.

[0118] Figure 17 and 18 Each of the diagrams schematically illustrates a device architecture applicable to a device according to at least one embodiment.

[0119] refer to Figure 17 , the electronic device architecture 1100 may include a memory unit 1010, an arithmetic logic unit (ALU) 1020, and a control unit 1030. The memory unit 1010, the ALU 1020, and the control unit 1030 may be electrically connected to each other. For example, the electronic device architecture 1100 may be implemented as a single chip including the memory unit 1010, the ALU 1020, and the control unit 1030.

[0120] The memory unit 1010, ALU 1020, and control unit 1030 can be interconnected on-chip via metal lines for direct communication. The memory unit 1010, ALU 1020, and control unit 1030 can be monolithically integrated on a single substrate to form a single chip. The input / output device 2000 can be connected to the electronic device architecture (chip) 1100. In addition, the memory unit 1010 can include both main memory and cache memory. The electronic device architecture (chip) 1100 can be an on-chip memory processing unit. The memory unit 1010 can include the capacitors described above and / or electronic devices including the same. The ALU 1020 or the control unit 1030 can also include the capacitors described above.

[0121] refer to Figure 18 Cache memory 1510, ALU 1520, and control unit 1530 may constitute a central processing unit (CPU) 1500. Cache memory 1510 may include static random access memory (SRAM). In addition to CPU 1500, main memory 1600 and auxiliary memory 1700 may be provided. Main memory 1600 may be DRAM and may include the capacitors and / or electronic devices including the same as described above. In some cases, the electronic device architecture may be implemented in a form in which computing unit elements and storage unit elements are adjacent to each other on a single chip without distinguishing between subunits.

[0122] It should be understood that some of the example embodiments described herein should be considered in a descriptive sense only and not for purposes of limitation. Descriptions of features or aspects in each embodiment should typically be considered applicable to other similar features or aspects in other embodiments. Although one or more embodiments have been described with reference to the accompanying drawings, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope as defined by the appended claims.

Claims

1. Capacitors, including: a first electrode; a second electrode facing the first electrode; as well as A dielectric layer between the first electrode and the second electrode includes an intermediate layer within the dielectric layer, and the intermediate layer includes aluminum oxide and gallium oxide.

2. The capacitor according to claim 1, wherein the intermediate layer comprises Al a Ga b O3, where 0 < a < 2 and 0 < b < 2. 3 . The capacitor according to claim 2 , wherein a ratio of gallium to aluminum in the intermediate layer satisfies 0.1≦b / a≦1. 4 . The capacitor according to claim 3 , wherein a ratio of gallium to aluminum in the intermediate layer satisfies 0.33≦b / a≦1.

5. The capacitor of claim 1 , wherein the dielectric layer further comprises: a first dielectric material layer adjacent to the first electrode, and a second dielectric material layer adjacent to the second electrode, and The intermediate layer is between the first dielectric material layer and the second dielectric material layer. 6 . The capacitor of claim 5 , wherein the first dielectric material layer and the second dielectric material layer comprise the same dielectric material. 7 . The capacitor of claim 5 , wherein the first dielectric material layer and the second dielectric material layer each comprise a dielectric material different from a dielectric material of the intermediate layer.

8. The capacitor of claim 5, wherein the first dielectric material layer and the second dielectric material layer each comprise at least one dielectric material selected from the group consisting of zirconium oxide, hafnium oxide, hafnium zirconium oxide, perovskite, or mixtures thereof.

9. The capacitor according to claim 5, wherein a composition ratio of aluminum oxide and a composition ratio of gallium oxide continuously change along a boundary between the first dielectric material layer and the intermediate layer, the intermediate layer, and a boundary between the second dielectric material layer and the intermediate layer. 10 . The capacitor according to claim 9 , wherein a peak of a composition ratio of aluminum oxide and a peak of a composition ratio of gallium oxide are inside the intermediate layer. 11 . The capacitor according to claim 9 , wherein a peak of a composition ratio of aluminum oxide and a peak of a composition ratio of gallium oxide are at the same position inside the intermediate layer.

12. The capacitor according to claim 9, wherein the composition ratio of aluminum oxide and the composition ratio of gallium oxide continuously increase from the outside of the boundary between the first dielectric material layer and the intermediate layer toward the intermediate layer, and continuously decrease from the intermediate layer toward the outside of the boundary between the second dielectric material layer and the intermediate layer.

13. The capacitor of claim 5, wherein materials of the first dielectric material layer and the second dielectric material layer are distributed in the intermediate layer.

14. The capacitor according to claim 13, wherein At the center of the intermediate layer, the sum of the composition ratios of the materials of the first dielectric material layer and the second dielectric material layer is smaller than the sum of the composition ratios of aluminum oxide and gallium oxide; At the center of the intermediate layer, the sum of the composition ratios of the materials of the first dielectric material layer and the second dielectric material layer is smaller than the composition ratio of aluminum oxide; and / or At the center of the intermediate layer, the sum of the composition ratios of the materials of the first dielectric material layer and the second dielectric material layer is greater than the composition ratio of gallium oxide.

15. The capacitor of claim 1, wherein the dielectric layer has a thickness of 3 nm to 10 nm.

16. The capacitor of claim 1, wherein the intermediate layer has a thickness of 1 nanometer (nm) or less.

17. The capacitor of claim 1 , wherein the first electrode and the second electrode each comprise at least one conductive metal selected from the group consisting of titanium (Ti), nickel (Ni), aluminum (Al), tantalum (Ta), tungsten (W), platinum (Pt), lead (Pd), gold (Au), iridium (Ir), rhodium (Rh), molybdenum (Mo), vanadium (V), niobium (Nb), ruthenium (Ru), and cobalt (Co), a conductive metal oxide of the at least one conductive metal, a conductive metal nitride of the at least one conductive metal, or a combination thereof.

18. Electronic equipment, including: transistor; and A capacitor according to any one of claims 1 to 17 electrically connected to the transistor.

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