Semiconductor device
Through the design of multi-layer dielectric layer structure and metal element material layer, the capacitor capacitance of semiconductor devices is improved, the problems of integrated density and leakage current are solved, and the capacitor design with high capacitance and low leakage is realized.
Patent Information
- Application Number
- CN202411255410.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2024-02-06
- Filing Date
- 2024-09-09
- Publication Date
- 2025-08-08
AI Technical Summary
It is difficult to realize capacitors with sufficiently high capacitance in a limited area of existing semiconductor devices, and there is a leakage current problem.
A multi-layer dielectric layer structure is adopted, including a first metal oxide layer, a second metal oxide layer and a third metal oxide layer. The third metal oxide layer is an AxB1-xO2 compound, and a material layer of metal elements is combined with a metal element to increase the electrostatic capacitance of the capacitor and reduce leakage current.
Increase the capacitor's capacitance within a limited area, reduce leakage current, and meet the integrated density requirements of semiconductor devices.
Smart Images
Figure CN120456567A_ABST
Abstract
Description
[0001] CROSS-REFERENCE TO RELATED APPLICATIONS
[0002] This application claims priority from Korean Patent Application No. 10-2024-0018171 filed on February 6, 2024, in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field
[0003] The present disclosure relates to a semiconductor device, and in particular, to a semiconductor device including a capacitor structure. Background Art
[0004] Semiconductor devices are considered important components in the electronics industry due to their small size, high functionality, and / or low cost. Semiconductor devices are categorized as semiconductor memory devices for storing data, semiconductor logic devices for processing data, and hybrid semiconductor devices that include both memory and logic elements.
[0005] As the integration density of semiconductor devices increases, capacitors with sufficiently high capacitance must be realized within a limited area. The capacitance of a capacitor varies directly with the surface area of the electrodes and the dielectric constant of the dielectric layer, and inversely with the equivalent oxide thickness of the dielectric layer. Recently, various research efforts are underway to increase the capacitance of capacitors. Summary of the Invention
[0006] Embodiments of the inventive concept provide a semiconductor device including a capacitor having increased electrostatic capacitance.
[0007] Embodiments of the inventive concept provide a semiconductor device including a capacitor having reduced leakage current.
[0008] According to an embodiment of the present invention, a semiconductor device may include: a bottom electrode, a top electrode on the bottom electrode, and a dielectric layer and a material layer between the bottom electrode and the top electrode. The dielectric layer may include: a first metal oxide layer, a second metal oxide layer on the first metal oxide layer, and a third metal oxide layer between the first metal oxide layer and the second metal oxide layer. The third metal oxide layer may include a chemical formula A x B 1-xA compound of O2, where A and B are two different elements and are selected from the group consisting of zirconium (Zr), hafnium (Hf), titanium (Ti), niobium (Nb), tantalum (Ta), strontium (Sr), and barium (Ba), where 0 < x < 1. The material layer may include one of a metal material containing a metal element, an oxide material containing a metal element, and a oxynitride material containing a metal element, and the metal element may include at least one of scandium (Sc), yttrium (Y), titanium (Ti), vanadium (V), niobium (Nb), tantalum (Ta), chromium (Cr), molybdenum (Mo), tungsten (W), iron (Fe), ruthenium (Ru), osmium (Os), cobalt (Co), rhodium (Rh), iridium (Ir), boron (B), tin (Sn), platinum (Pt), and lanthanum (La).
[0009] According to an embodiment of the inventive concept, a semiconductor device may include: a bottom electrode, a top electrode on the bottom electrode, and a dielectric layer and a material layer interposed between the bottom electrode and the top electrode. The dielectric layer may include: a first metal oxide layer, a second metal oxide layer on the first metal oxide layer, and a third metal oxide layer interposed between the first metal oxide layer and the second metal oxide layer. The first metal oxide layer and the second metal oxide layer may include zirconia, and the third metal oxide layer may include hafnium zirconia. The thickness of the third metal oxide layer may be 30% to 50% of the thickness of the dielectric layer.
[0010] According to an embodiment of the inventive concept, a semiconductor device may include: a substrate, a conductive contact on the substrate, a bottom electrode on the conductive contact, a top electrode on the bottom electrode, and a dielectric layer and a material layer between the bottom electrode and the top electrode. The dielectric layer may include a first metal oxide layer, a second metal oxide layer on the first metal oxide layer, and a third metal oxide layer on the second metal oxide layer. The first metal oxide layer and the third metal oxide layer may include zirconia, and the second metal oxide layer may include hafnium zirconia. The material layer may include one of a metal material containing a metal element, an oxide material containing a metal element, and a oxynitride material containing a metal element. The metal element may include at least one of scandium (Sc), yttrium (Y), titanium (Ti), vanadium (V), niobium (Nb), tantalum (Ta), chromium (Cr), molybdenum (Mo), tungsten (W), iron (Fe), ruthenium (Ru), osmium (Os), cobalt (Co), rhodium (Rh), iridium (Ir), boron (B), tin (Sn), platinum (Pt), and lanthanum (La). The first metal oxide layer and the third metal oxide layer may include a tetragonal phase, and the second metal oxide layer may include a tetragonal phase and an orthorhombic phase. BRIEF DESCRIPTION OF THE DRAWINGS
[0011] Figure 1Ais a cross-sectional view illustrating a capacitor structure of a semiconductor device according to example embodiments of the inventive concepts.
[0012] Figure 1B is a cross-sectional view illustrating a capacitor structure of a semiconductor device according to example embodiments of the inventive concepts.
[0013] Figure 1C is a cross-sectional view illustrating a capacitor structure of a semiconductor device according to example embodiments of the inventive concepts.
[0014] Figure 2 is a plan view illustrating a semiconductor device according to example embodiments of the inventive concepts.
[0015] Figures 3A to 3C It is along Figure 2 1 is a cross-sectional view taken along line AA′ for illustrating a semiconductor device according to an example embodiment of the inventive concept.
[0016] Figure 4 is a plan view illustrating a semiconductor device according to example embodiments of the inventive concepts.
[0017] Figure 5 and Figure 6 It is along Figure 4 Cross-sectional view taken along lines BB' and CC'.
[0018] Figure 7 FIG. 1 is a diagram showing a portion of a semiconductor device (eg, Figure 5 CU) is an enlarged cross-sectional view. DETAILED DESCRIPTION
[0019] Example embodiments of the inventive concept will now be described more fully with reference to the accompanying drawings, in which example embodiments are shown. Like reference numerals refer to like elements throughout.
[0020] It will be understood that when an element is referred to as being “connected” or “coupled” to or “on” another element, the element can be directly connected or coupled to or directly on the other element, or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to or “contacting” or “in contact with” another element (or any form of the term “contacting” is used), there are no intervening elements at the point of contact.
[0021] When referring to orientation, layout, position, shape, size, amount or other measurement, terms such as "same", "equal", "planar" or "coplanar" as used herein do not necessarily mean exactly the same orientation, layout, position, shape, size, amount or other measurement, but are intended to include nearly the same orientation, layout, position, shape, size, amount or other measurement within acceptable variations that may occur due to manufacturing processes, for example. Unless the context or other statements indicate otherwise, the term "substantially" may be used herein to emphasize this meaning.
[0022] [Example 1]
[0023] Figure 1A is a cross-sectional view illustrating a capacitor structure of a semiconductor device according to Example Embodiment 1 of the inventive concepts.
[0024] Reference Figure 1A The semiconductor device may include a capacitor structure CAP. In an embodiment, the capacitor structure CAP may function as a data storage element, thereby enabling the semiconductor device to function as a memory device. The capacitor structure CAP may include a bottom electrode BE, a dielectric layer DL, and a top electrode TE, arranged sequentially along a vertical direction VD. The vertical direction VD may be a direction perpendicular to the top surface of the bottom electrode BE or the top electrode TE. The dielectric layer DL may be interposed between the bottom electrode BE and the top electrode TE. Each of the bottom electrode BE and the top electrode TE may be formed of or include at least one of the following: vanadium nitride (VN), titanium nitride (TiN), niobium nitride (NbN), molybdenum nitride (MoN), tantalum nitride (TaN), ruthenium (Ru), ruthenium oxide (RuO2), platinum (Pt), iridium (Ir), strontium ruthenate (SrRuO3), tungsten (W), or tungsten nitride (WN). Each of the bottom electrode BE and the top electrode TE may be a single layer formed of a single material, or a composite layer including two or more materials.
[0025] The dielectric layer DL may include a first metal oxide layer DL1, a second metal oxide layer DL2, and a third metal oxide layer DL3 sequentially disposed on the bottom electrode BE in the vertical direction VD. In other words, the second metal oxide layer DL2 may be interposed between the first metal oxide layer DL1 and the third metal oxide layer DL3. In example embodiments, the bottom surface of the third metal oxide layer DL3 may contact the top surface of the second metal oxide layer DL2, and the bottom surface of the second metal oxide layer DL2 may contact the top surface of the first metal oxide layer DL1.
[0026] The first metal oxide layer DL1 and the third metal oxide layer DL3 may include the same material or may include materials different from each other. The first metal oxide layer DL1 and the third metal oxide layer DL3 may include: a material formed of at least one element selected from zirconium (Zr), titanium (Ti), niobium (Nb), tantalum (Ta), strontium (Sr), or barium (Ba), and an oxide material containing the element. As an example, the first metal oxide layer DL1 and the third metal oxide layer DL3 may include zirconia. In an embodiment, the first metal oxide layer DL1 and the third metal oxide layer DL3 may include zirconia doped with at least one of aluminum (Al), yttrium (Y), vanadium (V), or silicon (Si).
[0027] The second metal oxide layer DL2 may include a material different from the first metal oxide layer DL1 and the third metal oxide layer DL3. The second metal oxide layer DL2 may have the chemical formula A x B 1-X O2, where A and B are two different elements and are selected from the group consisting of zirconium (Zr), hafnium (Hf), titanium (Ti), niobium (Nb), tantalum (Ta), strontium (Sr), and barium (Ba), where 0 < x < 1. The concentration range of element A in the second metal oxide layer DL2 may be 20 at% to 80 at%. In an embodiment, the second metal oxide layer DL2 may have the chemical formula Hf X Zr 1-x O2, here, in the second metal oxide layer DL2, the concentration of zirconium (Zr) may be higher than the concentration of hafnium (Hf).
[0028] In an embodiment, the first metal oxide layer DL1 and the third metal oxide layer DL3 may have a tetragonal phase. The second metal oxide layer DL2 may have both a tetragonal phase and an orthorhombic phase.
[0029] The dielectric layer DL may have a first thickness TH1. The second metal oxide layer DL2 of the dielectric layer DL may have a second thickness TH2. The second thickness TH2 may be 30% to 50% of the first thickness TH1. In an embodiment, the range of the first thickness TH1 may be to The range of the second thickness TH2 may be to
[0030] The first material layer ML1 may be disposed between the bottom electrode BE and the dielectric layer DL. For example, the first material layer ML1 may be in contact with the top surface of the bottom electrode BE and the bottom surface of the dielectric layer DL. The first material layer ML1 may include one of a metal material containing a metal element, an oxide material containing a metal element, and an oxynitride material containing a metal element. The metal element may include at least one of scandium (Sc), yttrium (Y), titanium (Ti), vanadium (V), niobium (Nb), tantalum (Ta), chromium (Cr), molybdenum (Mo), tungsten (W), iron (Fe), ruthenium (Ru), osmium (Os), cobalt (Co), rhodium (Rh), iridium (Ir), boron (B), tin (Sn), platinum (Pt), or lanthanum (La). Here, the concentration of the metal material in the first material layer ML1 may range from 0at% to 30at%. In addition, the first material layer ML1 may also include an oxide material containing the elements included in the bottom electrode BE. The first material layer ML1 may have a third thickness TH3. In an embodiment, the range of the third thickness TH3 may be to
[0031] The capping layer PT may be interposed between the dielectric layer DL and the top electrode TE. In example embodiments, the capping layer PT may contact the top surface of the third metal oxide layer DL3 and the bottom surface of the top electrode TE. The capping layer PT may include at least one of silicon (Si), boron (B), lithium (Li), scandium (Sc), aluminum (Al), yttrium (Y), niobium (Nb), tantalum (Ta), titanium (Ti), molybdenum (Mo), or lanthanum (La). In embodiments, the capping layer PT may be omitted. In the case where the capping layer PT is omitted, the third metal oxide layer DL3 of the dielectric layer DL may contact the top electrode TE.
[0032] [Example 2]
[0033] Figure 1B is a cross-sectional view showing a capacitor structure of a semiconductor device according to an exemplary embodiment 2 of the present invention. Figure 1A The elements described above may be identified by the same reference numerals without repeated description.
[0034] Reference Figure 1B , the oxide layer BEO may be interposed between the dielectric layer DL and the bottom electrode BE. In example embodiments, the oxide layer BEO may contact the bottom surface of the dielectric layer DL and the top surface of the bottom electrode BE. That is, in Figure 1B In the capacitor structure CAP, Figure 1AUnlike the capacitor structure of FIG. 5 , an oxide layer BEO may be provided on the bottom electrode BE instead of the first material layer ML1 . The oxide layer BEO may include an oxide material including elements included in the bottom electrode BE.
[0035] The second material layer ML2 may be between the top electrode TE and the dielectric layer DL. In example embodiments, the second material layer ML2 may contact the top surface of the dielectric layer DL and the bottom surface of the top electrode TE. The second material layer ML2 may include one of a metal material containing a metal element, an oxide material containing a metal element, and a nitride oxide material containing a metal element, and the metal element may include at least one of scandium (Sc), yttrium (Y), titanium (Ti), vanadium (V), niobium (Nb), tantalum (Ta), chromium (Cr), molybdenum (Mo), tungsten (W), iron (Fe), ruthenium (Ru), osmium (Os), cobalt (Co), rhodium (Rh), iridium (Ir), boron (B), tin (Sn), platinum (Pt), or lanthanum (La). Here, the concentration range of the metal material in the second material layer ML2 may be 0at% to 30at%. The second material layer ML2 may have a fourth thickness TH4. The range of the fourth thickness TH4 may be to
[0036] The capping layer PT may be interposed between the dielectric layer DL and the second material layer ML2. That is, unlike Embodiment 1, the capping layer PT may be spaced apart from the top electrode TE. In the case where the capping layer PT is omitted, the third metal oxide layer DL3 of the dielectric layer DL may contact the top electrode TE.
[0037] [Example 3]
[0038] Figure 1C 1 is a cross-sectional view showing a capacitor structure of a semiconductor device according to an exemplary embodiment 3 of the present inventive concept. Figure 1A and Figure 1B The elements described above may be identified by the same reference numerals without repeated description.
[0039] Reference Figure 1C , the first material layer ML1 may be interposed between the bottom electrode BE and the dielectric layer DL. The second material layer ML2 may be interposed between the top electrode TE and the dielectric layer DL. That is, unlike the capacitor structure CAP in embodiments 1 and 2, the capacitor structure CAP in embodiment 3 may include the first material layer ML1 and the second material layer ML2. The first material layer ML1 and the second material layer ML2 may be configured to have the same Figure 1A and Figure 1B The features in the described embodiments are essentially the same features.
[0040] [Manufacturing method: Example 1]
[0041] Hereinafter, a method of manufacturing a capacitor structure according to Embodiment 1 will be described in more detail.
[0042] Referring to Embodiment 1, an oxide layer (not shown) may be formed on the bottom electrode BE. The oxide layer may be a layer formed when the material in the bottom electrode BE is oxidized by a natural oxidation process.
[0043] A preliminary first material layer (not shown) may be deposited on the oxide layer. The preliminary first material layer may include one of a metal material containing a metal element, an oxide material containing a metal element, and a nitrogen oxide material containing a metal element. The metal element may include at least one of scandium (Sc), yttrium (Y), titanium (Ti), vanadium (V), niobium (Nb), tantalum (Ta), chromium (Cr), molybdenum (Mo), tungsten (W), iron (Fe), ruthenium (Ru), osmium (Os), cobalt (Co), rhodium (Rh), iridium (Ir), boron (B), tin (Sn), platinum (Pt), or lanthanum (La).
[0044] A heat treatment process may be performed on the preliminary first material layer. In this case, the material in the preliminary first material layer may diffuse into the bottom electrode BE and the oxide layer. As a result of this process, the bottom electrode BE and the oxide layer may be doped with the material included in the preliminary first material layer. As a result of the doping process, the first material layer ML1 may be formed from the bottom electrode BE and the oxide layer. Next, a selective etching process may be performed to remove the preliminary first material layer and only leave the first material layer ML1 on the bottom electrode BE. In an embodiment, a heat treatment process may be performed on the first material layer ML1.
[0045] Next, a first metal oxide layer DL1, a second metal oxide layer DL2, and a third metal oxide layer DL3 of the dielectric layer DL may be sequentially formed on the first material layer ML1. The first metal oxide layer DL1, the second metal oxide layer DL2, and the third metal oxide layer DL3 of the dielectric layer DL may be formed by an atomic layer deposition (ALD) process.
[0046] Here, the second metal oxide layer DL2 of the dielectric layer DL may be formed of a material represented by the chemical formula A x B 1-X O2. Here, elements A and B are two different elements and are selected from the group consisting of zirconium (Zr), hafnium (Hf), titanium (Ti), niobium (Nb), tantalum (Ta), strontium (Sr), and barium (Ba). That is, elements A and B are different from each other, where 0 < x < 1. The concentration range of element A in the second metal oxide layer DL2 may be 20 at% to 80 at%.
[0047] In an embodiment, the concentration of element A in the second metal oxide layer DL2 may be adjusted by forming an oxide material containing element A between oxide materials containing element B and performing a heat treatment process to diffuse element A. In an embodiment, the concentration of element A may be adjusted by providing a cocktail precursor containing elements A and B on the first metal oxide layer DL1. In an embodiment, the concentration of element A may be adjusted by simultaneously or alternately providing a precursor containing element A and a precursor containing element B on the first metal oxide layer DL1.
[0048] Next, a top electrode TE may be formed on the dielectric layer DL. Figure 1A Capacitor structure CAP.
[0049] [Manufacturing method: Example 2]
[0050] Hereinafter, a method for manufacturing a capacitor structure according to Embodiment 2 will be described in more detail. In the following description of the manufacturing method in Embodiment 2, features overlapping with Embodiment 1 will be omitted.
[0051] Referring to Example 2, an oxide layer BEO may be formed on the bottom electrode BE. The oxide layer BEO may be a layer formed when the material in the bottom electrode BE is oxidized by a natural oxidation process. The dielectric layer DL may be formed on the oxide layer BEO. The dielectric layer DL may be formed using the same method as in Example 2. Figure 1A The same or similar manner as described above is formed.
[0052] Next, a second material layer ML2 may be formed on the dielectric layer DL. The second material layer ML2 may include one of a metal material containing a metal element, an oxide material containing a metal element, and an oxynitride material containing a metal element. The metal element may include at least one of scandium (Sc), yttrium (Y), titanium (Ti), vanadium (V), niobium (Nb), tantalum (Ta), chromium (Cr), molybdenum (Mo), tungsten (W), iron (Fe), ruthenium (Ru), osmium (Os), cobalt (Co), rhodium (Rh), iridium (Ir), boron (B), tin (Sn), platinum (Pt), or lanthanum (La).
[0053] Next, a top electrode TE may be formed on the second material layer ML2 to manufacture Figure 1B Capacitor structure CAP.
[0054] [Manufacturing method: Example 3]
[0055] Hereinafter, a method for manufacturing a capacitor structure according to Embodiment 3 will be described in more detail. In the following description of the manufacturing method in Embodiment 3, features overlapping with Embodiments 1 and 2 will be omitted.
[0056] Referring to Example 3, a first material layer ML1 and a dielectric layer DL may be formed on the bottom electrode BE. The first material layer ML1 and the dielectric layer DL may be formed using the same method as in Example 3. Figure 1A The same or similar manner as described above is formed.
[0057] A second material layer ML2 may be formed on the dielectric layer DL. The second material layer ML2 may be formed in a manner similar to or the same as that of Embodiment 2. Next, the capacitor structure CAP in Embodiment 3 may be manufactured by forming a top electrode TE on the second material layer ML2.
[0058] Figure 2 is a plan view illustrating a semiconductor device according to example embodiments of the inventive concepts. Figure 3A It is along Figure 2 A cross-sectional view taken along line AA'.
[0059] Reference Figure 2 and Figure 3A , a substrate 100 may be provided. The substrate 100 may be a semiconductor substrate. For example, the substrate 100 may be a silicon substrate, a germanium substrate, or a silicon-germanium substrate.
[0060] An interlayer insulating layer 162 may be provided on the substrate 100. The interlayer insulating layer 162 may cover at least a portion of the top surface of the substrate 100. The interlayer insulating layer 162 may contact at least a portion of the top surface of the substrate 100. In an embodiment, the interlayer insulating layer 162 may be formed of or include at least one of silicon nitride, silicon oxide, or silicon oxynitride. In an embodiment, the interlayer insulating layer 162 may include an empty region (e.g., an air gap).
[0061] A conductive contact portion 160 may be provided in the interlayer insulating layer 162. The conductive contact portion 160 may contact the top surface of the substrate 100. The interlayer insulating layer 162 may contact the side surface of the conductive contact portion 160. The top surfaces of the conductive contact portion 160 and the interlayer insulating layer 162 may be coplanar. In embodiments, a plurality of conductive contacts 160 may be provided and spaced apart from each other in the first direction D1 and the second direction D2.
[0062] In this specification, the first direction D1 may be defined as a direction parallel to the top surface of the substrate 100. The second direction D2 may be defined as a direction parallel to the top surface of the substrate 100 and perpendicular to the first direction D1. The third direction D3 may be defined as a direction perpendicular to the top surface of the substrate 100.
[0063] The conductive contact 160 may be formed of or include at least one of the following: a doped semiconductor material (e.g., polysilicon), a metal material (e.g., Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, Pt, Au, and Ag), a metal nitride material (e.g., nitride materials of Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, Pt, Au, and Ag), or a metal silicide material (e.g., silicide materials of Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, Pt, Au, and Ag). The conductive contact 160 may be electrically connected to an impurity region (e.g., a source / drain region) formed in the substrate 100.
[0064] A capacitor structure CAP, an etch stop layer ES, and a support layer SS may be provided on the conductive contact portion 160. The etch stop layer ES may be provided on the interlayer insulating layer 162. The etch stop layer ES may be provided to cover the interlayer insulating layer 162 and expose the conductive contact portion 160. For example, the bottom surface of the etch stop layer ES may contact the top surface of the interlayer insulating layer 162. The etch stop layer ES may be formed of or include at least one of silicon oxide, SiCN, or SiBN. In an embodiment, the capacitor structure CAP may correspond to Figures 1A to 1C The capacitor structure CAP may include a bottom electrode BE, a dielectric layer DL, and a top electrode TE.
[0065] A bottom electrode BE may be provided on the conductive contact 160. The bottom electrode BE may penetrate the etch stop layer ES and may be electrically connected to the conductive contact 160. For example, the bottom surface of the bottom electrode BE may contact the top surface of the conductive contact 160. The lower portion of the bottom electrode BE may be surrounded by the etch stop layer ES. Here, the bottom electrode BE may be a columnar pattern.
[0066] In an embodiment, a plurality of bottom electrodes BE may be provided, and the bottom electrodes BE may be spaced apart from each other in the first direction D1 and the second direction D2. When viewed in a plan view, the bottom electrodes BE may be arranged in a honeycomb shape. Specifically, the bottom electrodes BE may be arranged such that each bottom electrode BE is located at the center of a hexagon defined by the other six bottom electrodes BE.
[0067] Figure 3B It is along Figure 2 The cross-sectional view taken along the line AA' of FIG. Figure 2 and Figure 3A The elements described above may be identified by the same reference numerals without repeated description.
[0068] Reference Figure 3BThe bottom electrode BE may be a columnar pattern with a seam SE formed therein. The seam SE may extend from the center of the top surface of the bottom electrode BE toward the top surface of the conductive contact 160. The seam SE may be longer than half the height of the bottom electrode BE. The seam SE may not contact the top surface of the conductive contact 160.
[0069] Figure 3C It is along Figure 2 The cross-sectional view taken along the line AA' of FIG. Figure 2 and Figure 3A The elements described above may be identified by the same reference numerals without repeated description.
[0070] Reference Figure 3C , the bottom electrode BE may have a hollow cylindrical shape (eg, a cup shape) with one end closed. However, the shape of the bottom electrode BE is not limited to this example.
[0071] Return to reference Figure 2 and Figure 3A A support layer SS may be provided on the substrate 100. The support layer SS may be provided between adjacent bottom electrodes BE. The support layer SS may be in contact with and surround the side surfaces of the bottom electrodes BE. Thus, the support layer SS may mechanically support the bottom electrodes BE.
[0072] In an embodiment, the support layer SS may include multiple support layers SS, and the multiple support layers SS may be arranged spaced apart from each other in the third direction D3. The top surface of the uppermost support layer SS among the support layers SS may be located at a different or the same height as the top surface of the bottom electrode BE. In an embodiment, the support layer SS may be formed of or include at least one of the following: silicon nitride, SiBN, or SiCN.
[0073] A through-hole PH may be provided between adjacent bottom electrodes BE. In an embodiment, a circular through-hole PH may be provided between three adjacent bottom electrodes BE to expose a portion of the side surface of each of the three bottom electrodes BE. However, the present invention is not limited to this example, and through-holes PH of various shapes may be provided between the bottom electrodes BE. The through-hole PH may be provided to expose the etch-stop layer ES. In an embodiment, a plurality of through-holes PH may be provided, spaced apart from each other in the first direction D1 and the second direction D2.
[0074] A top electrode TE may be disposed on the bottom electrode BE. The top electrode TE may cover the bottom electrode BE and the support layer SS. The top electrode TE may be disposed to fill the through hole PH, the area between the bottom electrodes BE, the area between the support layers SS, and the area between the lowermost support layer SS of the support layers SS and the etching stop layer ES.
[0075] A dielectric layer DL may be interposed between each of the bottom electrodes BE and the top electrode TE. The dielectric layer DL may extend into the region between the support layer SS and the top electrode TE, and between the etch stop layer ES and the top electrode TE. The dielectric layer DL may conformally cover the support layer SS, the bottom electrode BE, and the etch stop layer ES. The dielectric layer DL may fill the through hole PH together with the top electrode TE.
[0076] Figure 4 is a plan view illustrating a semiconductor device according to example embodiments of the inventive concepts. Figure 5 and Figure 6 It is along Figure 4 Cross-sectional view taken along lines BB' and CC'.
[0077] Reference Figures 4 to 6 , a substrate 100 may be provided. The substrate 100 may correspond to Figure 3A substrate 100.
[0078] Device isolation patterns STI may be provided on the substrate 100. The device isolation patterns STI may be provided to define active patterns ACT on the substrate 100. Each of the active patterns ACT may be a protruding portion extending along the third direction D3. In embodiments, the device isolation patterns STI may be provided in the substrate 100, and the active pattern ACT may be a portion of the substrate 100 surrounded by the device isolation patterns STI. For ease of explanation, unless otherwise specified, the term "substrate 100" may refer to the remaining portion of the substrate 100 excluding the active patterns ACT.
[0079] The active patterns ACT may be spaced apart from each other in the first direction D1 and the second direction D2. The active patterns ACT may be isolated stripe patterns that are spaced apart from each other and elongated in the fourth direction D4. The fourth direction D4 may be parallel to the top surface of the substrate 100 and may not be parallel to the first direction D1 and the second direction D2.
[0080] Each of the active patterns ACT may include a pair of edge portions EA and a center portion CA. The pair of edge portions EA may be ends of the active pattern ACT that are opposite to each other in the fourth direction D4. The center portion CA may be a portion of the active pattern ACT between the pair of edge portions EA, and in particular, may be a portion of the active pattern ACT between a pair of word lines WL, which will be described below. The pair of edge portions EA and the center portion CA may be impurity regions doped with impurities (e.g., n-type impurities or p-type impurities).
[0081] The device isolation pattern (STI) may include an insulating material. For example, the device isolation pattern (STI) may be formed of or include at least one of silicon oxide or silicon nitride. The device isolation pattern (STI) may be a single layer formed of one of the aforementioned materials, or a composite layer formed of at least two of the aforementioned materials.
[0082] The word line WL may be arranged to intersect the active pattern ACT. As an example, the word line WL may be arranged to intersect the active pattern ACT and the device isolation pattern STI in the first direction D1. In an embodiment, a plurality of word lines WL may be provided. The word lines WL may be spaced apart from each other in the second direction D2. In an embodiment, a pair of word lines WL adjacent to each other in the second direction D2 may be provided to intersect the active pattern ACT.
[0083] In an embodiment, each word line WL may include a gate electrode GE, a gate insulation pattern GI, and a gate capping pattern GC. The gate electrode GE may be arranged to intersect the active pattern ACT and the device isolation pattern STI in a first direction D1. The gate insulation pattern GI may be interposed between the gate electrode GE and the active pattern ACT. The gate capping pattern GC may cover the top surface of the gate electrode GE.
[0084] A buffer pattern BP may be provided on the substrate 100. The buffer pattern BP may cover the active pattern ACT, the device isolation pattern STI, and the word line WL. The buffer pattern BP may be formed of or include at least one of silicon oxide, silicon nitride, or silicon oxynitride. The buffer pattern BP may be a single layer formed of a single material, or a composite layer including two or more materials.
[0085] A bit line node contact DC may be provided on each of the active patterns ACT, and in an embodiment, a plurality of bit line node contacts DC may be provided. Each of the bit line node contacts DC may be connected to a corresponding one of the center portions CA of the active pattern ACT. The bit line node contacts DC may be spaced apart from each other in a first direction D1 and a second direction D2. The bit line node contacts DC may be interposed between the active pattern ACT and the bit lines BL, which will be described below. Each of the bit line node contacts DC may connect a corresponding one of the bit lines BL to the center portion CA of a corresponding one of the active patterns ACT. In an embodiment, the bit line node contacts DC may be formed of or include doped polysilicon.
[0086] The bit line node contacts DC may be respectively disposed in the first recess regions RS1. The first recess regions RS1 may be disposed above the active pattern ACT and the device isolation pattern STI adjacent to each other. The first recess regions RS1 may be spaced apart from each other in the first direction D1 and the second direction D2.
[0087] The gap-filling insulating pattern BI may fill each of the first groove regions RS1. The gap-filling insulating pattern BI may fill the internal space of the first groove region RS1. In an embodiment, the gap-filling insulating pattern BI may cover the inner surface of the first groove region RS1 and at least a portion of the side surface of the bit line node contact DC (for example, at least a portion in the first groove region RS1). The gap-filling insulating pattern BI may be formed of at least one of silicon oxide or silicon nitride, or include at least one of silicon oxide or silicon nitride. The gap-filling insulating pattern BI may be a single layer formed of a single material, or a composite layer including two or more materials.
[0088] The bit line BL may be disposed on the bit line node contact DC. The bit line BL may be disposed on the bit line node contact DC linearly arranged along the second direction D2. In an embodiment, a plurality of bit lines BL may be provided. The bit lines BL may be spaced apart from each other in the first direction D1. The bit line BL may include a metal material. The bit line BL may be formed of or include at least one metal material (e.g., Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, Pt, Au, and Ag).
[0089] The polysilicon pattern PP may be interposed between the bit line BL and the buffer pattern BP. The top surface of the polysilicon pattern PP may be located at substantially the same height as the top surface of the bit line node contact DC. The polysilicon pattern PP may be formed of or include doped polysilicon.
[0090] An ohmic pattern OP may be interposed between the bit line BL and the bit line node contact DC, and between the bit line BL and the polysilicon pattern PP. The ohmic pattern OP may be formed of, or include, at least one metal silicide material (e.g., a silicide material containing Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, Pt, Au, and Ag). A barrier pattern (not shown) may also be interposed between the bit line BL and the bit line node contact DC, and between the bit line BL and the polysilicon pattern PP. The barrier pattern may be formed of, or include at least one conductive metal nitride material (e.g., a nitride material containing Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, Pt, Au, and Ag).
[0091] A bit line capping pattern BCP may be provided on the bit line BL. In an embodiment, the bit line capping patterns BCP may be provided on the top surfaces of the bit lines BL, respectively. In an embodiment, the bit line capping patterns BCP may extend along the corresponding bit lines BL or extend in the second direction D2, and may be spaced apart from each other in the first direction D1. Each of the bit line capping patterns BCP may vertically overlap with a corresponding bit line BL. The bit line capping pattern BCP may be composed of a single layer or multiple layers. As an example, the bit line capping pattern BCP may include a first capping pattern, a second capping pattern, and a third capping pattern (not shown) stacked in sequence. In an embodiment, each of the first to third capping patterns may include silicon nitride. As another example, the bit line capping pattern BCP may further include additional capping patterns (e.g., a fourth capping pattern and a fifth capping pattern) (not shown).
[0092] The bit line spacer SPC may be disposed on the side surface of the bit line BL and the side surface of the bit line capping pattern BCP. The bit line spacer SPC may cover the side surface of the bit line BL and the side surface of the bit line capping pattern BCP. The bit line spacer SPC on the side surface of the bit line BL may extend along the second direction D2.
[0093] Each of the bit line spacers SPC may include a plurality of subspacers. In an embodiment, each of the bit line spacers SPC may include three or more subspacers sequentially disposed on the side surfaces of the bit line BL. Each of the subspacers may independently include at least one of silicon nitride, silicon oxide, or silicon oxynitride. In an embodiment, at least one of the subspacers may include an air gap formed to separate the other subspacers from each other.
[0094] The storage node contact BC may be disposed between adjacent bit lines BL among the bit lines BL. In an embodiment, a plurality of storage node contacts BC may be disposed spaced apart from each other in the first direction D1 and the second direction D2. The storage node contact BC may fill a second recessed region RS2 formed on an edge portion EA of the active pattern ACT. The storage node contact BC may be electrically connected to the edge portion EA. The storage node contact BC may include a conductive material. In an embodiment, the storage node contact BC may be formed of at least one of doped polysilicon or a metal material (e.g., Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, Pt, Au, and Ag), or include at least one of the doped polysilicon or metal materials.
[0095] On the word line WL, the fence pattern FN may separate the storage node contacts BC from each other in the second direction D2. In an embodiment, the fence patterns FN may be spaced apart from each other in the second direction D2 with the storage node contacts BC interposed therebetween. In an embodiment, the fence pattern FN may be formed of or include silicon nitride.
[0096] The diffusion barrier layer DP may conformally cover the storage node contact BC and the bit line spacer SPC. The diffusion barrier layer DP may be formed of or include a conductive metal nitride material (e.g., containing at least one of Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, Pt, Au, or Ag). A metal silicide layer may also be interposed between the diffusion barrier layer DP and the storage node contact BC.
[0097] The landing pad LP may be provided on the storage node contact BC. In an embodiment, a plurality of landing pads LP may be provided, and the plurality of landing pads LP may be spaced apart from each other in the first direction D1 and the second direction D2. Each of the landing pads LP may be connected to a corresponding one of the storage node contacts BC. The landing pad LP may cover the top surface of the bit line capping pattern BCP. In an embodiment, the lower portion of the landing pad LP may vertically overlap with the storage node contact BC, and the upper portion of the landing pad LP may be offset relative to the lower portion in the second direction D2 or the opposite direction thereof. The landing pad LP may be formed of or include at least one metal material (e.g., Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, Pt, Au, and Ag).
[0098] A filling pattern FI may be provided to surround landing pads LP. The filling pattern FI may be provided between landing pads LP adjacent to each other. When viewed in a plan view, the filling pattern FI may be provided in a grid shape having holes, and in this case, landing pads LP may be provided in the holes to penetrate the filling pattern FI. The filling pattern FI may be formed of or include at least one of: silicon nitride, silicon oxide, or silicon oxynitride. Alternatively, the filling pattern FI may include an empty space having an air layer (e.g., an air gap). As used herein, the term "air" may refer to atmospheric air or other gases that may be present during the manufacturing process.
[0099] The capacitor structure CAP, the etch stop layer ES, and the support layer SS may be disposed on the conductive contact portion 160. The capacitor structure CAP, the etch stop layer ES, and the support layer SS may correspond to Figure 2 and Figures 3A to 3C The capacitor structure CAP, the etch stop layer ES and the support layer SS in the embodiment of FIG. Figures 4 to 6The capacitor structure CAP, the etch stop layer ES and the support layer SS may have the same structure as that of the reference Figure 2 and Figures 3A to 3C The described capacitor structure CAP, etch stop layer ES and support layer SS have substantially the same or similar features.
[0100] Figure 7 FIG. 1 is a diagram showing a portion of a semiconductor device (eg, Figure 5 CU) is an enlarged cross-sectional view. In detail, Figure 7 It shows that the application Figure 1C An enlarged view of a portion of a semiconductor device of a capacitor structure CAP.
[0101] Reference Figure 7 The first material layer ML1 may be disposed on the bottom electrode BE. The second material layer ML2 may be disposed on the top electrode TE. Here, the concentration of the metal material layer in the first material layer ML1 may range from 0 at % to 30 at %.
[0102] The first material layer ML1 on the bottom electrode BE may not extend to the support layer SS. That is, the first material layer ML1 may not be disposed on the support layer SS. Figure 7 The first material layer ML1 disposed on the bottom electrode BE is shown, but the present inventive concept is not limited to this example. In an embodiment, an oxide layer BEO may be interposed between the bottom electrode BE and the dielectric layer DL instead of the first material layer ML1. Figure 1B shown.
[0103] The capping layer PT may be interposed between the dielectric layer DL and the second material layer ML2 . Figure 7 The capping layer PT is shown as being interposed between the dielectric layer DL and the second material layer ML2, but the present invention is not limited to this example. Figure 1A As shown, without the second material layer ML2 , the capping layer PT may be interposed between the top electrode TE and the dielectric layer DL.
[0104] According to an embodiment of the present invention, the dielectric layer of the capacitor structure of the semiconductor device may include a first metal oxide layer and a third metal oxide layer containing zirconium oxide, and a second metal oxide layer containing hafnium zirconium oxide. Here, the concentration of zirconium in the second metal oxide layer may range from 20 at% to 80 at%. In other words, since the second metal oxide layer includes both a tetragonal phase and an orthorhombic phase, a morphotropic phase boundary (MPB) phenomenon may occur. Therefore, the capacitor structure may have improved capacitance characteristics and reduced leakage current, which may make it possible to improve the electrical characteristics of the semiconductor device.
[0105] Furthermore, the capacitor structure may include a tantalum-containing material layer. Due to this material layer, an MPB phenomenon may be induced in the second metal oxide layer in the dielectric layer, and in this case, the electrical characteristics of the capacitor structure may be improved.
[0106] According to an embodiment of the present inventive concept, a semiconductor device may include a capacitor structure. The dielectric layer of the capacitor structure may have regions where both a tetragonal phase and an orthorhombic phase exist, and in this case, a morphotropic phase boundary (MPB) phenomenon may occur. Therefore, the capacitor structure may have improved capacitance characteristics and reduced leakage current, which may make it possible to improve the electrical characteristics of the semiconductor device.
[0107] While example embodiments of the present inventive concepts have been particularly shown and described, it will be understood by those skilled in the art that changes may be made in form and details without departing from the spirit and scope of the appended claims.
Claims
1. A semiconductor device comprising: bottom electrode; a top electrode on the bottom electrode; as well as a dielectric layer and a material layer, between the bottom electrode and the top electrode, Wherein, the dielectric layer comprises: a first metal oxide layer; a second metal oxide layer on the first metal oxide layer; and a third metal oxide layer, located between the first metal oxide layer and the second metal oxide layer; The material layer includes one of a metal material containing a metal element, an oxide material containing a metal element, and a nitride oxide material containing a metal element, and The metal element includes at least one of scandium (Sc), yttrium (Y), titanium (Ti), vanadium (V), niobium (Nb), tantalum (Ta), chromium (Cr), molybdenum (Mo), tungsten (W), iron (Fe), ruthenium (Ru), osmium (Os), cobalt (Co), rhodium (Rh), iridium (Ir), boron (B), tin (Sn), platinum (Pt), and lanthanum (La). The third metal oxide layer includes a compound represented by the following Chemical Formula 1: [Chemical Formula 1] A x B 1-x O2, wherein A and B are two different elements and are selected from the group consisting of zirconium Zr, hafnium Hf, titanium Ti, niobium Nb, tantalum Ta, strontium Sr, and barium Ba, and Among them, 0 <x<1。 2. The semiconductor device according to claim 1, in, The chemical formula 1 consists of Hf x Zr 1-x O2 is given, and Wherein, the first metal oxide layer and the second metal oxide layer include zirconium oxide.
3. The semiconductor device according to claim 1, wherein The concentration of element A in the third metal oxide layer ranges from 20 at % to 80 at %.
4. The semiconductor device according to claim 1, wherein The concentration of the metal material in the material layer is in a range of 0 at % to 30 at %.
5. The semiconductor device according to claim 2, wherein The first metal oxide layer and the second metal oxide layer include zirconium oxide doped with at least one of aluminum (Al), yttrium (Y), vanadium (V), or silicon (Si). The semiconductor device according to claim 1 , wherein: Each of the bottom electrode and the top electrode includes at least one of vanadium nitride VN, titanium nitride TiN, niobium nitride NbN, molybdenum nitride MoN, tantalum nitride TaN, ruthenium Ru, ruthenium oxide RuO2, platinum Pt, iridium Ir, strontium ruthenate SrRuO3, tungsten W, or tungsten nitride WN.
7. The semiconductor device according to claim 6, in, The material layer is between the top electrode and the dielectric layer, The semiconductor device further comprises an oxide layer between the bottom electrode and the dielectric layer, and The oxide layer includes an oxide material, and the oxide material includes a material included in the bottom electrode.
8. The semiconductor device according to claim 6, in, The material layer includes: a first material layer between the bottom electrode and the dielectric layer; and a second material layer between the top electrode and the dielectric layer, wherein the first material layer is in contact with the first metal oxide layer of the dielectric layer, and The second material layer is in contact with the second metal oxide layer of the dielectric layer.
9. The semiconductor device according to claim 8, wherein The first material layer includes an oxide material including a material included in the bottom electrode.
10. A semiconductor device comprising: bottom electrode; a top electrode on the bottom electrode; as well as a dielectric layer and a material layer, between the bottom electrode and the top electrode, Wherein, the dielectric layer comprises: a first metal oxide layer; a second metal oxide layer on the first metal oxide layer; and a third metal oxide layer, located between the first metal oxide layer and the second metal oxide layer; wherein the first metal oxide layer and the second metal oxide layer comprise zirconium oxide, Wherein, the third metal oxide layer comprises hafnium zirconium oxide, and Wherein, the thickness of the third metal oxide layer is 30% to 50% of the thickness of the dielectric layer.
11. The semiconductor device according to claim 10, in, The thickness of the dielectric layer is in the range of to and Wherein, the thickness range of the third metal oxide layer is to 12. The semiconductor device according to claim 10, wherein The bottom electrode has a column shape or a cylindrical shape.
13. The semiconductor device according to claim 10, in, The material layer includes a first material layer and a second material layer, Wherein, the first material layer is in contact with the bottom electrode, wherein the second material layer contacts the top electrode, and Wherein, the thickness range of each of the first material layer and the second material layer is to 14. A semiconductor device comprising: substrate; a conductive contact portion on the substrate; a bottom electrode on the conductive contact; a top electrode on the bottom electrode; as well as a dielectric layer and a material layer between the bottom electrode and the top electrode, Wherein, the dielectric layer comprises: a first metal oxide layer; a second metal oxide layer on the first metal oxide layer; and a third metal oxide layer on the second metal oxide layer, wherein the first metal oxide layer and the third metal oxide layer comprise zirconium oxide, wherein the second metal oxide layer comprises hafnium zirconium oxide, The material layer includes one of a metal material containing a metal element, an oxide material containing a metal element, and a nitride oxide material containing a metal element. The metal element includes at least one of scandium (Sc), yttrium (Y), titanium (Ti), vanadium (V), niobium (Nb), tantalum (Ta), chromium (Cr), molybdenum (Mo), tungsten (W), iron (Fe), ruthenium (Ru), osmium (Os), cobalt (Co), rhodium (Rh), iridium (Ir), boron (B), tin (Sn), platinum (Pt), and lanthanum (La). wherein the first metal oxide layer and the third metal oxide layer include a tetragonal phase, and Wherein, the second metal oxide layer includes a tetragonal phase and an orthorhombic phase.
15. The semiconductor device according to claim 14, in, The material layer is between the dielectric layer and the top electrode, and the thickness of the material layer is in the range of to 16. The semiconductor device according to claim 15, further comprising: a support layer between the bottom electrodes; as well as The capping layer is located between the dielectric layer and the material layer.
17. The semiconductor device according to claim 16, wherein The capping layer includes at least one of silicon Si, boron B, lithium Li, scandium Sc, aluminum Al, yttrium Y, niobium Nb, tantalum Ta, titanium Ti, molybdenum Mo, and lanthanum La.
18. The semiconductor device according to claim 14, wherein The concentration of zirconium in the second metal oxide layer of the dielectric layer is higher than the concentration of hafnium.
19. The semiconductor device according to claim 14, wherein The concentration of the metal material in the material layer is in a range of 0 at % to 30 at %.
20. The semiconductor device according to claim 14, in, The thickness of the dielectric layer is in the range of to and Wherein, the thickness range of the second metal oxide layer is to
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