Preparation method of SiGeSn source-drain structure and semiconductor device

Abstract

The invention provides a preparation method of a SiGeSn source-drain structure and a semiconductor device, and the preparation method comprises the following steps: providing a silicon substrate, and forming a groove in one surface of the silicon substrate; a buffer layer is formed in the groove, the buffer layer comprises a first SiGe buffer layer and a second SiGe buffer layer, and the Ge concentration of the second SiGe buffer layer is larger than that of the first SiGe buffer layer; forming a SiGeSn layer on the buffer layer; and forming a cap layer on the SiGeSn layer. According to the preparation method of the SiGeSn source drain structure, selective SiGeSn epitaxial growth is achieved by introducing SiGeSn and through ClF3, a traditional SiGe main body layer is replaced with SiGeSn, an energy band structure of a channel material is optimized and changed by means of a larger stress effect generated by SiGeSn, the effective mass of carriers is effectively reduced, the carrier mobility is further remarkably improved, and the performance of the SiGeSn source drain structure is improved. The problem that the carrier mobility is not improved enough in the prior art is solved.

Description

Technical Field

[0001] The present invention relates to the technical field related to semiconductor preparation, and in particular to a method for preparing a SiGeSn source-drain structure and a semiconductor device. Background Art

[0002] As semiconductor technology continues to evolve, integrated circuit feature sizes continue to shrink, currently reaching the 28nm technology node and even lower. At this stage of development, improving transistor performance to meet the demands for ever-increasing computing power and low power consumption has become a core challenge that the semiconductor industry urgently needs to overcome. Traditional silicon-based materials face numerous physical challenges: reduced feature sizes lead to a significant decrease in carrier mobility, and leakage current caused by short-channel effects increases device static power consumption by 3-5 orders of magnitude, significantly limiting further improvements in device performance.

[0003] Silicon germanium (SiGe) materials are widely used in semiconductor technology. In complementary metal oxide semiconductor (CMOS) processes at 28nm and below, SiGe is often used for stress engineering. Due to the 4.2% lattice mismatch between SiGe and the silicon substrate, selective epitaxial growth of SiGe layers in the source and drain regions generates uniaxial compressive stress (PMOS) or tensile stress (NMOS) during selective epitaxial growth. This stress alters the channel lattice symmetry through the piezoelectric effect, increasing hole mobility and enhancing the transistor's drive capability.

[0004] However, with the further miniaturization of device size, the stress that SiGe can provide is gradually unable to meet the demand for higher performance. Its stress induction ability is limited, and its effectiveness in improving carrier mobility has gradually reached a bottleneck, making it difficult to fully tap the performance potential of the device. In recent years, silicon germanium tin (SiGeSn) has attracted widespread attention as an emerging semiconductor material. The introduction of the Sn element gives SiGeSn materials a series of unique advantages. Compared with SiGe, SiGeSn can more flexibly adjust the lattice constant and band structure of the material by regulating the Sn content, which is expected to provide greater stress and further improve the channel carrier mobility. In addition, SiGeSn has the potential to be compatible with existing CMOS processes, creating conditions for achieving performance improvements under the existing semiconductor manufacturing system.

[0005] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present invention, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0006] In response to the problems in the prior art, the purpose of the present invention is to provide a method for preparing a SiGeSn source-drain structure and a semiconductor device. In the preparation method, SiGeSn is introduced and ClF3 is used to achieve selective SiGeSn epitaxial growth. The greater stress generated by SiGeSn optimizes and changes the band structure of the channel material, effectively reducing the effective mass of carriers, thereby achieving a significant improvement in carrier mobility.

[0007] Specifically, the first aspect of the present invention provides a method for preparing a SiGeSn source-drain structure, the method comprising the following steps:

[0008] Providing a silicon substrate, wherein a groove is formed on one surface of the silicon substrate, and the groove is an undercut structure;

[0009] forming a buffer layer in the trench, the buffer layer comprising a first SiGe buffer layer and a second SiGe buffer layer, wherein the Ge concentration of the second SiGe buffer layer is greater than the Ge concentration of the first SiGe buffer layer;

[0010] forming a SiGeSn layer on the buffer layer;

[0011] A cap layer is formed on the SiGeSn layer.

[0012] According to the first aspect of the present invention, the preparation method further comprises the following steps:

[0013] forming a first passivation layer, wherein the step of forming the first passivation layer is before the step of forming the SiGeSn layer; and / or

[0014] A second passivation layer is formed, and the step of forming the second passivation layer is after the step of forming the SiGeSn layer.

[0015] According to the first aspect of the present invention, the first passivation layer is an aluminum oxide layer or a silicon nitride layer; and / or;

[0016] The second passivation layer is an aluminum oxide layer or a silicon nitride layer.

[0017] According to the first aspect of the present invention, the first SiGe buffer layer and the second SiGe buffer layer are formed by a chemical vapor deposition process.

[0018] According to the first aspect of the present invention, the thickness of the first SiGe buffer layer is between 5nm and 10nm;

[0019] The Ge concentration of the first SiGe buffer layer is between 10% and 20%.

[0020] According to the first aspect of the present invention, the thickness of the second SiGe buffer layer is between 5nm and 20nm;

[0021] The Ge concentration of the second SiGe buffer layer is between 20% and 40%.

[0022] According to a first aspect of the present invention, a SiGeSn layer is formed by a chemical vapor deposition process, wherein the tin source is tin tetrachloride (SnCl4) or dimethyltin (Sn(CH3)2).

[0023] According to the first aspect of the present invention, the reaction gas in the chemical vapor deposition process includes at least chlorine trifluoride (ClF3).

[0024] According to the first aspect of the present invention, the Sn concentration in the SiGeSn layer is between 5% and 20%; and / or

[0025] The thickness of the SiGeSn layer is between 50nm and 100nm; and / or

[0026] The Ge concentration of the SiGeSn layer is between 30% and 50%.

[0027] According to the first aspect of the present invention, the Ge concentration in the SiGeSn layer gradually increases in the thickness direction.

[0028] A second aspect of the present invention provides a semiconductor device, which includes at least a SiGeSn source-drain structure, and the SiGeSn source-drain structure is obtained by the preparation method described in the first aspect.

[0029] Compared with the prior art, the preparation method of the SiGeSn source-drain structure of the present invention introduces SiGeSn and uses ClF3 to achieve selective SiGeSn epitaxial growth, replacing the traditional SiGe main layer with SiGeSn. By virtue of the greater stress generated by SiGeSn, the band structure of the channel material is optimized and changed, effectively reducing the effective mass of the carriers, thereby achieving a significant improvement in the carrier mobility, and solving the problem of insufficient improvement in the carrier mobility in the prior art. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The drawings herein are incorporated into and constitute a part of the specification, illustrating embodiments consistent with the present application, and together with the specification, are used to explain the principles of the present application. By reading the detailed description of the non-limiting embodiments with reference to the following drawings, other features, purposes and advantages of the present invention will become more apparent. Obviously, the drawings described below are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative work. In addition, the drawings are only schematic illustrations of the present disclosure and are not necessarily drawn to scale. The same figure numbers in the figures represent the same or similar parts, and their repeated descriptions will be omitted. Some of the block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities.

[0031] Figure 1 This is a flow chart of a method for preparing a SiGeSn source-drain structure according to one embodiment of the present invention;

[0032] Figure 2 Schematic diagram of the structure of the silicon substrate corresponding to each step of the method for preparing the SiGeSn source-drain structure according to one embodiment of the present invention;

[0033] Figure 3 An energy dispersive X-ray spectrum diagram of a SiGeSn source-drain structure of a semiconductor device according to an embodiment of the present invention; and

[0034] Figure 4 FIG. 1 is a transmission electron microscope (TEM) image of a SiGeSn source-drain structure of a semiconductor device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0035] The following describes the embodiments of the present invention through specific examples. Those skilled in the art will readily understand the other advantages and benefits of the present invention from the disclosure herein. The present invention may also be implemented or applied in various other specific embodiments, and the various details of the present invention may be modified or altered based on different viewpoints and application systems without departing from the spirit of the present invention. It should be noted that the embodiments and features of the embodiments of the present invention may be combined with each other unless they conflict.

[0036] The following is a detailed description of the embodiments of the present invention with reference to the accompanying drawings so that those skilled in the art can easily implement the present invention. The present invention can be embodied in many different forms and is not limited to the embodiments described herein.

[0037] In the description of the present invention, reference to the terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with that embodiment or example are included in at least one embodiment or example of the present invention. Moreover, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, those skilled in the art may combine and integrate different embodiments or examples described in the present invention, as well as features of different embodiments or examples, unless otherwise inconsistent.

[0038] In order to clearly describe the present invention, components not related to the description are omitted, and the same or similar components are denoted by the same reference numerals throughout the specification.

[0039] Throughout this specification, when a device is said to be "connected" to another device, this includes not only "direct connection" but also "indirect connection" with other elements interposed therebetween. Furthermore, when a device is said to "include" a certain component, unless otherwise stated, this does not exclude the inclusion of other components but rather implies that the device may include other components.

[0040] When a device is said to be "on" another device, it may be directly on the other device, but there may also be other devices between it. In contrast, when a device is said to be "directly on" another device, there are no other devices between it.

[0041] Although the terms first, second, etc. are used in some instances herein to represent various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, the first interface and the second interface, etc. are represented. Furthermore, as used in this article, the singular forms "one," "an," and "the" are intended to also include the plural forms, unless there is a contrary indication in the context. It should be further understood that the terms "comprise," "include," and "include" indicate the presence of features, steps, operations, elements, components, items, types, and / or groups, but do not exclude the presence, occurrence, or addition of one or more other features, steps, operations, elements, components, items, types, and / or groups. The terms "or" and "and / or" used herein are interpreted as inclusive, or mean any one or any combination. Therefore, "A, B, or C" or "A, B, and / or C" means "any of the following: A; B; C; A and B; A and C; B and C; A, B, and C." Exceptions to this definition only occur when the combination of elements, functions, steps, or operations is inherently mutually exclusive in some way.

[0042] The technical terms used herein are intended only to refer to specific embodiments and are not intended to limit the present invention. The singular as used herein also includes the plural unless expressly stated to the contrary. The term "comprising" as used in this specification specifies specific features, regions, integers, steps, operations, elements, and / or components and does not exclude the presence or addition of other features, regions, integers, steps, operations, elements, and / or components.

[0043] Although not defined differently, all terms used herein, including technical and scientific terms, have the same meanings as those generally understood by those skilled in the art to which this invention belongs. Terms defined in commonly used dictionaries are to be interpreted as having meanings consistent with the relevant technical literature and current knowledge, and unless otherwise defined, they should not be overly interpreted as ideal or highly formalized meanings.

[0044] The following further illustrates the method for preparing the SiGeSn source-drain structure and the semiconductor device of the present invention in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments are not intended to limit the scope of protection of the present invention.

[0045] The present invention provides a method for preparing a SiGeSn source-drain structure. Figure 1 This is a flow chart of a method for preparing a SiGeSn source-drain structure according to an embodiment of the present invention. The SiGeSn source-drain structure can be used to form source-drain structures in metal oxide semiconductor field effect transistors (MOSFETs) and complementary metal oxide semiconductor (CMOS) devices. The preparation method of the present invention is further described below using the preparation of a SiGeSn source-drain structure for a P-type metal oxide semiconductor field effect transistor (PMOS). Figure 1 Flowchart of a method for preparing a SiGeSn source-drain structure according to an embodiment of the present invention. Specifically, the method comprises the following steps:

[0046] Step S100: providing a silicon substrate 100, a trench H being formed on one surface of the silicon substrate 100; wherein the silicon substrate 10 may be a single crystal silicon substrate, and its doping concentration may be determined according to the structure of the target semiconductor device. Of course, a PMOS gate structure 20 is also formed on the silicon substrate 10, and trenches H are formed in the silicon substrate 10 on both sides of the gate structure 20, and SiGeSn source and drain structures are formed in the trenches H.

[0047] Figure 2 FIG. 1 is a schematic diagram of the structure of the silicon substrate corresponding to each step of the method for preparing the SiGeSn source-drain structure according to an embodiment of the present invention. Figure 2As shown in part (a) of the figure, the sidewalls of trench H in silicon substrate 10 have a Σ-shaped cross-section, meaning the sidewalls of trench H are stepped and recessed, with a depth ranging from 10 nm to 30 nm. Such Σ-shaped trenches H can be achieved by forming a mask layer on the surface of silicon substrate 10, patterning the mask layer to form several openings exposing the surface of silicon substrate 10, and finally employing a dry etch process superimposed on a wet etch process by adjusting the parameters of each etch stage, such as the selected etching gas / liquid. Precise control of the etching process is crucial to the size, shape, and surface quality of the trench, directly impacting the quality of subsequent epitaxial growth and device performance. By optimizing etching parameters, such as etching gas type, flow rate, power, and time, the trench structure can be ensured to meet design requirements. Experimental results show that the SiGe layer in the Σ-shaped sidewalls of trench H exerts significant tensile stress on the trench H region.

[0048] Of course, the silicon substrate with the trench H must be cleaned before step S200. Depending on the cleaning method selected, further deoxidation or dehydrogenation treatment is performed. This step is intended to remove impurities, oxides, and adsorbed hydrogen atoms from the surface of the silicon substrate (trench H), thereby creating a clean and active surface environment for subsequent epitaxial growth. The cleaning process can adopt a mature process such as the standard RCA cleaning method to ensure the high quality of the surface on which the SnGe alloy is subsequently grown.

[0049] The SiGe atoms are deposited on the cleaned silicon substrate to obtain a buffer layer by epitaxial growth. That is, step S200 is performed: a buffer layer 51 is formed in the trench H. The buffer layer 51 includes a first SiGe buffer layer and a second SiGe buffer layer. Figure 2 Part (b). In step S200, the first SiGe buffer layer and the second SiGe buffer layer can be obtained by chemical vapor deposition processes, such as atmospheric pressure chemical vapor deposition (APCVD), low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition, etc. The silicon source can be dichlorodihydrogen silicon (SiH2Cl2), silane (SiH4) and / or disilane (Si2H6), the germanium source is germane (GeH4), and the growth process temperature is between 500°C and 1200°C. The Ge concentration and performance of the first SiGe buffer layer and the second SiGe buffer layer can be precisely controlled by using a combination of the above gases and precise optimization of the process conditions.

[0050] In the present invention, the Ge concentration of the second SiGe buffer layer is greater than that of the first SiGe buffer layer. The relatively low-Ge-concentration first SiGe buffer layer serves as the starting layer for epitaxial growth. It grows simultaneously along the sidewalls and bottom surface of trench H. The Ge concentration of this layer can be controlled within a range of 10% to 20%, and its thickness can be precisely controlled within a range of 5nm to 10nm. Its primary function is to provide a transition region between the silicon substrate and subsequently grown layers, preliminarily adjusting the lattice constant and reducing stress caused by lattice mismatch, thereby providing favorable nucleation conditions for the growth of subsequent layers.

[0051] The Ge concentration of the second SiGe buffer layer can be between 20% and 40%, and the thickness can be between 5nm and 20nm. The second SiGe buffer layer and the first SiGe buffer layer need to completely cover the sidewalls and bottom of the trench H. By further increasing the Ge concentration, the second SiGe buffer layer can gradually adapt to the lattice constant changes of the subsequent SiGeSn layer, further alleviating the lattice mismatch stress and improving the crystal quality of the epitaxial layer. At the same time, the growth process of the second SiGe buffer layer helps to optimize the surface flatness and provide a more ideal surface morphology for the subsequent growth of the SiGeSn layer.

[0052] In some embodiments, the Ge concentration of the second SiGe buffer layer gradually increases along the thickness direction of the silicon substrate 10. For example, when the Ge concentration of the first SiGe buffer layer is 10%, the thickness of the second SiGe buffer layer is 20nm. In the thickness direction of the second SiGe buffer layer, the Ge concentration can be gradually increased from 20% to 40%. The control of the Ge concentration of the second SiGe buffer layer can be achieved by controlling (gradually changing) the flow rate of the silicon source and the germanium source or the ratio between the two. The gradual Ge concentration design enables the second SiGe buffer layer to gradually release the lattice mismatch stress during the growth process, avoiding stress concentration and causing a large number of dislocations. The buffer layer 51 of the present invention includes two layers with different Ge concentrations, which are used to alleviate the lattice mismatch between the silicon substrate and the subsequent SiGeSn layer, reduce the dislocation density, and lay the foundation for the growth of high-quality SiGeSn layers.

[0053] Step S300: forming a SiGeSn layer 52 on the buffer layer 51. Figure 2 In part (c), in this step, a chemical vapor deposition process can be used to form the SiGeSn layer 52, wherein the reaction gas in the chemical vapor deposition process includes at least chlorine trifluoride (ClF3), the silicon source can be dichlorosilane (SiH2Cl2), silane (SiH4) and / or disilane (Si2H6), the germanium source can be germane (GeH4), and the tin source can be tin tetrachloride (SnCl4) or dimethyltin (Sn(CH3)2).

[0054] SiGeSn layer 52 serves as the core layer of the entire epitaxial structure. Its Ge concentration can be between 30% and 50%, and its thickness can be between 50nm and 100nm. During the chemical vapor deposition process of this layer, chlorine trifluoride (ClF3) gas is introduced at a controlled flow rate of 5-100sccm. The ClF3 gas performs in-situ cleaning and etching of the surface during deposition, removing surface impurities and defects, promoting the selective growth of SiGeSn, and regulating the surface chemical reaction kinetics, thereby helping to obtain a high-quality, uniformly composed SiGeSn epitaxial layer.

[0055] In some embodiments, the Ge concentration in the SiGeSn layer 52 gradually increases in the thickness direction. For example, the thickness of the SiGeSn layer 52 is 50 nm, and the Ge concentration can gradually increase from 30% to 50% in the thickness direction. The gradual Ge concentration design can effectively release lattice stress and reduce the generation and expansion of dislocations, thereby improving the crystal integrity and electrical properties of the epitaxial layer. Preferably, the Sn concentration in the SiGeSn layer is between 5% and 20%, such as the Sn concentration in the SiGeSn layer is 5%, 10%, 15% or 20%.

[0056] The selection of the deposition temperature for the buffer layer 51 in step S200 of the preparation method of the present invention should comprehensively consider factors such as the deposition rate of SiGe atoms, reaction kinetics, and the crystal quality of the epitaxial layer. The temperature of the silicon substrate is then adjusted to the deposition temperature of the SiGeSn layer, and SiGeSn is deposited on the grown SiGe buffer layer to achieve the growth of the SiGeSn epitaxial layer. The setting of the growth temperature of the SiGeSn layer should take into account the diffusion behavior of the various SiGeSn elements, the chemical reactivity, and the compositional uniformity of the epitaxial layer to ensure that a SiGeSn epitaxial layer with ideal performance is obtained.

[0057] In order to prevent the surface of the SiGeSn layer 52 in the trench from being oxidized or contaminated, step S400 is performed: a cap layer 53 is formed on the SiGeSn layer 52. Figure 2 (d) of FIG. Cap layer 53 may be a Si cap layer (SiCap) obtained by chemical vapor deposition. After step S400, a gaseous precursor (such as silane SiH4 or dichlorosilane SiH2Cl2) decomposes on the surface of silicon substrate 10, depositing silicon atoms to form the Si cap layer. The top surface of Si cap layer 53 protrudes above the top of trench H in silicon substrate 10. Si cap layer 53 can also improve the interface performance between the SiGeSn layer and subsequent structures in the semiconductor device, thereby enhancing the stability and reliability of the device.

[0058] This invention provides a novel method for selectively growing silicon-germanium-tin (SiGeSn) source-drain structures. By replacing traditional silicon-germanium (SiGe) materials with SiGeSn, the performance of semiconductor devices is improved. Placing a multilayer SiGe buffer layer with varying Ge concentrations before constructing the SiGeSn layer effectively reduces dislocations and defects at the interface between the silicon substrate and SiGeSn, thereby improving the material's crystal quality and device performance.

[0059] In some other embodiments, the method for preparing the SiGeSn source-drain structure of the present invention further includes the following steps:

[0060] The first passivation layer is formed before the step S300 of forming the SiGeSn layer 52 on the buffer layer 51; the first passivation layer can be an aluminum oxide (Al2O3) layer or a silicon nitride (SiN X ) layer, the first passivation layer can prevent the subsequent SiGeSn layer from diffusing into the buffer layer.

[0061] Furthermore, the method for preparing the SiGeSn source-drain structure further includes the following steps:

[0062] The second passivation layer is formed after step S300 of forming the SiGeSn layer 52. Similarly, the second passivation layer can be an aluminum oxide layer or a silicon nitride layer. The presence of the second passivation layer can protect the SiGeSn layer from the external environment and improve the stability and reliability of the semiconductor device.

[0063] To ensure the thermal stability of the SiGeSn layer 52, the subsequent process can optimize the heat treatment scheme and reduce the thermal budget. By precisely controlling the heat treatment parameters such as temperature, time, and atmosphere, the effects of thermal stress on the SiGeSn layer can be reduced, maintaining the stability of its crystal structure and performance.

[0064] The present invention also provides a semiconductor device, which comprises at least a SiGeSn source-drain structure, and the SiGeSn source-drain structure is obtained by the above-mentioned preparation method. Figure 3 and Figure 4 The following are energy dispersive X-ray spectroscopy (EDX) images and transmission electron microscope (TEM) images of the SiGeSn source-drain structure in a semiconductor device according to an embodiment of the present invention. The SiGeSn source-drain structure includes:

[0065] A silicon substrate 10 and a trench H thereon;

[0066] A buffer layer 51 is formed in the trench H, and the buffer layer 51 includes a first SiGe buffer layer and a second SiGe buffer layer, and the Ge concentration of the second SiGe buffer layer is greater than the Ge concentration of the first SiGe buffer layer;

[0067] forming a SiGeSn layer 52 on the buffer layer 51; and

[0068] A cap layer 53 is formed on the SiGeSn layer 52 .

[0069] As the feature size of semiconductor devices shrinks to the 28-nanometer node, the short channel effect becomes increasingly significant. This effect can cause a series of problems such as unstable device threshold voltage, increased leakage current, and reduced carrier mobility, seriously damaging the performance and reliability of the device. The ability of SiGe materials to suppress the short channel effect is gradually declining, making it difficult to effectively ensure the stability of device performance. The SiGeSn source-drain structure of the semiconductor device of the present invention uses SiGeSn as the channel material. By rationally designing the structure and composition of the buffer layer 51 and the SiGeSn layer 52, greater stress can be provided to the channel. This stress effect changes the band structure of the channel material, reduces the effective mass of the holes, and thus significantly improves the hole mobility. Compared with existing semiconductor devices, taking the SiGe PMOS device as an example, the hole mobility of the SiGeSn PMOS device of the present invention is expected to increase by 30% to 50%. For example, under the same operating voltage and size conditions, the hole mobility of a traditional Si PMOS device may be 100 to 150 cm 2 / Vs, and the hole mobility of the SiGeSn PMOS device of the present invention is expected to reach 130-225cm 2 / Vs.

[0070] In summary, the present invention enhances the ability of semiconductor devices to resist the short channel effect. Greater stress can improve the carrier transport characteristics, which is expected to reduce leakage current and stabilize the threshold voltage, thereby effectively alleviating the performance degradation problem caused by the short channel effect and greatly improving the reliability and stability of semiconductor devices.

[0071] Although the embodiments of the present invention have been shown and described above, it will be understood that the above embodiments are illustrative and are not to be construed as limitations on the present invention. A person skilled in the art may change, modify, replace and modify the above embodiments within the scope of the present invention.

[0072] The above is a further detailed description of the present invention in conjunction with specific preferred embodiments, and the specific implementation of the present invention should not be considered to be limited to these descriptions. For those skilled in the art of the present invention, without departing from the concept of the present invention, several simple deductions or substitutions can be made, which should be considered to fall within the scope of protection of the present invention.

Claims

1. A method for preparing a SiGeSn source-drain structure, characterized in that: The preparation method comprises the following steps: Providing a silicon substrate, wherein a groove is formed on one surface of the silicon substrate; forming a buffer layer in the trench, the buffer layer comprising a first SiGe buffer layer and a second SiGe buffer layer, wherein the Ge concentration of the second SiGe buffer layer is greater than the Ge concentration of the first SiGe buffer layer; forming a SiGeSn layer on the buffer layer; A cap layer is formed on the SiGeSn layer.

2. The method for preparing a SiGeSn source-drain structure according to claim 1, wherein: The preparation method further comprises the following steps: forming a first passivation layer, wherein the step of forming the first passivation layer is before the step of forming the SiGeSn layer; and / or A second passivation layer is formed, and the step of forming the second passivation layer is after the step of forming the SiGeSn layer.

3. The method for preparing a SiGeSn source-drain structure according to claim 2, wherein: The first passivation layer is an aluminum oxide layer or a silicon nitride layer; and / or; The second passivation layer is an aluminum oxide layer or a silicon nitride layer.

4. The method for preparing a SiGeSn source-drain structure according to claim 1, wherein: A first SiGe buffer layer and a second SiGe buffer layer are formed by a chemical vapor deposition process.

5. The method for preparing a SiGeSn source-drain structure according to claim 1, wherein: The thickness of the first SiGe buffer layer is between 5nm and 10nm; The Ge concentration of the first SiGe buffer layer is between 10% and 20%.

6. The method for preparing a SiGeSn source-drain structure according to claim 1, wherein: The thickness of the second SiGe buffer layer is between 5nm and 20nm; The Ge concentration of the second SiGe buffer layer is between 20% and 40%.

7. The method for preparing a SiGeSn source-drain structure according to claim 1, wherein: The SiGeSn layer is formed by a chemical vapor deposition process, wherein the tin source is tin tetrachloride (SnCl4) or dimethyltin (Sn(CH3)2).

8. The method for preparing a SiGeSn source-drain structure according to claim 7, wherein: The reaction gas in the chemical vapor deposition process includes at least chlorine trifluoride (ClF3).

9. The method for preparing a SiGeSn source-drain structure according to claim 7, wherein: The Sn concentration in the SiGeSn layer is between 5% and 20%; and / or The thickness of the SiGeSn layer is between 50nm and 100nm; and / or The Ge concentration of the SiGeSn layer is between 30% and 50%.

10. The method for preparing a SiGeSn source-drain structure according to claim 1, wherein: The Ge concentration in the SiGeSn layer gradually increases in the thickness direction.

11. A semiconductor device, characterized in that: The semiconductor device comprises at least a SiGeSn source-drain structure, and the SiGeSn source-drain structure is obtained by the preparation method according to any one of claims 1 to 10.

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