N-type back junction double-sided TOPCon battery and preparation method thereof

Abstract

The invention relates to the field of solar cells, and discloses an N-type back-junction double-sided TOPCon cell and a preparation method thereof.The N-type back-junction double-sided TOPCon cell comprises an N-type silicon substrate arranged in the middle, silicon oxide layers are arranged on the front face and the back face of the N-type silicon substrate, nitrogen-doped amorphous silicon films are deposited on the front face and the back face of the N-type silicon substrate with the silicon oxide layers, and the nitrogen-doped amorphous silicon films are arranged on the back face and the back face of the N-type silicon substrate with the silicon oxide layers. A boron-doped amorphous silicon film is arranged at the lower end of the back nitrogen-doped amorphous silicon film, a phosphorus-doped amorphous silicon film is arranged at the upper end of the front nitrogen-doped amorphous silicon film, an aluminum oxide film layer is deposited on the front of the N-type silicon substrate, and silicon nitride antireflection layers are deposited outside the boron-doped amorphous silicon film and the phosphorus-doped amorphous silicon film. The N-type back junction double-sided TOPCon battery prepared by the preparation method disclosed by the invention has good passivation performance, and the high efficiency of more than 25% is obtained.

Description

Technical Field

[0001] The present invention belongs to the technical field of solar cells, and in particular relates to an N-type back-junction double-sided TOPCon cell and a preparation method thereof. Background Art

[0002] The development of new crystalline silicon solar cells with high mass-produced photoelectric conversion efficiency and economic feasibility is currently a research hotspot in the photovoltaic industry. TOPCon (Tunneling Oxide Passivated Contact) technology is a new crystalline silicon solar cell technology that has rapidly developed in recent years. The contact uses a full-area polysilicon / silicon oxide passivation contact to replace the localized contact of PERC (Passivated Emitter and Rear Contact) cells. This suppresses minority carrier recombination at the metal-silicon interface while allowing majority carriers to be transmitted via ultra-thin silicon oxide quantum tunneling, resulting in excellent surface passivation with low-resistivity contacts and enabling higher efficiency in silicon solar cells. The core of TOPCon high-efficiency cell technology is the use of an ultra-thin silicon oxide layer and a heavily doped polysilicon layer to form a passivation contact structure, which can achieve excellent surface passivation and selective carrier collection.

[0003] The boron emitter in existing N-type TOPCon crystalline silicon solar cells is typically prepared using a thermal diffusion method. This method results in uneven emitter square resistance, the formation of a boron-rich layer, quartz tube cracking caused by byproduct adhesion, and a very high thermal budget. These problems lead to huge costs in the existing boron emitter preparation process and delay the industrialization of TOPCon cells. In addition, the existing technology uses ammonia as a precursor in plasma-enhanced chemical vapor deposition to introduce nitrogen atoms into the phosphorus-doped amorphous silicon film. After annealing, nitrogen-doped phosphorus-doped amorphous silicon is formed. The presence of nitrogen atoms improves the passivation performance of the TOPCon structure. However, the presence of nitrogen atoms inhibits the activation of phosphorus atoms, resulting in a low concentration of activated carriers on the material surface, which in turn affects the photoelectric conversion efficiency. Summary of the Invention

[0004] In order to address the deficiencies mentioned in the above background technology, the purpose of the present invention is to provide an N-type back-junction bifacial TOPCon cell and a preparation method thereof. The prepared N-type back-junction bifacial TOPCon cell has good passivation performance and achieves a high efficiency of more than 25%.

[0005] The purpose of the present invention can be achieved through the following technical solutions: An N-type back-junction bifacial TOPCon cell comprises an N-type silicon substrate disposed in the middle, wherein silicon oxide layers are provided on both the front and back surfaces of the N-type silicon substrate, nitrogen-doped amorphous silicon films are deposited on both the front and back surfaces of the N-type silicon substrate with the silicon oxide layers, a boron-doped amorphous silicon film is provided at the lower end of the nitrogen-doped amorphous silicon film on the back surface, and a phosphorus-doped amorphous silicon film is provided at the upper end of the nitrogen-doped amorphous silicon film on the front surface, an aluminum oxide film is deposited on the front surface of the N-type silicon substrate, silicon nitride anti-reflection layers are deposited on the outside of the boron-doped amorphous silicon film and the phosphorus-doped amorphous silicon film, and electrodes are provided on the silicon nitride anti-reflection layers.

[0006] Preferably, the thickness of the N-type silicon substrate is 50-200 μm, and the resistivity is 0.1-10 Ω·cm.

[0007] A method for preparing an N-type back-junction double-sided TOPCon cell comprises the following steps: S1. Select N-type silicon as the substrate and perform cleaning and alkali polishing on the substrate surface; S2, growing a thin silicon oxide layer on both sides of the N-type silicon substrate after alkali polishing; S3, depositing nitrogen-doped amorphous silicon thin films on both the front and back surfaces of the N-type silicon substrate with a thin silicon oxide layer; S4, depositing a boron-doped amorphous silicon film on the back side of the N-type silicon substrate with the nitrogen-doped amorphous silicon film; S5, depositing a phosphorus-doped amorphous silicon film on the front surface of the N-type silicon substrate with the nitrogen-doped amorphous silicon film; S6, placing the deposited N-type silicon substrate in a double-tube diffusion annealing furnace under a nitrogen atmosphere for annealing; S7, placing the annealed N-type silicon substrate in a hydrofluoric acid solution for 2-3 minutes, then soaking it in a nitric acid solution for 20-30 seconds, then soaking it in deionized water twice, then changing to a hydrofluoric acid solution and soaking it for 20-30 seconds, then soaking it in deionized water twice again, and repeating this operation until the back surface is hydrophobic; S8, placing the N-type silicon substrate after the source layer is etched and dried in an atomic layer deposition chamber to deposit an aluminum oxide film on the front side, and then annealing the N-type silicon substrate in a nitrogen atmosphere tube furnace to activate hydrogen passivation; S9, using plasma enhanced chemical vapor deposition to deposit a silicon nitride anti-reflection layer, and then annealing in a nitrogen-hydrogen mixed atmosphere at 400° C. to enhance the passivation effect of the silicon nitride anti-reflection layer; S10. Screen printing, sintering, testing and sorting are performed on the N-type silicon substrate that has completed the deposition process to prepare an N-type rear-junction double-sided TOPCon battery.

[0008] Preferably, the thickness of the thin silicon oxide layer in step S2 is 1-2 nm.

[0009] Preferably, plasma enhanced chemical vapor deposition is used in steps S3, S4 and S5, silane, phosphine, hydrogen and ammonia are used as precursors in step S3, silane, hydrogen and borane are used as precursors in step S4, and silane, phosphine and hydrogen are used as precursors in step S5.

[0010] Preferably, the thickness of the nitrogen-doped amorphous silicon film in step S3 is 10-20 nm; the thickness of the boron-doped amorphous silicon film in step S4 is 10-20 nm; and the thickness of the phosphorus-doped amorphous silicon film in step S5 is 10-20 nm.

[0011] Preferably, the annealing process parameters in step S6 are: keeping the temperature at 920-960° C. for 120-150 minutes, and taking out the N-type silicon substrate when the annealing furnace temperature drops below 300° C.

[0012] Preferably, the concentration of the hydrofluoric acid solution in step S7 is 2-5%, and the concentration of the nitric acid solution is 65-70%.

[0013] Preferably, the thickness of the aluminum oxide film layer in step S8 is 10-15 nm.

[0014] Preferably, the thickness of the silicon nitride anti-reflection layer in step S9 is 65-70 nm.

[0015] Beneficial effects of the present invention: The present invention adopts N-type silicon wafers, which have high tolerance to impurities and long scoop life, thereby improving battery conversion efficiency; an N-type tunneling poly layer is used on the front of the battery, which not only improves the passivation contact capability but also reduces the parasitic absorption of the front poly; a P-type tunneling poly layer is used on the back of the battery to form a PN junction; placing the P-type poly layer on the back side not only ensures the passivation contact capability of the back side but also reduces the problem of parasitic absorption of light caused by an excessively thick P-type poly layer requiring good contact; the double-sided TOPCon structure reduces surface recombination and improves passivation capability while ensuring good contact.

[0016] The present invention covers a phosphorus-doped amorphous silicon film and a boron-doped amorphous silicon film on the nitrogen-doped amorphous silicon film on both sides of an N-type silicon substrate, respectively. Nitrogen atoms diffuse at high temperature and are enriched at the interface of the silicon oxide layer. Silicon atoms and nitrogen atoms are bonded. In addition, the hydrogen content in the nitrogen-doped polycrystalline silicon sample is relatively high, especially at the interface of the silicon oxide layer, indicating that nitrogen atoms can more effectively capture hydrogen atoms to improve the passivation performance. In addition, a solid boron source is deposited by plasma-enhanced chemical vapor deposition, followed by high-temperature annealing to promote the diffusion of boron to form a boron emitter, which can effectively avoid the shortcomings of the traditional thermal diffusion method. In addition, a silicon oxide layer is introduced between the boron-doped amorphous silicon film and the silicon substrate to avoid direct contact between them during the high-temperature annealing process, thereby preventing the formation of defects such as epitaxial rearrangement and stacking faults in the polycrystalline silicon, thereby improving the passivation effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0018] Figure 1 It is a schematic structural diagram of the N-type back-junction double-sided TOPCon battery of the present invention.

[0019] In the figure: 1-N-type silicon substrate, 2-nitrogen-doped amorphous silicon film, 3-boron-doped amorphous silicon film, 4-silicon nitride anti-reflection layer, 5-phosphorus-doped amorphous silicon film, 6-aluminum oxide film layer, 7-electrode, 8-silicon oxide layer. DETAILED DESCRIPTION

[0020] The following will be combined with the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making any creative efforts shall fall within the scope of protection of the present invention.

[0021] Depend on Figure 1As shown, an N-type back-junction bifacial TOPCon cell includes an N-type silicon substrate 1 arranged in the middle, a silicon oxide layer 8 is provided on both the front and back surfaces of the N-type silicon substrate 1, a nitrogen-doped amorphous silicon film 2 is deposited on both the front and back surfaces of the N-type silicon substrate 1 with the silicon oxide layer 8, a boron-doped amorphous silicon film 3 is provided at the lower end of the nitrogen-doped amorphous silicon film 2 on the back, and a phosphorus-doped amorphous silicon film 5 is provided at the upper end of the nitrogen-doped amorphous silicon film 2 on the front, an aluminum oxide film 6 is deposited on the front surface of the N-type silicon substrate 1, a silicon nitride anti-reflection layer 4 is deposited on the outside of the boron-doped amorphous silicon film 3 and the phosphorus-doped amorphous silicon film 5, and an electrode 7 is provided on the silicon nitride anti-reflection layer 4.

[0022] Example 1 A method for preparing an N-type rear-junction double-sided TOPCon cell comprises the following steps: S1, select a thickness of about 170μm <100> Oriented N-type single crystal silicon wafers were used as substrates with a resistivity of 1~3Ω·cm. The substrate surface was cleaned and alkaline polished; S2. Soak in a hot nitric acid solution with a mass fraction of 68% at 110°C for 10 minutes to grow a thin silicon oxide layer of about 1.8 nm on both sides of the N-type silicon substrate; S3, transfer the N-type silicon substrate with a thin silicon oxide layer into a plasma-enhanced chemical vapor chamber, evacuate the chamber, preheat at 220°C, and then introduce silane (SiH4), phosphine (PH3), hydrogen (H2), and ammonia (NH3) as precursors to deposit a 15nm nitrogen-doped amorphous silicon film on both the front and back surfaces of the N-type silicon substrate; S4. Transfer the N-type silicon substrate with the nitrogen-doped amorphous silicon film into a plasma-enhanced chemical vapor chamber, evacuate the chamber, preheat at 220°C, and then introduce silane (SiH4), hydrogen (H2) and borane (B2H6) as precursors to deposit a 15nm boron-doped amorphous silicon film on the back side of the N-type silicon substrate. S5. The N-type silicon substrate with the nitrogen-doped amorphous silicon film is transferred to a plasma-enhanced chemical vapor chamber, evacuated, and preheated at 220°C. Silane (SiH4), phosphine (PH3), and hydrogen (H2) are then introduced as precursors to deposit a 15 nm phosphorus-doped amorphous silicon film on the front surface of the N-type silicon substrate. S6. Place the deposited N-type silicon substrate in a double-tube diffusion annealing furnace under a nitrogen atmosphere, keep the temperature at 960° C. for 120 minutes, and take out the N-type silicon substrate when the annealing furnace temperature drops below 300° C.; S7. Place the annealed N-type silicon substrate in a 2% hydrofluoric acid solution for 2 minutes, then soak it in a 68% nitric acid solution for 30 seconds, then soak it in deionized water twice, then change to a hydrofluoric acid solution and soak it in deionized water twice again, repeating ten cycles until the back surface is hydrophobic. S8, placing the N-type silicon substrate after etching the source layer and drying it in an atomic layer deposition chamber, depositing an aluminum oxide film layer on the front side, with a thickness of 15 nm, and then placing the N-type silicon substrate in a tube furnace with a nitrogen atmosphere, and annealing at 450° C. for 30 minutes to activate hydrogen passivation; S9. Using silane (SiH4) and ammonia (NH3) as reaction gases, a 70nm silicon nitride anti-reflection layer was deposited on the back and front of the N-type silicon substrate after the aluminum oxide film was deposited using plasma-enhanced chemical vapor deposition. The chamber temperature was set to 450°C and the deposition power was 6W. The substrate was then annealed in a nitrogen-hydrogen mixed atmosphere at 400°C for 30 minutes to improve the passivation effect of the silicon nitride anti-reflection layer. S10. Screen printing, sintering, and test sorting are performed on the N-type silicon substrate that has completed the deposition process. The sintering temperature is 750°C to prepare an N-type rear-junction double-sided TOPCon battery.

[0023] Example 2 A method for preparing an N-type rear-junction double-sided TOPCon cell comprises the following steps: S1, select a thickness of about 170μm <100> Oriented N-type single crystal silicon wafers were used as substrates with a resistivity of 1~3Ω·cm. The substrate surface was cleaned and alkaline polished; S2. Soak in a hot nitric acid solution with a mass fraction of 68% at 110°C for 10 minutes to grow a thin silicon oxide layer of about 1.8 nm on both sides of the N-type silicon substrate; S3, transfer the N-type silicon substrate with a thin silicon oxide layer into a plasma enhanced chemical vapor chamber, evacuate the chamber, preheat at 220°C, and then introduce silane (SiH4), phosphine (PH3), hydrogen (H2), and ammonia (NH3) as precursors to deposit a 20nm nitrogen-doped amorphous silicon film on both the front and back surfaces of the N-type silicon substrate; S4. Transfer the N-type silicon substrate with the nitrogen-doped amorphous silicon film into a plasma-enhanced chemical vapor chamber, evacuate the chamber, preheat at 220°C, and then introduce silane (SiH4), hydrogen (H2) and borane (B2H6) as precursors to deposit a 10 nm boron-doped amorphous silicon film on the back side of the N-type silicon substrate. S5. Transfer the N-type silicon substrate with the nitrogen-doped amorphous silicon film into a plasma-enhanced chemical vapor chamber, evacuate the chamber, preheat at 220°C, and then introduce silane (SiH4), phosphine (PH3) and hydrogen (H2) as precursors to deposit a 10 nm phosphorus-doped amorphous silicon film on the front surface of the N-type silicon substrate. S6. Place the deposited N-type silicon substrate in a double-tube diffusion annealing furnace under a nitrogen atmosphere, keep the temperature at 960° C. for 120 minutes, and take out the N-type silicon substrate when the annealing furnace temperature drops below 300° C.; S7. Place the annealed N-type silicon substrate in a 2% hydrofluoric acid solution for 2 minutes, then soak it in a 68% nitric acid solution for 30 seconds, then soak it in deionized water twice, then change to a hydrofluoric acid solution and soak it in deionized water twice again, repeating ten cycles until the back surface is hydrophobic. S8, placing the N-type silicon substrate after etching the source layer and drying it in an atomic layer deposition chamber, depositing an aluminum oxide film layer on the front side, with a thickness of 15 nm, and then placing the N-type silicon substrate in a tube furnace with a nitrogen atmosphere, and annealing at 450° C. for 30 minutes to activate hydrogen passivation; S9. Using silane (SiH4) and ammonia (NH3) as reaction gases, a 65nm silicon nitride anti-reflection layer was deposited on the back and front of the N-type silicon substrate after the aluminum oxide film was deposited using plasma-enhanced chemical vapor deposition. The chamber temperature was set to 450°C and the deposition power was 6W. The substrate was then annealed in a nitrogen-hydrogen mixed atmosphere at 400°C for 30 minutes to improve the passivation effect of the silicon nitride anti-reflection layer. S10. Screen printing, sintering, and test sorting are performed on the N-type silicon substrate that has completed the deposition process. The sintering temperature is 750°C to prepare an N-type rear-junction double-sided TOPCon battery.

[0024] Example 3 A method for preparing an N-type rear-junction double-sided TOPCon cell comprises the following steps: S1, select a thickness of about 170μm <100> Oriented N-type single crystal silicon wafers were used as substrates with a resistivity of 1~3Ω·cm. The substrate surface was cleaned and alkaline polished; S2. Soak in a hot nitric acid solution with a mass fraction of 68% at 110°C for 10 minutes to grow a thin silicon oxide layer of about 1.8 nm on both sides of the N-type silicon substrate; S3, transfer the N-type silicon substrate with a thin silicon oxide layer into a plasma-enhanced chemical vapor chamber, evacuate the chamber, preheat at 220°C, and then introduce silane (SiH4), phosphine (PH3), hydrogen (H2), and ammonia (NH3) as precursors to deposit a 10nm nitrogen-doped amorphous silicon film on both the front and back surfaces of the N-type silicon substrate; S4. Transfer the N-type silicon substrate with the nitrogen-doped amorphous silicon film into a plasma-enhanced chemical vapor chamber, evacuate the chamber, preheat at 220°C, and then introduce silane (SiH4), hydrogen (H2) and borane (B2H6) as precursors to deposit a 20nm boron-doped amorphous silicon film on the back side of the N-type silicon substrate. S5. Transfer the N-type silicon substrate with the nitrogen-doped amorphous silicon film into a plasma-enhanced chemical vapor chamber, evacuate the chamber, preheat at 220°C, and then introduce silane (SiH4), phosphine (PH3) and hydrogen (H2) as precursors to deposit a 20nm phosphorus-doped amorphous silicon film on the front surface of the N-type silicon substrate. S6. Place the deposited N-type silicon substrate in a double-tube diffusion annealing furnace under a nitrogen atmosphere, keep the temperature at 960° C. for 120 minutes, and take out the N-type silicon substrate when the annealing furnace temperature drops below 300° C.; S7. Place the annealed N-type silicon substrate in a 2% hydrofluoric acid solution for 2 minutes, then soak it in a 68% nitric acid solution for 30 seconds, then soak it in deionized water twice, then change to a hydrofluoric acid solution and soak it in deionized water twice again, repeating ten cycles until the back surface is hydrophobic. S8, placing the N-type silicon substrate after etching the source layer and drying it in an atomic layer deposition chamber, depositing an aluminum oxide film layer on the front side, with a thickness of 15 nm, and then placing the N-type silicon substrate in a tube furnace with a nitrogen atmosphere, and annealing at 450° C. for 30 minutes to activate hydrogen passivation; S9. Using silane (SiH4) and ammonia (NH3) as reaction gases, a 65nm silicon nitride anti-reflection layer was deposited on the back and front of the N-type silicon substrate after the aluminum oxide film was deposited using plasma-enhanced chemical vapor deposition. The chamber temperature was set to 450°C and the deposition power was 6W. The substrate was then annealed in a nitrogen-hydrogen mixed atmosphere at 400°C for 30 minutes to improve the passivation effect of the silicon nitride anti-reflection layer. S10. Screen printing, sintering, and test sorting are performed on the N-type silicon substrate that has completed the deposition process. The sintering temperature is 750°C to prepare an N-type rear-junction double-sided TOPCon battery.

[0025] Comparative Example 1 A method for preparing an N-type rear-junction double-sided TOPCon cell comprises the following steps: S1, select a thickness of about 170μm <100> Oriented N-type single crystal silicon wafers were used as substrates with a resistivity of 1~3Ω·cm. The substrate surface was cleaned and alkaline polished; S2. Soak in a hot nitric acid solution with a mass fraction of 68% at 110°C for 10 minutes to grow a thin silicon oxide layer of about 1.8 nm on both sides of the N-type silicon substrate; S3. Transfer the N-type silicon substrate with a thin silicon oxide layer into a plasma-enhanced chemical vapor chamber, evacuate the chamber, preheat it to 220°C, and then introduce silane (SiH4), hydrogen (H2), borane (B2H6) and nitrous oxide (N2O) as precursors to deposit a 15nm boron-doped amorphous silicon film on the back side of the N-type silicon substrate. S4. Transfer the N-type silicon substrate with the nitrogen-doped amorphous silicon film into a plasma-enhanced chemical vapor chamber, evacuate the chamber, preheat at 220°C, and then introduce silane (SiH4), phosphine (PH3), hydrogen (H2) and ammonia (NH3) as precursors to deposit a 15 nm phosphorus-doped amorphous silicon film on the front surface of the N-type silicon substrate. S5, placing the deposited N-type silicon substrate in a double-tube diffusion annealing furnace under a nitrogen atmosphere, keeping the temperature at 960° C. for 120 minutes, and taking out the N-type silicon substrate when the annealing furnace temperature drops below 300° C.; S6. Place the annealed N-type silicon substrate in a 2% hydrofluoric acid solution for 2 minutes, then soak it in a 68% nitric acid solution for 30 seconds, then soak it in deionized water twice, then change to a hydrofluoric acid solution and soak it in deionized water twice again, repeating ten cycles until the back surface is hydrophobic. S7, placing the N-type silicon substrate after etching the source layer and drying it in an atomic layer deposition chamber, and depositing an aluminum oxide film layer on the front side. The aluminum oxide layer has a thickness of 15 nm. Then, the N-type silicon substrate is placed in a tube furnace in a nitrogen atmosphere and annealed at 450° C. for 30 minutes to activate hydrogen passivation. S8. Using silane (SiH4) and ammonia (NH3) as reaction gases, a 70nm silicon nitride anti-reflection layer was deposited on the back and front sides of the N-type silicon substrate after the aluminum oxide film was deposited using plasma-enhanced chemical vapor deposition. The chamber temperature was set to 450°C and the deposition power was 6W. The substrate was then annealed in a nitrogen-hydrogen mixed atmosphere at 400°C for 30 minutes to enhance the passivation effect of the silicon nitride anti-reflection layer. S9. The N-type silicon substrate that has completed the deposition process is screen-printed, sintered, and tested and sorted at a sintering temperature of 750°C to prepare an N-type rear-junction double-sided TOPCon cell.

[0026] Comparative Example 2 A method for preparing an N-type rear-junction double-sided TOPCon cell comprises the following steps: S1, select a thickness of about 170μm <100> Oriented N-type single crystal silicon wafers were used as substrates with a resistivity of 1~3Ω·cm. The substrate surface was cleaned and alkaline polished; S2. A 1.8 nm tunneling oxide layer and a 30 nm polysilicon layer are sequentially deposited on the back side of the alkali-polished N-type silicon substrate using a low-pressure chemical vapor deposition furnace. The deposition temperature is 550° C., the deposition time is 120 min, the oxygen flow rate is 30,000 sccm, the SiH4 flow rate is 1,000 sccm, and the polysilicon layer is subjected to high-temperature boron diffusion to form a boron-doped polysilicon layer and a BSG protective layer. The diffusion source is boron trichloride. The driving temperature is 880° C., the driving time is 20 min, the oxidation temperature is 1,020° C., and the oxidation time is 30 min. S3, using a 30% hydrofluoric acid solution and a 5% sodium hydroxide solution to remove the BSG protective layer and the polysilicon layer on the front side of the boron-diffused N-type silicon substrate, and texturing the front side of the N-type silicon substrate; S4. Depositing a 1.8nm tunneling oxide layer and a 30nm polysilicon layer on the front surface of the textured N-type silicon substrate in sequence, and subjecting the polysilicon to high-temperature diffusion of phosphorus atoms to form a phosphorus-doped polysilicon layer and a PSG protective layer. The diffusion source is phosphorus oxychloride, the source flow rate is 1400sccm, the source flow time is 30min, the driving temperature is 880°C, and the driving time is 30min. S5, removing the PSG protective layer on the non-gate line printing area of the phosphorus-doped polysilicon layer by laser etching, and then removing the PSG protective layer and polysilicon layer on the back side and the excess phosphorus-doped polysilicon layer in the non-gate line area on the front side by hydrofluoric acid solution and sodium hydroxide solution respectively, and then removing the back side oxidized BSG protective layer by hydrofluoric acid; S6, depositing an aluminum oxide film with a thickness of 15 nm on the front surface of the N-type silicon substrate by atomic layer deposition; S7. Using silane (SiH4) and ammonia (NH3) as reaction gases, a 70nm silicon nitride anti-reflection layer was deposited on the back and front of the N-type silicon substrate after the aluminum oxide film was deposited using plasma-enhanced chemical vapor deposition. The chamber temperature was set to 450°C and the deposition power was 6W. The substrate was then annealed in a nitrogen-hydrogen mixed atmosphere at 400°C for 30 minutes to improve the passivation effect of the silicon nitride anti-reflection layer. S8. Screen printing, sintering and test sorting are performed on the N-type silicon substrate that has completed the deposition process. The sintering temperature is 750°C to prepare an N-type rear-junction double-sided TOPCon battery.

[0027] Performance testing The performance of the N-type back-junction double-sided TOPCon cells prepared in Examples 1-3 and Comparative Examples 1-2 was tested: the passivation performance was tested using a minority carrier lifetime tester, and the passivation indicators such as iVoc, J0,s and τeff of the test samples were tested. iVoc represents the maximum energy difference between electrons and holes in the solar cell, that is, the highest open-circuit voltage that the final solar cell device can reach. J0,s represents the current intensity generated when carriers recombine in some defect states. τeff represents the time required for the minority carrier concentration to drop to the initial concentration 1 / e under non-equilibrium state. Therefore, higher iVoc and τeff represent better passivation performance. At the same time, the smaller the corresponding J0,s, the better the passivation performance. The photoelectric conversion efficiency was measured using a solar simulator of model SS-F5-3A, which simulated the spectrum of AM1.5 with a total irradiance of 100mW / cm 2 , measure the battery's illumination IV curve, and thus obtain the battery's open circuit voltage (iVOC), short circuit current (Jsc) and fill factor (FF), and then obtain its photoelectric conversion efficiency. During the test, the temperature is basically maintained at 25°C, and the four-wire method is used for testing. The calculation formula for the battery's photoelectric conversion efficiency is: Where, P inis the incident light power per unit area, that is, the total irradiance, and the data results are shown in Table 1.

[0028]

[0029] The data in Table 1 demonstrate that the N-type rear-junction bifacial TOPCon cells prepared in Examples 1-3 of the present invention exhibit excellent passivation performance and achieve high efficiencies exceeding 25%. In Comparative Example 1, no nitrogen-doped amorphous silicon film was deposited, and nitrous oxide (N2O) was introduced as a precursor to the boron-doped amorphous silicon film, while ammonia (NH3) was introduced as a precursor to the phosphorus-doped amorphous silicon film. In Comparative Example 2, no nitrogen-doped amorphous silicon film was deposited, and a tunneling oxide layer and a polysilicon layer were sequentially deposited on the front and back surfaces of the N-type silicon substrate using low-pressure chemical vapor deposition. The passivation performance and photoelectric conversion efficiency of Comparative Examples 1-2 were lower than those of Examples 1-3.

[0030] Throughout this specification, references to terms such as "one embodiment," "example," or "specific example" indicate that the specific features, structures, materials, or characteristics described in conjunction with that embodiment or example are included in at least one embodiment or example of the present invention. In this specification, schematic representations of these terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

[0031] The basic principles, main features, and advantages of the present invention are shown and described above. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The above embodiments and descriptions are merely illustrative of the principles of the present invention. Various changes and modifications may be made to the present invention without departing from the spirit and scope of the present invention, and such changes and modifications fall within the scope of the invention as claimed.

Claims

1. An N-type back-junction double-sided TOPCon battery, characterized in that: The invention comprises an N-type silicon substrate arranged in the middle, wherein silicon oxide layers are provided on both the front and back surfaces of the N-type silicon substrate, nitrogen-doped amorphous silicon films are deposited on both the front and back surfaces of the N-type silicon substrate with the silicon oxide layer, a boron-doped amorphous silicon film is provided at the lower end of the nitrogen-doped amorphous silicon film on the back surface, and a phosphorus-doped amorphous silicon film is provided at the upper end of the nitrogen-doped amorphous silicon film on the front surface, an aluminum oxide film is deposited on the front surface of the N-type silicon substrate, silicon nitride anti-reflection layers are deposited on the outside of the boron-doped amorphous silicon film and the phosphorus-doped amorphous silicon film, and electrodes are provided on the silicon nitride anti-reflection layers.

2. The N-type back-junction double-sided TOPCon cell according to claim 1, characterized in that: The thickness of the N-type silicon substrate is 50-200 μm, and the resistivity is 0.1-10 Ω·cm.

3. A method for preparing an N-type back-junction double-sided TOPCon cell according to any one of claims 1 to 2, characterized in that: The following steps are involved: S1. Select N-type silicon as the substrate and perform cleaning and alkali polishing on the substrate surface; S2, growing a thin silicon oxide layer on both sides of the N-type silicon substrate after alkali polishing; S3, depositing nitrogen-doped amorphous silicon thin films on both the front and back surfaces of the N-type silicon substrate with a thin silicon oxide layer; S4, depositing a boron-doped amorphous silicon film on the back side of the N-type silicon substrate with the nitrogen-doped amorphous silicon film; S5, depositing a phosphorus-doped amorphous silicon film on the front surface of the N-type silicon substrate with the nitrogen-doped amorphous silicon film; S6, placing the deposited N-type silicon substrate in a double-tube diffusion annealing furnace under a nitrogen atmosphere for annealing; S7, placing the annealed N-type silicon substrate in a hydrofluoric acid solution for 2-3 minutes, then soaking it in a nitric acid solution for 20-30 seconds, then soaking it in deionized water twice, then changing to a hydrofluoric acid solution and soaking it for 20-30 seconds, then soaking it in deionized water twice again, and repeating this operation until the back surface is hydrophobic; S8, placing the N-type silicon substrate after the source layer is etched and dried in an atomic layer deposition chamber to deposit an aluminum oxide film on the front side, and then annealing the N-type silicon substrate in a nitrogen atmosphere tube furnace to activate hydrogen passivation; S9, using plasma enhanced chemical vapor deposition to deposit a silicon nitride anti-reflection layer, and then annealing in a nitrogen-hydrogen mixed atmosphere at 400° C. to enhance the passivation effect of the silicon nitride anti-reflection layer; S10. Screen printing, sintering, testing and sorting are performed on the N-type silicon substrate that has completed the deposition process to prepare an N-type rear-junction double-sided TOPCon battery.

4. The method for preparing an N-type back-junction double-sided TOPCon cell according to claim 3, characterized in that: The thickness of the thin silicon oxide layer in step S2 is 1-2 nm.

5. The method for preparing an N-type rear-junction double-sided TOPCon cell according to claim 3, characterized in that: Plasma enhanced chemical vapor deposition is used in steps S3, S4 and S5. Silane, phosphine, hydrogen and ammonia are used as precursors in step S3, silane, hydrogen and borane are used as precursors in step S4, and silane, phosphine and hydrogen are used as precursors in step S5.

6. The method for preparing an N-type rear-junction double-sided TOPCon cell according to claim 3, characterized in that: The thickness of the nitrogen-doped amorphous silicon film in step S3 is 10-20 nm; the thickness of the boron-doped amorphous silicon film in step S4 is 10-20 nm; and the thickness of the phosphorus-doped amorphous silicon film in step S5 is 10-20 nm.

7. The method for preparing an N-type rear-junction double-sided TOPCon cell according to claim 3, characterized in that: The annealing process parameters in step S6 are: keeping the temperature at 920-960° C. for 120-150 minutes, and taking out the N-type silicon substrate when the annealing furnace temperature drops below 300° C.

8. The method for preparing an N-type rear-junction double-sided TOPCon cell according to claim 3, characterized in that: The concentration of the hydrofluoric acid solution in step S7 is 2-5%, and the concentration of the nitric acid solution is 65-70%.

9. The method for preparing an N-type rear-junction double-sided TOPCon cell according to claim 3, characterized in that: The thickness of the aluminum oxide film layer in step S8 is 10-15 nm.

10. The method for preparing an N-type rear-junction double-sided TOPCon cell according to claim 3, characterized in that: The thickness of the silicon nitride anti-reflection layer in step S9 is 65-70 nm.

Images