Light emitting element array, display device including same, and method of manufacturing same

Abstract

The invention relates to a light emitting element array, a display device including the light emitting element array, and a method of manufacturing the light emitting element array. The light emitting element array includes light emitting elements on the substrate that emit light of different colors. Each light emitting element includes: a first semiconductor layer; a second semiconductor layer on the first semiconductor layer, doped to have the first conductivity type and containing indium; a light emitting layer on the second semiconductor layer and including indium; and a third semiconductor layer on the light emitting layer and doped to have the second conductivity type. The indium content of the light-emitting layer of a first light-emitting element among the light-emitting elements is higher than the indium content of the light-emitting layer of a second light-emitting element among the light-emitting elements. The second semiconductor layer of the first light emitting element includes first layers including indium and second layers alternately stacked with the first layers. The second semiconductor layer of the second light-emitting element is a single layer containing indium.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2024-0018460 filed on February 6, 2024, in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0003] Embodiments of the present disclosure generally relate to a light emitting element array, a display device including the light emitting element array, and a method of manufacturing the light emitting element array. Background Art

[0004] Light-emitting elements are widely used as light sources for various electronic devices including display devices. For example, light-emitting elements are used as light sources for various electronic devices including virtual reality (VR) devices and augmented reality (AR) devices, as well as portable electronic devices and televisions.

[0005] The background technology provided herein is for the purpose of generally presenting the context of the present disclosure. The work of the inventors of the present invention described to some extent in this background technology section, as well as aspects of the description that may not otherwise be identified as prior art at the time of filing, are neither explicitly nor implicitly admitted to be prior art with respect to the present disclosure. Summary of the Invention

[0006] Some aspects can provide a light emitting element array that includes light emitting elements that emit light of different colors.

[0007] Some aspects can provide a display device including a light emitting element array including light emitting elements that emit light of different colors.

[0008] Some aspects can provide a method of fabricating a light emitting element array including light emitting elements that emit light of different colors.

[0009] Additional aspects will be set forth in the detailed description which follows, and in part will be apparent from the disclosure, or may be learned by practice of the disclosed embodiments and / or claimed subject matter.

[0010] According to some embodiments, a light-emitting element array includes a substrate and light-emitting elements disposed on the substrate. The light-emitting elements include: a first light-emitting element configured to emit light of a first color; and a second light-emitting element configured to emit light of a second color different from the first color. Each of the light-emitting elements includes a first semiconductor layer, a second semiconductor layer, a light-emitting layer, and a third semiconductor layer. The second semiconductor layer is disposed on the first semiconductor layer, is doped to have a first conductivity type, and contains indium. The light-emitting layer is disposed on the second semiconductor layer and contains indium. The third semiconductor layer is disposed on the light-emitting layer and is doped to have a second conductivity type. The indium content of the light-emitting layer of the first light-emitting element is higher than the indium content of the light-emitting layer of the second light-emitting element. The second semiconductor layer of the first light-emitting element is a multilayer structure. The multilayer structure includes a first layer containing indium and a second layer stacked alternately with the first layer. The second semiconductor layer of the second light-emitting element is a single-layer structure containing indium.

[0011] In an embodiment, each of the first layers of the first light emitting elements may be an InGaN layer containing a dopant of the first conductivity type, and each of the second layers of the first light emitting elements may be a GaN layer.

[0012] In an embodiment, the second semiconductor layer of the second light emitting element may be a single InGaN layer including a dopant of the first conductivity type.

[0013] In an embodiment, a thickness of each of the first layers of the first light emitting element may be greater than a thickness of each of the second layers of the first light emitting element.

[0014] In an embodiment, the thickness of each of the first layers of the first light emitting element may be in a range of about 10 nm to about 20 nm.

[0015] In an embodiment, the thickness of each of the second layers of the first light emitting element may be less than or equal to about 5 nm and greater than 0 nm.

[0016] In an embodiment, an indium content of at least one of the first layers of the first light emitting element is different from an indium content of at least one other of the first layers of the first light emitting element.

[0017] In an embodiment, the second semiconductor layer of the first light-emitting element may include a first stack, a second stack, a third stack, and a fourth stack. The first stack may include one or more first pairs of layers disposed on the first semiconductor layer. Each of the one or more first pairs of layers may include a first layer among the first layers and a second layer among the second layers. The second stack may include one or more second pairs of layers disposed on the first stack. Each of the one or more second pairs of layers may include a first layer among the first layers and a second layer among the second layers. The third stack may include one or more third pairs of layers disposed on the second stack. Each of the one or more third pairs of layers may include a first layer among the first layers and a second layer among the second layers. The fourth stack may include one or more fourth pairs of layers disposed on the third stack. Each of the one or more fourth pairs of layers may include a first layer among the first layers and a second layer among the second layers. The indium content of the first layer of the second stack and the indium content of the first layer of the fourth stack may be at least about 5% lower than the indium content of the first layer of the first stack and the indium content of the first layer of the third stack.

[0018] In an embodiment, the number of one or more first pairs of layers in the first stack and the number of one or more third pairs of layers in the third stack may both be greater than the number of one or more second pairs of layers in the second stack and the number of one or more fourth pairs of layers in the fourth stack.

[0019] In an embodiment, the light emitting layer of the first light emitting element may include a quantum well layer including an indium content ranging from about 30% to about 40%, and the indium content of at least one of the first layers of the first light emitting element may be less than or equal to about 30% and greater than 0%.

[0020] In an embodiment, the peak wavelength of the light of the second color may be shorter than the peak wavelength of the light of the first color.

[0021] In an embodiment, the light-emitting element may further include a third light-emitting element configured to emit light of a third color. The peak wavelength of the third color light may be shorter than the peak wavelength of the second color light. The second semiconductor layer of the third light-emitting element may be a single-layer structure including indium.

[0022] In an embodiment, the light emitting element array may further include an insulating layer disposed on a surface of the substrate. At least a portion of the insulating layer may be disposed between the first light emitting element and the second light emitting element in a view perpendicular to the surface.

[0023] In an embodiment, the insulating layer may overlap at least a portion of each of the light emitting elements. Each of the portions of the light emitting elements may include a peripheral side surface of a corresponding light emitting element among the light emitting elements.

[0024] In an embodiment, a thickness of the insulating layer overlapping at least a portion of the first light emitting element may be different from a thickness of the insulating layer overlapping at least a portion of the second light emitting element.

[0025] In an embodiment, the light emitting element array may further include a reflective layer disposed on the insulating layer, and the reflective layer may overlap with the outer side surface of the light emitting element.

[0026] In an embodiment, at least portions of the first semiconductor layers of the light emitting elements may be integrated with each other.

[0027] According to some embodiments, a display device includes: a first pixel including a first light-emitting element configured to emit light of a first color; and a second pixel including a second light-emitting element configured to emit light of a second color. Each of the first light-emitting element and the second light-emitting element may include a first semiconductor layer, a second semiconductor layer, a light-emitting layer, and a third semiconductor layer. The second semiconductor layer is disposed on a surface of the first semiconductor layer, is doped to have a first conductivity type, and contains indium. The light-emitting layer is disposed on a surface of the second semiconductor layer and contains indium. The third semiconductor layer is disposed on a surface of the light-emitting layer and is doped to have a second conductivity type. The indium content of the light-emitting layer of the first light-emitting element is higher than the indium content of the light-emitting layer of the second light-emitting element. The second semiconductor layer of the first light-emitting element includes a first layer containing indium and a second layer alternately stacked with the first layer. The second semiconductor layer of the second light-emitting element is a single-layer structure containing indium.

[0028] According to some embodiments, a method for manufacturing a light-emitting element array may include: forming a first semiconductor layer on a surface of a substrate; and forming a first mask layer on the first semiconductor layer, the first mask layer defining a first opening that exposes a first region of the first semiconductor layer, the first mask layer overlapping both a second region and a third region of the first semiconductor layer in a direction perpendicular to the surface. The method further includes: sequentially forming a second semiconductor layer doped with a first conductivity type and containing indium, a light-emitting layer containing indium, and a third semiconductor layer doped with a second conductivity type on the first region. The method further includes: forming a second mask layer on the first mask layer, the second mask layer defining a second opening that exposes the second region. The second mask layer overlaps both the first region and the third region in the direction. The method further includes: sequentially forming the second semiconductor layer doped with the first conductivity type and containing indium, the light-emitting layer containing indium, and the third semiconductor layer doped with the second conductivity type on the second region. The method further includes: forming a third mask layer on the second mask layer, the third mask layer defining a third opening that exposes the third region. The third mask layer overlaps both the first region and the second region in the direction. The method further includes sequentially forming a second semiconductor layer doped with a first conductivity type and containing indium, a light-emitting layer containing indium, and a third semiconductor layer doped with a second conductivity type on the third region. The light-emitting layers formed on the first region, the second region, and the third region have different indium contents. The second semiconductor layer formed on the region of the first region, the second region, and the third region on which the light-emitting layer having the highest indium content is also formed has a multilayer structure. The multilayer structure includes first layers containing indium and second layers alternately stacked with the first layers.

[0029] In an embodiment, each of the second semiconductor layers on regions other than a region on which the light emitting layer having the highest indium content is formed among the first, second, and third regions may be formed in a single-layer structure.

[0030] According to some embodiments, a light-emitting element array may include a plurality of light-emitting elements, the plurality of light-emitting elements including a first light-emitting element and a second light-emitting element that emit light of different colors. In some embodiments, the indium content of the light-emitting layer of the first light-emitting element may be higher than the indium content of the light-emitting layer of the second light-emitting element, and the semiconductor layer disposed below the light-emitting layer of the first light-emitting element may be formed to have multiple layers containing indium. In some embodiments, the semiconductor layer disposed below the light-emitting layer of the second light-emitting element may be formed to have a single layer containing indium.

[0031] According to various embodiments, light-emitting elements that emit light of different colors from each other can be manufactured with relatively high quality on a substrate (e.g., a single substrate), and the quality of the first light-emitting element can be improved by injecting indium into the light-emitting layer of the first light-emitting element that contains a relatively high content of indium. Therefore, the manufacturing efficiency of the light-emitting element array and the display device including the light-emitting element array can be improved, and the manufacturing cost can be reduced. In addition, by distinguishing or optimizing the structure and / or material of the light-emitting element according to the (multiple) emission wavelengths and / or indium content of the light-emitting layer of the light-emitting element, the quality of the light-emitting element array and the display device including the light-emitting element array can be improved.

[0032] The foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the claimed subject matter. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Various embodiments disclosed herein are illustrated by way of example, and not by way of limitation, in the accompanying figures in which like reference numerals and / or characters refer to similar elements.

[0034] Figure 1 is a plan view schematically showing a light emitting element array according to an embodiment.

[0035] Figure 2 is a plan view schematically showing a light emitting element array according to an embodiment.

[0036] Figure 3 is a perspective view schematically showing a part of a light emitting element array according to an embodiment.

[0037] Figure 4 is a cross-sectional view schematically showing a portion of a light emitting element array according to an embodiment.

[0038] Figure 5 is a cross-sectional view schematically showing a light emitting element array according to an embodiment.

[0039] Figure 6 is a cross-sectional view schematically showing a light emitting element array according to an embodiment.

[0040] Figure 7 It is schematically shown in more detail according to the embodiment Figure 5 A cross-sectional view of area A1.

[0041] Figure 8 It is schematically shown in more detail according to the embodiment Figure 5 A cross-sectional view of area A1.

[0042] Figure 9is a cross-sectional view schematically showing the second semiconductor layer of the first light-emitting element according to the embodiment.

[0043] Figure 10 It is schematically shown in more detail according to the embodiment Figure 5 A cross-sectional view of area A1.

[0044] Figure 11 It is schematically shown in more detail according to the embodiment Figure 5 A cross-sectional view of area A2.

[0045] Figures 12 to 25 2 is a cross-sectional view schematically showing a light emitting element array at various stages of manufacture according to an embodiment.

[0046] Figure 26 is a perspective view schematically showing a display device according to an embodiment.

[0047] Figure 27 is a schematic diagram showing an embodiment of the Figure 26 FIG. 1 is a plan view of an example of area A3.

[0048] Figure 28 is a cross-sectional view schematically showing a display panel according to an embodiment.

[0049] Figure 29 is a cross-sectional view schematically showing a display panel according to an embodiment.

[0050] Figure 30 is a cross-sectional view schematically showing a display panel according to an embodiment.

[0051] Figure 31 is a diagram schematically illustrating a virtual reality device including a display device according to an embodiment.

[0052] Figure 32 is a diagram schematically illustrating a smart device including a display device according to an embodiment.

[0053] Figure 33 A vehicle instrument panel and a central instrument panel including a display device according to an embodiment are schematically shown.

[0054] Figure 34 is a diagram schematically illustrating a transparent display device including a display device according to an embodiment. DETAILED DESCRIPTION

[0055] In the following description, for the purpose of illustration, many specific details are set forth to provide a thorough understanding of various embodiments or implementations. The terms "embodiment" and "implementation" may be used interchangeably to describe one or more non-limiting examples of the systems, devices, methods, etc. described herein. However, it is apparent that the various embodiments may be practiced without these specific details or with one or more equivalent arrangements. In other cases, known structures and devices are shown in block diagram form to avoid unnecessarily obscuring the various embodiments. In addition, the various embodiments may be different, but not necessarily exclusive. For example, the specific shape, configuration, and characteristics of the embodiment may be used or implemented in another embodiment without departing from the teachings of the present disclosure.

[0056] Unless otherwise noted, the illustrated embodiments are to be understood as exemplary features providing varying details of some embodiments. Therefore, unless otherwise noted, the various illustrated features, components, modules, layers, films, regions, aspects, structures, etc. (hereinafter, individually or collectively referred to as "elements" or "elements") may be combined, separated, interchanged, and / or rearranged in other ways without departing from the teachings of the present disclosure.

[0057] The use of cross hatching and / or shading in the drawings is generally intended to make the boundaries between adjacent elements clear. Therefore, unless otherwise specified, the presence or absence of cross hatching or shading is not intended to convey or indicate any preference or requirement for a particular material, material properties, size, ratio, commonality between illustrated elements and / or any other characteristics, attributes, properties, etc. of the elements. In addition, in the drawings, the sizes and relative sizes of the elements may be exaggerated for clarity and / or description purposes. Thus, the sizes and relative sizes of the corresponding elements are not necessarily limited to the sizes and relative sizes shown in the drawings. In the case where the exemplary embodiments can be implemented differently, the specific processing order can be performed differently from the described order. For example, two processes described in succession can be performed substantially simultaneously, or in an order opposite to the described order. In addition, the same figure marks and / or reference numerals represent the same elements.

[0058] When an element (such as a layer) is referred to as being “on”, “over”, “connected to” (or “connected with”) or “coupled to” (or “coupled with”) another element, it may be directly on, directly on, directly connected to (or directly connected with) or directly coupled to (or directly coupled with) another element, or there may be at least one intervening element. However, when an element is referred to as being “directly on”, “directly on”, “directly connected to” (or “directly connected with”) or “directly coupled to” (or “directly coupled with”) another element, there are no intervening elements. Other terms and / or phrases used to describe the relationship between elements, if used herein, should be interpreted in a similar manner, such as “between” versus “directly between”, “adjacent” versus “directly adjacent”, “on” versus “directly on”, “contacting” versus “directly in contact with”, “touching” versus “directly touching”, etc. Additionally, the term "connected" may refer to physical, electrical, and / or fluidic connections. To this end, for purposes of this disclosure, the phrase "fluidically connected" may be used for volumes, plenums, holes, openings, and the like that may be connected to one another directly or via one or more intervening components or volumes to form a fluid connection, similar to how the phrase "electrically connected" may be used for components that are connected to form an electrical connection.

[0059] For the purposes of this disclosure, the first axis extending along the first direction DR1, the second axis extending along the second direction DR2, and the third axis extending along the third direction DR3 are not limited to the three axes of a rectangular coordinate system (such as the x-axis, y-axis, and z-axis of a Cartesian coordinate system), and may be interpreted in a broader sense. For example, the first axis, the second axis, and the third axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other. In addition, if used herein, the phrases "at least one of X, Y... and Z" and "at least one selected from the group consisting of X, Y... and Z" may be interpreted as any combination of only X, only Y,..., only Z, or two or more of X, Y... and Z (such as, for example, XYZ, XY, YZ, and XZ). In addition, if used herein, the term "and / or" includes any and all combinations of one or more of the relevant listed items.

[0060] Although the terms "first", "second", "third" etc. can be used in this article to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish an element from another element. Therefore, without departing from the teachings of the present disclosure, the first element discussed below can be referred to as the second element. For this reason, the use of such identifiers (e.g., "first element") should not be understood as suggesting (implicitly or inherently) that another example (e.g., "second element") must exist.

[0061] Spatially relative terms such as "beneath," "below," "under," "lower," "above," "upper," "over," "higher," "side" (e.g., as in "sidewall"), etc., may be used herein for descriptive purposes, and thereby to describe the spatial relationship of one element to at least one other element as shown in the accompanying drawings. Spatially relative terms are intended to encompass different orientations of the device in use, operation, and / or manufacture in addition to the orientation depicted in the accompanying drawings. For example, if the device in the accompanying drawings is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" or "above" the other elements or features. Thus, the term "below" can encompass both the above and below orientations. Furthermore, the device may be otherwise oriented (e.g., rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein interpreted accordingly.

[0062] The terms used herein are for the purpose of describing some embodiments, rather than being intended to limit. Unless the context clearly indicates otherwise, as used herein, the singular forms "one", "an" and "the" are intended to also include plural forms. It will be understood that the phrases "for each <item> in one or more <items>", "each <item> in one or more <items>", etc., if used in this article, include both single item groups and multinomial groups, i.e., the phrase "for ... each" is used in programming languages to represent the meaning of each item in any group of the quoted items. For example, if the group of the quoted items is a single item, then "each" will only refer to the single item (although the dictionary definition of "each" usually limits the term to represent "each of two or more things"), and will not imply that there must be at least two of these items. Similarly, the term "set" or "subset" itself should not be considered as necessarily comprising multiple items, but will be understood that a set or subset can only include one member or multiple members (unless the context indicates otherwise).

[0063] The terms "comprising," "including," "including," "has," "have," and / or "having," when used in this specification, indicate the presence of the stated features, integers, steps, operations, elements, parts, and / or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, parts, and / or groups thereof. It should also be noted that, as used herein, the terms "substantially," "about," "approximately," and other similar terms are used as terms of approximation and not as terms of degree, and are therefore used to allow for the inherent deviations in measurements, calculations, and / or provided values that one of ordinary skill in the art would recognize. Thus, if used herein, and unless otherwise indicated, the term "substantially" can mean within 5% of a reference value. For example, substantially perpendicular can mean within ±5% of parallel to the perpendicular. Furthermore, unless otherwise indicated, the term "between," if used herein in conjunction with a numerical range, will be understood to include the starting and ending values of the range. For example, between 1 and 5 will be understood to include the numbers 1, 2, 3, 4, and 5, rather than just the numbers 2, 3, and 4.

[0064] Various embodiments are described herein with reference to cross-sectional, isometric, perspective, orthographic, and / or exploded views, which are schematic depictions of idealized embodiments and / or intermediate structures. Thus, deviations from the illustrated shapes resulting from, for example, manufacturing techniques and / or tolerances, are to be expected. Thus, the embodiments disclosed herein should not be construed as limited to the particular illustrated shapes of regions, but are to include deviations in shapes resulting from, for example, manufacturing. To this end, the regions illustrated in the figures may be schematic in nature, and the shapes of these regions may not reflect the actual shapes of regions of a device and, thus, are not intended to be limiting.

[0065] According to the convention in the art, for functional blocks, units and / or modules, some embodiments can be described and shown in the accompanying drawings. It will be understood by those skilled in the art that these blocks, units and / or modules are physically implemented by electronic (or optical) circuits (such as, logic circuits, discrete components, microprocessors, hard-wired circuits, memory elements, wiring connections, etc.) that can be formed using semiconductor-based preparation technology or other manufacturing technology. When blocks, units and / or modules are implemented by microprocessors or other similar hardware, software (e.g., microcode) can be used to program and control the blocks, units and / or modules to perform the various functions discussed herein, and optionally, they can be driven by firmware and / or software. It is also considered that each block, unit and / or module can be implemented by dedicated hardware, or implemented as a combination of dedicated hardware that performs some functions and a processor that performs other functions (e.g., one or more programmed microprocessors and related circuits). In addition, without departing from the scope of this disclosure, each block, unit and / or module of some embodiments can be physically divided into two or more interactive and discrete blocks, units and / or modules. Furthermore, the blocks, units and / or modules of some embodiments may be physically combined into more complex blocks, units and / or modules without departing from the scope of the present disclosure.

[0066] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present disclosure belongs. Terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and should not be interpreted in an idealized or overly formal sense unless expressly defined as such herein.

[0067] Hereinafter, various embodiments will be described with reference to the accompanying drawings.

[0068] Figure 1 is a plan view showing a light emitting element array ARR according to the embodiment. Figure 2 : is a plan view showing a light emitting element array ARR according to an embodiment. For example, Figure 1 and Figure 2 Different embodiments are shown regarding the arrangement of light emitting elements, such as light emitting elements LE.

[0069] Figure 1 and Figure 2A first direction DR1, a second direction DR2, and a third direction DR3 are shown, which are perpendicular to each other. For example, the first direction DR1 and the second direction DR2 are perpendicular to each other and may define a plane parallel (or substantially parallel) to the bottom surface of the light-emitting element LE or the substrate SUB. The third direction DR3 may be perpendicular to both the first direction DR1 and the second direction DR2. For example, the third direction DR3 may be a height direction or a thickness direction of the substrate SUB or the light-emitting element LE.

[0070] refer to Figure 1 and Figure 2 , the light emitting element array ARR may include a substrate SUB and light emitting elements (eg, light emitting elements LE) disposed on the substrate SUB. Hereinafter, the light emitting elements may be collectively or individually referred to as (a plurality of) light emitting elements LE. Figure 1 and Figure 2 , the substrate SUB is shown to have a rectangular planar shape in the third direction DR3, but the shape of the substrate SUB may be changed variously. Hereinafter, the planar shape of an element will refer to the shape of the element in the third direction DR3. In some implementations, the substrate SUB may have another polygonal planar shape, a circular planar shape, an oval planar shape, an elliptical planar shape, a free-form planar shape, or another planar shape.

[0071] In an embodiment, the light emitting element array ARR may include a plurality of light emitting elements LE that emit light of different colors. For example, the light emitting element LE may include a first light emitting element LE1 that emits light of a first color, a second light emitting element LE2 that emits light of a second color, and a third light emitting element LE3 that emits light of a third color. In an embodiment, the first color, the second color, and the third color may be red light, green light, and blue light, respectively, but are not limited to these examples. In some embodiments, the light emitting element array ARR may include a plurality of first light emitting elements LE1, a plurality of second light emitting elements LE2, and a plurality of third light emitting elements LE3.

[0072] In an embodiment, the light emitting element LE may have a hexagonal planar shape, but does not necessarily have to have such a shape. For example, the light emitting element LE may have another polygonal planar shape, a circular planar shape, an oval planar shape, an elliptical planar shape, a free-form planar shape, or another planar shape.

[0073] The light emitting elements LE may be arranged in various shapes or patterns. Figure 1As shown in FIG, in a row extending along a first direction DR1, one first light emitting element LE1, one second light emitting element LE2, and one third light emitting element LE3 may be arranged continuously or sequentially, and the first light emitting element LE1, the second light emitting element LE2, and the third light emitting element LE3 may constitute one (or one) light emitting element unit UNT capable of displaying light of various colors. The arrangement order of the first light emitting element LE1, the second light emitting element LE2, and the third light emitting element LE3 may vary depending on the embodiment.

[0074] In some embodiments, such as Figure 2 As shown in , at least two first light emitting elements LE1 may be arranged adjacent to each other along the first direction DR1 and / or the second direction DR2, and at least two first light emitting elements LE1 may constitute a first light emitting element group GR1 (or a first light emitting element group GR1). For example, each first light emitting element group GR1 may include at least two first light emitting elements LE1 arranged adjacent to each other. Similarly, each second light emitting element group GR2 may include at least two second light emitting elements LE2 arranged adjacent to each other, and each third light emitting element group GR3 may include at least two third light emitting elements LE3 arranged adjacent to each other. Figure 2 As shown in FIG, the first light-emitting element group GR1 includes seven first light-emitting elements LE1, the second light-emitting element group GR2 includes seven second light-emitting elements LE2, and the third light-emitting element group GR3 includes seven third light-emitting elements LE3, but the embodiment is not limited to this example. In some implementations, at least one of the first light-emitting element group GR1, the second light-emitting element group GR2, and the third light-emitting element group GR3 may include fewer than seven but more than two light-emitting elements LE capable of displaying the same color, or may include more than seven light-emitting elements LE capable of displaying the same color. To this end, at least one of the first light-emitting element group GR1, the second light-emitting element group GR2, and the third light-emitting element group GR3 may include a different number of light-emitting elements LE than at least one other group among the first light-emitting element group GR1, the second light-emitting element group GR2, and the third light-emitting element group GR3. In an embodiment, the first light-emitting element group GR1, the second light-emitting element group GR2, and the third light-emitting element group GR3, which are adjacent to each other, may constitute a light-emitting element unit UNT (or a light-emitting element unit UNT).

[0075] In some implementations, the type and / or arrangement structure of the light emitting elements LE provided in the light emitting element array ARR, or the type, number and / or arrangement structure of the light emitting elements LE constituting each light emitting element unit UNT may vary according to the embodiment.

[0076] Figure 3 is a perspective view schematically showing a part of the light emitting element array ARR according to the embodiment. Figure 4 : is a cross-sectional view schematically showing a portion of the light emitting element array ARR according to the embodiment. For example, Figure 3 and Figure 4 Shows the settings Figure 1 and Figure 2 A light emitting element LE (or a light emitting element LE) in the light emitting element array ARR and the periphery of the light emitting element LE. Figure 3 and Figure 4 The light emitting element LE shown may be Figure 1 and Figure 2 One of the first light emitting element LE1, the second light emitting element LE2 and the third light emitting element LE3.

[0077] refer to Figures 1 to 4 The light emitting element array ARR may include a light emitting element LE disposed in each light emitting element area LEA. In an embodiment, the light emitting element array ARR may further include a first insulating layer INS1 disposed on the substrate SUB.

[0078] In an embodiment, the substrate SUB may be a manufacturing substrate (or sacrificial substrate) for forming the light emitting element LE. For example, the light emitting element array ARR may include a manufacturing substrate, and the light emitting element LE arranged and / or formed on the manufacturing substrate. However, the embodiment is not limited to this example. For example, the light emitting element LE may be manufactured on a manufacturing substrate and separated from the manufacturing substrate to be placed on a transfer substrate or substrate of an electronic device (for example, a backplane substrate or other substrate of a display device). For example, the substrate SUB may be a transfer substrate or substrate of an electronic device. For example, the light emitting element array ARR may include a transfer substrate or substrate of an electronic device, and the light emitting element LE arranged on the transfer substrate or substrate of the electronic device. Hereinafter, an embodiment in which the substrate SUB is a manufacturing substrate for manufacturing the light emitting element LE will be described.

[0079] The substrate SUB may be a semiconductor substrate for forming the light emitting element LE. The substrate SUB may be a wafer or a manufacturing substrate suitable for epitaxial growth. For example, the light emitting element LE may be formed on the substrate SUB by epitaxial growth.

[0080] In an embodiment, the substrate SUB may be a semiconductor substrate including at least one of silicon (Si), sapphire, GaAs, SiC, GaN, and ZnO, or another material. The type or material of the substrate SUB is not particularly limited if epitaxial growth for manufacturing the light emitting element LE can be easily performed.

[0081] The first semiconductor layer SEM1 of the light emitting element LE may be disposed on the substrate SUB. The light emitting element array ARR may further include a buffer layer (eg, an undoped GaN layer) disposed between the substrate SUB and the first semiconductor layer SEM1.

[0082] In an embodiment, the light emitting elements LE are formed using the same substrate SUB, and portions of the light emitting elements LE may be integrally formed (or integrally formed with each other) in the form of a common layer. For example, at least a portion of the first semiconductor layer SEM1 of the light emitting element LE (e.g., the lower portion of the first semiconductor layer SEM1) may be integrally (or substantially integrally) formed on the substrate SUB in the form of a common layer. The light emitting elements LE may be electrically connected to each other through the first semiconductor layer SEM1. Another portion of the first semiconductor layer SEM1 (e.g., the seed layer SEM1A positioned at the upper portion of the first semiconductor layer SEM1) may be formed separately in each light emitting element area LEA and may be surrounded (or enclosed) by the first insulating layer INS1 (or a portion of the first insulating layer INS1) when viewed in the third direction DR3.

[0083] However, embodiments are not limited to the above examples. For example, the light-emitting element LE manufactured on the substrate SUB may be separated from the substrate SUB and transferred or bonded to another substrate or electronic device, so that a portion of the first semiconductor layer SEM1 (e.g., a lower portion formed as a common layer) or the entire (or substantially the entire) first semiconductor layer SEM1 including the seed layer SEM1A may be separated from the light-emitting element LE. In some implementations, the light-emitting element LE may not include the first semiconductor layer SEM1.

[0084] The first insulating layer INS1 may be disposed on a portion of the first semiconductor layer SEM1 or the substrate SUB and may have an opening corresponding to each light-emitting element area LEA. For example, in a view in a third direction DR3 from a plane defined by the first direction DR1 and the second direction DR2, the first insulating layer INS1 (or a portion of the first insulating layer INS1) may be disposed around the light-emitting element LE to surround (or enclose) each light-emitting element area LEA. In some implementations, at least a portion of the first insulating layer INS1 may be disposed between the light-emitting element areas LEA and may include an opening corresponding to the planar shape of the light-emitting element LE.

[0085] The first insulating layer INS1 may include at least one insulating material. For example, the insulating material(s) may be silicon oxide (SiO x ) (e.g., SiO2), silicon nitride (SiN x ) (e.g., Si3N4), aluminum oxide (Al x O y) (e.g., Al2O3), titanium oxide (Ti x O y ) (e.g., TiO2) and hafnium oxide (HfO x ), or other insulating materials. In an embodiment, the first insulating layer INS1 may include a material suitable for use as a mask in a process of forming the light-emitting element LE, but is not limited to this example. For example, the material of the first insulating layer INS1 suitable for use as a mask may be selected based on the etching selectivity, photosensitivity, bonding strength, etc. of the material associated with various etching conditions or parameters.

[0086] The light-emitting element LE may be disposed in each light-emitting element area LEA defined (or at least partially defined) by the opening of the first insulating layer INS1 (or the opening in the first insulating layer INS1). The light-emitting element LE may have various forms depending on the embodiment. The light-emitting element LE may include a side surface that is substantially perpendicular to the surface of the substrate SUB on which the light-emitting element LE is disposed, or that is inclined (or tilted) relative to the surface of the substrate SUB on which the light-emitting element LE is disposed. For example, in a view in a direction perpendicular to the third direction DR3, for example, the light-emitting element LE may have a hexagonal truncated pyramid shape, but the shape of the light-emitting element LE is not limited to this example.

[0087] In an embodiment, the light emitting element LE may be an inorganic light emitting element made of at least one inorganic material. For example, the light emitting element LE may be an inorganic light emitting diode made of (or including) a nitride-based semiconductor material (e.g., at least one of GaN, AlGaN, GaAlN, InGaN, InAlGaN, AlN, and InN, or another nitride-based semiconductor material) and / or another inorganic material. The light emitting element LE may emit light of a specific color or light within a range of wavelengths typically associated with a given color. For example, the light emitting element LE may emit red light (e.g., light having a wavelength in the range of about 620 nm to about 750 nm), green light (e.g., light having a wavelength in the range of about 500 nm to about 570 nm), blue light (e.g., light having a wavelength in the range of about 450 nm to about 500 nm), or light of another color.

[0088] In embodiments, the light emitting element LE may be a micron light emitting diode (micron LED) having a relatively small size in the micron (μm) range. For example, the light emitting element LE may be a micron LED having a length (or height or other dimensions) in the range of hundreds of nanometers to hundreds of microns in the first direction DR1, the second direction DR2, and the third direction DR3. Each of the lengths of the light emitting element LE in the first direction DR1, the second direction DR2, and the third direction DR3 may be approximately 100 μm or less, but embodiments are not limited to these exemplary dimensions.

[0089] The light emitting element LE may include a first semiconductor layer SEM1, a second semiconductor layer SEM2, a light emitting layer EML, and a third semiconductor layer SEM3 sequentially disposed on a substrate SUB. However, embodiments are not limited to these examples. For example, the light emitting element LE may include only a portion of the first semiconductor layer SEM1 (e.g., the seed layer SEM1A), or may not include the first semiconductor layer SEM1.

[0090] In an embodiment, the light emitting element LE may further include a protective layer that surrounds (or covers) the outer (or exposed) peripheral surfaces (e.g., peripheral side surfaces) of the second semiconductor layer SEM2, the light emitting layer EML, and / or the third semiconductor layer SEM3. A larger first insulating layer INS1 may be provided to surround (or cover) the outer (or exposed) peripheral surfaces (e.g., peripheral side surfaces) of the second semiconductor layer SEM2, the light emitting layer EML, and / or the third semiconductor layer SEM3.

[0091] The first semiconductor layer SEM1 may be disposed on the substrate SUB. The first semiconductor layer SEM1 may be doped to have a first conductivity type. For example, the first semiconductor layer SEM1 may include a semiconductor material including a dopant of the first conductivity type.

[0092] In an embodiment, the first semiconductor layer SEM1 may include a nitride-based semiconductor material and a first conductivity-type dopant doped into the nitride-based semiconductor material. In an embodiment, the first semiconductor layer SEM1 may not include indium (In). For example, the first semiconductor layer SEM1 may be an n-type semiconductor layer (e.g., an n-GaN layer) made of a nitride-based semiconductor material that does not include indium and doped with an n-type dopant (e.g., at least one of Si, Ge, Sn, Se, etc.), but embodiments are not limited to this example.

[0093] In an embodiment, at least a portion of the first semiconductor layer SEM1 that is surrounded (or enclosed) by the first insulating layer INS1 in a view in, for example, the third direction DR3 (such as the seed layer SEM1A) may be a layer (e.g., an n-GaN seed layer) for relatively smooth (or uniform) growth of the second semiconductor layer SEM2.

[0094] While the embodiments have been described in which the seed layer SEM1A formed in each light-emitting element area LEA is part of the first semiconductor layer SEM1, the embodiments are not limited to this example. For example, the lower portion (e.g., the n-GaN common layer) of the first semiconductor layer SEM1, which is integrally provided on the substrate SUB and shared by the plurality of light-emitting elements LE, may be distinguished from the seed layer SEM1A or considered to be a separate element from the seed layer SEM1A. In some implementations, at least one of the lower portion of the first semiconductor layer SEM1 and the seed layer SEM1A may be referred to as the first semiconductor layer SEM1.

[0095] The second semiconductor layer SEM2 may be disposed on the first semiconductor layer SEM1. For example, the second semiconductor layer SEM2 may be disposed between the first semiconductor layer SEM1 and the light emitting layer EML in the third direction DR3.

[0096] In an embodiment, the second semiconductor layer SEM2 may contain indium and may be doped. For example, the second semiconductor layer SEM2 may include a nitride-based semiconductor material containing indium (e.g., InGaN, InAlGaN, etc.) and a dopant of the first conductivity type (e.g., an n-type dopant, such as at least one of Si, Ge, Sn, Se, etc.) doped into the nitride-based semiconductor material. For example, the second semiconductor layer SEM2 may be formed of a single semiconductor layer containing indium and doped to have the first conductivity type (e.g., an n-InGaN layer). In some embodiments, the second semiconductor layer SEM2 may be formed of a plurality of layers including a first layer containing indium and doped to have the first conductivity type (e.g., an n-InGaN layer) and second layers alternately stacked with the first layer. Each of the second layers may be a doped or undoped layer (e.g., a GaN layer, an n-GaN layer, etc.) that substantially does not contain indium. In an embodiment, the indium content (or indium composition) of the second semiconductor layer SEM2 (or the first layer of the second semiconductor layer SEM2 ) may be lower than or equal to the indium content (or indium composition) of the light emitting layer EML (or the quantum well layer QWL).

[0097] In an embodiment, the second semiconductor layer SEM2 of the light-emitting element LE whose light-emitting layer EML has the highest indium content among the first, second, and third light-emitting elements LE1, LE2, and LE3 may be a multilayer structure in which first and second layers are alternately stacked. For example, the light-emitting layer EML of the first light-emitting element LE1, which emits first color light (e.g., red light) of a relatively long wavelength (or range of wavelengths), may have a higher indium content than the light-emitting layers EML of the second and third light-emitting elements LE2 and LE3, and the second semiconductor layer SEM2 of the first light-emitting element LE1 may be a multilayer structure in which first and second layers are alternately and / or repeatedly stacked. The second semiconductor layer SEM2 of at least one of the second and third light-emitting elements LE2 and LE3 may be formed of a single semiconductor layer containing indium and doped to have the first conductivity type. For example, the second light-emitting element LE2 may emit second color light (e.g., green light) having a wavelength (or a range of wavelengths) shorter than the wavelength (or a range of wavelengths) of the first color light emitted from the first light-emitting element LE1, and the second semiconductor layer SEM2 of the second light-emitting element LE2 may be formed of a single semiconductor layer containing indium and doped to have the first conductivity type. In addition, the third light-emitting element LE3 may emit third color light (e.g., blue light) having a wavelength (or a range of wavelengths) shorter than the wavelength (or a range of wavelengths) of the second color light emitted from the second light-emitting element LE2, and the second semiconductor layer SEM2 of the third light-emitting element LE3 may be formed of a single semiconductor layer containing indium and doped to have the first conductivity type.

[0098] The second semiconductor layer SEM2 can reduce lattice mismatch through lattice matching. For example, by providing the second semiconductor layer SEM2 containing indium between the first semiconductor layer SEM1 and the light-emitting layer EML, stress (e.g., in-plane stress) caused at least in part by the lattice constant difference between the first semiconductor layer SEM1 and the light-emitting layer EML can be reduced. Therefore, in the step of forming the light-emitting layer EML on the second semiconductor layer SEM2, indium can be easily implanted into the light-emitting layer EML according to the target indium composition, and a relatively high-quality light-emitting layer EML with reduced defects can be formed. For example, when manufacturing a relatively long-wavelength light-emitting element LE (e.g., a first light-emitting element LE1, such as a red light-emitting element) in which the indium content of the light-emitting layer EML (or quantum well layer QWL) is approximately 30% or more, the second semiconductor layer SEM2 can be first formed on the first semiconductor layer SEM1, and the light-emitting layer EML can be formed on the second semiconductor layer SEM2. This allows indium to be easily implanted into the quantum well layer QWL, thereby improving the quality of the light-emitting element LE.

[0099] Furthermore, since the second semiconductor layer SEM2 may be doped (e.g., doped to have the first conductivity type), light emission from the second semiconductor layer SEM2 may be prevented or reduced. In an embodiment, the doping concentration of the second semiconductor layer SEM2 (or the first layer of the second semiconductor layer SEM2) may be approximately 10 16 dopant atoms / cm 3 or higher. Thus, unintentional light emission from the second semiconductor layer SEM2 can be effectively prevented. For example, even if the second semiconductor layer SEM2 contains indium, non-emissive recombination of carriers (e.g., electrons or holes) can be caused, at least in part, by the dopant doped into the second semiconductor layer SEM2, thereby preventing the second semiconductor layer SEM2 from generating light having a wavelength different from that of light emitted from the light-emitting layer EML. Consequently, the color purity of the light-emitting element LE can be improved.

[0100] The second semiconductor layer SEM2 may be formed to have a thickness taking into account at least one of a lattice matching effect, manufacturing efficiency of the light-emitting element LE, and luminous efficiency of the light-emitting element LE. For example, the second semiconductor layer SEM2 (or the first layer of the second semiconductor layer SEM2) may be formed to have a thickness of approximately 10 nm or greater to achieve the desired lattice matching effect. In an embodiment, the thickness of each of the first layers forming the second semiconductor layer SEM2 may be approximately 10 nm or greater, and the total thickness of the second semiconductor layer SEM2 may be approximately 300 nm or greater. Thus, a relatively high-quality light-emitting layer EML can be formed on the second semiconductor layer SEM2.

[0101] The light-emitting layer EML may be provided on the second semiconductor layer SEM2. For example, the light-emitting layer EML may be provided between the second semiconductor layer SEM2 and the third semiconductor layer SEM3 in the third direction DR3. The light-emitting layer EML may emit light by recombination of electron-hole pairs generated by an electrical signal applied via the first semiconductor layer SEM1 (or the second semiconductor layer SEM2) and the third semiconductor layer SEM3.

[0102] The light-emitting layer EML may include a nitride-based semiconductor material or another semiconductor material and may have a single quantum well structure or a multi-quantum well structure. For example, the light-emitting layer EML may include at least one quantum well layer QWL, wherein the at least one quantum well layer QWL includes a nitride-based semiconductor material containing indium. In an embodiment, the quantum well layer QWL may include a nitride-based semiconductor material having an indium content higher than or equal to the indium content in the second semiconductor layer SEM2 (or the first layer of the second semiconductor layer SEM2). In an embodiment, the light-emitting layer EML may have a multi-quantum well structure, in which a plurality of quantum well layers QWL containing InGaN and a plurality of barrier layers BRL containing GaN, AlGaN, or GaAlN are alternately and / or repeatedly arranged.

[0103] In embodiments, the light-emitting layer EML may emit light in a visible light wavelength band, for example, light in a wavelength band of about 400 nm to about 900 nm. For example, the light-emitting layer EML may emit blue light having a peak wavelength in a range of about 440 nm to about 480 nm, green light having a peak wavelength in a range of about 510 nm to about 550 nm, or red light having a peak wavelength in a range of about 610 nm to about 750 nm (for example, in a range of about 610 nm to about 650 nm). The light-emitting layer EML may emit light having a color or wavelength band different from the colors or wavelength bands exemplified above.

[0104] In embodiments, the color of light emitted from the light-emitting layer EML can be adjusted or changed by adjusting the indium content contained in the light-emitting layer EML. For example, the light-emitting layer EML of the first light-emitting element LE1 (or the quantum well layer QWL of the light-emitting layer EML) may contain an indium content of approximately 30% to approximately 40%, such that the first light-emitting element LE1 can emit red light. The light-emitting layer EML of the second light-emitting element LE2 (or the quantum well layer QWL of the light-emitting layer EML) may contain an indium content of approximately 20% to less than approximately 30%, such that the second light-emitting element LE2 can emit green light. The light-emitting layer EML of the third light-emitting element LE3 (or the quantum well layer QWL of the light-emitting layer EML) may contain an indium content of approximately 10% to less than approximately 20%, such that the third light-emitting element LE3 can emit blue light.

[0105] The third semiconductor layer SEM3 may be disposed on the light emitting layer EML. The third semiconductor layer SEM3 may be doped to have the second conductivity type. For example, the third semiconductor layer SEM3 may include a semiconductor material containing a dopant of the second conductivity type.

[0106] In an embodiment, the third semiconductor layer SEM3 may include a nitride-based semiconductor material and a second conductivity-type dopant doped into the nitride-based semiconductor material. For example, the third semiconductor layer SEM3 may be a p-type semiconductor layer (e.g., a p-GaN layer, a p-InGaN layer, etc.) doped with a p-type dopant (such as at least one of Mg, Zn, Ca, Ba, etc.), but is not limited to these examples.

[0107] In an embodiment, the third semiconductor layer SEM3 may be made of a nitride-based semiconductor material containing indium, similar to the second semiconductor layer SEM2, and the third semiconductor layer SEM3 may include a dopant of the second conductivity type. For example, the third semiconductor layer SEM3 may be a p-type semiconductor layer (e.g., a p-InGaN layer) made of a nitride-based semiconductor material containing indium (e.g., InGaN) and doped with a p-type dopant. In an embodiment, the third semiconductor layer SEM3 may have a single-layer structure, but in some implementations, the third semiconductor layer SEM3 may have a multi-layer structure.

[0108] In an embodiment, the width (e.g., length in the first direction DR1 or the second direction DR2) of each light emitting element area LEA or light emitting element LE provided in the light emitting element area LEA may be approximately several hundred nanometers (e.g., about 400 nm to about 800 nm). Since the second semiconductor layer SEM2 and the third semiconductor layer SEM3 are made of a nitride-based semiconductor material (e.g., InGaN) containing indium, relatively fine-sized light emitting elements LE having a width of approximately several hundred nanometers can be manufactured with relatively high quality.

[0109] Figure 5 is a cross-sectional view schematically showing a light emitting element array ARR according to the embodiment. Figure 6 : is a cross-sectional view schematically showing a light emitting element array ARR according to an embodiment. For example, Figure 5 and Figure 6 Shown along Figure 2 1 and 2 illustrate embodiments of a cross section of the light emitting element array ARR taken along a section line X1 - X1 ′, and illustrate different embodiments related to electrodes that can be formed in the light emitting element array ARR.

[0110] Joint Figures 1 to 4 refer to Figure 5 and Figure 6The light emitting element array ARR may include a first light emitting element LE1, a second light emitting element LE2, and a third light emitting element LE3 respectively disposed in a first light emitting element area LEA1, a second light emitting element area LEA2, and a third light emitting element area LEA3. Each of the first light emitting element LE1, the second light emitting element LE2, and the third light emitting element LE3 may include a first semiconductor layer SEM1 (and / or a seed layer SEM1A), a second semiconductor layer SEM2, a light emitting layer EML, and a third semiconductor layer SEM3 sequentially disposed on a substrate SUB.

[0111] The light emitting element array ARR may further include a first insulating layer INS1 that covers at least a portion of each of the light emitting elements LE (or overlaps at least a portion of each of the light emitting elements LE in the third direction DR3). For example, the first insulating layer INS1 may cover at least a portion of each of the light emitting elements LE, including a side surface (or exposed peripheral surface) of the light emitting element LE. In an embodiment, the light emitting element array ARR may further include a reflective layer RFL disposed on the first insulating layer INS1.

[0112] In an embodiment, the first insulating layer INS1 may include one or more portions used as masks for sequentially forming the first light-emitting element LE1, the second light-emitting element LE2, and the third light-emitting element LE3. For example, in one or more steps (or processes) of manufacturing the light-emitting element array ARR, the first insulating layer INS1 may include a first portion INS1A (also referred to as a "first mask layer") that defines (or at least partially defines) the third light-emitting element region LEA3 for forming the third light-emitting element LE3, a second portion INS1B (also referred to as a "second mask layer") that defines (or at least partially defines) the second light-emitting element region LEA2 for forming the second light-emitting element LE2, and a third portion INS1C (also referred to as a "third mask layer") that defines (or at least partially defines) the first light-emitting element region LEA1 for forming the first light-emitting element LE1.

[0113] In an embodiment, the first insulating layer INS1 may have different thicknesses depending on the region or portion. For example, the first insulating layer INS1 may have different thicknesses in the first light emitting element area LEA1, the second light emitting element area LEA2, and the third light emitting element area LEA3 (for example, in portions covering the first light emitting element LE1, the second light emitting element LE2, and the third light emitting element LE3, respectively (or portions overlapping the first light emitting element LE1, the second light emitting element LE2, and the third light emitting element LE3, respectively, for example, in the third direction DR3)).

[0114] For example, in a view in the third direction DR3, the first portion INS1A of the first insulating layer INS1 may be provided between and / or around the light emitting element regions LEA. For example, in a view in the third direction DR3, the first portion INS1A of the first insulating layer INS1 may be provided on a portion of the first semiconductor layer SEM1 between and / or around the light emitting element regions LEA (for example, a lower portion entirely (or substantially entirely) formed on the substrate SUB).

[0115] For example, in a view along the third direction DR3, the second portion INS1B of the first insulating layer INS1 may cover (or overlap) at least a portion of the third light-emitting element LE3 (for example, a portion of the upper surface and the side surface of the third light-emitting element LE3). For example, in a view along the third direction DR3, the second portion INS1B of the first insulating layer INS1 may be disposed between the light-emitting element areas LEA and / or around the light-emitting element areas LEA. For example, in a view along the third direction DR3, the second portion INS1B of the first insulating layer INS1 may be disposed between the light-emitting element areas LEA and / or around the light-emitting element areas LEA on the first portion INS1A of the first insulating layer INS1.

[0116] The third portion INS1C of the first insulating layer INS1 may cover (or overlap) at least a portion of each of the second light-emitting element LE2 and the third light-emitting element LE3, for example, in the third direction DR3. For example, in a view in the third direction DR3, the third portion INS1C of the first insulating layer INS1 may be disposed between and / or around the light-emitting element areas LEA. For example, in a view in the third direction DR3, the third portion INS1C of the first insulating layer INS1 may be disposed between and / or around the light-emitting element areas LEA on the second portion INS1B of the first insulating layer INS1.

[0117] In an embodiment, the first insulating layer INS1 may further include a fourth portion INS1D (also referred to as a "passivation layer") that covers at least a portion of each of the first light-emitting element LE1, the second light-emitting element LE2, and the third light-emitting element LE3 (or overlaps therewith in the third direction DR3) and protects the light-emitting elements LE. For example, in a view along the third direction DR3, the fourth portion INS1D of the first insulating layer INS1 may be disposed between and / or around the light-emitting element areas LEA. For example, in a view along the third direction DR3, the fourth portion INS1D of the first insulating layer INS1 may be disposed between and / or around the light-emitting element areas LEA on the third portion INS1C of the first insulating layer INS1.

[0118] In an embodiment, the light emitting element array ARR may include at least one electrode formed in (or formed as part of) the light emitting element LE, and the first insulating layer INS1 may be opened in a region where the electrode is provided. For example, the first insulating layer INS1 may define an opening that overlaps the first electrode ET1 of each of the light emitting elements LE and the second electrode ET2 electrically connected to the light emitting element LE. In some implementations, the outer boundary of the opening in the first insulating layer INS1 may surround a corresponding one of the first electrode ET1 and the second electrode ET2, respectively, when viewed in the third direction DR3.

[0119] The reflective layer RFL may cover at least a portion of the light emitting element LE (or overlap at least a portion of the light emitting element LE in, for example, the third direction DR3). For example, the reflective layer RFL may be provided on the first insulating layer INS1 to cover the side surface (or exposed peripheral surface) of each of the light emitting elements LE. The reflective layer RFL may further cover at least a portion of the upper surface of the light emitting element LE (or further overlap at least a portion of the upper surface of the light emitting element LE in, for example, the third direction DR3).

[0120] In an embodiment, the light emitting element array ARR may include at least one electrode formed in the light emitting elements LE, and the reflective layer RFL may have an opening in a region where the electrode is provided. For example, the reflective layer RFL may define an opening that overlaps, for example, with the first electrode ET1 of each of the light emitting elements LE and the second electrode ET2 electrically connected to the light emitting element LE when viewed in the third direction DR3. In some implementations, the outer boundary of the opening in the reflective layer RFL may surround a corresponding one of the first electrode ET1 and the second electrode ET2 when viewed in the third direction DR3.

[0121] In embodiments, the reflective layer RFL may include a metal having a relatively high light reflectivity. For example, the reflective layer RFL may include at least one metal having a relatively high reflectivity (such as at least one of aluminum (Al), molybdenum (Mo), titanium (Ti), copper (Cu), silver (Ag), magnesium (Mg), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), and chromium (Cr)) or another reflective material. In some embodiments, the reflective layer RFL may be formed as a distributed Bragg reflector, etc.

[0122] The reflective layer RFL can reflect the light generated (or emitted) from each light-emitting element LE. For example, the reflective layer RFL can reflect the light generated from the light-emitting layer EML of each light-emitting element LE and guided (or propagated) toward the side surface (or peripheral surface) of the light-emitting element LE to recycle the light. Therefore, the loss of light generated from the light-emitting element LE can be prevented or reduced, and the luminous efficiency of the light-emitting element LE can be further improved. In some implementations, the optical thickness of the reflective layer RFL can at least partially cause constructive interference and, in this way, further increase the corresponding luminous efficiency of the light-emitting element LE. To this end, the optical thickness of the reflective layer RFL can be different in one or more of the first light-emitting element area LEA1, the second light-emitting element area LEA2, and the third light-emitting element area LEA3. This can also improve the corresponding luminous efficiency of the various light-emitting elements LE.

[0123] In an embodiment, the light emitting element array ARR may further include at least one electrode electrically connected to the first semiconductor layer SEM1 or the third semiconductor layer SEM3 of each of the light emitting elements LE (or each of the light emitting elements LE of the light emitting element group, or each of the light emitting elements LE of the light emitting element unit UNT, or each of the light emitting elements LE in the unit area UA).

[0124] In an embodiment, the light emitting element array ARR may include a corresponding first electrode ET1 disposed on the third semiconductor layer SEM3 of each of the light emitting elements LE, and the second electrode ET2 may be disposed on the first semiconductor layer SEM1 of the light emitting element LE, such as Figure 5 As shown in .

[0125] The first electrode ET1 may be a connection electrode for electrically connecting the third semiconductor layer SEM3 (or a contact electrode provided on the third semiconductor layer SEM3) to another circuit element, electrode, wiring, etc. In an embodiment, the first electrode ET1 may have a size smaller than a corresponding size of the third semiconductor layer SEM3 (e.g., a smaller planar area than the third semiconductor layer SEM3) and may be provided on a portion of the third semiconductor layer SEM3, but the embodiment is not limited to this example.

[0126] In an embodiment, each first electrode ET1 may be disposed on (e.g., directly disposed on) the third semiconductor layer SEM3 of the corresponding light emitting element LE and electrically connected to the third semiconductor layer SEM3. Each first electrode ET1 may be a component included in the corresponding light emitting element LE among the light emitting elements LE. In an embodiment, the first electrode ET1 may be electrically connected to the electronic device using a light emitting element array ARR (e.g., a pixel electrode (or bonding pad) disposed in a corresponding pixel of a display device).

[0127] The second electrode ET2 may be a connection electrode for electrically connecting the first semiconductor layer SEM1 to another circuit element, electrode, wiring, etc. In an embodiment, the second electrode ET2 may be, but is not necessarily limited to, disposed in a contact region CNA that is located around (or partially around) the light-emitting element region LEA or positioned adjacent to the light-emitting element region LEA. In some embodiments, in a view in the third direction DR3, the contact region CNA may surround (or partially surround) one or more of the light-emitting element regions LEA. In an embodiment, the second electrode ET2 may be connected to a second pixel power line or a common electrode disposed in the display device, as will become more apparent below.

[0128] In an embodiment, the second electrode ET2 may be an electrode shared by a plurality of light-emitting elements LE. For example, the second electrode ET2 may be disposed (e.g., directly disposed) on the first semiconductor layer SEM1 shared by the first light-emitting element LE1, the second light-emitting element LE2, and the third light-emitting element LE3 formed in at least one unit area UA, and electrically connected to the first semiconductor layer SEM1. However, embodiments are not limited to this example. For example, the light-emitting element array ARR may include a plurality of second electrodes ET2, the number and / or resolution (or density) of which corresponds to the number and / or resolution (or density) of the light-emitting elements LE. For example, the second electrodes ET2 may correspond one to one with the light-emitting elements LE.

[0129] The first electrode ET1 and the second electrode ET2 may include at least one of a metal, a metal oxide, and other conductive materials. For example, the first electrode ET1 and the second electrode ET2 may include at least one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), but embodiments are not limited to these materials. In some implementations, the respective materials of the first electrode ET1 and the second electrode ET2 may be the same or different from each other.

[0130] In an embodiment, the light emitting element array ARR may include a transparent electrode CTE disposed on the third semiconductor layer SEM3 of each of the light emitting elements LE, such as Figure 6 As shown in . A transparent electrode CTE, which may be a contact electrode that protects the third semiconductor layer SEM3 and electrically connects the third semiconductor layer SEM3 to at least one electrode, circuit element, wiring, etc., may be provided in each light emitting element LE (or provided as a part of each light emitting element LE). For example, each light emitting element LE may include a corresponding transparent electrode CTE, such as Figure 6 As shown in .

[0131] The transparent electrode CTE may include at least one of a metal, a metal oxide, and other conductive materials. For example, the metal may be at least one of chromium (Cr), titanium (Ti), aluminum (Al), gold (Au), nickel (Ni), and copper (Cu), and / or an alloy comprising at least one of these metals. The metal oxide may be an oxide of at least one of these metals. In some implementations, the transparent electrode CTE may include a transparent conductive material such as at least one of indium tin oxide (ITO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), zinc oxide (ZnO), and indium oxide (In2O3), and / or another transparent conductive material. The transparent conductive material may be used alone or mixed (or combined) to form the transparent electrode CTE. However, the embodiments are not limited to these examples.

[0132] In embodiments, the transparent electrode CTE may be in contact (or direct contact) (e.g., physical and / or electrical contact) with the reflective layer RFL and may be electrically connected to at least one electrode, circuit element, wiring, etc. through the reflective layer RFL. For example, the reflective layer RFL may be formed to be in contact (e.g., direct physical and / or electrical contact) with a side surface (or peripheral surface) of the transparent electrode CTE and may extend to the contact region CNA, thereby serving as a connection electrode (e.g., a bonding electrode) for electrically connecting the third semiconductor layer SEM3 to another circuit element, electrode, wiring, etc. In embodiments, the reflective layer RFL may be in contact (e.g., direct physical and / or electrical contact) with the first semiconductor layer SEM1 within an opening formed in the contact region CNA of the first insulating layer INS1. In some embodiments, after manufacturing the light-emitting elements LE, the first semiconductor layers SEM1 of the light-emitting elements LE may be separated from each other. In some embodiments, the first semiconductor layers SEM1 of the light-emitting elements LE may be separated during manufacturing of the light-emitting elements LE. In addition, the first semiconductor layer SEM1 of the separated light emitting element LE (eg, the seed layer SEM1A of the first semiconductor layer SEM1 disposed in each light emitting element area LEA) may also be separated from the reflective layer RFL.

[0133] In some embodiments, the transparent electrode CTE can be connected (e.g., directly connected) to a bonding pad or electrode of an electronic device using a light-emitting element LE without forming a connection through a reflective layer RFL (or without using a reflective layer RFL). In some implementations, the transparent electrode CTE can be physically and / or electrically connected (e.g., directly connected) to a bonding pad or electrode of an electronic device using a light-emitting element LE without forming a connection through a reflective layer RFL (or without using a reflective layer RFL).

[0134] Figure 7 It is schematically shown in more detail according to the embodiment Figure 5 For example, Figure 7 An embodiment of the second semiconductor layer SEM2 of the first light emitting element LE1 is shown.

[0135] refer to Figures 1 to 7 The second semiconductor layer SEM2 of the first light emitting element LE1 may have a multilayer structure including at least one pair of the first layer L1 and the second layer L2. For example, the second semiconductor layer SEM2 of the first light emitting element LE1 may have a multilayer structure including at least two pairs of the first layer L1 and the second layer L2 (i.e., at least two first layers L1 and at least two second layers L2), and the first layers L1 and the second layers L2 are alternately and repeatedly arranged with each other.

[0136] The first layer L1 may be a semiconductor layer containing indium. For example, the first layer L1 may be a semiconductor layer containing indium and doped to have a first conductivity type (e.g., an n-InGaN layer). In an embodiment, the first layer L1 may be a layer for easily injecting indium into the light-emitting layer EML, and the indium content (or indium composition) of the first layer L1 may be lower than or equal to the indium content (or indium composition) of the light-emitting layer EML or the quantum well layer QWL. At least because the first layer L1 is doped (e.g., doped to have a first conductivity type), light generation in the first layer L1 (or emission from the first layer L1) may be prevented or reduced. In an embodiment, the doping concentration of the first layer L1 may be 10 16 dopant atoms / cm 3 Therefore, it is possible to effectively prevent light from being generated in (or emitted from) the first layer L1.

[0137] In an embodiment, the indium content of the first layer L1 may be substantially uniform, or may vary (or change), such as gradually. For example, the indium content of the first layers L1 may be substantially identical or similar to one another. In some embodiments, the indium content of the first layer L1 may vary (e.g., increase (e.g., gradually increase)) from one first layer L1 to another first layer L1 in a direction toward the light-emitting layer EML. In some implementations, the indium content of any given first layer L1 may be uniform, or may vary, such as gradually varying (e.g., increasing) as the distance from the light-emitting layer EML decreases. Therefore, indium can be easily injected into the light-emitting layer EML through the first layer L1, and the quality of the first light-emitting element LE1 can be improved.

[0138] The second layer L2 may be a semiconductor layer that does not include indium. For example, the second layer L2 may be a doped or undoped semiconductor layer (eg, an n-GaN layer) that does not include indium.

[0139] At least because the second semiconductor layer SEM2 of the first light-emitting element LE1 can be formed of a plurality of layers in which the first layer L1 and the second layer L2 are alternately arranged, the quality of the first light-emitting element LE1 can be improved. For example, if the second semiconductor layer SEM2 (or the first layer L1) of the first light-emitting element LE1 contains a higher content of indium than the second semiconductor layer SEM2 of the second light-emitting element LE2 and / or the third light-emitting element LE3, in-phase separation that may otherwise occur in the nitride-based semiconductor layer containing indium can be prevented. A relatively high-quality first light-emitting element LE1 can also be manufactured.

[0140] The thickness of the second semiconductor layer SEM2 and the thickness of each of the first layer L1 and the second layer L2 forming the second semiconductor layer SEM2 may be adjusted or varied, taking into account at least one of the lattice matching effect achieved by the second semiconductor layer SEM2, the manufacturing efficiency of the light-emitting element LE, and the luminous efficiency of the light-emitting element LE. For example, the thickness of each of the first layers L1 may be greater than the thickness of each of the second layers L2. Thus, it is possible to ensure carrier mobility while achieving an appropriate (or determined) lattice matching effect.

[0141] In an embodiment, the thickness of each of the first layers L1 may be approximately 10 nm or greater, thereby improving or ensuring a lattice matching effect. For example, the thickness of each of the first layers L1 may be in a range of approximately 10 nm to approximately 20 nm, thereby allowing the first layer L1 to be formed more smoothly and / or appropriately and ensuring a certain lattice matching effect. In an embodiment, the thickness of each of the second layers L2 may be approximately 5 nm or less (for example, in a range of approximately 1 nm to approximately 5 nm), allowing carriers (for example, electrons) to move more easily. In an embodiment, the total thickness of the second semiconductor layer SEM2 may be approximately 300 nm or greater, thereby improving or ensuring a certain lattice matching effect.

[0142] Figure 8 It is schematically shown in more detail according to the embodiment Figure 5 For example, Figure 8 The second semiconductor layer SEM2 of the first light emitting element LE1 is different from Figure 7 An embodiment of the embodiment shown in .

[0143] refer to Figures 1 to 8The second semiconductor layer SEM2 of the first light-emitting element LE1 may include a plurality of stacks (or layers) sequentially arranged along a third direction DR3. Each stack may include at least one of the first layers L1 and at least one of the second layers L2. In other words, each stack may include at least one pair of layers, each pair including a first layer L1 and a second layer L2. For example, the second semiconductor layer SEM2 of the first light-emitting element LE1 may include first through fourth stacks LM1 through LM4, sequentially arranged along the third direction DR3 on the first semiconductor layer SEM1 (e.g., the seed layer SEM1A), each including at least one of the first layers L1 and at least one of the second layers L2. Furthermore, the second semiconductor layer SEM2 of the first light-emitting element LE1 may include first layers L1 having different indium contents. For example, at least one stack among the first through fourth stacks LM1 through LM4 may include a first layer L1 having an indium content different from the indium content of the first layers L1 of the other stacks among the first through fourth stacks LM1 through LM4. For example, two stacks sequentially or continuously arranged along the third direction DR3 may include first layers L1 having different indium contents.

[0144] In an embodiment, the indium content contained in the first layer L1B included in the second and fourth stacks LM2 and LM4 may be at least approximately 5% lower than the indium content of the first layer L1A included in the first and third stacks LM1 and LM3. For example, the first stack LM1 may include a first layer L1A (also referred to as a "first indium-containing layer") containing a first indium content, and a second layer L2 on the first layer L1A. The second stack LM2 may include a first layer L1B (also referred to as a "second indium-containing layer") containing a second indium content, the second content being at least approximately 5% lower than the first content, and a second layer L2 on the first layer L1B. Furthermore, the third stack LM3 may include a first layer L1A (also referred to as a "first indium-containing layer") containing a first indium content, and a second layer L2 on the first layer L1A. The fourth stack LM4 may include a first layer L1B (also referred to as a "second indium-containing layer") containing a second indium content, the second content being at least approximately 5% lower than the first content, and a second layer L2 on the first layer L1B.

[0145] In an embodiment, the indium contents of the first layers L1A included in the first and third stacks LM1 and LM3 may be equal (or substantially equal) to each other, but the embodiment is not limited to this example. For example, the indium contents of the first layers L1A included in the first and third stacks LM1 and LM3 may be different from each other. In addition, when each of the first and third stacks LM1 and LM3 includes a plurality of first layers L1A, the indium contents of the plurality of first layers L1A may be equal (or substantially equal) to each other or different from each other.

[0146] The indium contents of the first layers L1B included in the second and fourth stacks LM2 and LM4 may be equal (or substantially equal) to each other, but embodiments are not limited to this example. For example, the indium contents of the first layers L1B included in the second and fourth stacks LM2 and LM4 may be different from each other. Furthermore, in the case where each of the second and fourth stacks LM2 and LM4 includes a plurality of first layers L1B, the indium contents of the plurality of first layers L1B may be equal (or substantially equal) to each other or different from each other.

[0147] In embodiments, the indium content of the light-emitting layer EML (or quantum well layer QWL) of the first light-emitting element LE1 emitting red light may be in a range of approximately 30% to approximately 40%, and the indium content of the first layer L1 containing a higher indium content (e.g., the first content) within the first layer L1 of the second semiconductor layer SEM2 forming the first light-emitting element LE1 may be less than or equal to 40%. In embodiments, the indium content of the first layer L1 of the second semiconductor layer SEM2 forming the first light-emitting element LE1 may be adjusted to be less than or equal to the indium content of the quantum well layer QWL of the first light-emitting element LE1, for example, less than or equal to 30%. For example, the indium content of the first layer L1A containing the first content of indium within the first layer L1 of the second semiconductor layer SEM2 forming the first light-emitting element LE1 may be in a range of approximately 25% to approximately 30%, and the indium content of the first layer L1B containing the second content of indium may be less than or equal to approximately 25%. Thus, the lattice matching effect can be improved or optimized while facilitating the formation of the second semiconductor layer SEM2.

[0148] In an embodiment, to control or change the indium content of the first layer L1, the flow of the indium source may be adjusted, or the growth temperature (or growth temperature range) of the first layer L1 may be adjusted. For example, to reduce the indium content, the flow of the indium source may be changed (e.g., increased), or the growth temperature (or growth temperature range) of the first layer L1 may be increased.

[0149] In embodiments, stacks having different indium contents can be formed using processes at different temperatures (or temperature ranges). For example, the semiconductor layers of the first and third stacks LM1 and LM3 (e.g., the respective first and second layers L1A and L2) can be formed by regrowth (or growth) at a relatively low temperature (or a first temperature (or a first temperature range)), and the semiconductor layers of the second and fourth stacks LM2 and LM4 (e.g., the respective first and second layers L1B and L2) can be formed by regrowth (or growth) at a relatively high temperature (or a second temperature (or a second temperature range)). The semiconductor layers regrowed (or grown) at a relatively high temperature (e.g., the semiconductor layers of the second and fourth stacks LM2 and LM4) can exhibit reduced surface roughness. Because at least a portion of the stack forming the second semiconductor layer SEM2 can be formed using a relatively high-temperature process, the optical characteristics (e.g., luminous efficiency) of the light-emitting element LE including the second semiconductor layer SEM2 can be improved.

[0150] In an embodiment, the light emitting characteristics of the light emitting element LE may be improved or adjusted by adjusting or changing the position and / or thickness of at least one of the second stack LM2 and the fourth stack LM4. For example, by disposing the semiconductor layers of the second stack LM2 and the fourth stack LM4 at the middle layer and the uppermost layer of the second semiconductor layer SEM2, the light emitting efficiency of the light emitting element LE may be improved.

[0151] although Figure 8 In the embodiment shown, the first and third stacks LM1 and LM3 include first layers L1A having the same (or substantially the same) indium content, and the second and fourth stacks LM2 and LM4 include first layers L1B having the same (or substantially the same) indium content, but the embodiment is not limited to this example. For example, the indium content of the first layer L1A of the first stack LM1 and the indium content of the first layer L1A of the third stack LM3 may be different from each other, and the indium content of the first layer L1A of the first stack LM1 and the indium content of the first layer L1A of the third stack LM3 may be higher than the indium content of the first layer L1B of the second and fourth stacks LM2 and LM4, respectively. The indium content of the first layer L1B of the second stack LM2 and the indium content of the first layer L1B of the fourth stack LM4 may be different, and the indium content of the first layer L1B of the second stack LM2 and the indium content of the first layer L1B of the fourth stack LM4 may be lower than the indium content of the first layer L1A of the first stack LM1 and the indium content of the first layer L1A of the third stack LM3, respectively.

[0152] Figure 9 : is a cross-sectional view schematically showing the second semiconductor layer SEM2 of the first light emitting element LE1 according to the embodiment. Figure 9Schematically shows the application of a combination of Figure 8 The cross-sectional shape of the second semiconductor layer SEM2 of the described embodiment(s) is shown.

[0153] refer to Figures 1 to 9 The first layer L1 and the second layer L2 of the second semiconductor layer SEM2 may be alternately arranged not only in the thickness direction (e.g., the third direction DR3) of the first light-emitting element LE1, but also in another direction (e.g., a lateral direction) transverse to the thickness direction (e.g., the third direction DR3) of the first light-emitting element LE1. For example, the first layer L1 and the second layer L2 of the second semiconductor layer SEM2 may be deposited or otherwise formed on the inclined (or skewed) surface(s) of the second semiconductor layer SEM2, as well as on the upper surface (e.g., flat surface(s)) of the second semiconductor layer SEM2. In some embodiments, the first layer L1 and the second layer L2 of the second semiconductor layer SEM2 may be deposited or otherwise formed on the surface of the second semiconductor layer SEM2 corresponding to the r-plane (e.g., the 1012 plane) and the surface corresponding to the c-plane (e.g., the 0001 plane). In some implementations, the first layer L1 and the second layer L2 of the second semiconductor layer SEM2 can be deposited or otherwise formed to have a thickness thinner on the inclined surface (or the surface associated with the r-plane) than on the upper surface (or the surface associated with the c-plane).

[0154] Figure 10 It is schematically shown in more detail according to the embodiment Figure 5 For example, Figure 10 Shown in conjunction with Figure 8 The described embodiment(s) are similar and relate to the second semiconductor layer SEM2 of the first light emitting element LE1 .

[0155] refer to Figures 1 to 10 The second semiconductor layer SEM2 of the first light emitting element LE1 may include more first layers L1 and second layers L2. For example, the second semiconductor layer SEM2 of the first light emitting element LE1 may include 10 or more pairs of layers, each pair including a first layer L1 and a second layer L2.

[0156] By adjusting the number of the first layer L1 and the second layer L2 included in the stacks such as the first stack LM1 to the fourth stack LM4, the thickness and position (or height) of the stacks and / or the optical characteristics of the light emitting element LE can be adjusted. For example, by adjusting the number of the first layer L1 and the second layer L2 included in each stack such as the first stack LM1 to the fourth stack LM4, the thickness and position of each stack and / or the optical characteristics of the light emitting element LE affected by the number of the first layer L1 and the second layer L2 can be adjusted.

[0157] In an embodiment, the stacks having different indium contents from each other among the first to fourth stacks LM1 to LM4 may include different numbers of first layers L1 and second layers L2. In an embodiment, each of the first stack LM1 and the third stack LM3 containing a higher indium content (e.g., the first content) may include a larger number of pairs of layers (e.g., a larger number of first layers L1A and second layers L2) than the number of pairs of layers (e.g., the number of first layers L1B and second layers L2) included in each of the second stack LM2 and the fourth stack LM4 containing a lower indium content (e.g., the second content). Therefore, the lattice matching effect of the second semiconductor layer SEM2 of the first light emitting element LE1 may be improved or optimized. Although Figure 10 An embodiment is shown in which each of the second stack LM2 and the fourth stack LM4 includes a pair of layers (e.g., a pair of layers including a first layer L1B and a second layer L2), but each of the second stack LM2 and the fourth stack LM4 may include at least two pairs of layers, each pair of layers including a first layer L1B and a second layer L2.

[0158] In embodiments, each of the first and third laminates LM1 and LM3 may include six or more pairs of layers (or six or more cycles), each pair including a first layer L1A and a second layer L2; and each of the second and fourth laminates LM2 and LM4 may include five or fewer pairs of layers (or five or fewer cycles), each pair including a first layer L1B and a second layer L2 (or a single first layer L1B and a single second layer L2). In embodiments, the first and third laminates LM1 and LM3 may include the same or different numbers of first layers L1A and L2. For example, the first laminate LM1 may include a greater number of first layers L1A and L2 (e.g., nine to twenty-one pairs of layers), and the third laminate LM3 may include a smaller number of first layers L1A and L2 (e.g., nine or fewer pairs of layers) than the first laminate LM1. In some embodiments, the second and fourth laminates LM2 and LM4 may include the same or different numbers of first layers L1B and L2.

[0159] In some implementations, the structure, thickness, and / or material (or content of the material) of the second semiconductor layer SEM2 may be variously changed according to target quality and / or optical characteristics of the first light emitting element LE1 including the second semiconductor layer SEM2 .

[0160] Figure 11 It is schematically shown in more detail according to the embodiment Figure 5 For example, Figure 11An embodiment of a second semiconductor layer SEM2 of the second light emitting element LE2 is shown.

[0161] refer to Figures 1 to 11 The second semiconductor layer SEM2 of the second light-emitting element LE2 may have a structure different from that of the second semiconductor layer SEM2 of the first light-emitting element LE1. For example, the second semiconductor layer SEM2 of the second light-emitting element LE2 may be formed of a single semiconductor layer. For example, the second semiconductor layer SEM2 of the second light-emitting element LE2 may be formed of a single semiconductor layer containing indium and doped to have the first conductivity type.

[0162] In an embodiment, the second semiconductor layer SEM2 of the third light emitting element LE3 may have a structure identical (or substantially identical) to the structure of the second semiconductor layer SEM2 of the second light emitting element LE2. For example, the second semiconductor layer SEM2 of the third light emitting element LE3 may be formed of a single semiconductor layer containing indium and doped to have the first conductivity type.

[0163] The indium content of each of the second semiconductor layers SEM2 of the second light-emitting element LE2 and the third light-emitting element LE3 can be substantially uniform, or can vary (or change), such as gradually. For example, each of the second semiconductor layers SEM2 of the second light-emitting element LE2 and the third light-emitting element LE3 can include a uniform (or substantially uniform) content of indium. In some implementations, the indium content of each of the second semiconductor layers SEM2 of the second light-emitting element LE2 and the third light-emitting element LE3 can vary (e.g., gradually vary) (e.g., increase) along the third direction DR3. Thus, the quality of the second light-emitting element LE2 and the third light-emitting element LE3 can be improved.

[0164] In some embodiments, the structure of the second semiconductor layer SEM2 of each of the first, second, and third light-emitting elements LE1, LE2, and LE3 can be differentiated (or formed to have different structures) based on the emission wavelength or indium content of the corresponding light-emitting layer EML of each of the first, second, and third light-emitting elements LE1, LE2, and LE3. For example, the second semiconductor layer SEM2 of the first light-emitting element LE1 (wherein the light-emitting layer EML has a relatively high indium content and therefore emits light of a relatively long wavelength (e.g., red light)) can be formed to have a multilayer structure including multiple first layers L1 and multiple second layers L2. Consequently, the light-emitting layer EML of the first light-emitting element LE1 can be formed more smoothly (e.g., with less surface roughness) and / or appropriately, and the optical characteristics of the first light-emitting element LE1 (e.g., at least one of luminous efficiency, brightness, and color purity) can be improved. Furthermore, the second semiconductor layer SEM2 of each of the second and third light-emitting elements LE2 and LE3 (wherein the light-emitting layer EML has a relatively low indium content and therefore emits light of a relatively short wavelength (e.g., green or blue light)) can be formed to have a single-layer structure. Therefore, the second light emitting element LE2 and the third light emitting element LE3 can be easily formed, and the quality of the second light emitting element LE2 and the third light emitting element LE3 can be improved or ensured.

[0165] Figures 12 to 25 1 is a cross-sectional view schematically showing a light emitting element array ARR at various stages of manufacture according to an embodiment. Figures 12 to 22 The method of manufacturing the light emitting element array ARR is described below. Figures 12 to 22 Each of the above is used to describe one or more manufacturing steps or processes, and at the same time, various manufacturing steps or processes can be used to form a product such as at least one combination of Figures 1 to 5 In some embodiments, the method can be used to Figure 5 The first light emitting element LE1, the second light emitting element LE2, and the third light emitting element LE3 (or the semiconductor layers of the first light emitting element LE1, the second light emitting element LE2, and the third light emitting element LE3) are formed (eg, sequentially formed) in the unit area UA shown in FIG. Figures 23 to 25 The light emitting element array ARR according to the embodiment is schematically shown at various stages of manufacture, wherein the second insulating layer INS2 and the bonding electrode are further formed as part of the light emitting element array ARR. Figure 5 In addition to the components shown in FIG. 1 , the light emitting element array ARR according to the embodiment may further include components such as Figure 25 , a second insulating layer INS2 , one or more first bonding electrodes BDE1 , and at least one second bonding electrode BDE2 are shown in FIG.

[0166] refer to Figures 1 to 12 , a substrate SUB for manufacturing a light emitting element array ARR can be prepared.

[0167] The substrate SUB may be a semiconductor substrate suitable for epitaxial growth, and may be a semiconductor substrate containing the materials listed above. For example, the substrate SUB may be at least one of a sapphire substrate, a silicon substrate, and a GaN substrate (e.g., a GaN bulk substrate), but is not limited to these examples. The substrate SUB may include a light-emitting element area LEA for forming the light-emitting element LE, and a contact area CNA positioned around (or adjacent to) the light-emitting element area LEA when viewed in the third direction DR3.

[0168] When the substrate SUB is prepared, the first semiconductor layer SEM1 may be formed (e.g., grown, deposited, etc.) on the substrate SUB. In an embodiment, a buffer layer may be formed (e.g., formed first) on the substrate SUB before forming the first semiconductor layer SEM1, and thus the first semiconductor layer SEM1 may be formed on the buffer layer. For example, the buffer layer may be formed between the first semiconductor layer SEM1 and the substrate SUB in the third direction DR3.

[0169] The first semiconductor layer SEM1 may be made of at least one of the previously described semiconductor materials and may be doped to have a first conductivity type. For example, the first semiconductor layer SEM1 may be formed of an n-type semiconductor layer including GaN doped with an n-type dopant (eg, n-GaN).

[0170] refer to Figures 1 to 13 A first mask layer INS1A may be formed on the first semiconductor layer SEM1, wherein the first mask layer INS1A defines an opening corresponding to the first region (or overlapping with the first region in the third direction DR3) (for example, the opening exposes the first semiconductor layer SEM1 in the first region such as the third light-emitting element region LEA3), and the first mask layer INS1A covers one or more of the other regions (for example, the second light-emitting element region LEA2 and the first light-emitting element region LEA1) (or overlaps with them in the third direction DR3).

[0171] The first region may be a region for forming any one of the first light emitting element LE1, the second light emitting element LE2, and the third light emitting element LE3 to be formed in each unit area UA. For example, in the case where the third light emitting element LE3 is formed first among the first light emitting element LE1, the second light emitting element LE2, and the third light emitting element LE3, the first region may be the third light emitting element region LEA3. The order of forming the light emitting elements LE and the first region corresponding to the light emitting element LE formed first may vary according to the embodiment. Figures 13 to 25 Hereinafter, an embodiment in which the first region is the third light emitting element region LEA3 will be described.

[0172] The first mask layer INS1A may be formed as, for example Figure 5 The first portion INS1A of the first insulating layer INS1 (or a portion of the first portion INS1A) is shown in FIG. The first mask layer INS1A may be made of at least one of the aforementioned insulating materials described for the first insulating layer INS1, but the material of the first mask layer INS1A is not limited to these exemplary materials.

[0173] refer to Figures 1 to 14 , may be formed (eg, sequentially formed) (eg, grown, regrown, deposited, etc.) in the first region (eg, the third light emitting element region LEA3)

[0174] The second semiconductor layer SEM2, the light emitting layer EML, and the third semiconductor layer SEM3. In an embodiment, after first forming a seed layer SEM1A including the same material as the first semiconductor layer SEM1 (e.g., n-GaN including GaN and an n-type dopant) in the first region, the second semiconductor layer SEM2, the light emitting layer EML, and the third semiconductor layer SEM3 may be formed (e.g., sequentially formed) on the seed layer SEM1A in the first region.

[0175] The second semiconductor layer SEM2 may be made of a semiconductor material containing indium and may be doped to have a first conductivity type. For example, the second semiconductor layer SEM2 may be formed of an n-type semiconductor layer containing InGaN doped with an n-type dopant (e.g., n-InGaN), but the embodiment is not limited to this example. In an embodiment, when the third light-emitting element LE3 is formed in the first region, the second semiconductor layer SEM2 in the first region may be formed to have a single-layer structure.

[0176] The light-emitting layer EML may include a quantum well layer QWL containing indium. For example, the light-emitting layer EML may be formed to have a multi-quantum well structure, in which quantum well layers QWL containing indium and barrier layers BRL are alternately arranged. In an embodiment, the quantum well layer QWL may be made of a semiconductor material containing indium (e.g., InGaN), and the indium content of the quantum well layer QWL may vary according to the emission wavelength of the light-emitting element LE (e.g., the third light-emitting element LE3) formed (or to be formed) in the first region. In an embodiment, when the third light-emitting element LE3 formed in the first region is a blue light-emitting element that emits blue light, the quantum well layer QWL in the first region may contain an indium content in the range of about 10% to less than about 20%. In an embodiment, the barrier layer BRL may be made of at least one of the aforementioned semiconductor materials (e.g., GaN, AlGaN, or GaAlN), but the material is not limited to these examples.

[0177] As exemplified above, the third semiconductor layer SEM3 may be made of a semiconductor material containing indium and may be doped to have the second conductivity type. For example, the third semiconductor layer SEM3 may be formed of a p-type semiconductor layer containing InGaN doped with a p-type dopant (e.g., p-InGaN), but the materials and dopants are not limited to these examples. In an embodiment, the third semiconductor layer SEM3 may be formed to have a single-layer structure, but is not limited to a single-layer structure.

[0178] refer to Figures 1 to 15 A second mask layer INS1B may be formed on the first mask layer INS1A. The second mask layer INS1B defines an opening corresponding to the second region (or overlapping the second region in the third direction DR3) (for example, the opening exposes the first semiconductor layer SEM1 in the second region, such as the second light-emitting element region LEA2), and the second mask layer INS1B covers one or more of the other regions (for example, the third light-emitting element region LEA3 and the first light-emitting element region LEA1) (or overlaps therewith in the third direction DR3). An opening corresponding to the second region may also be formed in the first mask layer INS1A. The second mask layer INS1B may cover the semiconductor layers formed in the first region (for example, the first semiconductor layer SEM1 (or seed layer SEM1A), the second semiconductor layer SEM2, the light-emitting layer EML, and the third semiconductor layer SEM3 of the third light-emitting element LE3) (or overlap therewith in the third direction DR3).

[0179] The second region may be a region for forming any one of the first light emitting element LE1, the second light emitting element LE2, and the third light emitting element LE3 to be formed in each unit area UA. For example, in the case where the second light emitting element LE2 among the first light emitting element LE1, the second light emitting element LE2, and the third light emitting element LE3 is formed second, the second region may be the second light emitting element region LEA2. The order of forming the light emitting elements LE and the second region corresponding to the light emitting element LE formed second may vary according to the embodiment. Figures 15 to 25 Hereinafter, an embodiment in which the second region is the second light emitting element region LEA2 will be described.

[0180] The second mask layer INS1B may be formed as, for example Figure 5 1B (or a portion of the second portion INS1B) of the first insulating layer INS1 is shown in FIG. In an embodiment, the second mask layer INS1B may be made of at least one of the aforementioned insulating materials described for the first insulating layer INS1, and may be made of the same material as the first mask layer INS1A, but embodiments are not limited to these examples. For example, in some embodiments, the second mask layer INS1B may be made of a material different from that of the first mask layer INS1A. In some implementations, the first insulating layer INS1 may include multiple layers made of different insulating materials.

[0181] refer to Figures 1 to 16 , the second semiconductor layer SEM2, the light emitting layer EML, and the third semiconductor layer SEM3 may be formed (e.g., sequentially formed) (e.g., grown, regrown, deposited, etc.) in the second region (e.g., the second light emitting element region LEA2). In an embodiment, after a seed layer SEM1A including the same material as the first semiconductor layer SEM1 (e.g., n-GaN) is first formed in the second region, the second semiconductor layer SEM2, the light emitting layer EML, and the third semiconductor layer SEM3 may be formed (e.g., sequentially formed) on the seed layer SEM1A in the second region.

[0182] The second semiconductor layer SEM2 may be made of a semiconductor material containing indium and may be doped to have a first conductivity type. For example, the second semiconductor layer SEM2 may be formed of an n-type semiconductor layer containing InGaN doped with an n-type dopant (e.g., n-InGaN), but the embodiment is not limited to this example. In an embodiment, when the second light-emitting element LE2 is formed in the second region, the second semiconductor layer SEM2 in the second region may be formed to have a single-layer structure.

[0183] The light-emitting layer EML may include a quantum well layer QWL containing indium. For example, the light-emitting layer EML may be formed to have a multi-quantum well structure in which quantum well layers QWL containing indium and barrier layers BRL are alternately arranged. In an embodiment, the quantum well layer QWL may be made of a semiconductor material containing indium (e.g., InGaN), and the indium content of the quantum well layer QWL may vary depending on the emission wavelength of the light-emitting element LE (e.g., the second light-emitting element LE2) formed (or to be formed) in the second region. In an embodiment, when the second light-emitting element LE2 formed in the second region is a green light-emitting element that emits green light, the quantum well layer QWL in the second region may contain an indium content in the range of about 20% to less than about 30%. In an embodiment, the barrier layer BRL may be made of at least one of the aforementioned semiconductor materials (e.g., GaN, AlGaN, or GaAlN), but the material is not limited to these examples.

[0184] As exemplified above, the third semiconductor layer SEM3 may be made of a semiconductor material containing indium and may be doped to have the second conductivity type. For example, the third semiconductor layer SEM3 may be formed of a p-type semiconductor layer containing InGaN doped with a p-type dopant (e.g., p-InGaN), but the materials and dopants are not limited to these examples. In an embodiment, the third semiconductor layer SEM3 may be formed to have a single-layer structure, but is not limited to a single-layer structure.

[0185] refer to Figures 1 to 17 A third mask layer INS1C may be formed on the second mask layer INS1B. The third mask layer INS1C defines an opening corresponding to the third region (or overlapping the third region in the third direction DR3) (for example, the opening exposes the first semiconductor layer SEM1 in the third region such as the first light-emitting element region LEA1), and the third mask layer INS1C covers one or more of the other regions (for example, the third light-emitting element region LEA3 and the second light-emitting element region LEA2) (or overlaps with them in the third direction DR3). An opening corresponding to the third region may also be formed in the first mask layer INS1A and the second mask layer INS1B. The third mask layer INS1C may cover the semiconductor layers formed in the second region (for example, the first semiconductor layer SEM1 (or seed layer SEM1A), the second semiconductor layer SEM2, the light-emitting layer EML, and the third semiconductor layer SEM3 of the second light-emitting element LE2) (or overlap with them in the third direction DR3), and the third mask layer INS1C may cover the semiconductor layers formed in the first region (for example, the first semiconductor layer SEM1 (or seed layer SEM1A), the second semiconductor layer SEM2, the light-emitting layer EML, and the third semiconductor layer SEM3 of the third light-emitting element LE3) (or overlap with them in the third direction DR3).

[0186] The third region may be a region for forming any one of the first light emitting element LE1, the second light emitting element LE2, and the third light emitting element LE3 to be formed in each unit area UA. For example, in the case where the first light emitting element LE1 among the first light emitting element LE1, the second light emitting element LE2, and the third light emitting element LE3 is subsequently formed, the third region may be the first light emitting element region LEA1. The formation order of the light emitting elements LE and the third region corresponding to the subsequently formed light emitting element LE may vary according to the embodiment. Figures 17 to 25 Hereinafter, an embodiment in which the third region is the first light emitting element region LEA1 will be described.

[0187] The third mask layer INS1C may be formed as, for example Figure 5 1C (or a portion of the third portion INS1C) of the first insulating layer INS1 shown in FIG. In an embodiment, the third mask layer INS1C may be made of at least one of the aforementioned insulating materials described with respect to the first insulating layer INS1, and may be made of the same material as that of the first mask layer INS1A and the second mask layer INS1B, but the embodiment is not limited to this example.

[0188] refer to Figures 1 to 18 , the second semiconductor layer SEM2, the light emitting layer EML, and the third semiconductor layer SEM3 may be formed (e.g., sequentially formed) (e.g., grown, regrown, deposited, etc.) in the third region (e.g., the first light emitting element region LEA1). In an embodiment, after first forming a seed layer SEM1A including the same material as the first semiconductor layer SEM1 (e.g., n-GaN) in the third region, the second semiconductor layer SEM2, the light emitting layer EML, and the third semiconductor layer SEM3 may be formed (e.g., sequentially formed) on the seed layer SEM1A in the third region.

[0189] The second semiconductor layer SEM2 may be made of a semiconductor material containing indium and may be doped to have a first conductivity type. For example, the second semiconductor layer SEM2 may be formed of an n-type semiconductor layer containing InGaN doped with an n-type dopant (e.g., n-InGaN), but the embodiment is not limited to this example. In an embodiment, among the light emitting elements LE, a light emitting element LE (e.g., a first light emitting element LE1) in which the indium content of the light emitting layer EML is the highest may be formed in the third region. In some implementations, the second semiconductor layer SEM2 in the third region may be formed to have a plurality of layers including a first layer L1 containing indium and a second layer L2 alternately stacked with the first layer L1, such as in combination with Figures 7 to 10For example, the first layer L1 and the second layer L2 can be alternately formed (e.g., grown, regrown, deposited, etc.) on the first semiconductor layer SEM1 (e.g., the seed layer SEM1A) in the third region. Thus, a relatively high-quality light-emitting layer EML can be formed on the second semiconductor layer SEM2 in the third region.

[0190] The light-emitting layer EML may include a quantum well layer QWL containing indium. For example, the light-emitting layer EML may be formed to have a multi-quantum well structure, in which quantum well layers QWL containing indium and barrier layers BRL are alternately arranged. In an embodiment, the quantum well layer QWL may be made of a semiconductor material containing indium (e.g., InGaN), and the indium content of the quantum well layer QWL may vary according to the emission wavelength of the light-emitting element LE (e.g., the first light-emitting element LE1) formed (or to be formed) in the third region. In an embodiment, when the first light-emitting element LE1 formed in the third region is a red light-emitting element that emits red light, the quantum well layer QWL in the third region may contain an indium content in the range of about 30% to about 40%. In an embodiment, the barrier layer BRL may be made of at least one of the aforementioned semiconductor materials (e.g., GaN, AlGaN, or GaAlN), but the material is not limited to these examples.

[0191] As exemplified above, the third semiconductor layer SEM3 may be made of a semiconductor material containing indium and may be doped to have the second conductivity type. For example, the third semiconductor layer SEM3 may be formed of a p-type semiconductor layer containing InGaN doped with a p-type dopant (e.g., p-InGaN), but the materials and dopants are not limited to these examples. In an embodiment, the third semiconductor layer SEM3 may be formed to have a single-layer structure, but is not limited to a single-layer structure.

[0192] refer to Figures 1 to 19 A passivation layer INS1D (e.g., a protective layer or a fourth mask layer) may be formed on the third mask layer INS1C. The passivation layer INS1D may be formed entirely (or substantially entirely) on the semiconductor layer and the third mask layer INS1C to cover the semiconductor layer formed in the light emitting element region LEA (or overlap with it in the third direction DR3).

[0193] The passivation layer INS1D may be formed as, for example Figure 5. In an embodiment, the passivation layer INS1D may be formed of at least one of the aforementioned insulating materials described with respect to the first insulating layer INS1, and may be formed of the same material as the first mask layer INS1A, the second mask layer INS1B, and the third mask layer INS1C, but the material of the passivation layer INS1D is not limited to this example.

[0194] refer to Figures 1 to 20 , a reflective layer RFL may be formed on the first insulating layer INS1 including the first mask layer INS1A, the second mask layer INS1B, the third mask layer INS1C, and the passivation layer INS1D. For example, the reflective layer RFL may be formed entirely (or substantially entirely) on the first insulating layer INS1. The reflective layer RFL may be formed of at least one of the aforementioned materials (e.g., metal) described for the reflective layer RFL, but the material of the reflective layer RFL is not limited to this example.

[0195] refer to Figures 1 to 21 , a first opening OPN1 may be formed in the first insulating layer INS1 and the reflective layer RFL in each light emitting element area LEA. Furthermore, a second opening OPN2 may be formed in the first insulating layer INS1 and the reflective layer RFL in the contact area CNA. The first opening OPN1 and the second opening OPN2 may be formed simultaneously with each other, but embodiments are not limited to this example. The first opening OPN1 may expose a corresponding portion of the third semiconductor layer SEM3 formed in the corresponding light emitting element area LEA. The second opening OPN2 may expose a portion of the first semiconductor layer SEM1 formed in the contact area CNA.

[0196] refer to Figures 1 to 22 , a first electrode ET1 electrically connected to the third semiconductor layer SEM3 may be formed in the first opening OPN1, and a second electrode ET2 electrically connected to the first semiconductor layer SEM1 may be formed in the second opening OPN2. The first electrode ET1 and the second electrode ET2 may be formed of at least one of the aforementioned conductive materials, but the materials of the first electrode ET1 and the second electrode ET2 are not limited to these examples.

[0197] Combined with at least Figure 5 The light emitting element array ARR described by et al. can be referred to Figures 12 to 22 In an embodiment, such as Figures 23 to 25 As shown in , the light emitting element array ARR may further include at least one of a second insulating layer INS2 covering the light emitting elements LE, a first bonding electrode BDE1 electrically connected to the first electrode ET1, and a second bonding electrode BDE2 electrically connected to the second electrode ET2.

[0198] refer to Figures 1 to 23 A second insulating layer INS2 may be formed on the light emitting element LE and the reflective layer RFL. In an embodiment, the second insulating layer INS2 may be formed to have a single-layer structure or a multi-layer structure including an organic insulating material, and the upper surface of the second insulating layer INS2 may be substantially flat (or planar). For example, in some embodiments, the second insulating layer INS2 and the upper surface of the substrate SUB may be parallel (or substantially parallel) to each other.

[0199] refer to Figures 1 to 24 , a first through hole VH1 may be formed in the second insulating layer INS2 in each light-emitting element area LEA. Furthermore, a second through hole VH2 may be formed in the second insulating layer INS2 in the contact area CNA. The first through hole VH1 and the second through hole VH2 may be formed simultaneously, but embodiments are not limited to this example. The first through hole VH1 may expose the first electrode ET1 formed in the corresponding light-emitting element area LEA. The second through hole VH2 may expose the second electrode ET2 formed in the contact area CNA.

[0200] refer to Figures 1 to 25 , a bonding electrode (or wiring) can be formed in each through-hole. For example, the corresponding first bonding electrode BDE1 can be formed to fill the corresponding first through-hole VH1 formed in the light-emitting element area LEA, and the second bonding electrode BDE2 can be formed to fill the second through-hole VH2 formed in the contact area CNA. The first bonding electrode BDE1 and the second bonding electrode BDE2 can be formed by a damascene process, etc., but the embodiment is not limited to this example.

[0201] In an embodiment, a subsequent process such as a chemical mechanical polishing (CMP) process may be performed after the formation process of at least one of the first bonding electrode BDE1 and the second bonding electrode BDE2. In an embodiment, when an electronic device (e.g., a display device) including a light-emitting element LE is manufactured, a subsequent process such as a process of bonding the light-emitting element LE to (or with) a substrate of the electronic device (e.g., a semiconductor circuit substrate, a backplane substrate, or other substrate of the display device) may be performed.

[0202] For example, a method for manufacturing a display device using a light emitting element array ARR according to some embodiments may include: manufacturing a light emitting element array ARR as described above or preparing a light emitting element array ARR manufactured according to at least one of the aforementioned embodiments; and combining the light emitting elements LE of the light emitting element array ARR onto (or combining with) a semiconductor circuit substrate (or a backplane substrate or other substrate) of a display panel. For example, using a light emitting element array ARR in combination with, for example Figures 12 to 25The method for manufacturing a display device with the light emitting element array ARR manufactured as described above may further include: combining the light emitting element array ARR with a substrate having a structure such as Figure 28 and Figure 29 The semiconductor circuit substrate of the display panel 100 (eg, in Figure 28 and Figure 29 The semiconductor circuit substrate 110 shown in FIG. 1 is formed on (or combined with) a backplane substrate (or other substrate).

[0203] In an embodiment, the substrate SUB may be separated from the light-emitting element LE before or after the bonding process. In some implementations, the substrate SUB may be separated from the light-emitting element LE during the bonding process. In some embodiments, the substrate SUB may be embedded in (or otherwise used in conjunction with) an electronic device without being separated from the light-emitting element LE.

[0204] According to some embodiments, light-emitting elements LE that emit light of different colors can be manufactured on a substrate SUB (e.g., one substrate SUB). For example, a first light-emitting element LE1, a second light-emitting element LE2, and a third light-emitting element LE3 that emit light of different colors can be formed (e.g., sequentially formed) on a substrate SUB using, for example, one or more growth and / or regrowth methods. The order in which the first light-emitting element LE1, the second light-emitting element LE2, and the third light-emitting element LE3 (or the semiconductor layers of the first light-emitting element LE1, the second light-emitting element LE2, and the third light-emitting element LE3) are formed can vary depending on the embodiment. According to some embodiments, by manufacturing light-emitting elements LE that emit light of different colors on one substrate SUB (or one substrate SUB), manufacturing efficiency can be improved and manufacturing costs of the light-emitting elements LE and electronic devices (e.g., display devices) including the light-emitting elements LE can be reduced.

[0205] In an embodiment, the light-emitting element array ARR can be formed on the substrate SUB with a size and / or arrangement structure corresponding to the pixel arrangement structure of a display device, etc., in which the light-emitting elements LE are to be used, or the size, arrangement structure, arrangement spacing, etc. of the light-emitting elements LE provided in the pixels. Therefore, (multiple) bonding processes, etc. can be simplified or facilitated, and the manufacturing efficiency of the display device including the light-emitting elements LE can be further improved. In some implementations, a relatively high-resolution display device can be more easily manufactured.

[0206] Figure 26 is a perspective view schematically showing a display device 10 according to an embodiment. Figure 27 is a schematic diagram showing an embodiment of the Figure 26 FIG. 1 is a plan view of an example of area A3.

[0207] refer to Figure 26and Figure 27 , the display device 10 according to the embodiment may include a display panel 100 having a display area DA and a non-display area NDA.

[0208] The display panel 100 may have a quadrangular planar shape having long sides in the first direction DR1 and short sides in the second direction DR2. Figure 26 and Figure 27 , the first direction DR1 may represent the horizontal direction of the display panel 100 on the plane, and the second direction DR2 may represent the vertical direction of the display panel 100 on the plane, but the embodiment is not limited to this example. The first direction DR1 may represent the vertical direction of the display panel 100 on the plane, and the second direction DR2 may represent the horizontal direction of the display panel 100 on the plane. The third direction DR3 may represent the thickness direction or height direction of the display panel 100. However, the planar shape of the display panel 100 is not limited to this example, and the display panel 100 may have a different planar shape. For example, the display panel 100 may have at least one of a polygonal planar shape other than a quadrilateral planar shape, a circular planar shape, an elliptical planar shape, an oval planar shape, and an irregular (or free) planar shape.

[0209] The display area DA may be an area where an image is displayed, and the non-display area NDA may be an area where no image is displayed. In an embodiment, the planar shape of the display area DA may follow (or may be similar to) the planar shape of the display panel 100, but the embodiment is not limited to this example. Figure 26 An embodiment in which the display area DA has a quadrilateral planar shape is shown. The display area DA may be provided in the central area of the display panel 100. In a view viewed in the third direction DR3, the non-display area NDA may be provided adjacent to the display area DA (e.g., at least partially surrounding the display area DA). For example, the non-display area NDA may surround the display area DA in a view viewed in the third direction DR3.

[0210] The display panel 100 may include a plurality of pixels PX arranged in the display area DA. For example, the display panel 100 may include a first pixel PX1 that emits light of a first color, a second pixel PX2 that emits light of a second color, and a third pixel PX3 that emits light of a third color. In an embodiment, the first color may be red, the second color may be green, and the third color may be blue, but the colors are not limited to this example. At least one first pixel PX1, at least one second pixel PX2, and at least one third pixel PX3 that are adjacent to each other may constitute a unit pixel UPX that can emit light of various colors. For example, a first pixel PX1, a second pixel PX2, and a third pixel PX3 that are adjacent to each other in the Kth (where K is a natural number greater than 0) row of the display area DA may constitute a unit pixel UPX. The number, type, and / or arrangement structure of the pixels PX that constitute the unit pixel UPX may vary depending on the embodiment.

[0211] Each pixel PX may include at least one light emitting element LE. For example, each pixel PX may include a single light emitting element LE or may include a plurality of light emitting elements LE that emit light of the same color.

[0212] In an embodiment, a pixel PX may include a light-emitting element LE that emits light of different colors. For example, a first pixel PX1, a second pixel PX2, and a third pixel PX3 may include light-emitting elements LE that emit light of a first color, a second color, and a third color, respectively. However, embodiments are not limited to this example. For example, a first pixel PX1, a second pixel PX2, and a third pixel PX3 may include light-emitting elements LE that emit light of the same color, and a light conversion pattern (for example, a wavelength conversion pattern including, for example, quantum dots) and / or a color filter may be provided in the emission region of the first pixel PX1, the second pixel PX2, and / or the third pixel PX3 to convert or control the color of light emitted from the light-emitting element LE provided in the corresponding pixel PX.

[0213] In an embodiment, the pixel PX may include a light emitting element LE according to at least one of the aforementioned embodiments. For example, each first pixel PX1 may include one or more first light emitting elements LE1 including a second semiconductor layer SEM2 having a multi-layer structure. In addition, each second pixel PX2 may include one or more second light emitting elements LE2 including a second semiconductor layer SEM2 having a single-layer structure, and each third pixel PX3 may include one or more third light emitting elements LE3 including a second semiconductor layer SEM2 having a single-layer structure.

[0214] In an embodiment, the pixels PX may be arranged in the display area DA in a matrix form, a stripe form, or any other form or pattern. The sizes of the pixels PX (or the emission areas of the pixels PX) may be substantially identical to or different from each other.

[0215] In an embodiment, the pixel PX may have a quadrilateral planar shape, such as a rectangular planar shape or a diamond planar shape, but the embodiment is not limited to these examples. For example, the pixel PX may have at least one of another polygonal planar shape (e.g., a hexagonal planar shape, a diamond-like planar shape, etc.), a circular planar shape, an elliptical planar shape, an oval planar shape, a free planar shape, and any other planar shape.

[0216] The non-display area NDA may include a first common voltage supply area CVA1 , a second common voltage supply area CVA2 , a first pad area PDA1 , a second pad area PDA2 , and a peripheral area PHA.

[0217] In a view such as that viewed in the third direction DR3, the first common voltage supply area CVA1 may be disposed between the first pad area PDA1 and the display area DA. In a view such as that viewed in the third direction DR3, the second common voltage supply area CVA2 may be disposed between the second pad area PDA2 and the display area DA. Each of the first common voltage supply area CVA1 and the second common voltage supply area CVA2 may include a common electrode connection portion CVS electrically connected to a common electrode of the pixel PX, a second pixel power line, and the like. A second pixel voltage (e.g., a common voltage) may be supplied to the pixel PX via the common electrode connection portion CVS.

[0218] The common electrode connection portion CVS may be disposed in the common voltage supply area (eg, the first common voltage supply area CVA1 and / or the second common voltage supply area CVA2) of the non-display area NDA and may include a conductive material (eg, a metal material such as aluminum (Al)). Figure 26 and Figure 27 The display device 10 is schematically shown in which the common electrode connection portion CVS is located in the non-display area NDA, but the embodiment is not limited to this example. For example, the common electrode connection portion CVS may be located in the display area DA, in the non-display area NDA, or in both the display area DA and the non-display area NDA.

[0219] The common electrode connection portion CVS of the first common voltage supply area CVA1 may be electrically connected to any one of the first pads PD1 of the first pad area PDA1. For example, the common electrode connection portion CVS of the first common voltage supply area CVA1 may receive the second pixel voltage (e.g., the common voltage) from any one of the first pads PD1 of the first pad area PDA1.

[0220] The first pad PD1 may be disposed in the first pad area PDA1. The first pad PD1 may be electrically connected to a circuit board (not shown) via at least one conductive connection member (e.g., wiring, transmission line, etc.). For example, the first pad PD1 may be electrically connected to a circuit pad disposed on the circuit board via at least one wiring.

[0221] The common electrode connection portion CVS of the second common voltage supply area CVA2 can be electrically connected to any one of the second pads of the second pad area PDA2. For example, the common electrode connection portion CVS of the second common voltage supply area CVA2 can receive the second pixel voltage (e.g., the common voltage) from any one of the second pads of the second pad area PDA2. In an embodiment, the display panel 100 may not include the second common voltage supply area CVA2.

[0222] In a view in the third direction DR3, the first pad area PDA1 may be provided on one side (eg, upper side) of the display panel 100. The first pad area PDA1 may include first pads PD1 electrically connectable to an external circuit board.

[0223] In the view in the third direction DR3, the second pad area PDA2 may be provided on one side (or one side) (e.g., the lower side) of the display panel 100. The second pad area PDA2 may include a second pad that may be electrically connected to an external circuit board. In an embodiment, the display panel 100 may not include the second pad area PDA2.

[0224] The second pad may be provided in the second pad area PDA2 of the non-display area NDA. The second pad may be electrically connected to a circuit board (not shown) via at least one conductive connection member (such as a wiring, a transmission line, etc.). For example, the second pad may be electrically connected to a circuit pad provided on the circuit board via one or more wirings.

[0225] The peripheral area PHA may be an area of the non-display area NDA excluding the first common voltage supply area CVA1, the second common voltage supply area CVA2, the first pad area PDA1, and the second pad area PDA2. In a view in the third direction DR3, the peripheral area PHA may at least partially surround (or enclose) not only the display area DA, but also at least partially surround (or enclose) the first common voltage supply area CVA1, the second common voltage supply area CVA2, the first pad area PDA1, and the second pad area PDA2. In some implementations, in a view in the third direction DR3, the peripheral area PHA may be disposed between at least two of the display area DA, the first common voltage supply area CVA1, the second common voltage supply area CVA2, the first pad area PDA1, and the second pad area PDA2.

[0226] Figure 28 is a cross-sectional view schematically showing a display panel 100 according to an embodiment. Figure 29 is a cross-sectional view schematically showing a display panel 100 according to an embodiment. For example, Figure 28 and Figure 29 Schematically shows the Figure 27 Implementation of a cross section of the display panel 100 taken along the section line X2 - X2 ′. Figure 28 and Figure 29 The cross section shown in FIG schematically illustrates a first pixel PX1, a second pixel PX2, and a third pixel PX3 in a unit pixel UPA located in the display area DA. The unit pixel UPA may correspond to the previously described unit pixel UPX. Figure 28 and Figure 29 Different embodiments with regard to the structure of the protection layer PRL are schematically shown.

[0227] Figure 28 and Figure 29 An embodiment in which the display device 10 is a light emitting diode on silicon (LEDoS) (wherein the light emitting diode is formed as a light emitting element LE on a semiconductor circuit substrate 110 formed via at least one semiconductor process using a silicon wafer) is schematically shown. However, the device including the light emitting element LE is not limited to this example. For example, the light emitting element LE (or the light emitting element array ARR including the light emitting element LE) manufactured according to one or more of the aforementioned embodiments can be applied to (or used in combination with) display devices of different types and / or structures, or can be applied to (or used in combination with) devices of different types and / or structures such as lighting devices.

[0228] refer to Figures 1 to 29 The display panel 100 may include a semiconductor circuit substrate 110 (or a backplane substrate or other substrates) and a light emitting element layer 120 .

[0229] In an embodiment, the display panel 100 may further include an additional component (or additional element) between the semiconductor circuit substrate 110 and the light emitting element layer 120, for example, in the third direction DR3. For example, the display panel 100 may further include: connection electrodes (e.g., one or more first connection electrodes CNE1 and one or more second connection electrodes CNE2) disposed on the semiconductor circuit substrate 110 and electrically connecting corresponding pixel circuits PXC, pixel electrodes PXE, and at least one second pixel power line VSL of the semiconductor circuit substrate 110 to corresponding light emitting elements LE of the light emitting element layer 120; and a third insulating layer INS3 disposed near at least one of the first connection electrode CNE1 and the second connection electrode CNE2 and covering the semiconductor circuit substrate 110 (or overlapping the semiconductor circuit substrate 110 in the third direction DR3).

[0230] In an embodiment, the display panel 100 may further include at least one additional component (or additional element) disposed on the light emitting element layer 120. For example, the display panel 100 may further include a protective layer PRL disposed on the light emitting element layer 120. The display panel 100 may further include a light output structure (e.g., a lens, a window, etc.) disposed on the protective layer PRL.

[0231] The semiconductor circuit substrate 110 may include a display area DA in which a pixel circuit PXC of a pixel PX is formed. The semiconductor circuit substrate 110 may also include a substrate incorporating Figure 26 and Figure 27 In some embodiments, the semiconductor circuit substrate 110 may further include a common electrode connection portion CVS, a first pad PD1, and / or a second pad disposed in the non-display area NDA.

[0232] The semiconductor circuit substrate 110 may include a base substrate SB, pixel circuits PXC disposed or formed on the base substrate SB, and pixel electrodes PXE (or first bonding pads) electrically connected to the respective pixel circuits PXC. The semiconductor circuit substrate 110 may also include wiring (or other circuit components) electrically connected to the pixels PX. For example, the semiconductor circuit substrate 110 may also include signal lines and power lines (e.g., first pixel power lines to which a first pixel voltage is applied) electrically connected to the pixel circuits PXC, and second pixel power lines VSL to which a second pixel voltage may be applied.

[0233] In an embodiment, the semiconductor circuit substrate 110 may be formed by at least one semiconductor process using a silicon wafer. For example, the base substrate SB may be a silicon wafer. In an embodiment, the base substrate SB may be made of single crystal silicon. However, it is contemplated that any other suitable base substrate SB may be used.

[0234] The pixel circuit PXC may be provided in the semiconductor circuit substrate 110 to correspond to a region where a corresponding pixel PX is provided or formed (e.g., overlapped with the region in the third direction DR3). In an embodiment, each of the pixel circuits PXC may include a complementary metal oxide semiconductor (CMOS) circuit formed using at least one semiconductor process. In an embodiment, each of the pixel circuits PXC may include at least one transistor and at least one capacitor formed using at least one semiconductor process. Figure 28 and Figure 29 The positions of the pixel circuits PXC provided in (or as a part of) the first pixel PX1 , the second pixel PX2 , and the third pixel PX3 are schematically shown as examples of elements provided in the semiconductor circuit substrate 110 .

[0235] The pixel electrode PXE may be disposed on the corresponding pixel circuit PXC. The pixel electrode PXE may be electrically connected to the corresponding pixel circuit PXC. For example, the pixel circuit PXC of each pixel PX may be electrically connected to the pixel electrode PXE of the corresponding pixel PX. The pixel electrode PXE may receive a first pixel voltage (e.g., an anode voltage) from the pixel circuit PXC, respectively.

[0236] In an embodiment, the pixel electrode PXE may be integrally formed with the corresponding pixel circuit PXC, and / or the pixel electrode PXE may be integral with the corresponding pixel circuit PXC. For example, the pixel electrode PXE may be an exposed electrode protruding from the top surface of the corresponding pixel circuit PXC.

[0237] The pixel electrode PXE may include at least one conductive material. For example, the pixel electrode PXE may include, but is not limited to, at least one of copper (Cu), titanium (Ti), silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), and calcium (Ca).

[0238] The pixel electrodes PXE can be electrically connected to corresponding light-emitting elements LE via the first connection electrode CNE1. For example, the pixel electrode PXE of the first pixel PX1 can be electrically connected to the first light-emitting element LE1 of the first pixel PX1 via the first connection electrode CNE1 disposed in (or as a part of) the first pixel PX1. The pixel electrode PXE of the second pixel PX2 can be electrically connected to the second light-emitting element LE2 of the second pixel PX2 via the first connection electrode CNE1 disposed in (or as a part of) the second pixel PX2. The pixel electrode PXE of the third pixel PX3 can be electrically connected to the third light-emitting element LE3 of the third pixel PX3 via the first connection electrode CNE1 disposed in (or as a part of) the third pixel PX3.

[0239] The second pixel power line VSL may be disposed in the contact area CNA and electrically connected to the second connection electrode CNE2 and to the second electrode ET2 electrically connected to the first semiconductor layer SEM1 of the light emitting element LE through the second connection electrode CNE2.

[0240] The third insulating layer INS3 may be provided on the semiconductor circuit substrate 110. The third insulating layer INS3 may include openings corresponding to the first connection electrode CNE1 and the second connection electrode CNE2. For example, in a view perpendicular to the third direction DR3, the third insulating layer INS3 may surround (or contact, for example, directly contact) side surfaces (or peripheral surfaces or lateral surfaces) of the first connection electrode CNE1 and the second connection electrode CNE2.

[0241] The third insulating layer INS3 may include at least one insulating material and may have a single-layer or multi-layer structure. In an embodiment, the third insulating layer INS3 may include an inorganic insulating material (eg, silicon oxide (SiO x ), silicon nitride (SiN x ), aluminum oxide (Al x O y ), titanium oxide (Ti x O y ), hafnium oxide (HfO x ) and at least one of any other inorganic insulating materials), but is not limited to these examples.

[0242] The first and second connection electrodes CNE1 and CNE2 may include a conductive metal. For example, the first and second connection electrodes CNE1 and CNE2 may include at least one of gold (Au), copper (Cu), tin (Sn), titanium (Ti), aluminum (Al), and silver (Ag). The first and second connection electrodes CNE1 and CNE2 may serve as a bonding metal (or bonding structure) for physically and / or electrically connecting and / or adhering the semiconductor circuit substrate 110 to the light emitting element layer 120.

[0243] The light emitting element layer 120 may include the second electrode ET2 of the pixel PX and the light emitting element LE. In an embodiment, the light emitting element layer 120 may be formed by combining Figure 5 At least one of the light emitting element arrays ARR in the embodiments described in the above, or according to the combination of Figures 12 to 25 At least one of the light emitting element arrays ARR manufactured in the described embodiments is formed. For example, as combined Figure 25 The described light emitting element array ARR (or the light emitting elements LE of the light emitting element array ARR) may be coupled to (or combined with) the first connection electrode CNE1 and the second connection electrode CNE2 to form the light emitting element layer 120 of the display panel 100 .

[0244] The light emitting element LE may have a structure described in conjunction with at least one of the aforementioned embodiments. For example, each of the light emitting elements LE may include: a first semiconductor layer SEM1 doped to have a first conductivity type; a second semiconductor layer SEM2 provided on one surface (or one surface) of the first semiconductor layer SEM1 (e.g., Figure 28 The light-emitting elements LE further include a first semiconductor layer SEM2 (shown in FIG. 1 ), a lower surface thereof (shown in FIG. 2 ), doped to have a first conductivity type, and containing indium; a light-emitting layer EML disposed on one surface (or one surface) of the second semiconductor layer SEM2 and containing indium; and a third semiconductor layer SEM3 disposed on one surface (or one surface) of the light-emitting layer EML and doped to have a second conductivity type. In an embodiment, each of the light-emitting elements LE may further include a first electrode ET1 electrically connected to the third semiconductor layer SEM3. In an embodiment, the second electrode ET2 may be electrically connected to the first semiconductor layer SEM1 of the light-emitting element LE.

[0245] The first electrode ET1 of the light emitting element LE may be physically and / or electrically connected to the first connection electrode CNE1 via the first bonding electrode BDE1. The second electrode ET2 electrically connected to the first semiconductor layer SEM1 of the light emitting element LE may be physically and / or electrically connected to the second connection electrode CNE2 via the second bonding electrode BDE2. In an embodiment, the light emitting element LE may be formed on a manufacturing substrate (or a manufacturing substrate) (e.g., on a substrate such as Figure 5The display panel 100 may be provided on a substrate SUB) shown in FIG. 1 and may be electrically connected to the pixel circuit PXC.

[0246] In some embodiments, the indium content of the light-emitting layer EML of the first light-emitting element LE1 may be higher than the indium content of the light-emitting layer EML of the second light-emitting element LE2 and the third light-emitting element LE3. In some implementations, the second semiconductor layer SEM2 of the first light-emitting element LE1 may be formed to have multiple layers, the multiple layers including the first layer L1 containing indium and the second layer L2 disposed between the first layer L1. The second semiconductor layer SEM2 of at least one of the second light-emitting element LE2 and the third light-emitting element LE3 may be formed to have a single layer containing indium.

[0247] At least because the light emitting element array ARR (or light emitting element LE) can be bonded to (or bonded to) the semiconductor circuit substrate 110, a pixel PX including a light emitting element LE and a pixel circuit PXC can be formed. For example, a first pixel PX1 can include a first light emitting element LE1 and a pixel circuit PXC electrically connected to the first light emitting element LE1. A second pixel PX2 can include a second light emitting element LE2 and a pixel circuit PXC electrically connected to the second light emitting element LE2. A third pixel PX3 can include a third light emitting element LE3 and a pixel circuit PXC electrically connected to the third light emitting element LE3.

[0248] In an embodiment, the substrate SUB used as a manufacturing substrate for manufacturing the light emitting element LE may be substantially transparent, and the light emitting element LE may not be separated from the substrate SUB. Figure 28 As shown in FIG, the substrate SUB may be provided in the display panel 100 together with the light emitting element LE or provided as a part of the display panel 100 to form the protection layer PRL.

[0249] In some embodiments, the substrate SUB may be separated from the light emitting element LE before, after, or during the bonding process, and a separate protection layer PRL may be provided (or formed) on the light emitting element LE. Figure 29 As shown in FIG, a separate protection layer PRL may be provided (or formed) on the first semiconductor layer SEM1 of the light emitting element LE separated from the substrate SUB. In an embodiment, the protection layer PRL may include at least one of a capping layer CPL and an overcoat layer OCL.

[0250] The capping layer CPL may be entirely (or substantially entirely) disposed in the display area DA to cover the light emitting element LE (or overlap the light emitting element LE in the third direction DR3 ). In an embodiment, the capping layer CPL may include an inorganic material.

[0251] The overcoat layer OCL may be entirely (or substantially entirely) disposed on the capping layer CPL. The overcoat layer OCL may include a material capable of protecting the light emitting element layer 120 and the like.

[0252] Figure 30 is a cross-sectional view schematically showing a display panel 100 according to an embodiment. For example, Figure 30 Schematically shows the Figure 27 The embodiment of the cross section of the display panel 100 taken along the section line X2-X2' is combined with Figure 28 and Figure 29 The described implementations are different.

[0253] refer to Figures 1 to 30 , the display panel 100 may include using a combination of Figure 6 The light emitting element array ARR of at least one of the described embodiments forms the light emitting element layer 120. For example, the light emitting element LE may include a transparent electrode CTE disposed on the third semiconductor layer SEM3.

[0254] The transparent electrode CTE may be electrically connected to the second pixel power line VSL in the contact area CNA through the reflective layer RFL. In some implementations, the third semiconductor layer SEM3 of the light emitting element LE may be commonly electrically connected to the second pixel power line VSL.

[0255] In an embodiment, combined with Figure 6 A portion of the light emitting element array ARR described (in which the first semiconductor layers SEM1 of the light emitting elements LE are formed integrally with each other (or are integrated with each other)) (for example, in Figure 6Before the light-emitting element LE is bonded to (or bonded to) the semiconductor circuit substrate 110, the seed layer SEM1A of each light-emitting element LE may be separated from the light-emitting element LE, and only the seed layer SEM1A of each light-emitting element LE may remain in each light-emitting element LE as part of the first semiconductor layer SEM1. The seed layer SEM1A may be electrically connected to the corresponding pixel circuit PXC of the pixel PX. For example, the seed layer SEM1A of each light-emitting element LE may be disposed on the corresponding first connection electrode CNE1 of the corresponding pixel PX as the first semiconductor layer SEM1 of the corresponding light-emitting element LE, and may be electrically connected to the pixel electrode PXE of the corresponding pixel PX via the corresponding first connection electrode CNE1. In some embodiments, the light-emitting element LE may be bonded to (or bonded to) the first connection electrode CNE1, and at least a portion of the seed layer SEM1A may also be separated from the light-emitting element LE. For example, before the remaining portion of the seed layer SEM1A is coupled to (or with) the first connection electrode CNE1 , at least a portion of the seed layer SEM1A may be removed together with the first semiconductor layer SEM1 .

[0256] The second insulating layer INS2 may be disposed on the light emitting element LE and the reflective layer RFL. The protective layer PRL may be disposed on the second insulating layer INS2. In an embodiment, the protective layer PRL may be a single layer or a multilayer. In an embodiment, the protective layer PRL may be formed by combining Figure 29 The described capping layer CPL or the overcoat layer OCL may be formed, or may include both the capping layer CPL and the overcoat layer OCL.

[0257] Figure 31 2 is a diagram schematically showing a virtual reality device 1 including a display device 10_1 according to an embodiment.

[0258] refer to Figure 31 The virtual reality device 1 according to the embodiment may be a glasses-type device. The virtual reality device 1 according to the embodiment may include a display device 10_1, a left lens 10a, a right lens 10b, a support frame 20, temples 30a and 30b, a reflective member 40, and a display device housing 50.

[0259] although Figure 31The virtual reality device 1 is schematically shown as including temples 30a and 30b, but embodiments are not limited to this example. For example, the virtual reality device 1 may be applied to (or used as part of) a head-mounted display that includes a headband that can be worn on the head in place of temples 30a and 30b. The virtual reality device 1 according to some embodiments may also be applied to (or used as part of) various other electronic devices.

[0260] The display device housing 50 may house the display device 10_1 and the reflective member 40. The image displayed on the display device 10_1 may be reflected by the reflective member 40 and provided to the user's right eye through the right lens 10b. Thus, the user may view the virtual reality image displayed on the display device 10_1 through the right eye.

[0261] although Figure 31 The display device housing 50 is schematically shown as being positioned at the right end of the support frame 20, but embodiments are not limited to this example. For example, the display device housing 50 may be positioned at the left end of the support frame 20, and in some implementations, the image displayed on the display device 10_1 may be reflected by the reflective member 40 and presented to the user's left eye through the left lens 10a. Thus, the user can view the virtual reality image displayed on the display device 10_1 through their left eye. In some embodiments, the display device housing 50 may be positioned at both the left and right ends of the support frame 20, or between the left and right ends of the support frame 20. In this manner, the user can view the virtual reality image displayed on the display device 10_1 through both their left and right eyes.

[0262] Figure 32 is a diagram schematically illustrating a smart device including a display device 10_2 according to an embodiment.

[0263] refer to Figure 32, the display device 10_2 according to the embodiment can be applied to a smart watch 2 which is one of the smart devices (or applied as a part thereof). The planar shape of the clock display of the smart watch 2 can follow (or correspond to) the planar shape of the display device 10_2. For example, in the case where the display device 10_2 according to the embodiment has a planar shape (such as a circular planar shape or an elliptical planar shape), the clock display of the smart watch 2 can also have a corresponding planar shape (such as a corresponding circular planar shape or a corresponding elliptical planar shape). In the case where the display device 10_2 according to the embodiment has a quadrilateral planar shape, the clock display of the smart watch 2 can also have a corresponding quadrilateral planar shape. However, the embodiment is not limited to these examples, and the clock display of the smart watch 2 may not follow (or correspond to) the planar shape of the display device 10_2.

[0264] Figure 33 Schematically shows a car dashboard and a central instrument panel including display devices 10_a, 10_b, 10_c, 10_d and 10_e according to an embodiment. For example, Figure 33 Vehicles to which the display devices 10_a, 10_b, 10_c, 10_d, and 10_e according to the embodiments are applied or used are schematically shown.

[0265] refer to Figure 33 The display devices 10_a, 10_b, and 10_c according to the embodiment can be applied to at least one of a vehicle's instrument panel (or its central information display (CID)) and a central instrument panel of the vehicle (or applied as a part thereof). In some implementations, the display devices 10_d and 10_e according to the embodiment can be applied to (or as a part of) a room mirror display (or a cockpit mirror display) that replaces a side mirror of the vehicle, wherein the side mirror is configured to provide a corresponding external side view of the vehicle and / or an external environment adjacent to the corresponding external side of the vehicle.

[0266] Figure 34 10_3 is a diagram schematically illustrating a transparent display device including a display device 10_3 according to an embodiment.

[0267] refer to Figure 34The display device 10_3 according to an embodiment can be applied to a transparent display device (or formed as part of a transparent display device). The transparent display device can display an image IM and can also transmit light. Therefore, a user located in front of the transparent display device can see not only the image IM displayed on the display device 10_3, but also an object RS or background located behind the transparent display device. In the case where the display device 10_3 is applied to a transparent display device (or applied as part thereof), the display panel 100 may include a light-transmitting portion configured to transmit light and / or may be formed on a substrate member made of a material configured to transmit light.

[0268] Although the embodiments described above have been described in some detail for purposes of clarity of understanding, it will be apparent that certain changes and modifications may be implemented within the scope of the appended claims. It should be noted that there are many alternative ways of implementing the processes, systems, and apparatus of the disclosed embodiments. Therefore, the embodiments are to be considered as illustrative rather than restrictive, and the embodiments are not to be limited to the details given herein.

Claims

1. A light emitting element array comprising: substrate; as well as A light-emitting element is provided on the substrate, and the light-emitting element includes: a first light-emitting element configured to emit light of a first color; and a second light emitting element configured to emit light of a second color different from the first color, wherein Each of the light emitting elements comprises: a first semiconductor layer; a second semiconductor layer disposed on the first semiconductor layer, the second semiconductor layer being doped to have a first conductivity type and containing indium; a light-emitting layer disposed on the second semiconductor layer, the light-emitting layer comprising indium; and a third semiconductor layer, disposed on the light emitting layer, wherein the third semiconductor layer is doped to have a second conductivity type; The indium content of the light-emitting layer of the first light-emitting element is higher than the indium content of the light-emitting layer of the second light-emitting element. The second semiconductor layer of the first light emitting element is a multilayer structure including a first layer containing indium and a second layer alternately stacked with the first layer, and The second semiconductor layer of the second light-emitting element has a single-layer structure including indium.

2. The light emitting element array according to claim 1, wherein Each of the first layers of the first light emitting element is an InGaN layer containing a dopant of the first conductivity type, and Each of the second layers of the first light-emitting elements is a GaN layer.

3. The light emitting element array according to claim 2, wherein: The second semiconductor layer of the second light-emitting element is a single InGaN layer containing a dopant of the first conductivity type.

4. The light emitting element array according to claim 2, wherein: A thickness of each of the first layers of the first light-emitting element is greater than a thickness of each of the second layers of the first light-emitting element.

5. The light emitting element array according to claim 4, wherein The thickness of each of the first layers of the first light-emitting element is in a range of 10 nm to 20 nm.

6. The light emitting element array according to claim 5, wherein The thickness of each of the second layers of the first light-emitting element is less than or equal to 5 nm and greater than 0 nm.

7. The light emitting element array according to claim 1, wherein The indium content of at least one of the first layers of the first light-emitting element is different from the indium content of at least one other of the first layers of the first light-emitting element.

8. The light emitting element array according to claim 7, wherein: The second semiconductor layer of the first light emitting element includes: A first stack includes one or more first pairs of layers disposed on the first semiconductor layer, each of the one or more first pairs of layers including a first layer among the first layers and a second layer among the second layers; a second stack comprising one or more second pairs of layers disposed on the first stack, each of the one or more second pairs of layers comprising a first layer among the first layers and a second layer among the second layers; a third stack comprising one or more third pairs of layers disposed on the second stack, each of the one or more third pairs of layers comprising a first layer among the first layers and a second layer among the second layers; and a fourth stack comprising one or more fourth pairs of layers disposed on the third stack, each of the one or more fourth pairs of layers comprising a first layer among the first layers and a second layer among the second layers, and The indium content of the first layer of the second stack and the indium content of the first layer of the fourth stack are at least 5% lower than the indium content of the first layer of the first stack and the indium content of the first layer of the third stack.

9. The light emitting element array according to claim 8, wherein The number of the one or more first pairs of layers in the first stack and the number of the one or more third pairs of layers in the third stack are both greater than the number of the one or more second pairs of layers in the second stack and the number of the one or more fourth pairs of layers in the fourth stack.

10. The light emitting element array according to claim 1, wherein The light emitting layer of the first light emitting element includes a quantum well layer containing indium in a content ranging from 30% to 40%, and An indium content of at least one of the first layers of the first light-emitting element is less than or equal to 30% and greater than 0%.

11. The light emitting element array according to claim 1, wherein The peak wavelength of the second color light is shorter than the peak wavelength of the first color light.

12. The light emitting element array according to claim 11, wherein The light emitting element further includes a third light emitting element configured to emit light of a third color having a peak wavelength shorter than the peak wavelength of the second color light, and The second semiconductor layer of the third light-emitting element has a single-layer structure including indium.

13. The light emitting element array according to claim 1, further comprising: an insulating layer disposed on the surface of the substrate, Wherein, in a view in a direction perpendicular to the surface, at least a portion of the insulating layer is disposed between the first light-emitting element and the second light-emitting element.

14. The light emitting element array according to claim 13, wherein The insulating layer overlaps with at least a portion of each of the light emitting elements, each of the portions of the light emitting elements including a peripheral side surface of a corresponding light emitting element among the light emitting elements.

15. The light emitting element array according to claim 14, wherein A thickness of the insulating layer overlapping the at least a portion of the first light emitting element is different from a thickness of the insulating layer overlapping the at least a portion of the second light emitting element.

16. The light emitting element array according to claim 14, further comprising: a reflective layer, disposed on the insulating layer, The reflective layer overlaps with the outer side surface of the light emitting element.

17. The light emitting element array according to claim 1, wherein At least parts of the first semiconductor layers of the light emitting elements are integrated with each other.

18. A display device comprising: a first pixel comprising a first light-emitting element configured to emit light of a first color; as well as A second pixel includes a second light emitting element configured to emit light of a second color, wherein Each of the first light-emitting element and the second light-emitting element includes: a first semiconductor layer; The second semiconductor layer is provided on the surface of the first semiconductor layer. The second semiconductor layer is doped to have the first conductivity type and contains indium; a light-emitting layer disposed on a surface of the second semiconductor layer, the light-emitting layer comprising indium; and a third semiconductor layer, disposed on the surface of the light emitting layer, wherein the third semiconductor layer is doped to have a second conductivity type; The indium content of the light-emitting layer of the first light-emitting element is higher than the indium content of the light-emitting layer of the second light-emitting element. The second semiconductor layer of the first light emitting element includes a first layer containing indium and a second layer alternately stacked with the first layer, and The second semiconductor layer of the second light-emitting element has a single-layer structure including indium.

19. A method for manufacturing a light emitting element array, the method comprising: forming a first semiconductor layer on a surface of the substrate; forming a first mask layer on the first semiconductor layer, wherein the first mask layer defines a first opening exposing a first region of the first semiconductor layer, and the first mask layer overlaps both the second region and the third region of the first semiconductor layer in a direction perpendicular to the surface; sequentially forming a second semiconductor layer doped to have a first conductivity type and containing indium, a light emitting layer containing indium, and a third semiconductor layer doped to have a second conductivity type on the first region; forming a second mask layer on the first mask layer, wherein the second mask layer defines a second opening exposing the second region, and the second mask layer overlaps both the first region and the third region in the direction; sequentially forming a second semiconductor layer doped to have the first conductivity type and containing indium, a light emitting layer containing indium, and a third semiconductor layer doped to have the second conductivity type on the second region; forming a third mask layer on the second mask layer, wherein the third mask layer defines a third opening exposing the third region, and the third mask layer overlaps both the first region and the second region in the direction; as well as A second semiconductor layer doped to have the first conductivity type and containing indium, a light emitting layer containing indium, and a third semiconductor layer doped to have the second conductivity type are sequentially formed on the third region, wherein: The indium contents of the light emitting layers formed on the first region, the second region, and the third region are different from each other, and The second semiconductor layer formed on the region on which the light-emitting layer having the highest indium content is also formed among the first region, the second region, and the third region has a multilayer structure including first layers containing indium and second layers alternately stacked with the first layers.

20. The method according to claim 19, wherein Each of the second semiconductor layers on regions other than the region on which the light emitting layer having the highest indium content is formed among the first region, the second region, and the third region is formed as a single-layer structure.

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