Data acquisition device and method based on FPGA (Field Programmable Gate Array) and CPU (Central Processing Unit), medium, program product and terminal

Abstract

According to the data acquisition device and method based on the FPGA and the CPU, the medium, the program product and the terminal, the defects of the FPGA in the aspects of complex logic processing and diversified equipment driving support are overcome by combining the FPGA and the CPU, and the limitation of the CPU in the aspects of parallel computing capacity and low-delay processing is overcome. The FPGA core processing unit is responsible for high-performance parallel computing and low-delay data processing, and the CPU unit is responsible for complex logic processing and diversified equipment driving support. The cooperative working mode not only improves the efficiency of data acquisition and processing, but also remarkably reduces the development difficulty and the research and development period, and is suitable for complex scenes with multiple types and quantity of sensors, high data transmission rate and flexible expansion. Besides, through the low-speed and high-speed transmission interfaces provided by the inter-board connector, the expansibility and compatibility of the device are further enhanced, so that the device can better adapt to the acquisition requirements of various different sensor numbers in various scenes in the agricultural field.

Description

Technical Field

[0001] The present application relates to the field of smart agriculture, and in particular to a data acquisition device, method, medium, program product, and terminal based on FPGA and CPU. Background Art

[0002] In fields such as modern industrial automation and agricultural automation, there is widespread demand for real-time sensor data acquisition and high-speed image data processing. For example, industrial production lines require real-time data collection of temperature, humidity, gas concentration, and other data to monitor production status. In agricultural scenarios, crop growth environments require data collection on temperature, humidity, light intensity, and soil composition, while simultaneously monitoring growth using images from depth cameras. Furthermore, intelligent inspection robots must process image data from multiple depth cameras in real time to obtain depth information about objects.

[0003] With the development of FPGA technology, FPGAs have been widely used in large-capacity, high-speed data processing due to their high flexibility, strong parallel computing capabilities, low latency, and high bandwidth. However, FPGA technology still faces many challenges in practical applications: high development difficulty and long R&D cycles. Especially in complex and closed systems, limited technical support from manufacturers is available. As a result, FPGAs are relatively inadequate in processing complex logic and diverse device drivers. They also struggle to independently support the communication protocols of multiple image acquisition devices (such as USB, GigE, and SDI), further limiting their applicability in real-world scenarios. Summary of the Invention

[0004] In view of the shortcomings of the prior art described above, the purpose of this application is to provide a data acquisition device, method, medium, program product and terminal based on FPGA and CPU, which is used to solve the problem in the prior art that it is difficult to independently support the communication protocols of multiple image acquisition devices due to the difficulty of FPGA development, long R&D cycle, and deficiencies in complex logic processing and diversified device driver support.

[0005] To achieve the above-mentioned purpose and other related purposes, the first aspect of the present application provides a data acquisition device based on FPGA and CPU, including: an FPGA core processing unit, which is communicatively connected to the CPU unit; used to receive user instructions, and send an enable signal to the CPU unit based on the user instructions, and receive optimized image data sent by the CPU unit; a CPU unit, which is communicatively connected to the image acquisition unit; used to perform image acquisition operations on the image acquisition unit based on the enable signal to generate raw image data, perform image processing operations on the raw image data to generate optimized image data, and send the optimized image data to the FPGA core processing unit.

[0006] In some embodiments of the first aspect of the present application, the FPGA core processing unit is communicatively connected to the CPU unit through at least one low-speed transmission interface and at least one high-speed transmission interface; the CPU unit sends the optimized image data to the FPGA core processing unit through the high-speed transmission interface; and the FPGA core processing unit sends the enable signal to the CPU unit through the low-speed transmission interface.

[0007] In some embodiments of the first aspect of the present application, the CPU unit includes: a core processor module, used to perform the image acquisition operation on the image acquisition unit; a chipset module, used to manage data transmission between the CPU unit and the FPGA core processing unit, and data transmission between the CPU unit and the image acquisition unit; an interface module, including the low-speed transmission interface and the high-speed transmission interface.

[0008] In some embodiments of the first aspect of the present application, the interface module includes an HDMI channel, and the HDMI channel is communicatively connected to the display interface.

[0009] In some embodiments of the first aspect of the present application, the FPGA core processing unit is communicatively connected to multiple expansion modules through an inter-board connector; wherein the inter-board connector includes multiple groups of connectors, each group of connectors providing multiple low-speed transmission interfaces and multiple high-speed transmission interfaces.

[0010] In some embodiments of the first aspect of the present application, the expansion module includes an Ethernet module and a sensor module; the Ethernet module communicates with the FPGA core processing module through the high-speed transmission interface; and the sensor module communicates with the FPGA core processing module through the low-speed transmission interface.

[0011] To achieve the above-mentioned purpose and other related purposes, the second aspect of the present application provides a data acquisition method based on FPGA and CPU, which is applied to the FPGA core processing unit, and the FPGA core processing unit is communicatively connected to the CPU unit. The method includes: receiving user instructions and sending an enable signal to the CPU unit based on the user instructions, so that the CPU unit performs image acquisition operations and image processing operations based on the enable signal to generate optimized image data; and receiving the optimized image data sent by the CPU unit.

[0012] To achieve the above-mentioned purpose and other related purposes, the third aspect of the present application provides a computer-readable storage medium having a computer program stored thereon, which implements the data acquisition method based on FPGA and CPU when executed by a processor.

[0013] To achieve the above-mentioned objectives and other related objectives, the fourth aspect of the present application provides a computer program product, which includes computer program code. When the computer program code is run on a computer, the computer implements the data acquisition method based on FPGA and CPU.

[0014] To achieve the above-mentioned purpose and other related purposes, the fifth aspect of the present application provides an electronic terminal, including a memory, a processor and a computer program stored in the memory; the processor executes the computer program to implement the data acquisition method based on FPGA and CPU.

[0015] As described above, the data acquisition device, method, medium, program product and terminal based on FPGA and CPU of the present application have the following beneficial effects: by combining the technical advantages of FPGA and CPU, the shortcomings of FPGA in complex logic processing and diversified device driver support, as well as the limitations of CPU in parallel computing capabilities and low-latency processing are solved. The FPGA core processing unit is responsible for high-performance parallel computing and low-latency data processing, while the CPU unit is responsible for complex logic processing and diversified device driver support, especially supporting communication protocols for various image acquisition devices. This collaborative working mode not only improves the efficiency of data acquisition and processing, but also significantly reduces the development difficulty and R&D cycle. It is suitable for complex scenarios with many types and quantities of sensors, high data transmission rates, and flexible expansion. In addition, the low-speed and high-speed transmission interfaces provided by the inter-board connector further enhance the scalability and compatibility of the device, enabling it to better adapt to the needs of various image acquisition devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 A structural diagram of an embodiment of a data acquisition device based on FPGA and CPU in the present application is shown.

[0017] Figure 2 A structural diagram of another embodiment of the data acquisition device based on FPGA and CPU in the present application is shown.

[0018] Figure 3 A schematic diagram of the structure of the FPGA core processing unit in an embodiment of the data acquisition device based on FPGA and CPU of the present application is shown.

[0019] Figure 4 The figure shows the structure of the CPU unit in one embodiment of the data acquisition device based on FPGA and CPU of the present application.

[0020] Figure 5 A schematic diagram of the structure of the low-speed transmission interface in an embodiment of the data acquisition device based on FPGA and CPU of the present application is shown.

[0021] Figure 6 A schematic diagram of the structure of a high-speed transmission interface in an embodiment of a data acquisition device based on FPGA and CPU of the present application is shown.

[0022] Figure 7 The figure shows the structure of the Ethernet interface module in an embodiment of the data acquisition device based on FPGA and CPU of the present application.

[0023] Figure 8 A flow chart of an embodiment of a data acquisition method based on FPGA and CPU is shown.

[0024] Figure 9 The figure shows a schematic diagram of the structure of an embodiment of a data acquisition terminal based on FPGA and CPU of the present application. DETAILED DESCRIPTION

[0025] The following describes the embodiments of the present application through specific examples. Those skilled in the art can easily understand the other advantages and effects of the present application from the content disclosed in this specification. The present application can also be implemented or applied through other different specific embodiments. The details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that the following embodiments and features in the embodiments can be combined with each other unless they conflict.

[0026] Before further explaining the present invention in detail, the nouns and terms involved in the embodiments of the present invention are explained. The nouns and terms involved in the embodiments of the present invention are subject to the following interpretations:

[0027] <1> Field Programmable Gate Array (FPGA): An integrated circuit that can be programmed by the user on site. It has a high degree of flexibility and parallel processing capabilities and is widely used in data processing and control systems.

[0028] <2> Central Processing Unit (CPU): Used to perform various computing tasks, including but not limited to arithmetic operations, logical operations, data storage and retrieval, input and output control, and system management functions.

[0029] <3> Inter-board connector: A functional interface used to connect the core processing module with various expandable modules, supporting the transmission of multiple signals and power supplies, with high efficiency, stability and scalability.

[0030] <4> Recommended Standard 485 (RS485): A commonly used serial communication standard suitable for long-distance and multi-point communication, often used in industrial automation and data acquisition systems.

[0031] <5> Controller Area Network (CAN): A communications protocol used in automotive and industrial equipment that supports real-time data exchange between multiple nodes.

[0032] <6> Universal Serial Bus 3.0 (USB 3.0): A high-speed data transmission standard that provides faster data transfer rates and higher power supply capabilities and is commonly used to connect external devices.

[0033] <7> Ethernet: A widely used local area network technology that supports data transmission between computers and devices, usually using an RJ45 interface.

[0034] <8> Double Data Rate 3 Synchronous Dynamic Random Access Memory (DDR3): A type of memory with high data transfer rates and low power consumption, commonly used in computers and embedded systems.

[0035] <9> Depth camera: A camera that can capture the depth information of an object, commonly used in applications such as 3D modeling and robotic vision.

[0036] <10> Software Development Kit (SDK): A set of tools and documentation for developing software applications, typically including libraries, APIs, and sample code.

[0037] <11> Joint Test Action Group (JTAG): A standard interface for testing and debugging circuit boards that allows developers to access debugging features inside the chip.

[0038] <12> General Purpose Input / Output (GPIO): A programmable digital signal interface that allows a device to interact with external hardware.

[0039] <13> Scalable Interface (SEAF): An interface standard for connecting different modules, supporting multiple signal and power transmission.

[0040] <14> GTX (Gigabit Transceiver): An interface used for high-speed data transmission, typically used to connect FPGAs and other high-speed devices.

[0041] To facilitate understanding of the embodiments of this application, first Figure 1 Detailed description. Figure 1 The following is a schematic diagram of the structure of a data acquisition device 100 based on FPGA and CPU in an embodiment of the present invention. The data acquisition device based on FPGA and CPU in this embodiment mainly includes the following parts:

[0042] The FPGA core processing unit 101 is communicatively connected to the CPU unit; it is used to receive user instructions, send an enable signal to the CPU unit based on the user instructions, and receive optimized image data sent by the CPU unit.

[0043] A CPU unit 102 is communicatively connected to the image acquisition unit; based on the enable signal, the CPU unit performs an image acquisition operation on the image acquisition unit to generate raw image data, performs an image processing operation on the raw image data to generate optimized image data, and sends the optimized image data to the FPGA core processing unit.

[0044] Figure 2The schematic diagram of the structure of an embodiment of the present application is shown. This embodiment is applied to fields such as industrial automation and agricultural monitoring, including environmental monitoring, equipment status monitoring, and intelligent control, thereby significantly improving the efficiency and accuracy of the system. This device is composed of an FPGA core processing unit and a CPU unit. It aims to solve the problem in the existing technology that it is difficult to independently support the communication protocols of multiple image acquisition devices due to the difficulty of FPGA development, long R&D cycle, and deficiencies in complex logic processing and diversified device driver support. In order to adapt to the various needs of complex industrial and agricultural scenarios, this embodiment adopts a modular design to ensure its compatibility with standard peripherals widely used in the market.

[0045] like Figure 2 As shown, the FPGA core processing unit in this embodiment focuses on data processing and control, and includes: an FPGA chip (such as XC7K325T) as the core processor to perform high-speed data processing; a low-speed interface module integrating multiple RS485 / CAN interfaces for connecting temperature and humidity sensors, gas composition, concentration detection sensors, and motor encoders, etc., supporting multiple functions such as data acquisition and motor control; the high-speed interface module is connected to industrial cameras, webcams and other devices through multiple USB 3.2 interfaces to achieve high-speed image data transmission; in addition, the Ethernet interface module uses multiple PHY modules to connect to Ethernet devices including industrial cameras and routers, supporting high-speed data exchange; the memory module (16Gbit DDR3L) provides support for data storage and program execution, and the user interface facilitates debugging and configuration.

[0046] This embodiment is actually applied to an Agaricus bisporus inspection robot in the agricultural field. In actual production, to accurately obtain the posture and status data of Agaricus bisporus, an Intel D400 series depth camera is required. Its stereo vision algorithm is used to efficiently capture the three-dimensional information of the mushroom body, providing reliable data support for subsequent analysis. In the existing technology, simply using an FPGA as the computing core is difficult to directly support the data acquisition and complex vision algorithm processing of the D400 series camera, mainly due to the FPGA's insufficient data processing capabilities and development flexibility. To address this problem, this solution innovatively introduces an expansion module based on the Intel i5-12500TE CPU on the FPGA. The CPU is responsible for driving the depth camera's data acquisition and preliminary processing, while supporting the FPGA to complete efficient calculations, thus ensuring performance while balancing cost, power consumption, and development efficiency.

[0047] Furthermore, the CPU unit is connected to the image acquisition unit, primarily for acquiring image data from Intel's depth camera and deploying machine learning algorithms. The depth camera can simultaneously acquire RGB images and depth information, providing basic data for accurate measurement of the growth morphology and size of Agaricus bisporus. Based on the enable signal sent by the FPGA core processing unit, the CPU unit performs image acquisition operations on the image acquisition unit, generating raw image data. It then performs image processing operations on this raw image data to generate optimized image data, and finally sends the optimized image data to the FPGA core processing unit via the PCIE high-speed interface for analysis and processing. Image processing operations include preprocessing steps such as image filtering, enhancement, and segmentation to improve the accuracy of subsequent analysis.

[0048] Specifically, the CPU chip of the CPU unit is connected to the FPGA core processing unit through the PCIE Gen2 / 3 interface. PCIE Gen2 / 3 is a high-speed computer bus standard that supports transmission rates of 5GT / s and 8GT / s respectively, and is used to connect graphics cards, solid-state drives and other devices. The CPU unit is mainly responsible for executing advanced application logic (such as image processing) and user interface display, and includes a processor, chipset, storage interface, user debugging interface and high-speed interface module. Among them, the CPU processor undertakes complex logical calculation tasks, while the chipset (such as H610E) is responsible for coordinating data interaction between the processor and external devices. The storage interface is connected to the M.2 solid-state drive to ensure high-speed data access efficiency. The M.2 solid-state drive is a compact storage device that supports SATA and NVMe protocols and can reach speeds of more than 3500MB / s when transmitted through the PCIE interface.

[0049] The user debugging interface facilitates system testing and configuration, supporting program downloads, debugging, and parameter configuration. Furthermore, the high-speed interface module supports fast connection to external devices, including four USB 3.2 ports, each connected to a D400 camera, for efficient data transmission and processing.

[0050] Furthermore, the FPGA core processing unit, as the core processor of the data acquisition device, interacts with the warehouse control system (WCS, Warehouse Control System) in the intelligent agricultural factory through the Ethernet interface using the Message Queue Telemetry Transport Protocol (MQTT) for telemetry and remote control data. The WCS system is responsible for warehouse logistics management and control, coordinating and managing the storage, transportation and distribution of agricultural products. The MQTT protocol is a lightweight publish / subscribe message transmission protocol suitable for remote communication in low-bandwidth, high-latency or unreliable network environments. The FPGA core processing unit is used to receive user instructions and send enable signals to the CPU unit based on these instructions, while also receiving optimized image data sent by the CPU unit.

[0051] Considering that this application is primarily used in Agaricus bisporus cultivation environments, it is responsible for collecting environmental parameters such as temperature, humidity, carbon dioxide concentration, and atmospheric pressure at each growth stage of Agaricus bisporus, as well as collecting data on the growth morphology and individual size of Agaricus bisporus using a depth camera. The collected data is analyzed and processed by machine learning algorithms deployed in the CPU processing unit. The machine learning algorithms used include computer vision algorithms for identifying the growth status of Agaricus bisporus, such as convolutional neural networks (CNN) for morphological recognition, and regression models for growth prediction. These algorithms can extract features such as the size, shape, and color of Agaricus bisporus from image data and perform comprehensive analysis based on environmental parameters. The processing results are then transmitted to the WCS and warehouse management system (WMS). The WMS system is responsible for managing materials, product inventory, and related information within the agricultural factory, working in conjunction with the WCS system to optimize the production and logistics processes of agricultural products.

[0052] Furthermore, embodiments of the present application also provide an intelligent decision-making module for timely intervention and adjustment of the mushroom house environment. For example, it adjusts parameters such as temperature, humidity, and carbon dioxide concentration to create optimal environmental conditions for Agaricus bisporus growth. The intelligent decision-making module can also predict the current picking time and yield of Agaricus bisporus within the mushroom house, enabling the deployment, scheduling, and decision-making of intelligent harvesting robots in advance. Based on information provided by the system, the intelligent harvesting robots can accurately locate mature Agaricus bisporus and perform efficient and non-destructive harvesting operations, thereby improving the growth quality and work efficiency of Agaricus bisporus.

[0053] In one embodiment of the present application, the FPGA core processing unit is equipped with a user debugging interface and a high-speed interface module to achieve efficient system operation and precise control. The user debugging interface integrates three communication methods: an Ethernet interface using a standard RJ45 network cable provides network communication capabilities; JTAG and UART interfaces are integrated into a single Type-C port, facilitating program downloads, debugging, and parameter configuration. The high-speed interface module is responsible for implementing camera control functions. This module connects to the D400 camera via dedicated signals and precisely controls the camera synchronization signals, ensuring that multiple cameras capture images at the same time. This synchronization mechanism ensures temporal image consistency in the multi-camera system, providing a reliable foundation for subsequent image processing and analysis. The system uses an FPGA as the core control unit, responsible for generating and managing enable signals to coordinate the operation of various modules. Users can use the debugging interface to monitor and configure the system in real time, obtain enable signal status information, and dynamically evaluate and adjust the device's operating status. This design not only improves system response speed and operational efficiency, but also ensures the coordination of various modules in the multi-camera system, providing a strong guarantee for overall performance optimization.

[0054] In this embodiment, the CPU unit also supports the acquisition and analysis of conventional sensor data via USB and Universal Asynchronous Receiver / Transmitter (UART) interfaces, serving as a backup for the FPGA core processing unit. These interfaces are used to connect to various sensor devices, such as temperature and humidity sensors, carbon dioxide concentration sensors, and atmospheric pressure sensors. The FPGA core processing unit and the CPU unit provide complementary functions, enabling automatic or manual switching based on actual conditions, thereby improving system reliability and flexibility.

[0055] In one embodiment of the present application, the FPGA core processing unit is communicatively connected to the CPU unit through at least one low-speed transmission interface and at least one high-speed transmission interface; the CPU unit sends the optimized image data to the FPGA core processing unit through the high-speed transmission interface; and the FPGA core processing unit sends the enable signal to the CPU unit through the low-speed transmission interface.

[0056] Figure 3The schematic diagram of the structure of the FPGA core processing unit in one embodiment of the present application is shown. The FPGA core processing unit includes an FPGA chip, a DDR3L large-capacity cache module, a power management module, a flash memory module (FLASH), an IO interface, and a user debugging interface. In the core processing module of the present invention, the FPGA chip adopts Xilinx's K7 series product XC7K325T-2FFG900I, which contains 326080 logic units, 16-way GTX high-speed interface, 500 GPIO interfaces, 1 PCIE Gen2 hard core, and supports PCIE Gen soft core, and its BRAM capacity is 4Mb. These rich logic resources can meet the needs of most data acquisition and processing tasks.

[0057] In this embodiment, the DDR3L high-capacity cache module consists of four 16-bit DDR3L chips, achieving a 64-bit data width, a total capacity of 16Gbit, and a data rate of 1333Mb / s. This module can be used to cache various data during device operation, including sensor data, image data, user data, and service data.

[0058] In this embodiment, the flash memory module (FLASH) is used to store the FPGA chip's bitstream file and user-bound parameters, with a total capacity of 512Mb. The user debug interface supports Ethernet, JTAG, and UART. JTAG and UART are integrated into a single Type-C connector, while the Ethernet interface uses a standard RJ45 network cable. Users can use this debug interface to upgrade, debug, and modify product functions, programs, and parameters.

[0059] In this embodiment, the IO interface is used to control the camera synchronization signal. By synchronizing the IO control signal, all cameras can capture images at the same time, thereby ensuring the consistency of image data.

[0060] In this embodiment, the power management module is responsible for providing multiple power supply voltages to all related components in the core processing module and components in the expansion modules. This module supports both AC-220V and DC-12V power supply modes, making it easy to select the appropriate power supply in actual applications.

[0061] In one embodiment of the present application, the CPU unit includes: a core processor module, used to perform the image acquisition operation on the image acquisition unit; a chipset module, used to manage data transmission between the CPU unit and the FPGA core processing unit, and data transmission between the CPU unit and the image acquisition unit; an interface module, including the low-speed transmission interface and the high-speed transmission interface.

[0062] Figure 4The functional block diagram of the CPU unit in one embodiment of the present application is shown. The CPU unit is composed of an I5-12500TE CPU and an H610E chipset, and is connected to the FPGA core processing module through a SEAM inter-board connector. The CPU unit is used to implement the image data acquisition and processing functions of the D400 series depth camera. Specifically, the CPU unit can be connected to four groups of D400 series depth cameras at the same time through four USB 3.2 interfaces. When the camera receives the trigger enable signal sent by the FPGA core processing module, it starts to capture the current image and transmits the collected data to the CPU processor for processing and analysis. The parsed image data is transmitted back to the FPGA core processing module through the PCIE Gen2 interface, and is further processed and analyzed by the core processing module. In addition, the CPU unit also includes a 1T M.2 interface solid-state drive for long-term storage of various types of information such as image data, sensor data, and business data.

[0063] In one embodiment of the present application, the interface module includes an HDMI channel, and the HDMI channel is communicatively connected to the display interface.

[0064] In this embodiment, the CPU unit can transmit the device's operating status information, processed image data, and other business data to the display via the HDMI interface. By configuring a corresponding UI interface, the current system status can be intuitively displayed. Through the HDMI channel, the CPU unit can present image data and sensor data processed by the FPGA core processing module in real time, facilitating real-time monitoring and operation of the device's operating status.

[0065] In one embodiment of the present application, the FPGA core processing unit is communicatively connected to multiple expansion modules through an inter-board connector; wherein the inter-board connector includes multiple groups of connectors, each group of connectors provides multiple low-speed transmission interfaces and multiple high-speed transmission interfaces.

[0066] In this embodiment, the core processing module connects to various expandable modules via SEAF inter-board connectors. Four SEAF connectors are designed, each providing a DC-5V, 5A power supply, 80 GPIO ports, and four GTX high-speed ports. Expansion modules can use these resources as needed. The SEAF connectors support a maximum data rate of 56 Gbps, each pin can handle 0.3A of current, and have a voltage withstand capability of 240V.

[0067] In this embodiment, Figure 5The structural diagram of the low-speed transmission interface in one embodiment of the present application is shown. The low-speed transmission interface module consists of 5 groups of RS485 interfaces and a group of CAN interfaces. Each group of RS485 interface buses allows the mounting of 256 nodes. The 5 groups of RS485 interfaces can communicate with up to 1280 nodes, with a maximum transmission rate of up to 16Mbps, which is suitable for long-distance communication scenarios such as sensors and industrial equipment. The CAN interface can mount up to 110 sub-nodes, supporting efficient data transmission and reliable communication protocols. In addition, redundant input and output (IO) resources, that is, unused hardware interface resources, can be further expanded through another SEAF connector to meet the needs of more device access.

[0068] In this embodiment, Figure 6 A schematic diagram of the high-speed transmission interface in one embodiment of the present application is shown. The high-speed transmission interface utilizes a USB 3.0 interface module, which consists of four USB 3.0 interfaces. The USB 3.0 interface module connects to the core processing module via a SEAM connector, supporting simultaneous data transmission across four USB interfaces with a maximum transmission rate of 5Gbps. This makes it suitable for high-bandwidth applications such as real-time transmission of industrial camera images. Furthermore, excess input / output (IO) resources, i.e., hardware interfaces that can be used to connect to other devices or expand functionality, can be further expanded via SEAF connectors to enhance system flexibility and scalability.

[0069] It should be noted that inter-board connectors are used to connect the hardware interfaces of different functional modules to enable data transmission and power supply between modules. In the present invention, the inter-board connectors include SEAF connectors and SEAM connectors, which are used to connect the core processing module to the expansion module and the core processing module to the CPU unit, respectively, to build a highly flexible and scalable system architecture.

[0070] Specifically, the SEAF connectors used in the high-speed and low-speed transmission structures are primarily used to connect the core processing module with various expandable modules, such as the low-speed interface module, Ethernet interface module, and USB 3.0 interface module. Each SEAF connector provides a DC-5V, 5A power supply, 80 GPIO (general-purpose input and output) interfaces, and four GTX high-speed interfaces, supporting a maximum transmission rate of 56Gbps. Each pin can withstand 0.3A of current and has a voltage resistance of 240V. Excess IO resources can be further expanded through the SEAF connector.

[0071] The SEAM connector, used to connect the FPGA core unit and the CPU unit, connects the core processing module to the CPU unit, supporting high-speed data transmission, such as the PCIE Gen2 interface for transmitting image data and processing results. Through these two connectors, this application achieves a modular design, enabling flexible connection of different functional modules based on actual needs, meeting various data acquisition, processing, and transmission requirements while ensuring high performance and scalability of the system.

[0072] In one embodiment of the present application, the expansion module includes an Ethernet module and a sensor module; the Ethernet module communicates with the FPGA core processing module through the high-speed transmission interface; and the sensor module communicates with the FPGA core processing module through the low-speed transmission interface.

[0073] In this embodiment, the Ethernet interface module consists of 5 groups of Gigabit Ethernet interfaces, and its structural diagram is shown in FIG. Figure 7 The Ethernet interface module connects to the core processing module via a SEAM connector and supports simultaneous transmission of five Gigabit Ethernet datagrams. The module's RJ45 network port integrates a network transformer, eliminating the need for a separate network transformer in the circuit, simplifying design and reducing costs.

[0074] In addition, the Ethernet interface module is designed with a reserved SFP+ (Small Form-factor Pluggable Plus) interface to support data transmission using the 10 Gigabit Ethernet protocol, suitable for ultra-high-speed application scenarios. This makes the system more flexible and efficient when handling large amounts of data transmission. To further increase the scalability of the system, the module also retains redundant input and output (IO) resources, which can be expanded via SEAF connectors to meet the access needs of different functional modules in the future. Through this design, the Ethernet interface module not only improves data transmission speed, but also enhances the flexibility and scalability of the entire system.

[0075] In this embodiment, the sensor module communicates with the FPGA core processing module via a low-speed transmission interface. Specifically, the low-speed transmission interface module consists of five RS485 interfaces and one CAN interface, effectively supporting the connection of a variety of sensors, such as temperature and humidity sensors, gas composition / concentration sensors, and motor encoders. The design of these interfaces enables data exchange between the sensor module and the FPGA core processing module, ensuring real-time acquisition and processing of sensor data.

[0076] It should be noted that in the embodiments of this application, words such as "exemplary" or "for example" represent examples, illustrations, or descriptions. Any embodiment or design described in this application as "exemplary" or "for example" should not be interpreted as being preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0077] In the embodiments of the present application, "at least one" refers to one or more, and "more" refers to two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: the existence of A alone, the existence of A and B at the same time, and the existence of B alone, where A and B can be singular or plural. The character " / " generally indicates that the previous and next associated objects are in an "or" relationship. "At least one of the following items" or similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b or c can represent: a, b, c, ab, ac, bc or abc, where a, b, c can be single or multiple.

[0078] Figure 8 Schematic diagram of the data acquisition method based on FPGA and CPU provided in the embodiment of the present application. Figure 8 As shown, the method has the following steps:

[0079] Step S81: Receive user instructions.

[0080] Step S82: Sending an enable signal to the CPU unit based on the user instruction, so as to enable the CPU unit to perform image acquisition operations and image processing operations based on the enable signal to generate optimized image data.

[0081] Step S83: Receive the optimized image data sent by the CPU unit.

[0082] It should be understood that the specific process of each module executing the above corresponding steps has been described in detail in the above method embodiment, and for the sake of brevity, it will not be repeated here.

[0083] It should also be understood that the division of modules in the embodiments of the present application is illustrative and is merely a logical functional division. In actual implementation, other division methods may be used. Furthermore, the functional modules in the various embodiments of the present application may be integrated into a single processor, or may exist physically separately, or two or more modules may be integrated into a single module. The aforementioned integrated modules may be implemented in the form of hardware or software functional modules.

[0084] Figure 9This is a schematic block diagram of an electronic terminal provided in an embodiment of the present application. Figure 9 As shown, the electronic terminal includes: at least one processor 901, a memory 902, at least one network interface 903 and a user interface 905. The various components in the device are coupled together via a bus system 904. It is understood that the bus system 904 is used to achieve connection and communication between these components. In addition to the data bus, the bus system 904 also includes a power bus, a control bus and a status signal bus. However, for the sake of clarity, Figure 9 Various buses are labeled as bus systems.

[0085] The user interface 905 may include a display, a keyboard, a mouse, a trackball, a click gun, keys, buttons, a touch pad or a touch screen.

[0086] It will be appreciated that the memory 902 may be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memories. Among them, the non-volatile memory may be a read-only memory (ROM) or a programmable read-only memory (PROM), which is used as an external cache. By way of example but not limitation, many forms of RAM are available, such as static random access memory (SRAM) and synchronous static random access memory (SSRAM). The memory described in the embodiments of the present invention is intended to include, but is not limited to, these and any other suitable types of memory.

[0087] The memory 902 in the embodiment of the present invention is used to store various categories of data to support the operation of the electronic terminal 900. Examples of such data include: any executable program for operating on the electronic terminal 900, such as an operating system 9021 and an application 9022; the operating system 9021 includes various system programs, such as a framework layer, a core library layer, a driver layer, etc., for implementing various basic services and processing hardware-based tasks. The application 9022 can include various applications, such as a media player (Media Player), a browser (Browser), etc., for implementing various application services. The data acquisition method based on FPGA and CPU provided in the embodiment of the present invention can be included in the application 9022.

[0088] The methods disclosed in the above embodiments of the present invention can be applied to or implemented by processor 901. Processor 901 may be an integrated circuit chip with signal processing capabilities. During implementation, each step of the above method can be completed by hardware integrated logic circuits in processor 901 or by software instructions. The above processor 901 may be a general-purpose processor, a digital signal processor (DSP), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. Processor 901 can implement or execute the various methods, steps, and logic block diagrams disclosed in the embodiments of the present invention. The general-purpose processor 901 may be a microprocessor or any conventional processor. The steps of the accessory optimization method provided in the embodiments of the present invention can be directly implemented and executed by a hardware decoding processor, or by a combination of hardware and software modules in the decoding processor. The software module can be located in a storage medium located in a memory. The processor reads the information in the memory and, in conjunction with its hardware, completes the steps of the above method.

[0089] In an exemplary embodiment, the electronic terminal 900 may be configured to execute the aforementioned method using one or more application specific integrated circuits (ASICs), DSPs, programmable logic devices (PLDs), or complex programmable logic devices (CPLDs).

[0090] According to the method provided in the embodiments of the present application, the present application also provides a computer program product, which includes: computer program code, which, when running on a computer, enables the computer to execute the data acquisition method based on FPGA and CPU in any of the embodiments shown above.

[0091] According to the method provided in the embodiments of the present application, the present application also provides a computer-readable storage medium, which stores program code. When the program code runs on a computer, the computer executes the data acquisition method based on FPGA and CPU in any of the embodiments shown above.

[0092] As used in this specification, the terms "component," "module," "system," and the like are used to represent computer-related entities, hardware, firmware, a combination of hardware and software, software, or software in execution. For example, a component can be, but is not limited to, a process running on a processor, a processor, an object, an executable file, an execution thread, a program, and / or a computer. By way of illustration, both an application running on a computing device and a computing device can be a component. One or more components can reside in a process and / or an execution thread, and a component can be located on a computer and / or distributed between two or more computers. In addition, these components can be executed from various computer-readable media having various data structures stored thereon. Components can communicate, for example, via local and / or remote processes based on signals having one or more data packets (e.g., data from two components interacting with another component on a local system, a distributed system, and / or a network, such as the Internet interacting with other systems via signals).

[0093] Those skilled in the art will appreciate that the various illustrative logical blocks and steps described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0094] Those skilled in the art will clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0095] In the several embodiments provided in this application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are merely schematic. For example, the division of units is only a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0096] Units described as separate components may or may not be physically separate, and components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.

[0097] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0098] In the above embodiments, the functions of each functional unit can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When software is used for implementation, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions (programs). When the computer program instructions (program) are loaded and executed on a computer, the process or function according to the embodiment of the present application is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from a website, computer, server or data center to another website, computer, server or data center by wired (such as coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (such as infrared, wireless, microwave, etc.) mode. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that includes one or more available media integrations. Available media can be magnetic media (e.g., floppy disks, hard disks, tapes), optical media (e.g., high-density digital video discs (DVDs), or semiconductor media (e.g., solid-state drives (SSDs)).

[0099] If the function is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the various embodiments of the present application. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0100] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of the present application. Therefore, the scope of protection of the present application should be based on the scope of protection of the claims.

[0101] In summary, the present application provides a data acquisition device, method, medium, program product and terminal based on FPGA and CPU. By combining the technical advantages of FPGA and CPU, it solves the shortcomings of FPGA in complex logic processing and diversified device driver support, as well as the limitations of CPU in parallel computing capabilities and low-latency processing. The FPGA core processing unit is responsible for high-performance parallel computing and low-latency data processing, while the CPU unit is responsible for complex logic processing and diversified device driver support, especially supporting communication protocols for various image acquisition devices. This collaborative working mode not only improves the efficiency of data acquisition and processing, but also significantly reduces the development difficulty and R&D cycle. It is suitable for complex scenarios with many types and quantities of sensors, high data transmission rates, and flexible expansion. In addition, the low-speed and high-speed transmission interfaces provided by the inter-board connector further enhance the scalability and compatibility of the device, enabling it to better adapt to the needs of various image acquisition devices. Therefore, the present application effectively overcomes the various shortcomings of the existing technology and has high industrial utilization value.

[0102] The above embodiments are merely illustrative of the principles and effects of this application and are not intended to limit this application. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of this application. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical concepts disclosed in this application shall be covered by the claims of this application.

Claims

1. A data acquisition device based on FPGA and CPU, characterized in that: include: FPGA core processing unit, the FPGA core processing unit is communicatively connected to the CPU unit; Used to receive a user instruction, and send an enable signal to the CPU unit based on the user instruction, and receive optimized image data sent by the CPU unit; A CPU unit is communicatively connected to the image acquisition unit; based on the enable signal, the CPU unit performs an image acquisition operation on the image acquisition unit to generate raw image data, performs an image processing operation on the raw image data to generate optimized image data, and sends the optimized image data to the FPGA core processing unit.

2. The data acquisition device based on FPGA and CPU according to claim 1, characterized in that: The FPGA core processing unit is communicatively connected to the CPU unit via at least one low-speed transmission interface and at least one high-speed transmission interface; The CPU unit sends the optimized image data to the FPGA core processing unit through the high-speed transmission interface; The FPGA core processing unit sends the enable signal to the CPU unit through the low-speed transmission interface.

3. The data acquisition device based on FPGA and CPU according to claim 2, characterized in that: The CPU unit includes: a core processor module, configured to perform the image acquisition operation on the image acquisition unit; A chipset module, used to manage data transmission between the CPU unit and the FPGA core processing unit, and data transmission between the CPU unit and the image acquisition unit; The interface module includes the low-speed transmission interface and the high-speed transmission interface.

4. The data acquisition device based on FPGA and CPU according to claim 3, characterized in that: The interface module includes an HDMI channel, and the HDMI channel is communicatively connected to the display interface.

5. The data acquisition device based on FPGA and CPU according to claim 1, characterized in that: The FPGA core processing unit is communicatively connected to a plurality of expansion modules via an inter-board connector; wherein the inter-board connector includes a plurality of groups of connectors, each group of connectors providing a plurality of low-speed transmission interfaces and a plurality of high-speed transmission interfaces.

6. The data acquisition device based on FPGA and CPU according to claim 5, characterized in that: The expansion module includes an Ethernet module and a sensor module; The Ethernet module communicates with the FPGA core processing module via the high-speed transmission interface; The sensor module realizes communication with the FPGA core processing module through the low-speed transmission interface.

7. A data acquisition method based on FPGA and CPU, characterized in that: The method is applied to an FPGA core processing unit, wherein the FPGA core processing unit is communicatively connected to a CPU unit, and the method includes: Receive a user instruction, and send an enable signal to the CPU unit based on the user instruction, so that the CPU unit performs an image acquisition operation and an image processing operation based on the enable signal to generate optimized image data; receive the optimized image data sent by the CPU unit.

8. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the data acquisition method based on FPGA and CPU as claimed in claim 7 is implemented.

9. A computer program product, characterized in that The computer program product includes computer program code, and when the computer program code is run on a computer, the computer is enabled to implement the data acquisition method based on FPGA and CPU as claimed in claim 7.

10. An electronic terminal comprising a memory, a processor, and a computer program stored in the memory, characterized in that: The processor executes the computer program to implement the data acquisition method based on FPGA and CPU as claimed in claim 7.

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